Memory device for improving programming operation and operating method of memory device

Abstract

The disclosure provides a memory device and an operating method of a memory device. The memory device includes a cell array and a control circuit. The cell array includes a plurality of cell strings coupled to a word line and a drain select line. The control circuit is configured to, during a program period, apply a program voltage to the word line and control the drain select line to avoid programming data in a plurality of memory cells included in the plurality of cell strings during a portion of a duration of the program period.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2024-0177239, filed on December 3, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure described herein relate to a memory device, and more particularly, to a memory device that performs improved programming operations and a method of operating the memory device. Background Technology

[0004] The computing system increases its computational load in response to user demands. As the computational load increases, the amount of data generated or stored also increases. The memory system within the computing system performs data input and output operations in response to requests from external devices such as the host. The memory system may include at least one memory device. The memory device may include at least one of volatile memory cells and non-volatile memory cells for storing data. Summary of the Invention

[0005] Embodiments of this disclosure may provide a memory device, a memory system including the memory device, or a data processing apparatus including the memory system.

[0006] Embodiments of this disclosure may provide a memory device and a method of operating the memory device that can reduce or avoid differences in effective or active programming time caused by delays in voltage applied via word lines, based on the location of multiple cell strings included in the memory device or at memory cells located at intervals.

[0007] Furthermore, embodiments of this disclosure may provide a memory device and a memory system including the memory device, which are capable of equally adjusting the effective time period for programming data to multiple memory cells due to programming voltage applied through word lines, regardless of the location or positioning of multiple memory cells, thereby improving the reliability of programming and verification operations.

[0008] In embodiments of this disclosure, a memory device may include: a cell array including a plurality of cell strings coupled to word lines and drain select lines; and control circuitry configured to apply a programming voltage to the word lines during a programming period and to control the drain select lines to prevent data from being programmed into a plurality of memory cells included in the plurality of cell strings for a portion of the programming period.

[0009] Part of the duration may include the delay time during which the programming voltage reaches the second cell string furthest from the control circuit after it has been applied via the word line.

[0010] The multiple unit strings include a first unit string closest to the control circuit and a second unit string farthest from the control circuit. The valid time period for programming data in the first unit string and the valid time period for programming data in the second unit string can be substantially equal to each other.

[0011] Each effective time slot can be 50% or less of the programmed time slot.

[0012] The control circuit can be configured to disable the drain selection line for a portion of the duration.

[0013] Partial duration can be determined based on the number of multiple unit strings connected to the word line.

[0014] The programming voltage can have a higher voltage level than the pass voltage, which is applied to other word lines adjacent to the word line. The control circuitry can be configured to apply the programming voltage to the word line after the pass voltage has been applied to the other word lines.

[0015] The control circuit can be configured to disable the drain selection line when a pass voltage is applied.

[0016] The control circuit can be configured to control the drain selection line to avoid verifying data programmed into multiple memory cells during a portion of the verification period, during which a verification voltage is applied to the word line.

[0017] In another embodiment, a method of operating a memory device may include: applying a programming voltage to a plurality of memory cells via word lines during a programming period; and controlling a drain selection line to prevent data from being programmed into the plurality of memory cells, which are included in a plurality of cell strings, for a portion of the programming period.

[0018] The multiple unit strings include a first unit string closest to the control circuit and a second unit string farthest from the control circuit. The valid time period for programming data in the first unit string and the valid time period for programming data in the second unit string can be substantially equal to each other.

[0019] Partial duration can be determined based on the number of multiple unit strings connected to the word line.

[0020] Controlling the drain selection line may include disabling the drain selection line for a portion of the time.

[0021] Applying a programming voltage may include: applying a pass voltage to multiple word lines and disabling the drain select line while applying the pass voltage; and applying a programming voltage to a word line selected among the multiple word lines.

[0022] The method may further include: applying a verification voltage to a word line; and controlling a drain selection line to avoid verifying data in multiple memory cells included in multiple cell strings during a portion of the verification period, during which the verification voltage is applied to the word line.

[0023] In another embodiment, a memory device may include: a plurality of drain select lines respectively connected to each of a plurality of cell strings; at least one word line connected to the plurality of cell strings; and control circuitry configured to apply a programming voltage to the word line during a programming period and control the plurality of drain select lines to prevent data from being programmed into the plurality of memory cells included in the plurality of cell strings for a portion of the programming period.

[0024] The multiple unit strings include a first unit string closest to the control circuit and a second unit string farthest from the control circuit. The valid time period for programming data in the first unit string and the valid time period for programming data in the second unit string can be substantially equal to each other.

[0025] Partial duration can be determined based on the number of multiple unit strings connected to the word line.

[0026] In another embodiment, a memory device may include: a plurality of word lines connected to a plurality of cell strings; and control circuitry configured to select a word line among the plurality of word lines and to apply a first voltage to at least one adjacent word line adjacent to the word line before applying a programming voltage to the word line, the first voltage having a higher level than the pass voltage.

[0027] At least one adjacent word line may include a first word line and a second word line, the second word line being closer to the first word line than the first word line. The control circuitry may be configured to: apply a pass voltage to the second word line before and during a preset time period after the programming voltage is applied to the word line; apply a first voltage to the first word line before the programming voltage is applied to the word line; and apply a pass voltage to the first word line during the preset time period.

[0028] These and other features and advantages of the invention will become apparent from the detailed description of the embodiments and the accompanying drawings of this disclosure. Attached Figure Description

[0029] The description herein refers to the accompanying drawings, in which the same reference numerals refer to the same parts throughout the drawings.

[0030] Figure 1 A first memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 2A second memory device according to an embodiment of the present disclosure is shown.

[0032] Figure 3 A first cell array structure according to an embodiment of the present disclosure is shown.

[0033] Figure 4 A second cell array structure according to an embodiment of the present disclosure is shown.

[0034] Figure 5 A third cell array structure according to an embodiment of the present disclosure is shown.

[0035] Figure 6 A fourth cell array structure according to an embodiment of the present disclosure is shown.

[0036] Figure 7 The programming and verification operations according to embodiments of this disclosure are illustrated.

[0037] Figure 8 The programming operation mode according to embodiments of this disclosure is illustrated.

[0038] Figure 9 The delays associated with voltages or signals applied to a cell array are shown according to embodiments of this disclosure.

[0039] Figure 10 A first programming operation according to an embodiment of this disclosure is shown.

[0040] Figure 11 A second programming operation according to an embodiment of this disclosure is shown.

[0041] Figure 12 A third programming operation is shown according to an embodiment of this disclosure.

[0042] Figure 13 A fourth programming operation is shown according to an embodiment of this disclosure. Detailed Implementation

[0043] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. In this disclosure, elements and features may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0044] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may be combined in the same embodiment or may not necessarily be combined in the same embodiment.

[0045] In this disclosure, the terms “comprising,” “including,” “containing,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0046] In this disclosure, various units, circuits, or other components may be described or referred to as being "configured" to perform one or more tasks. In this context, "configured" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when a specified block / unit / circuit / component is not currently operational, such as not being turned on or enabled, it can be said that the block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits used with the language "configured" include hardware, circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured" may include causing a general-purpose structure, such as a general-purpose circuit, to be manipulated by software and / or firmware, such as an FPGA or a general-purpose processor running software, to operate in a manner capable of performing the relevant task(s). "Configured" may also include adapting a manufacturing process, such as a semiconductor manufacturing facility, to manufacture means suitable for performing or implementing one or more tasks, such as integrated circuits.

[0047] As used herein, the terms “machine,” “circuit,” or “logic” refer to all of the following: (a) a purely hardware circuit implementation, such as an implementation of purely analog and / or digital circuits; (b) a combination of circuitry with software and / or firmware, such as (if applicable): (i) a combination of processors or (ii) a processor / software comprising a digital signal processor, software, and memory, which work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit, such as a microprocessor or a portion thereof, which requires software or firmware for operation even if the software or firmware is not physically present. This definition of “machine,” “circuit,” or “logic” applies to all uses of the term in this application, including all uses of the term in any claim. As a further example, as used herein, the terms “machine,” “circuit,” or “logic” also cover implementations of only one or more processors or portions thereof and their accompanying software and / or firmware. For example, if applicable to a particular claim element, the terms “machine,” “circuit,” or “logic” also cover integrated circuits of memory devices.

[0048] As used herein, the terms “first,” “second,” “third,” etc., serve as labels preceding nouns and do not imply any type of ordering, such as spatial, temporal, or logical. The terms “first” and “second” do not necessarily mean that the first value must precede the second value. Furthermore, while these terms may be used herein to distinguish various elements, these elements are not limited by these terms. These terms are used to differentiate one element from another that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0049] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on those factors, or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0050] Embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0051] Figure 1 A first memory device 150A according to an embodiment of the present disclosure is shown.

[0052] Reference Figure 1 The first memory device 150A may include at least one memory die. The first memory device 150A may receive or output multiple control signals CE#, CLE, ALE, WE#, RE#, WP#, R / B#, and receive or transmit data or operation information through channels I / O[7:0] and I / O[15:0]. For example, a predetermined amount of data (e.g., 1 byte (8 bits) or 2 bytes (16 bits)) may be transmitted and received according to the channels (e.g., I / O[7:0], I / O[15:0]) connecting the first memory device 150A and the controller.

[0053] According to an embodiment, the first memory device 150A may include multiple pins or pads. For example, multiple control signals CE#, CLE, ALE, WE#, RE#, WP#, and R / B# can be transmitted or received through specially assigned pins. The control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, a write protection signal WP#, and a status signal R / B# indicating a ready or busy state, etc. The control signals CE#, CLE, ALE, WE#, RE#, WP#, and R / B# can be controlled (transmitted and received) by the control circuitry 180 included in the first memory device 150A.

[0054] The first memory device 150A may include input and output (I / O) control circuitry 380. The I / O control circuitry 380 may be connected to other devices or components (e.g., a controller) via channels I / O [7:0] and I / O [15:0]. The I / O control circuitry 380 in the first memory device 150A may be connected to multiple registers 372, 374, 376 and a cache register 256, which is connected to a cell array 330.

[0055] According to an embodiment, where the first memory device 150A may include multiple memory chips, the input / output control circuitry 380 may include a chip selection decoder. The chip selection function can be used to enable one of multiple memory chips included in or connected to the memory system or data processing system. According to an embodiment, the chip selection decoder may be implemented using combinational logic gates that enable a specific output line in response to an input binary code. The memory system or data processing system can use the enabled output line to enable or "select" a specific chip or device from multiple devices connected to the memory system or data processing system. For example, if multiple memory chips (e.g., flash memory chips in a solid-state drive (SSD)) exist on the same bus, for most operations, it is not possible to communicate with all memory chips simultaneously because data entries or commands sent via the bus may be routed to all memory chips. Instead, a chip selection signal can be used to select which chip to communicate with at any given time. The chip selection decoder can manage and control data communication between multiple devices (e.g., multiple memory chips) sharing the same bus or connection line in the system by enabling a specific device based on an input selection code or signal.

[0056] According to an embodiment, the first memory device 150A may include a cache register 256, an address register 372, a status information register 374, and a command register 376. The cache register 256 may temporarily store data. When the first memory device 150A performs a read operation, the cache register 256 may store read data entries output from the cell array 330. When the first memory device 150A performs a write operation or a programming operation, the cache register 256 may store write data entries. The address register 372 may store an address indicating the location of the cell array 330 where a read or write operation will be performed. The command register 376 may store a command to be executed by the first memory device 150A. The status information register 374 may store status information, such as the result (failure / success) of an operation performed in the first memory device 150A or the ready state of the operation. For example, when the memory die in the first memory device 150A includes multiple memory planes, the status information register 374 may store status information related to each of the multiple memory planes. Data, commands, and information transmitted or received through the input / output control circuit 380 in the first memory device 150A can be controlled by the control circuit 180 (e.g., transmitted, moved, or output).

[0057] During a read operation in the first memory device 150A, the row decoder 334 and column decoder 332 can select one or more memory cells in the cell array 330 based on the address stored in the address register 372 and control signals from the control circuit 180. During the read operation, read data entries output from the cell array 330 can be stored in the data register 254 and then transferred from the data register 254 to the cache register 256. The read data entries stored in the cache register 256 are transferred to the input / output control circuit 380 via input / output lines. The read data entries transferred to the input / output control circuit 380 can be output to the controller via channels I / O [7:0] and I / O [15:0].

[0058] During a write or programming operation in the first memory device 150A, the row decoder 334 and column decoder 332 can select one or more memory cells in the cell array 330 in response to the address stored in the address register 372 and control signals from the control circuit 180. During a write operation, write data entries transferred from the controller to the input / output control circuit 380 via channels I / O [7:0] and I / O [15:0] can be stored in the cache register 256. Thereafter, the write data entries can be transferred from the cache register 256 to the data register 254. The write data entries stored in the data register 254 can be programmed by the control circuit 180 into the selected memory cells in the cell array 330.

[0059] Data register 254 and cache register 256 may be included in read / write circuitry that includes a sense amplifier, page buffer, etc. According to an embodiment, a page buffer or data latch included in the first memory device 150A may correspond to data register 254 and / or cache register 256. Furthermore, cache register 256 is configured to temporarily store data transferred between data register 254 and input / output control circuitry 380. According to an embodiment, cache register 256 may have a pipe latch structure.

[0060] A pipelined (or piped-in) system including at least one pipeline latch may include a device capable of parallelizing multiple data entries for serial input and output. According to embodiments, the pipelined system may be applied to input / output control circuitry 380 or cache register 256. Furthermore, according to embodiments, the pipelined system may be used to compensate for delays and noise occurring during data transmission due to the increased length of the data path for data transmission within the first memory device 150A of the memory system.

[0061] Figure 1 The cell array 330 shown can have a two-dimensional or three-dimensional structure. The various structures of the cell array 330 and operations for programming data or verifying programmed data in the multiple memory cells included in the cell array 330 will be described in detail below.

[0062] Figure 2 A second memory device according to an embodiment of the present disclosure is shown.

[0063] Reference Figure 2The second memory device 150B may include a cell array 330. The cell array 330 may have a two-dimensional or three-dimensional structure. The cell array 330 may include multiple memory cells capable of storing data and multiple switching transistors capable of controlling the electrical connections between bit lines, source lines, etc., and the multiple memory cells. (See below for further details.) Figures 3 to 6 Describe the structure of cell array 330.

[0064] The second memory device 150B may include control circuitry 180. Control circuitry 180 may receive a programming command PG_CMD input from an external source of the memory device. For example, the programming command PG_CMD may be transmitted from a memory controller or host operatively coupled to the second memory device 150B. The programming command PG_CMD may be used to store data in cell array 330. According to an embodiment, another command, in addition to the programming command PG_CMD, for checking the operating status of the second memory device 150B or performing operations to improve the input / output performance, lifespan, wear rate, etc., of the second memory device 150B may be transmitted to control circuitry 180.

[0065] The control circuit 180, which receives the programming command PG_CMD, can transmit the control signal CTRS to the voltage supply circuit 170. The voltage supply circuit 170 can generate at least one voltage in response to the control signal CTRS and transmit that at least one voltage to the cell array 330. For example, in response to the control signal CTRS, the voltage supply circuit 170 can generate or control the programming voltage, pass voltage, verification voltage, etc., applied to the cell array 330. For example, the control circuit 180 can determine whether to perform a programming operation or a verification operation. See below for further details. Figure 7 Examples of programming and verification operations are provided. Additionally, the control signal CTRS can vary depending on the programming mode PG_MODES. See below for further details. Figure 8 An example describing the programming mode PG_MODES.

[0066] In a write operation based on the write command PG_CMD, control circuit 180 can control voltage supply circuit 170, which generates a voltage and applies it to cell array 330. Voltage supply circuit 170 can apply voltages of various levels to cell array 330 via various lines. For example, based on the voltage applied by voltage supply circuit 170, each cell string included in cell array 330 can be selected via drain select line DSL in cell array 330. Furthermore, voltage supply circuit 170 can apply programming voltage or pass voltage via multiple word lines WL in cell array 330. Voltage supply circuit 170 can select a portion of cell array 330 for programming operations via source select line SSL, common source line (CSL), or central switch word line CSWL within cell array 330 (see [link to relevant documentation]). Figure 4 ).

[0067] Furthermore, control circuitry 180 can transfer programming data PG_DATA to page buffer 322. Page buffer 322 may include multiple latches that can temporarily store data stored or to be stored in each memory cell included in cell array 330. For example, when multiple bits of data are stored in each memory cell, each of the multiple bits of data may be stored in each of the multiple latches. According to an embodiment, based on a programming operation scheme (e.g., fuzzy-fine programming method, binary programming method, etc.), control circuitry 180 may store in page buffer 322 values ​​corresponding to data bits (e.g., LSB data, MSB data, etc.) stored in each memory cell within cell array 330.

[0068] Page buffer 322 and cell array 330 can be connected via bit line BL (see...) Figure 3 The data can be programmed into memory cells where a programming voltage is applied, based on the value stored in page buffer 322. While data is being programmed into each memory cell, control circuitry 180 can verify the data stored in the memory cells of cell array 330. When voltage supply circuitry 170 applies a verification voltage via word line during verification operation, the memory cells in cell array 330 connected to that word line can output the stored data via bit line. This verification data VER_DATA can be temporarily stored in page buffer 322. Control circuitry 180 can check the data stored in page buffer 322 to verify whether the programming data PG_DATA has been correctly stored in the corresponding memory cell. (See below for further details.) Figure 7 and Figure 8 Describe the programming and verification operations.

[0069] The data storage capacity of the second memory device 150B can be determined based on the number of bits of data stored in each memory cell and the number of memory cells included in the cell array 330. To store a larger capacity of data, the cell array 330 can include more memory cells. The cell array 330 can have a three-dimensional structure that can integrate more memory cells. Furthermore, as the number of memory cells increases, the number of memory cells connected to a single word line WL or a single bit line BL may also increase.

[0070] During programming and verification operations, the voltage supply circuit 170 applies various voltage levels, such as programming voltage, pass voltage, and verification voltage, through the word line WL. If the length of the word line WL is increased to integrate more memory cells, the voltage applied through the word line WL may be delivered at different times to a first memory cell physically closer to the voltage supply circuit 170 and a second memory cell physically farther away from the voltage supply circuit 170. This will be discussed later. Figure 9 This describes a problem caused by a delay in the voltage applied through the word line WL. Furthermore, see below. Figures 10 to 13 This describes a memory device and a method of operating the memory device to avoid problems caused by voltage delay.

[0071] Figure 3 The structure of a first cell array 330A according to an embodiment of the present disclosure is shown.

[0072] Reference Figure 3 The first unit array 330A may include multiple unit strings SG0, SG1, ..., SG7. These multiple unit strings SG0, SG1, ..., SG7 can be connected to bit lines BL. The connection between each of the multiple unit strings SG0, SG1, ..., SG7 and the bit line BL can be determined by drain selection lines DSL0, DSL1, ..., DSL7.

[0073] Among multiple unit strings SG0, SG1, ..., SG7, the first unit string SG0 may include multiple memory cells, a switching transistor connected to a first drain select line DSL0, and a switching transistor connected to a source select line SSL for controlling the connection with the source line SL. Each memory cell can store one bit of data or multiple bits of data. According to an embodiment, each switching transistor may include multiple transistors.

[0074] Multiple memory cells can be connected to multiple word lines Main_WL. A single memory cell can be connected to a single word line among the multiple word lines Main_WL. Based on bit line BL and one word line among the multiple word lines Main_WL, control circuitry 180 can select a specific memory cell in a selected string of cells within the first cell array 330A.

[0075] For example, the word line Main_WL can be connected to a memory cell included in each of multiple cell strings SG0, SG1, ..., SG7. As the number of cell strings SG0, SG1, ..., SG7 connected to the word line Main_WL increases, the data storage capacity of the first cell array 330A can increase. Due to delays (e.g., RC delay, etc.), voltages of various levels transmitted through the word line Main_WL may arrive at the first cell string SG0 and the eighth cell string SG7 at different times. As the number of cell strings SG0, SG1, ..., SG7 connected to the word line Main_WL increases, the time at which voltage is applied to the cell string closest to the voltage supply circuit 170 (e.g., the first cell string SG0) and the cell string farthest from the voltage supply circuit 170 (e.g., the eighth cell string SG7) may differ more significantly. According to embodiments of the present disclosure, a memory device and a method of operating the memory device will be described below, which can avoid or solve the problem caused by the phenomenon that the voltage is applied at different times to each of the multiple cell strings SG0, SG1, ..., SG7 connected to the word line Main_WL.

[0076] Figure 4 The structure of the second cell array 330B according to an embodiment of the present disclosure is shown.

[0077] Reference Figure 4 The second cell array 330B may have a structure including portions or layers stacked in the vertical direction D1. The second cell array 330B may include at least one memory block. Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as the first direction D1, and two directions parallel to the upper surface of the substrate and intersecting each other may be defined as the second direction D2 and the third direction D3, respectively. For example, the second direction D2 and the third direction D3 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as the vertical direction, the second direction D2 may be referred to as the row direction, and the third direction D3 may be referred to as the column direction. Directions indicated by arrows in the figure and their opposite directions are described as the same direction.

[0078] For ease of description, Figure 4 The NAND string or cell string SG1 to SGk is shown as a cell string within a memory block that is connected to a bit line BL and a common source line CSL.

[0079] A memory block may include multiple cell strings SG1 to SGk connected between the same bit line (BL) and the common source line CSL. Each of the cell strings SG1 to SGk may include at least one source select transistor SST controlled by the source select line SSL, multiple memory cells controlled by the word line WL, a central switch transistor CST disposed in the intermediate boundary layer IBL and controlled by the central switch word line CSWL, and a drain select transistor DST controlled by each drain select line DSL1, DSL2, DSL3, ..., DSLk.

[0080] According to an embodiment, a plurality of memory cells connected to at least one word line at both ends of the first stack ST1 and the second stack ST2 in the first direction D1 can be dummy cells. Dummy cells may not store any data. Furthermore, according to an embodiment, dummy cells can be used to store data with fewer bits compared to other memory cells. According to an embodiment, the intermediate boundary layer IBL may include at least one gate line. One gate line corresponds to a central switch word line CSWL, which can simultaneously control the switching operation of the central switch transistor CST connected thereto. Although Figure 4 The diagram illustrates the structure of a first stack ST1 and a second stack ST2, but three or more stacks can be stacked vertically in the second cell array 330B. When multiple stacks are stacked, an intermediate boundary layer IBL can be formed and disposed between every two stacks. The intermediate boundary layer IBL may include at least one switching transistor configured to connect a memory cell in one of the two stacks to another memory cell in the other stack.

[0081] Figure 4 An embodiment is shown in which the source select transistors SST included in multiple cell strings SG1 to SGk are connected to a common source line CSL. However, according to the embodiment, a number of source select transistors can be connected to each of multiple source-to-ground select lines.

[0082] Reference Figures 3 to 4 The first cell array 330A or the second cell array 330B may include multiple memory blocks arranged along multiple directions D1, D2, D3. In an embodiment, the memory blocks may be composed of... Figure 1 The control circuit 180 shown is used for selection. For example, read voltage, programming voltage, or erase voltage can be applied to the memory block and word line selected by the control circuit 180.

[0083] Each of the cell strings SG1 to SGk may include multiple switching transistors and multiple memory cells capable of storing data. Here, the multiple switching transistors may include a drain-select transistor (DST), a source-select transistor (SST), and a central switching transistor (CST). Figure 4 An embodiment is shown in which each of the cell strings SG1 to SGk includes a drain select transistor (DST), a source select transistor (SST), and a central switch transistor (CST). However, according to the embodiment, each of the cell strings SG1 to SGk may include multiple drain select transistors (DST), multiple source select transistors (SST), or multiple central switch transistors (CST).

[0084] Figure 5 The structure of a third cell array 330C according to an embodiment of the present disclosure is shown.

[0085] Reference Figure 4 and Figure 5 The third unit array 330C can be used as follows Figure 4 The multiple stacks ST1 and ST2 shown are stacked in the vertical direction (D1, Z), and the non-volatile memory cells can be arranged in three-dimensional (3D) space. Specifically, Figure 5 A third cell array 330C in a 3D non-volatile memory device according to an embodiment of the present disclosure is shown.

[0086] The third cell array 330C may include multiple memory cells MC in a cell string STR arranged in multiple memory layers (e.g., three memory layers L1, L2, L3). Memory layers L1, L2, L3 are connected to multiple bit lines BL1, BL2, BL3 respectively via the first ends of multiple channel lines CL, and to common source lines CSL1, CSL2, CSL3 respectively via the second ends of the multiple channel lines CL. The third cell array 330C may include multiple source select lines SSL1 to SSL4 connected to source select transistors SST1 to SST4. Additionally, multiple word lines WL1 to WLn and a ground select line GSL may be connected to each of the memory layers L1, L2, L3. The multiple source select lines SSL1 to SSL4, the multiple word lines WL1 to WLn, and the ground select line GSL may be arranged in a direction intersecting with the multiple channel lines CL. Each of the multiple channel lines can be described as a cell string STR. Each cell in the string STR may include source select transistors SST1 to SST4, which are respectively connected to multiple source select lines SSL1 to SSL4. The ground select line GSL may be grounded to turn off the ground select transistor GST.

[0087] Multiple word lines WL1 to WLn can each be connected to the control gate of a memory cell arranged in the column direction. Each of multiple bit lines BL1 to BL3 can be connected to one end of a source selection transistor. Multiple memory cells in the row direction, each with a control gate connected to a word line WL1 to WLn, can be configured as pages, where a page is a unit for storing data or data entries. The number of pages can be changed or determined based on the storage capacity of the memory cells.

[0088] Figure 6 The structure of a fourth cell array 330D according to an embodiment of the present disclosure is shown. Specifically, Figure 6 The internal configuration of the fourth unit array 330D is described.

[0089] Reference Figure 6 The fourth unit array 330D may include multiple storage blocks BLK(k+1), BLK(k), and BLK(k-1). Figure 6 Three memory blocks BLK(k+1), BLK(k), and BLK(k-1) are shown, but the fourth cell array 330D may include multiple memory blocks arranged in two or three dimensions. Figure 6 In this configuration, each memory block BLK(k+1), BLK(k), and BLK(k-1) has multiple memory cells connected to 16 word lines WL0 to WL15. The 16 word lines WL0 to WL15 and the ground select line GSL can be arranged in parallel in a direction perpendicular to the row or bit line. However, the number of word lines included in each memory block can vary depending on the embodiment. Each memory block BLK(k+1), BLK(k), and BLK(k-1) can include a cell string corresponding to each bit line. In memory block BLK(k), each cell string can be connected to a source select transistor SST(k) connected to the corresponding bit line and a ground select transistor GST(k) connected to the common source line CSL. The cell string can include 16 memory cells MC15 to MC0 connected in series between the source select transistor SST(k) and the ground select transistor GST(k). The number of memory cells included in the cell string can correspond to the number of word lines. The source select transistor SST(k), memory cells MC15 to MC0 and ground select transistor GST(k) are respectively connected to the source select line SSL(k), word lines WL15 to WL0 and ground select line GSL(k).

[0090] Reference Figures 1 to 6Since memory devices 150A and 150B are designed to store more data, the source select lines of adjacent memory blocks arranged in two or three dimensions can be electrically connected to each other. Furthermore, the ground select lines of adjacent memory blocks can be electrically connected to each other. For example, the source select line SSL(k) of memory block BLK(k) can be electrically connected to the source select line SSL(k+1) of the adjacent memory block BLK(k+1). Additionally, adjacent string / ground select transistors along the bit lines can share contacts to achieve electrical connections between adjacent string / ground select lines.

[0091] When designed to share a ground select line or cell string between adjacent memory blocks, the interference effect caused by read or write operations performed on a specific memory block may affect adjacent memory blocks (e.g., memory blocks that share a cell string but are not selected). Here, the scheme of sharing a cell string between adjacent memory blocks can include the following structures: the cell string uses electrodes or functional layers such as any region stacked on a semiconductor substrate or any semiconductor layer, or body electrodes formed in trenches in a semiconductor substrate on which the cell string is formed, to share the same components. Furthermore, when adjacent memory blocks are designed to share a ground select line or cell string, the interference effect caused by read or write operations performed on a specific memory block within the adjacent memory blocks may be greater than when the cell string is not shared by adjacent memory blocks. Depending on whether the adjacent memory blocks of memory devices 150A and 150B share a cell string, the read interference effect differs depending on whether read operations on open memory blocks are performed.

[0092] Reference Figures 1 to 6 To store more data in memory devices 150A and 150B, more memory cells can be integrated in three-dimensional space. As the number of memory cells increases, the number of various control lines connected to the memory cells (e.g., word lines, drain select lines, source select lines, etc.) also increases. With the increase in the number of control lines, each control line can be layered to improve efficiency and performance. In this document, layering can mean that memory devices 150A and 150B are designed to divide the first cell array 330A, the second cell array 330B, the third cell array 330C, or the fourth cell array 330D into predetermined regions, and that only some layered control lines are used in the divided regions.

[0093] Figure 7 The programming and verification operations according to embodiments of this disclosure are illustrated.

[0094] Reference Figure 7After performing a programming voltage application operation Pgm during incremental step pulse programming (ISPP) operation, memory devices 150A and 150B perform a verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can increase the threshold voltage VTH of the non-volatile memory cell. For example, each programming voltage application operation Pgm increases the threshold voltage VTH of the non-volatile memory cell by a first potential difference ΔV. After performing a programming voltage application operation Pgm, the threshold voltage VTH of the non-volatile memory cell can be compared with a verification voltage in the verification operation. When the threshold voltage VTH of the non-volatile memory cell is less than the verification voltage, the next programming voltage application operation Pgm can be performed again to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, in response to the corresponding programming voltage application operation Pgm, the verification operation Ver is performed. Repeated programming voltage application operations Pgm can be performed until the threshold voltage VTH of the non-volatile memory cell reaches a target voltage (e.g., the verification voltage).

[0095] According to an embodiment, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. When the threshold voltage VTH of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm, the accuracy of the programming voltage application operation can be increased. However, as the number of possible programming voltage application operations increases, the delay time and power consumption may become longer and greater. On the other hand, when the threshold voltage VTH of the non-volatile memory cell is greatly increased by each programming voltage application operation Pgm, the power consumption and operation time of the programming voltage application operation Pgm may increase. The operation time Δt of the programming voltage application operation Pgm and the verification operation Ver can vary depending on the objective of each programming voltage application operation Pgm (e.g., a change in the threshold voltage VTH).

[0096] For example, in a memory device comprising a three-level nonvolatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently depending on the purpose and process of programming data into the least significant bit (LSB), middle significant bit (CSB), and most significant bit (MSB) of the memory cell. A memory device comprising a three-level nonvolatile memory cell (TLC) has been described as an example, but the above programming operations can also be applied to memory devices comprising a four-level nonvolatile memory cell (QLC) for storing 4 bits of data or nonvolatile memory cells capable of storing 5 or more bits of data.

[0097] According to an embodiment, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased by a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same (i.e., unchanged). In the verification operation Ver for each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can vary. Furthermore, when the verification operation is performed by reflecting the noise generated according to the operating characteristics of the memory devices 150A and 150B, the memory devices 150A and 150B can change or adjust the voltage level of the verification pulse.

[0098] Figure 8 The programming operation modes according to embodiments of this disclosure are illustrated. Figure 8 In this context, a non-volatile memory cell can store a single bit (1 bit) of data. Memory devices 150A and 150B can be controlled so that the threshold voltage of the non-volatile memory cell changes to either an erase state (E) or a programming state (P). When referenced... Figure 7 When performing incremental step pulse programming (ISPP) operation, the threshold voltage of the non-volatile memory cell can change from the erase state E to the programming state P. (Refer to...) Figure 7 Verification operations can be performed after a programming pulse is applied.

[0099] Reference Figure 8 The verification operation can use two verification voltages, Vvfyp and Vvfym. Specifically, data programming operations supporting Dual Verification Programming (DPGM) can be performed using two verification voltages at different levels during the verification operation. By utilizing two different verification voltage levels, the degree to which a non-volatile memory cell is programmed in response to the next programming pulse can be adjusted. For example, memory devices 150A and 150B can determine the amount of change in the threshold voltage that may be caused by the next programming pulse.

[0100] According to an embodiment, the verification voltage may include a pre-verification voltage Vvfyp and a main verification voltage Vvfym. Here, the main verification voltage Vvfym may be a verification voltage corresponding to the target state of the data programming operation, and the pre-verification voltage Vvfyp has a lower level than the main verification voltage Vvfym. In the verification operation, the pre-verification voltage Vvfyp can be used to check the extent to which a data programming operation has been performed on the non-volatile memory cell. When the verification operation using the main verification voltage Vvfym detects that the threshold voltage of the non-volatile memory cell has changed to a programming state P, the non-volatile memory cell does not need to be further programmed by the next programming pulse. Moreover, when the threshold voltage of the non-volatile memory cell is less than the pre-verification voltage Vvfyp, the non-volatile memory cell can be programmed by the next programming pulse. If the threshold voltage of a non-volatile memory cell is within the range between the pre-verification voltage Vvfyp and the main verification voltage Vvfym, the non-volatile memory cell may be overprogrammed when normally programmed with the next programming pulse (e.g., the threshold voltage of the non-volatile memory cell may rise too much, i.e., overprogramming). Therefore, memory devices 150A and 150B can reduce the amount of threshold voltage change. In this case, memory devices 150A and 150B can control or adjust the degree to which the non-volatile memory cell is programmed (e.g., the amount of threshold voltage change) when the next programming pulse is applied.

[0101] Reference Figure 8When multiple non-volatile memory cells are programmed via programming pulses and then verified using a pre-verification voltage Vvfyp and a main verification voltage Vvfym, the multiple non-volatile memory cells may be in three different states MC1, MC2, and MC3. For a non-volatile memory cell in the first state MC1 with a voltage lower than the pre-verification voltage Vvfyp, memory devices 150A and 150B can apply the next programming pulse to cause a change in the threshold voltage of the corresponding memory cell by an amount or change corresponding to the next programming pulse. This general programming mode (PGM Mode) can be referred to as the first programming mode. On the other hand, if a non-volatile memory cell has a third state MC3 with a voltage higher than the main verification voltage Vvfym, memory devices 150A and 150B prevent the non-volatile memory cell from being further programmed via the next programming pulse because the threshold voltage of the non-volatile memory cell has already reached the programming state P. In this document, prohibiting the further programming of non-volatile memory cells can be referred to as the programming prohibition mode. Furthermore, when the non-volatile memory cell is in the second state MC2, the threshold voltage of the non-volatile memory cell may rise too much when it is programmed in the first programming mode (PGM Mode). Therefore, when the next programming pulse is applied to the non-volatile memory cell in the second programming mode (DPGM Mode), the change in threshold voltage can be less than that caused in the first programming mode (PGM Mode).

[0102] The degree to which a non-volatile memory cell is programmed (e.g., the amount of change in threshold voltage) can be determined based on the timing of the applied programming pulse, the number of programming pulses applied, and the potential difference between the programming pulses. Although a single programming pulse is applied to multiple non-volatile memory cells connected to a single word line, memory devices 150A and 150B can change or adjust the amount of threshold voltage change for each of the non-volatile memory cells connected to the single word line. To change the threshold voltage of the multiple non-volatile memory cells by different amounts, memory devices 150A and 150B can change or adjust the potential of the bit lines connected to the individual non-volatile memory cells connected to the single word line.

[0103] For example, during the period when a programming pulse is applied to the word line, a ground voltage is applied to the first bit line, a programming adjustment voltage greater than the ground voltage is applied to the second bit line, and a programming disable voltage greater than the programming adjustment voltage is applied to the third bit line. The first bit line is connected to a first memory cell with a threshold voltage in a first state MC1, the second bit line is connected to a second memory cell with a threshold voltage in a second state MC2, and the third bit line is connected to a third memory cell with a third state MC3. In this case, there is a potential difference between the word line and each of the first to third bit lines. Since the potential difference between the word line and the bit line connected to the non-volatile memory cell is small, the change in the threshold voltage of the non-volatile memory cell caused by the programming pulse can be small. Furthermore, when the potential difference between the word line and the bit line is less than a preset level, the non-volatile memory cell will not be programmed. Because the potential difference of the second memory cell with the second state MC2 is less than the potential difference of the first memory cell with the first state MC1, the degree to which the second memory cell is programmed by the next programming pulse can be less than the degree to which the first memory cell is programmed. Furthermore, when the next programming pulse is applied to the third memory cell and the potential difference between the programming pulse and the programming inhibit voltage applied to the third memory cell with the third state MC3 is less than a preset level, the third memory cell with the third state MC3 may not be further programmed despite the presence of the next programming pulse.

[0104] Reference Figure 8 The programming mode can be determined based on the verification result corresponding to the programming operation performed on the non-volatile memory cell. The programming mode can include a first programming mode (PGM Mode), a second programming mode (DPGM Mode), and a third programming mode (PGM Inhibit Mode). For example, a successful verification can indicate that the non-volatile memory cell is read as a cutoff cell in response to the verification voltage. A failed verification can indicate that the non-volatile memory cell is read as a conducting cell in response to the verification voltage. If the threshold voltage of the non-volatile memory cell is less than the verification voltage, the non-volatile memory cell is read as a conducting cell. However, if the threshold voltage is greater than or equal to the verification voltage, the non-volatile memory cell is read as a cutoff cell.

[0105] Reference Figure 8In the first programming mode (PGM Mode), a non-volatile memory cell can be read as an active cell by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. In the second programming mode (DPGM Mode), another non-volatile memory cell can be read as a deactivated cell by the pre-verification voltage Vvfyp and as an active cell by the main verification voltage Vvfym. In the third programming mode (PGM Inhibit Mode), another non-volatile memory cell can be read as a deactivated cell by both the pre-verification voltage Vvfyp and the main verification voltage Vvfym. Furthermore, because the level of the pre-verification voltage Vvfyp is lower than the level of the main verification voltage Vvfym, there is no situation where a non-volatile memory cell is read as an active cell by the pre-verification voltage Vvfyp and as a deactivated cell by the main verification voltage Vvfym.

[0106] Figure 9 The delays associated with voltages or signals applied to the cell array are shown according to embodiments of the present disclosure.

[0107] Reference Figure 9 Multiple bit lines BL can be arranged in the direction (BL direction) intersecting with the word lines (WL direction). This paper describes how to transmit voltage or signals through a selected word line SEL_WL among multiple word lines.

[0108] Figure 2 The voltage supply circuit 170 described herein can apply a programming pulse (PGM Pulse) to the selected word line SEL_WL. A logic high-level control signal can be applied to the gate of a switching element connecting the voltage supply circuit 170 and the selected word line SEL_WL. When the switching element is turned on, current can flow to the selected word line SEL_WL.

[0109] The programming voltage or programming pulse (PGM Pulse) can have a very high voltage level. For example, the programming pulse (PGM Pulse) can have a higher voltage level than the pass voltage. As the number of memory cells connected to the selected word line SEL_WL increases, the length of the selected word line SEL_WL may become longer. Multiple memory cells can be arranged in the selected word line SEL_WL between the region closest to the voltage supply circuit 170 or the switching element (e.g., near local word line, Near LWL) and the region farthest from the voltage supply circuit 170 or the switching element. Multiple memory cells can be interpreted as components with capacitance. The selected word line SEL_WL may include conductive material. However, the selected word line SEL_WL may have a resistive value. For this reason, a delay (e.g., RC delay) may occur during the transmission of the programming pulse (PGM Pulse) from the near region (Near LWL) to the far region (Far LWL) in the selected word line SEL_WL. Here, delay (e.g., RCDelay) can be estimated or calculated as a value obtained by multiplying the resistance (R) value and the capacitance (C) value. Delay (e.g., RCDelay) can represent the signal or voltage delay of the electrical signal transmission speed. When a voltage level transition occurs, such as a programming voltage or programming pulse (PGMPulse), a delay (e.g., RC Delay) may occur due to the charging or discharging speed of the selected word line SEL_WL.

[0110] Due to delays occurring within the selected word line SEL_WL, the slope of the programming pulse in the Near LWL and the slope of the programming pulse in the Far LWL may differ. This difference in slope can result in different effective durations of the programming pulse (PGM Pulse). For example, when comparing a first memory cell located in the Near LWL with a second memory cell located in the Far LWL, the effective duration of the programming pulse applied to the first memory cell may be longer than that applied to the second memory cell. This means that even if the same programming pulse is applied to the selected word line SEL_WL, the data programmed into the memory cell may differ depending on the location of the memory cell.

[0111] Figure 10 A first programming operation according to an embodiment of this disclosure is shown.

[0112] Reference Figure 10During the first programming operation, a voltage VPASS can be applied to the selected word line SELWL, the word line adjacent to the selected word line SELWL (N+-1 WL), and the unselected word line (Unsel WL). For example, when the row address of the selected word line SELWL is "3", the row address of the word line adjacent to the selected word line SELWL (N+-1 WL) can be "2" or "4". According to an embodiment, the selected word line SELWL and the adjacent word line (N+-1 WL) can be set differently. Furthermore, because as... Figures 3 to 6 As described, the cell array structure can be different, so the selected word line SELWL and adjacent word lines (N+-1 WL) can be determined according to the cell array structure.

[0113] When a programming voltage or programming pulse is applied to the selected word line SELWL, the potential of the selected word line SELWL can rise from the voltage level of the through voltage VPASS to the voltage level of the programming voltage or programming pulse (VPASS rising segment).

[0114] Subsequently, after the first timing T1, the voltage level applied to the adjacent word line (N+-1WL) adjacent to the selected word line SELWL can be increased to a preset level. For example, a first voltage with a higher preset level than the pass voltage can be applied to the adjacent word line (N+-1WL). At this time, the voltage level applied to the unselected word line (UnselWL) can remain unchanged.

[0115] Subsequently, during the second timing T2, a first voltage, which rises from a preset level through the voltage, can be applied to the adjacent word line (N+-1 WL) adjacent to the selected word line SELWL.

[0116] like Figure 9 As described, in order to compensate for the shortening of the effective period (e.g., second timing T2) of the programming pulse in the memory cell located in the region (Far LWL) farthest from the voltage supply circuit 170 or switching element in the selected word line SELWL during the first programming operation, the voltage level applied to the adjacent word line (N+-1 WL) adjacent to the selected word line SELWL can be increased by a preset level through the voltage VPASS. When the voltage level applied to the adjacent word line (N+-1 WL) adjacent to the selected word line SELWL is increased by the preset level, the slope of the programming pulse in the farthest region (Far LWL) can be improved due to coupling. In this way, the reduction in the effective period (e.g., second timing T2) of the programming pulse in the second memory cell located in the region (Far LWL) farthest from the voltage supply circuit 170 or switching element in the selected word line SELWL can be reduced.

[0117] However, in the first programming operation, if the voltage level applied to the adjacent word line (N+-1WL) adjacent to the selected word line SELWL is increased by a preset level, then not only in the second memory cell located in the region (Far LWL) of the selected word line SELWL that is farthest from the voltage supply circuit 170 or the switching element, but also in the first memory cell located in the region (Near LWL), effects due to coupling may occur. Therefore, the effect of improving the delay occurring in the region (Far LWL) of the selected word line SELWL that is farthest from the voltage supply circuit 170 or the switching element may be reduced.

[0118] Figure 11 A second programming operation according to an embodiment of this disclosure is shown.

[0119] Reference Figure 11 Compared to the first programming operation, the second programming operation performed in memory devices 150A and 150B can be applied to a wider area of ​​the selected word line SELWL and adjacent word lines (N+-1 WL, N+-2 WL).

[0120] The method of applying voltage VPASS and programming voltage or programming pulse to the selected word line SELWL and the unselected word line (Unsel WL) during the second programming operation can be the same as in the first programming operation. Furthermore, the method of controlling the voltage applied to the first adjacent word line (N+-1 WL) during the second programming operation can also be substantially the same as in the first programming operation.

[0121] Compared to the first programming operation, the second programming operation may further include controlling the voltage applied to the second adjacent word line (N+-2 WL). For example, when the row address of the selected word line SELWL is "3", the row address of the first adjacent word line (N+-1 WL) can be "2" or "4", and the row address of the second adjacent word line (N+-2 WL) can be "1" or "5". The second programming operation can include a driving scheme through the first adjacent word line (N+-1 WL) by additionally controlling the second adjacent word line (N+-2 WL), such that the second programming operation can improve the slope of the programming pulse in the farthest region (Far LWL).

[0122] In the second programming operation, after applying the pass voltage and before applying the programming voltage or programming pulse to the selected word line SELWL (VPASS rising segment), a first voltage with a level greater than a preset level than the pass voltage can be applied to the second adjacent word line (N+-2 WL). Thereafter, during the first timing T1 and the second timing T2, the first adjacent word line (N+-1 WL) and the second adjacent word line (N+-2 WL) can be driven or controlled in the same manner.

[0123] The second programming operation may include applying a first voltage with a higher level than the voltage applied to the first adjacent word line (N+-1 WL) to the second adjacent word line (N+-2 WL), and then applying a voltage of the same level to both the first adjacent word line (N+-1 WL) and the second adjacent word line (N+-2 WL). When a programming voltage or programming pulse is applied to the selected word line SELWL, the coupling between the selected word line SELWL and the first adjacent word line (N+-1 WL) can be reduced, thereby reducing the potential increase of the first adjacent word line (N+-1 WL). For example, by lowering the potential of the second adjacent word line (N+-2 WL) during the first timing T1, the potential of the first adjacent word line (N+-1 WL) that has risen or been driven due to coupling with the selected word line SELWL can be reduced.

[0124] During the second timing T2, the second programming operation may include increasing not only the voltage level applied to the first adjacent word line (N+-1WL), but also the voltage level applied to the second adjacent word line (N+-2WL). In this case, based on the coupling phenomenon, the slope of the programming pulse in the farthest region (Far LWL) of the selected word line SELWL can be improved (e.g., the slope becomes steeper or sharper).

[0125] Figure 12 A third programming operation according to an embodiment of this disclosure is illustrated. Figure 12 In this context, the third programming operation can be included in Figure 8 The operation in the first programming mode (PGM Mode) and the operation in the second programming mode (DPGM Mode) described herein, wherein the first programming mode causes a threshold voltage change at a preset level, and the second programming mode causes a smaller threshold voltage change compared to the first programming mode (PGM Mode).

[0126] Reference Figure 12 The third programming operation may include controlling the voltage on a selected word line (VSELWL) among multiple word lines and controlling the voltage on a selected drain select line (SELDSL) among multiple drain select lines. See reference. Figures 3 to 6 The drain select line can select a cell string from multiple cell strings, while the word line can specify the memory cell for programming data within the selected cell string. The third programming operation may include enabling the selected drain select line (SEL DSL) before applying a programming pulse (e.g., before the first time point t0), applying a pass voltage to the selected word line (Pass Rising), and applying a programming voltage or programming pulse (Pulse Rising) at the first time point t0. At the third time point t2, the voltage level of the selected word line (VSELWL) can be reduced to 0V. After the voltage level of the selected word line (VSELWL) drops to 0V, the selected drain select line (SEL DSL) can be deactivated.

[0127] Return to reference Figure 8 At least some of the selected memory cells can be programmed with data in a first programming mode (PGM Mode), and at least some of the selected memory cells can be programmed with data in a second programming mode (DPGM Mode). When a programming voltage or programming pulse is applied (e.g., from t0 to t2), the first programming mode (PGM Mode) or the second programming mode (DPGM Mode) can be determined based on the potential difference of the cell string. For example, the bit line BL connected to a memory cell programmed in the first programming mode (PGM Mode) can be maintained at 0V, while another line BL connected to a memory cell programmed in the second programming mode (DPGM Mode) can be maintained at a potential greater than 0V by a preset level. The potential of the bit line BL can be transferred to the cell string selected by the selected drain select line (SEL DSL), such that the channel of the selected cell string (e.g., SEL String Channel) can have a substantially similar potential to the bit line. The cell string corresponding to an unselected drain select line among the multiple drain select lines becomes floating, so that data cannot be programmed into the memory cells included in the corresponding cell string.

[0128] The third programming operation may include enabling the drain select line for stringing programmable data cells when a programming voltage or programming pulse is applied (e.g., from t0 to t2). The memory device may control the programming mode via the bit line BL (e.g., PGM0V or DPGM #V, #V being greater than 0V) and apply a high-level programming voltage or programming pulse to the selected word line. During this process, the effective duration of the programming voltage or programming pulse (e.g., Effective tNET) may vary due to the delay (e.g., RC Delay) between the nearest and farthest regions selected by the selected word line (SELWL). For example, in the nearest region, the effective duration of the programming voltage or programming pulse (Effective tNET) may be ensured from the second time point t1 to the third time point t2, while in the farthest region, the programming voltage or programming pulse may be rising at the second time point t1. Therefore, in the farthest region, the effective duration of the programming voltage or programming pulse (Effective tNET) may be reduced. The third programming operation may present difficulties in addressing the problem of shortened effective time tNET of programming pulses in memory cells located in the region (Far) furthest from the voltage supply circuit 170 or the switching element used to connect the selected word line (SELWL) to the voltage supply circuit 170.

[0129] Figure 13 A fourth programming operation is shown according to an embodiment of this disclosure.

[0130] Reference Figure 12 and Figure 13 For controlling the potential of a selected word line (VSELWL) among multiple word lines, the third and fourth programming operations can include the same scheme. Furthermore, for controlling the potential difference of bit line BL in the first programming mode (PGM Mode) and the second programming mode (DPGM Mode) when a programming voltage or programming pulse is applied (e.g., from t0 to t2), the third and fourth programming operations can have the same scheme.

[0131] For the fourth programming operation, which controls the selection of one of multiple drain select lines (SEL DSL), the fourth programming operation can include different schemes compared to the third programming operation. Because the control of the selected drain select line (SEL DSL) among the multiple drain select lines is changed, the potential of the channel of the selected cell string can be changed.

[0132] The fourth programming operation may include deactivating the selected drain select line (SEL DSL) (e.g., DSL off) at a first time point t0 when a programming voltage or programming pulse is applied. When the selected drain select line (SEL DSL) becomes 0V at the first time point t0, the channel of the selected cell string (SEL String Channel) can be floated (i.e., become floating), allowing the potential to rise. Subsequently, the selected drain select line (SEL DSL) is re-enabled at a second time point t1. Here, the second time point t1 may indicate the time point at which the potential of the selected word line (VSELWL) in the region furthest from the voltage supply circuit 170 or the switching element (Far) can sufficiently increase to the target level. The fourth programming operation ensures that the period from the second time point t1 to the third time point t2 is the effective time period (Effective tNET) of the programming voltage or programming pulse.

[0133] When the selected drain select line (SEL DSL) is deactivated from the first time point t0 to the second time point t1 and the channel of the selected cell string is floating, a potential difference (PGM Potential) for programming operations may not form between the selected word line (SELWL) and the channel of the selected cell string. When multiple cell strings connected to the selected word line are floating, the difference in the effective time of the programming voltage or programming pulse between the nearest and farthest regions due to delays (e.g., RC delay) in the selected word line (SELWL) can be avoided or reduced. For example, if the programming voltage or programming pulse rises sufficiently for the first memory cell located in the nearest region corresponding to the selected word line (SELWL) before the second time point t1, data cannot be programmed into the first memory cell because the selected drain select line (SEL DSL) is deactivated.

[0134] After a sufficiently increased programming voltage or programming pulse is applied to both the first memory cell located in the region closest to the voltage supply circuit 170 or the switching element (Near) and the second memory cell located in the region farthest from the voltage supply circuit 170 or the switching element (Far) (e.g., after the second time point t1), the selected drain selection line (SEL DSL) can be enabled. Therefore, the effective time period (Effective tNET) of the programming voltage or programming pulse for both the first and second memory cells can be substantially the same.

[0135] Reference Figure 7 and Figure 13When there is no significant difference in the effective time period (tNET) of the programming pulse or the operation time (Δt) of the programming operation (Pgm) and the verification operation (Ver) between the region closest to the voltage supply circuit 170 or the switching element (Near) and the region farthest from the voltage supply circuit 170 or the switching element, the accuracy or efficiency of the programming and verification operations of the memory device can be improved. For example, if the programming voltage or the effective time period (tNET) of the programming pulse is substantially the same, then under the same programming mode, the data programmed into the first memory cell and the second memory cell (e.g., the range of the threshold voltage to be changed) can be substantially the same. When the difference between the first memory cell located in the region closest to the voltage supply circuit 170 or the switching element (Near) and the second memory cell located in the region farthest from the voltage supply circuit 170 or the switching element (Far) decreases, the accuracy of the programming and verification operations can be improved, thereby improving the operating efficiency of the memory device.

[0136] According to an embodiment, even when the selected drain selection line (SELDSL) is deactivated from the first time point t0 to the second time point t1, the channel of the selected cell string (SELString Channel) is floating, and the potential of the channel of the selected cell string (SELString Channel) can also change in response to the change in the potential of the bit line BL applied based on the first programming mode (PGM Mode) or the second programming mode (DPGM Mode).

[0137] According to an embodiment, the second time point t1 affecting the effective period (Effective tNET) of the programming voltage or programming pulse can be determined by simulation or testing during the design or manufacturing process. Furthermore, because it may be difficult to measure by simulation or testing the exact time at which a sufficiently increased programming voltage or programming pulse applied to the second memory cell located in the farthest region (Far) can be applied, the memory device can store multiple optional timing options for enabling or disabling the selected drain select line (SEL DSL). For example, the memory device can perform programming and verification operations based on multiple optional timing options, and select a preferred timing option corresponding to the operating state of the memory device based on the results of the programming and verification operations (e.g., success or failure of the operation and the time spent on the operation).

[0138] The memory device according to embodiments of this disclosure can determine or adjust the effective time period (tNET) of the programming voltage or programming pulse by controlling the enabling and disabling of the drain select line (SEL DSL) during at least a portion of the region where the programming voltage or programming pulse is applied. This reduces potential discrepancies or imbalances caused by delays in the programming voltage or programming pulse applied to a first memory cell located in the region closest to the voltage supply circuit 170 or switching element and a second memory cell located in the region farthest from the voltage supply circuit 170 or switching element. Because the accuracy and efficiency of programming and verification operations are improved, the time spent on programming and verification operations can be reduced.

[0139] As described above, according to embodiments of the present disclosure, a memory device or memory system can use a cell string selection signal to reduce or avoid problems caused by delays resulting from different distances from a voltage supply device capable of applying at least one voltage through a word line to each location of a plurality of memory cells connected to the word line, thereby improving the reliability or accuracy of programming and verification operations performed within the memory device or memory system.

[0140] According to embodiments of this disclosure, when a programming voltage or programming pulse is applied for programming data, the voltage level applied through selected word lines and adjacent word lines connected to the memory cells can be increased by a preset level, thereby reducing or eliminating problems caused by delays due to the different distances from the voltage supply device capable of applying the voltage to each location of the plurality of memory cells connected to the word lines. The coupling effect from this scheme can improve the reliability or accuracy of programming and verification operations performed within the memory device or memory system.

[0141] Furthermore, the memory device or memory system according to embodiments of this disclosure can substantially balance and clearly set the time for programming and verification operations performed based on voltages applied to multiple memory cells, thereby improving the accuracy and efficiency of programming and verification operations and reducing the resources spent on programming operations performed within the memory device or memory system.

[0142] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be an element described herein, or an element other than one described herein. Because the algorithms underlying the methods or operations of the computer, processor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0143] Alternatively, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be volatile or non-volatile memory or other storage devices that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device that will execute code or instructions for performing the operations of the method or device embodiments described herein.

[0144] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features disclosed in the embodiments herein can be implemented, for example, with non-transient logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features can be, for example, any of various integrated circuits including, but not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

[0145] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be elements described herein, or elements other than those described herein. Because the algorithms that form the basis of the methods or operations of the computer, processor, microprocessor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0146] While embodiments of the present disclosure have been shown and described with reference to specific examples, it will be apparent to those skilled in the art, based on the disclosure, that various changes and modifications can be made to the embodiments without departing from the spirit and scope of the disclosure. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory device, comprising: A cell array, comprising multiple cell strings connected to word lines and drain select lines; as well as Control circuit: During the programming period, a programming voltage is applied to the word line, and The drain selection line is controlled to prevent data from being programmed into the multiple memory cells included in the multiple cell strings during a portion of the programming period.

2. The memory device according to claim 1, wherein, The duration includes the delay time during which the programming voltage reaches the second unit string furthest from the control circuit after being applied through the word line.

3. The memory device according to claim 1, wherein, The plurality of unit strings include a first unit string that is closest to the control circuit and a second unit string that is farthest from the control circuit, and the effective time period for programming the data in the first unit string and the effective time period for programming the data in the second unit string are equal to each other.

4. The memory device according to claim 3, wherein, Each valid time period is 50% or less of the programmed time period.

5. The memory device according to claim 1, wherein, The control circuit disables the drain selection line during the specified duration.

6. The memory device according to claim 1, wherein, The duration of the portion is determined based on the number of the plurality of unit strings connected to the word line.

7. The memory device according to claim 1, wherein, The programming voltage has a higher voltage level than the pass voltage, which is applied to other word lines adjacent to the word line. The control circuit applies the programming voltage to the word line after applying the pass voltage to the other word lines.

8. The memory device according to claim 7, wherein, The control circuit disables the drain selection line when the through voltage is applied.

9. The memory device according to claim 1, wherein, The control circuit controls the drain selection line to avoid verifying the data programmed into the plurality of memory cells during a portion of the verification period, during which a verification voltage is applied to the word line.

10. A method of operating a memory device, the method comprising: During the programming period, programming voltage is applied to multiple memory cells via word lines; as well as The drain selection line is controlled to prevent data from being programmed into the plurality of memory cells, which are included in a plurality of cell strings, during a portion of the programming period.

11. The method according to claim 10, wherein, The plurality of unit strings include a first unit string that is closest to the control circuit and a second unit string that is farthest from the control circuit, and the effective time period for programming the data in the first unit string and the effective time period for programming the data in the second unit string are equal to each other.

12. The method according to claim 10, wherein, The duration of the portion is determined based on the number of the plurality of unit strings connected to the word line.

13. The method according to claim 10, wherein, Controlling the drain selection line includes: During the specified duration, the drain selection line is deactivated.

14. The method of claim 10, wherein, Applying the programming voltage includes: A pass voltage is applied to multiple word lines, and the drain select line is deactivated while the pass voltage is applied; and The programming voltage is applied to the word line selected from the plurality of word lines.

15. The method of claim 10, further comprising: Apply a verification voltage to the word line; as well as The drain selection line is controlled to avoid verifying the data in the plurality of memory cells included in the plurality of cell strings during a portion of the verification period, during which the verification voltage is applied to the word line.

16. A memory device, comprising: Multiple drain selection lines are connected to each of the multiple cell strings; At least one word line connects to the plurality of unit strings; as well as Control circuit: During the programming period, a programming voltage is applied to the word line, and The multiple drain selection lines are controlled to prevent data from being programmed into the multiple memory cells included in the multiple cell strings during a portion of the programming period.

17. The memory device according to claim 16, wherein, The plurality of unit strings include a first unit string that is closest to the control circuit and a second unit string that is farthest from the control circuit, and the effective time period for programming the data in the first unit string and the effective time period for programming the data in the second unit string are equal to each other.

18. The memory device according to claim 17, wherein, The duration of the portion is determined based on the number of the plurality of unit strings connected to the word line.

19. A memory device, comprising: Multiple word lines connect to multiple unit strings; as well as The control circuit selects a word line from the plurality of word lines and applies a first voltage to at least one adjacent word line adjacent to the word line before applying a programming voltage to the word line, the first voltage having a higher level than the pass voltage.

20. The memory device according to claim 19, wherein, The at least one adjacent character line includes a first character line and a second character line, wherein the second character line is closer to the character line than the first character line, and The control circuit includes: The pass voltage is applied to the second word line during a preset time period before the programming voltage is applied to the word line and after the programming voltage is applied to the word line; Before applying the programming voltage to the word line, the first voltage is applied to the first word line; and During the preset time period, the voltage is applied to the first word line.

Images