Flash memory device and erase method thereof

Abstract

The present application provides a flash memory device and an erase method thereof. The erase method includes the following steps: applying an erase voltage to a target memory block in a memory block; performing a first erase verification on the target memory block using a first erase verification voltage; in a case where there is a group of memory cells in the target memory block that fails the first erase verification, performing a second erase verification on the target memory block using a second erase verification voltage that is higher than the first erase verification voltage; and setting a first erase flag and a second erase flag corresponding to each group of memory cells in the target memory block according to the verification results of the first erase verification and the second erase verification, so as to classify each group of memory cells and adjust the increase amount of the erase voltage.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a flash memory device and its erasure method. Background Technology

[0002] Flash memory devices can perform write, erase, and read operations, with the erase operation taking the longest. Therefore, the time required for the erase operation largely determines the performance of the flash memory device. If the erase verification fails after multiple applications of erase voltage, the erase voltage will be increased to reduce the erase operation time. However, the erase speed of each memory cell within a memory block is not uniform. Even if only one memory cell in a memory block fails the erase verification, an erase voltage will still be applied to the entire memory block, leading not only to an increase in erase time but also to an increase in leakage current. Summary of the Invention

[0003] The present invention provides a flash memory device and an erasing method thereof, which can dynamically adjust the increase in erasing voltage and the range of applied erasing voltage to improve the overall efficiency of the erasing operation.

[0004] The erasure method of the present invention is applicable to flash memory devices comprising multiple memory blocks. Each memory block is divided into multiple memory cell groups. The erasure method for the flash memory device includes the following steps: applying an erasure voltage to a target memory block within the memory block; performing a first erasure verification on the target memory block using a first erasure verification voltage; performing a second erasure verification on the target memory block using a second erasure verification voltage higher than the first erasure verification voltage if there are memory cell groups in the target memory block that have failed the first erasure verification; and setting a first erasure flag and a second erasure flag corresponding to each memory cell group in the target memory block based on the verification results of the first and second erasure verifications, so as to classify each memory cell group and adjust the increase in the erasure voltage accordingly.

[0005] The flash memory device of the present invention includes a memory array, a flag register, and a control circuit. The memory array has multiple memory blocks, each memory block being divided into multiple memory cell groups. The flag register is configured to store a first erase flag and a second erase flag corresponding to each memory cell group. The control circuit is coupled to the memory array and the flag register and is configured to perform an erase operation on a target memory block within the memory blocks. The control circuit applies an erase voltage to the target memory block and performs a first erase verification using a first erase verification voltage. If there are memory cell groups in the target memory block that fail the first erase verification, the control circuit performs a second erase verification using a second erase verification voltage higher than the first erase verification voltage, and sets the first erase flag and the second erase flag corresponding to each memory cell group in the target memory block based on the verification results of the first and second erase verifications, thereby classifying each memory cell group and adjusting the increase in the erase voltage accordingly.

[0006] Based on the above, the flash memory device and erasure method of the present invention can dynamically adjust the increase in erasure voltage and the range of the applied erasure voltage according to the type of memory cell group that has not yet passed the erasure verification. In this way, not only can the erasure time spent on the erasure operation be reduced, but the increase in leakage current can also be avoided, thereby improving the overall efficiency of the erasure operation.

[0007] To make the above-mentioned features and advantages of this case more apparent and understandable, specific embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 A schematic diagram of a flash memory device according to an embodiment of the present invention is shown;

[0009] Figure 2A and Figure 2B A flowchart illustrating the steps of an erasing method for a flash memory device according to an embodiment of the present invention is shown.

[0010] Figure 3A and Figure 3B A flowchart illustrating the steps of an erasing method for a flash memory device according to an embodiment of the present invention is shown.

[0011] Figures 4A to 4C A flowchart illustrating the steps of an erasing method for a flash memory device according to an embodiment of the present invention is shown. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0013] Please refer to Figure 1 One embodiment of the present invention provides a flash memory device 100, for example, of the inverse OR (NOR) type, including a memory array 110, a flag register 120, and control circuitry 130. The memory array 110 has multiple memory blocks 112. Each memory block 112 can be divided into multiple memory cell groups 114. Each memory cell group 114 includes multiple memory cells, for example, a memory tunneling oxide (ETOX) structure. Each memory block 112 includes, for example, 16 sectors (i.e., 64 KB) of memory cells, but the present invention does not limit the number of memory blocks 112, memory cell groups 114, and memory cells.

[0014] Flag register 120 is used to store erase flags F1 and F2 corresponding to each memory cell group 114. The initial values ​​of erase flags F1 and F2 corresponding to each memory cell group 114 are second logic values ​​(e.g., logic 0). Furthermore, although... Figure 1 The flag register 120 is shown to be independent of the memory array 110 and the control circuit 130, but the flag register 120 can also be integrated into the memory array 110 or the control circuit 130.

[0015] Control circuitry 130 is coupled to memory array 110 and flag register 120. Control circuitry 130 can select a target memory block 112T from multiple memory blocks 112 within memory array 110 according to a received erase command ECM, and perform an erase operation on the target memory block 112T. Control circuitry 130 can be, for example, a state machine, central processing unit, or other programmable general-purpose or special-purpose microprocessor, digital signal processor, programmable controller, application-specific integrated circuit, programmable logic device, or other similar device or combination thereof. It can also be a hardware circuit designed using a hardware description language or any other known digital circuit design method, and implemented using a field-programmable gate array or complex programmable logic device.

[0016] Please refer to the following at the same time Figure 1 and Figure 2A The erasure method in this embodiment is applicable to Figure 1 The following describes the various steps of the erasure method according to an embodiment of the present invention in conjunction with the components of the flash memory device 100. First, in step S200, the control circuit 130 applies an erasure voltage Vers to the target memory block 112T. The initial value of the erasure voltage Vers is, for example, approximately 15 volts.

[0017] Next, in step S202, the control circuit 130 uses the first erase verification voltage EV0 to perform a first erase verification on the target memory block 112T. Specifically, due to the limited number of sensing amplifiers, the control circuit 130 can only obtain the threshold voltage of multiple memory cells (e.g., 16-byte memory cells) addressed by access addresses in a selected memory cell group (one of the memory cell groups 114) of the target memory block 112T at a time, and compares the threshold voltage with the first erase verification voltage EV0. If the threshold voltage is less than the first erase verification voltage EV0, it indicates that the corresponding memory cell has passed the first erase verification (erasure successful). If the threshold voltage is not less than the first erase verification voltage EV0, it indicates that the corresponding memory cell has not passed the first erase verification (erasure failed).

[0018] Furthermore, detailed instructions on using the first erase verification voltage EV0 to perform the first erase verification on the target memory block 112T can be found in [reference needed]. Figure 2B The various steps in the process. First, in step S210, the control circuit 130 uses the first erase verification voltage EV0 to determine whether the selected memory cell group in the target memory block 112T has passed the first erase verification. For example... Figure 2B As shown, step S210 includes steps S211, S212, and S213. In step S211, the control circuit 130 uses the first erase verification voltage EV0 to determine whether multiple memory cells addressed by access addresses in the selected memory cell group of the target memory block 112T have passed the first erase verification. When the addressed memory cell fails the first erase verification, in step S214, the control circuit 130 determines that the target memory block 112T has failed the first erase verification. Incidentally, when performing an erase operation on the target memory block 112T, the selected memory cell group is initially, for example, the first memory cell group 114 in the target memory block 112T, and the initial value of the access address corresponds, for example, to the initial address of the first memory cell group 114.

[0019] When the addressed memory cell passes the first erase verification, in step S212, the control circuit 130 determines whether the current access address corresponds to the last address of the selected memory cell group. If not, in step S213, the control circuit 130 increases the access address to address multiple consecutive memory cells in the selected memory cell group, and returns to step S211 to continue the first erase verification.

[0020] If the current access address corresponds to the last address of the selected memory cell group, then in step S215, the control circuit 130 determines that the selected memory cell group has passed the first erase verification. Next, in step S216, the control circuit 130 determines whether the selected memory cell group is the last memory cell group 114 in the target memory block 112T. If not, then in step S217, the control circuit 130 selects the next memory cell group 114 in the target memory block 112T as the selected memory cell group, and returns to step S211 to continue the first erase verification.

[0021] If the selected storage cell group is the last storage cell group 114 in the target memory block 112T, then in step S218, the control circuit 130 determines that the target memory block 112T has passed the first erase verification.

[0022] It should be noted that, in this embodiment, each time the first erase verification is performed on the target memory block 112T, the first erase verification is performed on multiple memory cells addressed by the current access address. Since the access address will increase when the addressed memory cell passes the first erase verification, the first erase verification will not be performed again on the memory cell that has passed the first erase verification.

[0023] Please return Figure 2A In step S204, if there is a group of memory cells 114 in the target memory block 112T that failed the first erase verification (i.e., the target memory block 112T failed the first erase verification), the control circuit 130 performs a second erase verification on the target memory block 112T using a second erase verification voltage EV1 that is higher than the first erase verification voltage EV0. The second erase verification voltage EV1 is, for example, 0.5 to 1 volt higher than the first erase verification voltage EV0.

[0024] Finally, in S206, the control circuit 130 sets the erase flag F1 and erase flag F2 corresponding to each memory cell group 114 in the target memory block 112T according to the verification results of the first erase verification and the second erase verification, so as to classify each memory cell group 114 and adjust the increase of the erase voltage Vers accordingly.

[0025] Specifically, the control circuit 130 can set the erase flag F1 corresponding to each memory cell group 114 that passes the second erase verification to a first logic value (e.g., logic 1), and set the erase flag F2 corresponding to each memory cell group 114 that fails the second erase verification to a first logic value. Furthermore, the control circuit 130 can classify memory cell groups 114 with erase flag F1 set to the first logic value (those without slow erase cells) into normal groups with normal erase speeds, and classify memory cell groups 114 with erase flag F2 set to the first logic value (those with slow erase cells) into slow groups with slow erase speeds. Through this method, the control circuit 130 can increase the erase voltage Vers by a larger amount for memory cell groups 114 classified as slow groups, reducing the erase time spent by the slow groups, thereby improving the overall efficiency of the erase operation.

[0026] The following is as follows Figure 3A and Figure 3B The illustrated embodiments further illustrate the erasure method disclosed herein. Please also refer to... Figure 1 , Figure 3A and Figure 3B The following describes the various steps of the erasure method according to an embodiment of the present invention in conjunction with the components in the flash memory device 100. In this embodiment, parts that are the same as or similar to those described in the foregoing embodiments will not be repeated. First, in step S300, the control circuit 130 applies an erasure voltage Vers to the target memory block 112T. Next, in step S302, the control circuit 130 uses a first erasure verification voltage EV0 to determine whether the target memory block 112T passes the first erasure verification. Specifically, the control circuit 130 can determine whether multiple memory cells in the target memory block 112T addressed by the current access address pass the first erasure verification. If the multiple memory cells addressed by the current access address pass the first erasure verification, the control circuit 130 continuously increases the access address to repeatedly perform the first erasure verification on the consecutive multiple memory cells. When the control circuit 130 determines in step S302 that the last memory cell group 114 in the target memory block 112T has also passed the first erase verification, it indicates that the target memory block 112T has passed the first erase verification. At this time, the control circuit 130 will end the erase method of this embodiment.

[0027] If multiple memory cells addressed by the current access address fail the first erase verification in step S302, it indicates that there is a group of memory cells 114 in the target memory block 112T that has failed the first erase verification (i.e., the target memory block 112T has failed the first erase verification). In this case, in step S304, the control circuit 130 accumulates the number of times the erase voltage Vers is applied and determines whether the accumulated number of applications has reached a preset number (e.g., 8 or 16 times). If not, in step S306, the control circuit 130 keeps the erase voltage Vers unchanged and then returns to step S300 to continue applying the erase voltage Vers to the target memory block 112T. Thus, the control circuit 130 can repeatedly apply the erase voltage Vers to the target memory block 112T until all memory cell groups 114 in the target memory block 112T pass the first erase verification.

[0028] Whenever the cumulative number of times the erase voltage Vers is applied reaches a preset number (yes in step S304), in step S308, the control circuit 130 resets the number of applications and uses the second erase verification voltage EV1 to sequentially perform the second erase verification on all memory cell groups 114 in the target memory block 112T, so as to know all memory cell groups 114 in the target memory block 112T that can pass the second erase verification.

[0029] Next, in step S310, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that passed the second erase verification to the first logic value, and sets the erase flag F2 corresponding to each memory cell group 114 that failed the second erase verification to the first logic value.

[0030] Next, in step S312, the control circuit 130 determines whether all memory cell groups 114 in the target memory block 112T whose erase flag F1 is set to the first logic value have passed the first erase verification. If not, in step S314, the control circuit 130 increases the erase voltage Vers by a first increase ΔVA (e.g., 0.4~0.5 volts), and then returns to step S300 to continue applying the currently adjusted erase voltage Vers to the target memory block 112T.

[0031] If all memory cell groups 114 in target memory block 112T with erase flag F1 set to the first logical value pass the first erase verification, it means that all memory cell groups 114 classified as normal have passed the first erase verification, and only memory cell groups 114 classified as slow have failed the first erase verification. At this time, proceed via node A to... Figure 3BStep S316. In step S316, the control circuit 130 increases the erase voltage Vers by a second increase ΔVB (e.g., 0.8 to 1 volt) greater than the first increase ΔVA. Then, in step S318, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 (all memory cell groups 114 classified into slow groups) in the target memory block 112T where the erase flag F2 is set to the first logic value.

[0032] Next, in step S320, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T with the erase flag F2 set to the first logic value have passed the first erase verification. Specifically, the control circuit 130 can determine whether multiple memory cells in the target memory block 112T addressed by the current access address have passed the first erase verification. If multiple memory cells addressed by the current access address have passed the first erase verification, the control circuit 130 can continuously adjust the access address according to the address of all memory cell groups 114 (all memory cell groups 114 classified as slow groups) with the erase flag F2 set to the first logic value, so as to repeatedly perform the first erase verification on multiple memory cells connected within all memory cell groups 114 classified as slow groups. When the control circuit 130 determines that the last memory cell group 114 among all memory cell groups 114 whose erase flag F2 is set to the first logic value has passed the first erase verification, it indicates that all memory cell groups 114 classified as slow groups have passed the first erase verification (yes in step S320). At this time, the control circuit 130 will end the erase method of this embodiment.

[0033] If multiple memory cells addressed by the current access address fail the first erase verification, it indicates that there are still memory cell groups 114 in the target memory block 112T that have failed the first erase verification and whose erase flag F2 is set to the first logic value (i.e., memory cell groups 114 classified as slow groups) (no in step S320). At this time, in step S322, the control circuit 130 accumulates the number of times the erase voltage Vers is applied and determines whether the number of applications has reached a preset number. If not, in step S324, the control circuit 130 keeps the erase voltage Vers unchanged, and then returns to step S318 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T whose erase flag F2 is set to the first logic value. Therefore, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 (i.e. all memory cell groups 114 classified as slow groups) in the target memory block 112T where the erase flag F2 is set to the first logic value, until all memory cell groups 114 in the target memory block 112T where the erase flag F2 is set to the first logic value pass the first erase verification.

[0034] Whenever the cumulative number of times the erase voltage Vers is applied reaches a preset number (yes in step S322), in step S326, the control circuit 130 resets the number of applications, then returns to step S316 to increase the erase voltage Vers by a second increment ΔVB, and in step S318 continues to apply the currently adjusted erase voltage Vers to the target memory block 112T.

[0035] Using the above method, the control circuit 130 can increase the amount of the erase voltage Vers after all memory cell groups 114 classified as normal have passed the first erase verification, and limit the range of applied erase voltage Vers to memory cell groups 114 classified as slow. This not only reduces the erase time spent on slow groups but also prevents continuous leakage current from normal groups, thereby improving the overall efficiency of the erase operation.

[0036] The following example further illustrates the erasure method of the present invention. Please also refer to... Figure 1 , Figures 4A to 4CThe following describes the various steps of the erasure method according to an embodiment of the present invention in conjunction with the components in the flash memory device 100. In this embodiment, parts that are the same as or similar to those described in the foregoing embodiments will not be repeated. First, in step S400, the control circuit 130 applies an erasure voltage Vers to the target memory block 112T. Next, in step S402, the control circuit 130 uses a first erasure verification voltage EV0 to sequentially perform a first erasure verification on all memory cell groups 114 in the target memory block 112T, so as to determine all memory cell groups 114 in the target memory block 112T that currently pass the first erasure verification.

[0037] Next, in step S404, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 in the target memory block 112T that has passed the first erase verification to a first logic value. Then, in step S406, the control circuit 130 determines whether there are any memory cell groups 114 in the target memory block 112T whose erase flag F1 remains at a second logic value. If not, it indicates that all memory cell groups 114 in the target memory block 112T have passed the first erase verification. At this time, the control circuit 130 terminates the erase method of this embodiment.

[0038] If there is a group of memory cells 114 in the target memory block 112T where the erase flag F1 is held at the second logic value, then in step S408, the control circuit 130 uses the second erase verification voltage EV1 to sequentially perform a second erase verification on all groups of memory cells 114 in the target memory block 112T where the erase flag F1 is held at the second logic value, so as to know all groups of memory cells 114 in the target memory block 112T that can pass the second erase verification.

[0039] Next, in step S410, the control circuit 130 sets the erase flag F2 corresponding to each memory cell group 114 that failed the second erase verification to a first logic value, and then proceeds via node B to... Figure 4B Step S412.

[0040] In step S412, the control circuit 130 increases the erase voltage Vers by a first increment ΔVA. Next, in step S414, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 in the target memory block 112T where both erase flags F1 and F2 remain at the second logic value. Then, in step S416, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T where both erase flags F1 and F2 remain at the second logic value have passed the first erase verification. If not, in step S418, the control circuit 130 determines whether the number of times the erase voltage Vers has been applied has reached a preset number. If the number of times the erase voltage Vers is applied has not reached the preset number, in step S420, the control circuit 130 keeps the erase voltage Vers unchanged, and then returns to step S414 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both the erase flag F1 and the erase flag F2 are at the second logic value. Thus, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both the erase flag F1 and the erase flag F2 are at the second logic value until all memory cell groups 114 in the target memory block 112T pass the first erase verification.

[0041] Whenever the cumulative number of times the erase voltage Vers is applied reaches a preset number (yes in step S418), in step S422, the control circuit 130 resets the number of applications, then returns to step S412 to increase the erase voltage Vers by a first increment ΔVA, and in step S414 continues to apply the currently adjusted erase voltage Vers to all memory cell groups 114 in the target memory block 112T where both the erase flag F1 and the erase flag F2 are kept at the second logic value.

[0042] If all memory cell groups 114 in target memory block 112T where both erase flags F1 and F2 are at the second logic value pass the first erase verification (yes in step S416), then in step S424, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that passed the first erase verification to the first logic value, and then proceeds through node C to... Figure 4C Step S426.

[0043] In step S426, the control circuit 130 increases the erase voltage Vers by a second increment ΔVB. Next, in step S428, the control circuit 130 applies the erase voltage Vers only to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value. Then, in step S430, the control circuit 130 uses the first erase verification voltage EV0 to determine whether all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value have passed the first erase verification. If not, in step S432, the control circuit 130 determines whether the cumulative number of times the erase voltage Vers has been applied has reached a preset number. If the number of times the erase voltage Vers is applied has not reached the preset number, in step S434, the control circuit 130 keeps the erase voltage Vers unchanged, and then returns to step S428 to continue applying the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value. Thus, the control circuit 130 can repeatedly apply the erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value, until all memory cell groups 114 in the target memory block 112T pass the first erase verification.

[0044] Whenever the cumulative number of times the erase voltage Vers is applied reaches a preset number (yes in step S432), in step S436, the control circuit 130 resets the number of applications, then returns to step S426 to increase the erase voltage Vers by a second increment ΔVB, and in step S428 continues to apply the currently adjusted erase voltage Vers to all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value.

[0045] If all memory cell groups 114 in the target memory block 112T where the erase flag F1 is held at the second logic value and the erase flag F2 is set to the first logic value pass the first erase verification (yes in step S430), then in step S438, the control circuit 130 sets the erase flag F1 corresponding to each memory cell group 114 that passes the first erase verification to the first logic value.

[0046] In one embodiment, when the total number of times the control circuit 130 applies the erase voltage Vers to the target memory block 112T reaches an excessive number, the control circuit 130 may also directly abandon (stop) the erase operation performed on the target memory block 112T to avoid wasting too much erase time.

[0047] In summary, the flash memory device and erasure method of the present invention can dynamically adjust the increase in erasure voltage and the range of applied erasure voltage according to the type of memory cell group that has not yet passed erasure verification. This not only reduces the number of times erasure voltage is applied and the erasure time spent on the erasure operation, but also avoids continuous leakage current generation in memory cell groups classified as normal groups, thereby improving the overall efficiency of the erasure operation.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An erasing method for a flash memory device, the flash memory device comprising a plurality of memory blocks, each of the plurality of memory blocks being divided into a plurality of memory cell groups, the erasing method being characterized in that, Includes the following steps: An erase voltage is applied to the target memory block among the plurality of memory blocks; The target memory block is subjected to a first erase verification using a first erase verification voltage. If there is a group of memory cells in the target memory block that has failed the first erase verification, the target memory block is subjected to a second erase verification using a second erase verification voltage that is higher than the first erase verification voltage. as well as Based on the verification results of the first erase verification and the second erase verification, a first erase flag and a second erase flag are set for each of the plurality of memory cell groups in the target memory block to classify each of the plurality of memory cell groups and adjust the increase in the erase voltage accordingly.

2. The erasing method according to claim 1, characterized in that, The step of performing the first erase verification on the target memory block using the first erase verification voltage includes: The first erase verification voltage is used to determine whether the selected memory cell group in the target memory block has passed the first erase verification; When the selected storage cell group passes the first erase verification, it is determined whether the selected storage cell group is the last storage cell group in the target memory block; If so, the target memory block is determined to have passed the first erase verification; and If not, the next group of storage cells in the target memory block is selected as the selected group of storage cells to perform the first erase verification.

3. The erasure method according to claim 2, characterized in that, Determining whether the selected memory cell group in the target memory block passes the first erase verification using the first erase verification includes: The first erase verification voltage is used to determine whether multiple memory cells in the selected memory cell group that are addressed by access address have passed the first erase verification. When the multiple memory cells being addressed pass the first erase verification, it is determined whether the current access address corresponds to the last address of the selected memory cell group; If so, then the selected storage unit group is determined to have passed the first erase verification; and If not, the access address is increased to address multiple consecutive storage cells in the selected storage cell group to perform the first erase verification.

4. The erasing method according to claim 1, characterized in that, In the case that a group of memory cells in the target memory block has failed the first erase verification, the step of performing the second erase verification on the target memory block using a second erase verification voltage higher than the first erase verification voltage includes: If there are memory cell groups in the target memory block that have failed the first erase verification, the erase voltage is repeatedly applied to the target memory block until all of the plurality of memory cell groups in the target memory block pass the first erase verification; The cumulative number of times the erase voltage is applied; and Whenever the cumulative number of applications reaches a preset number, the number of applications is reset, and the second erase verification voltage is used to sequentially perform the second erase verification on all the plurality of memory cell groups in the target memory block. The step of setting the first erase flag and the second erase flag target corresponding to each of the plurality of memory cell groups in the target memory block based on the verification results of the first erase verification and the second erase verification includes: The first erase flag corresponding to each of the plurality of storage cell groups that passed the second erase verification is set to the first logical value, and the second erase flag corresponding to each of the plurality of storage cell groups that failed the second erase verification is set to the first logical value.

5. The erasure method according to claim 4, characterized in that, The steps of classifying the plurality of storage cell groups include: The group of memory cells for which the first erase flag is set to the first logical value is classified into a normal group; and The memory cell group whose second erase flag is set to the first logical value is classified into a slow group.

6. The erasure method according to claim 4, characterized in that, The steps for adjusting the increase in the erasure voltage include: Determine whether all of the plurality of memory cell groups in the target memory block whose first erase flag is set to the first logical value have passed the first erase verification; If not, the erase voltage is increased by a first increment, and the erase voltage continues to be applied to the target memory block; and If so, the erase voltage is increased by a second increase greater than the first increase, and the erase voltage is applied to all of the plurality of memory cell groups in the target memory block where the second erase flag is set to the first logic value.

7. The erasing method according to claim 6, characterized in that, After applying the erase voltage to all of the plurality of memory cell groups in the target memory block where the second erase flag is set to the first logic value, the method further includes: The first erase verification voltage is used to determine whether all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value have passed the first erase verification. If not, the erase voltage is repeatedly applied to all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value, until all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value pass the first erase verification; and Whenever the cumulative number of times the erase voltage is applied reaches the preset number, the number of applications is reset, and the erase voltage is increased by the second increment.

8. The erasing method according to claim 1, characterized in that, In the case that a group of memory cells in the target memory block has failed the first erase verification, the step of performing the second erase verification on the target memory block using a second erase verification voltage higher than the first erase verification voltage includes: Set the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification in the target memory block to a first logical value; Determine whether the memory cell group in the target memory block has the first erase flag held at the second logic value; and If so, the second erase verification voltage is used to sequentially perform the second erase verification on all of the plurality of memory cell groups in the target memory block whose first erase flag is held at the second logic value.

9. The erasure method according to claim 8, characterized in that, Based on the verification results of the first erase verification and the second erase verification, the step of setting the first erase flag and the second erase flag target corresponding to each of the plurality of memory cell groups in the target memory block includes: The second erase flag corresponding to each of the plurality of storage cell groups that failed the second erase verification is set to the first logical value. The step of adjusting the increase in the erasure voltage includes: Increase the erasure voltage by a first increment; The erase voltage is applied to all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held at the second logic value; The first erase verification voltage is used to determine whether all the multiple memory cell groups in the target memory block whose first erase flag and second erase flag are both kept at the second logic value have passed the first erase verification. If so, the first erase flag corresponding to each of the plurality of storage cell groups that have passed the first erase verification will be set to the first logical value; If not, the erase voltage is repeatedly applied to all groups of memory cells in the target memory block where both the first erase flag and the second erase flag are held at the second logic value, until all groups of memory cells in the target memory block where both the first erase flag and the second erase flag are held at the second logic value pass the first erase verification; and Whenever the cumulative number of times the erase voltage is applied reaches a preset number, the number of applications is reset, and the erase voltage is increased by the first increment.

10. The erasure method according to claim 9, characterized in that, After the step of setting the first erase flag corresponding to each of the plurality of storage cell groups that have passed the first erase verification to the first logical value, the method further includes: Increase the erasure voltage by a second increase that is greater than the first increase; The erase voltage is applied to all of the plurality of memory cell groups in the target memory block where the first erase flag is held at the second logic value and the second erase flag is set to the first logic value; The first erase verification voltage is used to determine whether the plurality of memory cell groups in the target memory block whose first erase flag is held at the second logic value and whose second erase flag is set to the first logic value have passed the first erase verification. If so, the first erase flag corresponding to each of the plurality of storage cell groups that have passed the first erase verification will be set to the first logical value; If not, the erase voltage is repeatedly applied to all the plurality of memory cell groups in the target memory block where the first erase flag is held at the second logic value and the second erase flag is set to the first logic value, until all the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are held at the second logic value pass the first erase verification; and Whenever the cumulative number of times the erase voltage is applied reaches the preset number, the number of applications is reset, and the erase voltage is increased by the second increment.

11. A flash memory device, characterized in that, include: A memory array having multiple memory blocks, each of which is divided into multiple memory cell groups; A flag register is configured to store a first erase flag and a second erase flag corresponding to each of the plurality of memory cell groups; as well as A control circuit, coupled to the memory array and the flag register, is configured to perform an erase operation on a target memory block among the plurality of memory blocks. Specifically, the control circuit applies an erase voltage to the target memory block and uses a first erase verification voltage to perform a first erase verification on the target memory block. If there are memory cell groups in the target memory block that have failed the first erase verification, the control circuit uses a second erase verification voltage higher than the first erase verification voltage to perform a second erase verification on the target memory block. Based on the verification results of the first erase verification and the second erase verification, the control circuit sets the first erase flag and the second erase flag corresponding to each of the plurality of memory cell groups in the target memory block to classify each of the plurality of memory cell groups and adjust the increase in the erase voltage accordingly.

12. The flash memory device according to claim 11, characterized in that, The control circuit uses the first erase verification voltage to determine whether the selected memory cell group in the target memory block has passed the first erase verification. When the selected memory cell group passes the first erase verification, the control circuit determines whether the selected memory cell group is the last memory cell group in the target memory block. If yes, the control circuit determines that the target memory block has passed the first erase verification. If no, the control circuit selects the next memory cell group in the target memory block as the selected memory cell group to perform the first erase verification.

13. The flash memory device according to claim 12, characterized in that, The control circuit uses the first erase verification voltage to determine whether multiple memory cells in the selected memory cell group that are addressed by access addresses have passed the first erase verification. When the addressed plurality of memory cells pass the first erase verification, the control circuit determines whether the current access address corresponds to the last address of the selected memory cell group. If yes, the control circuit determines that the selected memory cell group has passed the first erase verification. If no, the control circuit increases the access address to address the consecutive plurality of memory cells in the selected memory cell group to perform the first erase verification.

14. The flash memory device according to claim 11, characterized in that, If any group of memory cells in the target memory block fails the first erase verification, the control circuit repeatedly applies the erase voltage to the target memory block until all of the plurality of memory cell groups in the target memory block pass the first erase verification. The control circuit accumulates the number of times the erase voltage is applied. Whenever the accumulated number of applications reaches a preset number, the control circuit resets the number of applications and uses the second erase verification voltage to sequentially perform the second erase verification on all the plurality of memory cell groups in the target memory block. The control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the second erase verification to a first logic value, and sets the second erase flag corresponding to each of the plurality of memory cell groups that have failed the second erase verification to the first logic value.

15. The flash memory device according to claim 14, characterized in that, The control circuit classifies the group of memory cells whose first erase flag is set to the first logic value into a normal group, and classifies the group of memory cells whose second erase flag is set to the first logic value into a slow group.

16. The flash memory device according to claim 14, characterized in that, The control circuit determines whether all the plurality of memory cell groups in the target memory block whose first erase flag is set to the first logic value have passed the first erase verification. If not, the control circuit increases the erase voltage by a first increment and continues to apply the erase voltage to the target memory block. If yes, the control circuit increases the erase voltage by a second increment greater than the first increment and applies the erase voltage to all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value.

17. The flash memory device according to claim 16, characterized in that, The control circuit uses the first erase verification voltage to determine whether all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value have passed the first erase verification. If not, the control circuit repeatedly applies the erase voltage to all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value until all the plurality of memory cell groups in the target memory block whose second erase flag is set to the first logic value have passed the first erase verification. Whenever the cumulative number of times the erase voltage is applied reaches the preset number, the control circuit resets the number of applications and increases the erase voltage by the second increment.

18. The flash memory device according to claim 11, characterized in that, The control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups in the target memory block that has passed the first erase verification to a first logic value. The control circuit determines whether there is a group of memory cells in the target memory block where the first erase flag is held at the second logic value. If so, the control circuit uses the second erase verification voltage to sequentially perform the second erase verification on all the plurality of memory cell groups in the target memory block where the first erase flag is held at the second logic value.

19. The flash memory device according to claim 18, characterized in that, The control circuit sets the second erase flag corresponding to each of the plurality of memory cell groups that failed the second erase verification to the first logic value. The control circuit increases the erase voltage by a first increment and applies the erase voltage to all of the plurality of memory cell groups in the target memory block where both the first erase flag and the second erase flag are maintained at the second logic value. The control circuit uses the first erase verification voltage to determine whether all the plurality of memory cell groups in the target memory block whose first erase flag and second erase flag are both maintained at the second logic value have passed the first erase verification. If yes, the control circuit sets the first erase flag corresponding to each plurality of memory cell groups that have passed the first erase verification to the first logic value. If no, the control circuit repeatedly applies the erase voltage to all the plurality of memory cell groups in the target memory block whose first erase flag and second erase flag are both maintained at the second logic value until all the plurality of memory cell groups in the target memory block whose first erase flag and second erase flag are both maintained at the second logic value have passed the first erase verification. Whenever the cumulative number of times the erase voltage is applied reaches a preset number, the control circuit resets the number of applications and increases the erase voltage by the first increment.

20. The flash memory device according to claim 19, characterized in that, The control circuit increases the erase voltage by a second increase greater than the first increase, and applies the erase voltage to all of the plurality of memory cell groups in the target memory block where the first erase flag is held at the second logic value and the second erase flag is set to the first logic value. The control circuit uses the first erase verification voltage to determine whether the plurality of memory cell groups in the target memory block whose first erase flag is held at the second logic value and whose second erase flag is set to the first logic value have passed the first erase verification. If yes, the control circuit sets the first erase flag corresponding to each of the plurality of memory cell groups that have passed the first erase verification to the first logic value. If no, the control circuit repeatedly applies the erase voltage to all the plurality of memory cell groups in the target memory block whose first erase flag is held at the second logic value and whose second erase flag is set to the first logic value, until all the plurality of memory cell groups in the target memory block whose first erase flag and second erase flag are both held at the second logic value have passed the first erase verification. Whenever the cumulative number of times the erase voltage is applied reaches the preset number, the control circuit resets the number of applications and increases the erase voltage by the second increment.

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