Memory for generating pass / fail information and method of operating the memory

Abstract

The present disclosure relates to a memory for generating pass / fail information and an operating method of the memory. A memory includes a cell array including a plurality of memory cells, a pass / fail determination circuit configured to divide multi-bit data read from a memory cell selected by a row address and a column address from among the plurality of memory cells into a plurality of groups, and determine whether the data is a “pass” or a “fail” for each group, and a section fail determination circuit configured to determine section fail information of a section corresponding to the row address and the column address as a “pass” when a number of groups determined as a “fail” by the pass / fail determination circuit among the plurality of groups is greater than or equal to a first threshold value.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0179075, filed with the Korean Intellectual Property Office on December 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a memory in a semiconductor device. Background Technology

[0004] As the capacity of large memory devices continues to increase, the number of memory areas requiring testing is also rapidly increasing, and the time required for testing has a significant impact on overall productivity. Furthermore, when defects are over-detected and screened during testing, an "over-correction" problem can occur when dealing with too many defects, potentially reducing memory yield. Therefore, a technique is needed to properly filter unnecessary errors from test results; this filtering can improve memory yield and prevent over-correction. Summary of the Invention

[0005] According to one embodiment of this disclosure, a memory may include: a cell array including a plurality of memory cells and providing read data from the plurality of memory cells selected by row address and column address; a pass / fault determination circuit configured to divide the read data into a plurality of multi-bit data groups and determine whether each multi-bit data group is "pass" or "fault"; and a segment fault determination circuit configured to determine a segment fault information of a segment corresponding to the received row address and column address and where each segment is associated with one of the plurality of multi-bit data groups as "fault" by the pass / fault determination circuit as "fault" when the number of the plurality of multi-bit data groups determined as "fault" by the pass / fault determination circuit is greater than or equal to a first threshold.

[0006] According to one embodiment of the present invention, a method of operating a memory may include: reading data from a memory cell selected by a row address and a column address; dividing the data read from the memory cell into multiple groups; determining whether the data in each group is "pass" or "fault"; and generating segment fault information of the segment corresponding to the row address and column address as "fault" when the number of groups among the multiple groups determined as "fault" by the pass / fault determination circuit is greater than or equal to a first threshold. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a memory according to an embodiment of the present disclosure.

[0008] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1A block diagram of an example test circuit.

[0009] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 Block diagrams of examples of pass / fault determination circuits and section fault determination circuits.

[0010] Figures 4 to 7 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram illustrating the operation of the filter circuit. Detailed Implementation

[0011] Various embodiments of this disclosure relate to techniques for filtering and outputting memory-related pass / fail information.

[0012] According to embodiments of this disclosure, pass / fail information of the memory can be filtered and output, and unnecessary errors in test results can be reduced.

[0013] In the following description, various embodiments based on the technical spirit of this disclosure are illustrated with reference to the accompanying drawings.

[0014] Figure 1 This is a block diagram illustrating a memory according to an embodiment of the present disclosure.

[0015] See Figure 1 The memory 100 includes: a command address receiving circuit 101, a data sending / receiving circuit 103, a command decoder 110, a row control circuit 121, a column control circuit 123, an address control circuit 125, a cell array 130, a row circuit 131, a column circuit 133, and a test circuit 140.

[0016] Command address receiving circuit 101 receives commands and addresses input to multiple command address terminals CA. Depending on the specifications of memory 100, commands and addresses can be input to the same input terminal or separate input terminals. Here, as an example, it is described that commands and addresses are input to the same input terminal CA.

[0017] The data transmission / reception (input / output) circuit 103 receives data sent to or to multiple data terminals DQ. During a write operation, the data transmission / reception circuit 103 receives data DATA to be written to the cell array 130, and during a read operation, it transmits data DATA read from the cell array 130.

[0018] Command decoder 110 decodes commands and addresses to identify the operation type of the instruction given to memory 100. Furthermore, when an instruction sets a test mode, command decoder 110 can activate the test mode signal TM. Additionally, command decoder 110 can generate signals F1, F2, and F3 during test mode to indicate the filtering mode of test circuit 140.

[0019] When the decoding result of the command decoder 110 indicates that a row operation, such as an activation operation or a precharge operation, is instructed, the row control circuit 121 controls the row operation. The activation signal ACT is a signal indicating an activation operation, and the precharge signal PCG is a signal indicating a precharge operation.

[0020] When the decoding result of the command decoder 110 indicates that a column operation, such as a write operation or a read operation, is instructed, the column control circuit 123 controls the column operation. The write signal WR is a signal indicating a write operation, and the read signal RD is a signal indicating a read operation.

[0021] Address control circuit 125 classifies the address received from command decoder 110 into row address R_ADD and column address C_ADD, and sends row address R_ADD and column address C_ADD to row circuit 131 and column circuit 133 respectively. When the decoding result of command decoder 110 indicates that an activation operation is instructed, address control circuit 125 can classify the received address as row address R_ADD, while when the decoding result of command decoder 110 indicates that a read operation or a write operation is instructed, it can classify the received address as column address C_ADD.

[0022] Cell array 130 includes memory cells arranged in multiple rows and columns. Row circuit 131 controls the rows of cell array 130. When activation signal ACT is activated, row circuit 131 activates the row selected by row address R_ADD from the rows of cell array 130. During activation, data in the memory cells of the selected row can be detected and amplified. Furthermore, when precharge signal PCG is activated, row circuit 131 can precharge the activated row.

[0023] During a write operation, column circuit 133 writes data DATA to the column selected by column address C_ADD from the columns of cell array 130. That is, column circuit 133 writes data to the memory cell corresponding to the active row and the selected column. Similarly, during a read operation, column circuit 133 reads data DATA from the column selected by column address C_ADD from the columns of cell array 130. That is, column circuit 133 reads data from the memory cell corresponding to the active row and the selected column.

[0024] When the test mode signal TM is activated, the test circuit 140 is activated and operates in test mode. In test mode, the test circuit 140 can generate a test result TM_RESULT using the data DATA read by the column circuit 133. The test result TM_RESULT generated by the test circuit 140 can be output through the data transmission / reception circuit 103. That is, in test mode, the data transmission / reception circuit 103 can output the test result TM_RESULT instead of the data DATA.

[0025] Test circuit 140 uses data DATA read from cell array 130 to generate test result TM_RESULT. Before test circuit 140 generates the test result, the same data can be written to all memory cells of cell array 130. That is, "1" can be stored in all memory cells of cell array 130, or "0" can be stored in all memory cells of cell array 130.

[0026] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example test circuit.

[0027] See Figure 2 The test circuit 140 includes: a pass / fault determination circuit 210, a section fault determination circuit 220, and a filtering circuit 230.

[0028] Pass / fault determination circuit 210 divides the data DATA read from the memory cell array into multiple groups and determines whether the data DATA in each group is "pass" or "fault". For example, 64-bit data DATA can be divided into 8 groups, each with 8 bits of data, and each group can be determined as "pass" or "fault".

[0029] When the number of groups in a segment that are determined to be “faulty” by the pass / fault determination circuit 210 reaches or exceeds a predetermined number (e.g., 3 or more), the segment fault determination circuit 220 determines the segment fault information of the segment corresponding to the row address R_ADD and column address C_ADD of the memory cell that performed the read operation as “faulty”.

[0030] When a filtering mode is set and one of the filtering mode signals F1, F2, and F3 is activated, the filtering circuit 230 filters the section fault information generated by the section fault determination circuit 220. When all filtering mode signals F1, F2, and F3 are deactivated, the filtering circuit 230 can be deactivated, and the unfiltered section fault information can be generated as the test result TM_RESULT.

[0031] Figure 3This illustrates an embodiment according to the present disclosure. Figure 2 Block diagrams of examples of pass / fault determination circuits and section fault determination circuits.

[0032] See Figure 3 The pass / fault determination circuit 210 includes pass / fault determination units 311 to 318. Starting from the read operation, the 64-bit data DATA is divided into 8 groups, each with 8 bits of data, and each 8-bit data is input to a different pass / fault determination unit 311 to 318. When all 8 bits of data input to the pass / fault determination units 311 to 318 have the same value, each of the pass / fault determination units 311 to 318 can determine the corresponding 8-bit data input as "pass". When at least one bit in the 8 bits of data has a different value, each of the pass / fault determination units 311 to 318 can determine the 8-bit data input as "fault". That is, the pass / fault determination units 311 to 318 can each perform an XOR operation and generate pass / fault signals PF1 to PF8. As signals indicating the passage or fault of a group of 8-bit data, the pass / fault signals PF1 to PF8 can have a value of "0" when the data is determined to be "pass" and a value of "1" when the data is determined to be "fault". Although in Figure 3 In this example, the data DATA is read as having 64 bits, and the 64-bit data DATA is divided into 8 groups. However, this is just an example, and it is obvious that in other embodiments, the number of bits and the number of groups of data DATA can be changed.

[0033] The segment fault determination circuit 220 determines the segment fault information SEC_FAIL of the segment corresponding to the row address R_ADD and column address C_ADD in the row address and column address of the read data. For example, in Figure 3 In this context, when the number of signals identified as "fault" among the pass / fault signals PF1 to PF8 in multiple groups is greater than or equal to a threshold (e.g., 3), the segment fault information for the corresponding row and column addresses of these multiple groups is set to "fault". The segment fault information SEC_FAIL can have a format such as [row address value / column address value / fault status]. The row address value and column address value can represent the row address and column address values ​​corresponding to the data DATA. When the corresponding segment is identified as "pass", the fault status value can be "0", and when the corresponding segment is identified as "fault", the fault status value can be "1".

[0034] Figures 4 to 7 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram illustrating the operation of the filter circuit.

[0035] Figure 4 This is a table showing multiple segment fault messages SEC_FAIL generated by the segment fault determination circuit 220. The table starts at the intersection of the segment fault messages in row 0 (row address value 0) and column 0 (column address value 0), and ends at row k and column i, listing (k+1)*(i+1) segment fault messages SEC_FAIL. The value "0 or 1" indicates that the value of the segment fault message SEC_FAIL is "0" when the segment corresponding to the row address and column address is "passed," and "1" when the segment corresponding to the row address and column address is "faulted." Because a single segment fault message may be generated during a single read operation, Figure 4 The segment fault information shown can be the result of (k+1)*(i+1) read operations performed as the row address R_ADD and column address C_ADD change or increment.

[0036] exist Figure 4 In the example shown, no filtering is performed on the section fault information. When the filtering circuit 230 does not perform filtering operation, that is, when all filtering mode signals F1, F2 and F3 are deactivated, the following can be generated: Figure 4 The test result shown is TM_RESULT.

[0037] Figure 5 This diagram illustrates the test result TM_RESULT generated by the filtering circuit 230 when the first filtering mode is set (i.e., when the filtering mode signal F1 is activated). The first filtering mode is a filtering mode in which segment fault information corresponding to predetermined address values ​​of the target row address and column address remains unchanged, while segment fault information for the remaining row and column addresses is processed as "pass". For example, in Figure 5 In this context, the filtering mode signal F1 corresponds to preset values ​​for the target row and column addresses located in the diagonal portion of the cell array 130. See also... Figure 5 As can be seen, the segment fault information for the target row and column addresses located in the diagonal portion retains its original value of "0 or 1", while the segment fault information for the remaining row and column addresses has a value of "0". As a result, the segment fault information for the remaining row and column addresses, which is not predetermined according to the filtering mode signal F1, is processed as "pass" and the segment fault information is set to "0". Therefore, the first filtering mode can be used when only selecting and monitoring or analyzing the pass / fault information of the region of interest or the region to be analyzed.

[0038] In the first filtering mode, it is possible to generate and output such as Figure 5 The filtered test result TM_RESULT is shown. Figure 5In this context, the unfiltered region is the region located in the diagonal portion of the cell array 130. However, it is evident that in other embodiments, the unfiltered region may be located in other regions and may be arranged differently.

[0039] Figure 6 This is a diagram showing the test result TM_RESULT generated by the filtering circuit 230 when the second filtering mode is set (i.e., when the filtering mode signal F2 is activated). The second filtering mode is a filtering mode in which the number of segments with the segment fault information "fault" in N adjacent rows is greater than or equal to a threshold (e.g., Figure 6 When there are 3 or more rows, the fault information of the adjacent N rows remains unchanged, while the fault information of the other rows is processed as "passed". See also Figure 6 Only the fault information in the second, third, and fourth rows retains its original value of "0 or 1," while the fault information in all other rows is set to "0." This means that fault information in all other rows, except for the N adjacent target rows, is processed as "pass." Since the number of faulty segments in three consecutive rows (i.e., the second, third, and fourth rows) is greater than or equal to the threshold, the fault information in the second, third, and fourth rows retains its original value, while the other rows are processed as "pass" because no row meets the condition corresponding to the filtering mode signal F2. In this example, the second filtering mode can be used when only selecting and monitoring or analyzing pass / fault information where faults occur excessively in consecutive rows.

[0040] Figure 7 This is a graph showing the test result TM_RESULT generated by the filtering circuit 230 when the third filtering mode is set (i.e., when the filtering mode signal F3 is activated). The third filtering mode is a filtering mode in which the number of segments with the fault information "fault" in M ​​adjacent columns is greater than or equal to a threshold (e.g., Figure 7 When there are 3 or more columns, the section fault information in the adjacent M columns remains unchanged, while the section fault information in other columns is processed as "passed". See also Figure 7 Only the fault information in rows 5, 6, and 7 retains its original value of "0 or 1," while the fault information in all columns is "0." This means that fault information in all other columns (excluding the adjacent M columns) is processed as "pass." Since the number of faulty segments in three consecutive columns (i.e., columns 5, 6, and 7) is greater than or equal to the threshold, the fault information in columns 5, 6, and 7 retains its original value, while the other rows are processed as "pass," because no column meets the condition corresponding to the filter mode signal F3. In this example, the third filter mode can be used when only selecting and monitoring or analyzing pass / fault information where faults occur excessively in consecutive columns.

[0041] Although the technical spirit of this disclosure has been described above with reference to embodiments, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Within the scope of the technical spirit of this disclosure, those skilled in the art to which this disclosure pertains can apply various embodiments.

Claims

1. A memory, comprising: A cell array comprising multiple storage cells and providing read data from the multiple storage cells selected by row address and column address; The pass / fault determination circuit divides the read data into multiple multi-bit data groups and determines whether each multi-bit data group is a "pass" or a "fault"; and A segment fault determination circuit, wherein: when the number of the plurality of multi-bit data groups determined as "fault" by the pass / fault determination circuit is greater than or equal to a first threshold, the segment fault information of the segment corresponding to the received row address and column address and associated with one of the plurality of multi-bit data groups is determined as "fault".

2. The memory according to claim 1, wherein, The read operation is performed multiple times by changing one or more values ​​of the row address and the column address, and each time a read operation is performed, the fault determination operation of the pass / fault determination circuit and the segment fault determination circuit is performed.

3. The memory according to claim 2, further comprising: A filtering circuit, wherein: the segment fault information generated for each of the row address and the column address is filtered; and The output circuit outputs the filtering result of the filtering circuit.

4. The memory according to claim 3, wherein, When the filtering mode is set, the filtering circuit keeps the segment fault information corresponding to the predetermined target row address and column address unchanged, and processes the remaining segment fault information as "pass".

5. The memory according to claim 4, wherein, The predetermined target row and column addresses have values ​​for the row and column addresses located on the diagonal portion of the cell array.

6. The memory according to claim 3, wherein, When the filtering mode is set and the number of segments with the fault information "fault" in N adjacent rows is greater than or equal to the second threshold, the filtering circuit keeps the segment fault information of the segments in the N adjacent rows unchanged and assigns "pass" values ​​to the segments in the remaining rows, where "N" is an integer greater than or equal to 2.

7. The memory according to claim 3, wherein, When the filtering mode is set and the number of segments with "fault" information in M ​​adjacent columns is greater than or equal to the third threshold, the filtering circuit keeps the segment fault information of the segments in the M columns unchanged and processes the segment fault information of the remaining columns as "pass", where "M" is an integer greater than or equal to 2.

8. The memory according to claim 1, wherein, The pass / fail determination circuit performs an XOR operation on each group and determines whether it is "pass" or "fail".

9. A method of operating a memory, the method comprising: Read data from the memory cell selected by row and column addresses; The data read from the storage unit is divided into multiple groups; For each group, determine whether the data is "passed" or "faulted"; as well as When the number of groups among the plurality of groups that are determined to be "fault" by the pass / fault determination circuit is greater than or equal to a first threshold, the segment fault information of the segment corresponding to the row address and the column address is generated as "fault".

10. The operating method according to claim 9, wherein, By changing one or more of the row address and the column address, the process of reading data from the storage unit, dividing the data, determining whether the data is "passed" or "faulted", and generating the segment fault information is performed multiple times.

11. The operating method according to claim 10, further comprising: Filter the segment fault information generated for each value of the row address and the column address; as well as Output filtered section fault information.

12. The operating method according to claim 11, wherein, The filtering of the segment fault information includes: keeping the segment fault information corresponding to the predetermined values ​​of the row address and the column address unchanged, and processing other segment fault information as "pass" in response to the setting of the filtering mode.

13. The operating method according to claim 12, wherein, The predetermined values ​​of the row address and the column address are the row address and column address values ​​of the segment located in the diagonal portion of the cell array.

14. The operating method according to claim 11, wherein, Filtering the fault information of the aforementioned section includes: In response to the filtering mode setting, select rows from N adjacent rows where the number of segments with the segment fault information "fault" is greater than or equal to a second threshold, where "N" is an integer greater than or equal to 2; and The fault information of the selected adjacent N rows is kept unchanged, while the fault information of other segments is processed as "pass".

15. The operating method according to claim 11, wherein, Filtering the fault information of the aforementioned section includes: In response to the filtering mode setting, select columns from adjacent M columns where the number of segments with the fault information "fault" is greater than or equal to a third threshold, where "M" is an integer greater than or equal to 2; and The fault information of the selected adjacent M columns is kept unchanged, and the fault information of other columns is determined as "pass".

16. The operating method according to claim 9, wherein, Determining whether the data is "passed" or "faulted" involves performing an XOR operation on each group.

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