Capacitors including dielectric layers comprising high-k materials, electronic devices including the capacitors, and methods of fabricating the capacitors

Abstract

Capacitors including a dielectric layer including a high-k material, electronic devices including the capacitors, and methods of fabricating the capacitors are provided. The capacitor includes a first electrode, a second electrode facing the first electrode, a dielectric layer between the first electrode and the second electrode, and a conductive interface layer between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a rutile crystal phase. The dielectric layer includes a first intermediate layer and a second intermediate layer provided in the dielectric layer. The first intermediate layer includes an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc). The second intermediate layer includes an oxide of a group IVA metal element having a rutile crystal phase.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0177588, filed on December 3, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to capacitors including dielectric layers comprising high-k materials, electronic devices including said capacitors, and methods of manufacturing said capacitors. Background Technology

[0004] As the integration of electronic devices (such as memory) increases, the electronic components within these devices are becoming increasingly smaller. However, since the capacitance of a capacitor is proportional to its area, the capacitance decreases as the size of the capacitor decreases. Therefore, to compensate for the reduction in capacitor size and ensure the desired capacitance, methods to further increase the dielectric constant of the dielectric layer have been investigated. Additionally, methods to suppress the increase in leakage current caused by capacitor miniaturization have been studied. Summary of the Invention

[0005] Provides a capacitor comprising a dielectric layer containing a high-k material and an electronic device comprising said capacitor.

[0006] Provides a capacitor with improved leakage current characteristics and an electronic device including said capacitor.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned through practice of some of the exemplary embodiments presented in this disclosure.

[0008] According to one aspect of this disclosure, the capacitor includes a first electrode, a second electrode facing the first electrode, a dielectric layer between the first electrode and the second electrode, and a conductive interface layer between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a rutile crystalline phase. The dielectric layer includes a first intermediate layer and a second intermediate layer in the dielectric material. The first intermediate layer includes an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and the second intermediate layer includes an oxide of a group IVA metal having a rutile crystalline phase.

[0009] For example, the dielectric material of the dielectric layer may include titanium oxide (TiO2) having a rutile crystal phase.

[0010] The metal content of the first intermediate layer in the dielectric layer can be greater than 0 atomic% and about 20 atomic% or less.

[0011] The oxide of the second intermediate layer may include an oxide of at least one of germanium (Ge), silicon (Si), or tin (Sn).

[0012] The metal content of the second intermediate layer in the dielectric layer can be about 0.1 atomic% or more and about 10 atomic% or less.

[0013] The second intermediate layer may have a thickness of about 0.1 nm or greater and about 0.5 nm or less.

[0014] The thickness of the second intermediate layer can be less than the thickness of the first intermediate layer.

[0015] The gap between the conductive interface layer and the second intermediate layer can be 0.5 nm or larger.

[0016] The second intermediate layer may be located between the first intermediate layer and the conductive interface layer.

[0017] The first intermediate layer may be located between the second intermediate layer and the conductive interface layer.

[0018] The conductive interface layer may include a first conductive interface layer between the first electrode and the dielectric layer, and a second conductive interface layer between the first conductive interface layer and the dielectric layer. The first conductive interface layer may include a conductive metal oxide material having a stable crystal structure in the rutile phase, and the conduction band offset (CBO) between the second conductive interface layer and the dielectric layer may be greater than the CBO between the first conductive interface layer and the dielectric layer.

[0019] The first conductive interface layer may include molybdenum oxide (MoO2) doped with tin (Sn).

[0020] The Sn doping concentration in the first conductive interface layer can be about 0.1 atomic% or more and about 10 atomic% or less.

[0021] The first conductive interface layer may have a thickness of about 0.3 nm or greater and about 4 nm or less.

[0022] The second conductive interface layer may include tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (SnO2). x Ge 1-x O2, 0 <x<1)。

[0023] The second conductive interface layer may have a thickness of about 0.3 nm or greater and about 1 nm or less.

[0024] The first electrode may include at least one or any combination of titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN) and cobalt nitride (CoN).

[0025] According to another aspect of this disclosure, an electronic device is provided, comprising a transistor and a capacitor electrically connected to the transistor, wherein the capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a first metal oxide, a second metal oxide, and a third metal oxide, the first metal oxide comprising titanium oxide having a rutile phase, the second metal oxide comprising an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and the third metal oxide comprising an oxide of at least one of germanium (Ge), silicon (Si), or tin (Sn).

[0026] The contents of the second metal oxide and the third metal oxide in the dielectric layer can be different from each other.

[0027] According to another aspect of this disclosure, a method for manufacturing a capacitor is provided, the method comprising: forming a conductive interface layer on a first electrode; forming a dielectric layer on the conductive interface layer, the dielectric layer comprising a first metal oxide, a second metal oxide, and a third metal oxide; and forming a second electrode on the dielectric layer, wherein the first metal oxide comprises titanium oxide having a rutile phase, the second metal oxide comprises an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and the third metal oxide comprises an oxide of at least one of germanium (Ge), silicon (Si), or tin (Sn). Attached Figure Description

[0028] The above and other aspects, features, and advantages of some exemplary embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 This is a cross-sectional view showing a schematic structure of a capacitor according to at least one exemplary embodiment;

[0030] Figure 2 It is a display Figure 1 A schematic band diagram illustrating an example of conduction band offset (CBO) between the second conductive interface layer and the dielectric layer in a capacitor.

[0031] Figures 3A to 3D It schematically shows the formation Figure 1 The image shows a cross-sectional view of the process of the conductive interface layer of the capacitor.

[0032] Figure 4 High-resolution transmission electron microscopy (HR-TEM) images of an actual manufactured capacitor according to an embodiment are shown.

[0033] Figure 5This is a figure showing an example of ultraviolet (UV) photoelectron spectroscopy (UPS) spectrum obtained by UPS measurement for the first conductive interface layer;

[0034] Figure 6 It is a graph showing a comparison of leakage current characteristics between a capacitor including a conductive interface layer according to an embodiment and a capacitor including a conductive interface layer according to a comparative example.

[0035] Figure 7 It is a graph showing a comparison of leakage current characteristics between capacitors based on the tin (Sn) content in the first conductive interface layer;

[0036] Figure 8 An example showing grazing incidence X-ray diffraction (GI-XRD) measurements, which compares the crystallinity between dielectric layers grown in multiple layered structures;

[0037] Figure 9 It is a graph showing a comparison of the leakage current characteristics of capacitors with different contents of the first and second intermediate layers.

[0038] Figure 10 This is a graph showing a comparison of the leakage current characteristics of capacitors based on the thickness of the second intermediate layer;

[0039] Figure 11 It is a graph showing a comparison of the leakage current characteristics of the capacitors based on the location of the second intermediate layer;

[0040] Figure 12 This is a cross-sectional view showing a schematic structure of a capacitor according to at least one exemplary embodiment;

[0041] Figure 13 It is a circuit diagram used to describe the schematic circuit configuration and operation of an electronic device including a capacitor according to some exemplary embodiments.

[0042] Figure 14 This is a schematic diagram illustrating an electronic device according to at least one exemplary embodiment;

[0043] Figure 15 This is a schematic diagram illustrating an electronic device according to at least one exemplary embodiment;

[0044] Figure 16 It is a plan view showing an electronic device according to at least one exemplary embodiment;

[0045] Figure 17 It is along Figure 16 A cross-sectional view of the electronic device taken by line A-A';

[0046] Figure 18This is a cross-sectional view showing an electronic device according to at least one exemplary embodiment; and

[0047] Figure 19 and 20 It is a conceptual diagram schematically illustrating a device architecture that can be applied to a device according to at least one example implementation. Detailed Implementation

[0048] Some exemplary embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, exemplary embodiments are described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." modify the entire list of elements when preceding it and do not modify individual elements of the list.

[0049] In the following description, capacitors comprising dielectric layers containing high-k materials and electronic devices including them are described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals denote the same elements, and the dimensions of the elements in the drawings may be exaggerated for clarity and ease of illustration. Furthermore, the embodiments described herein are merely examples, and various modifications can be made to these embodiments. Additionally, when the terms “about” or “substantially” are used in conjunction with numerical and / or geometric terms in this specification, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ±10%) around the stated values. Furthermore, regardless of whether numerical and / or geometric terms are modified to “about” or “substantially,” it will be understood that these values ​​should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometries. As used herein, the term “metal” includes both metals and quasi-metals.

[0050] In the following text, the terms “above,” “on,” “below,” or “under” will include not only those directly above, below, to the left, or to the right of something in a contact manner, but also those in a non-contact manner. Furthermore, spatially relative terms, such as above, below, etc., are based on the orientation shown in the accompanying drawings and may be used in other ways when the orientation of the corresponding object changes. In other words, such spatially relative terms are intended to cover different orientations of a device in use or operation, in addition to those depicted in the figures, such that the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly. Unless the context clearly indicates otherwise, the singular forms used herein are also intended to include the plural forms. It will be understood that the terms “comprising,” “including,” or “having” as used herein specify the presence of the stated element, but do not exclude the presence or addition of one or more other elements.

[0051] The term “the (the, definite article)” and similar indicator words can be used for both singular and plural forms. The operations constituting a method can be performed in any suitable order unless otherwise stated herein or clearly contradicted by the context, and are not necessarily limited to the order stated.

[0052] Furthermore, terms such as “unit” and “module” described in the specification refer to a unit configured to perform at least one function or operation, and may be implemented as a processing circuitry system such as hardware, software, or a combination of hardware and software. For example, a processing circuitry system may include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), unless otherwise expressly stated.

[0053] The connecting lines or connecting elements shown in the figures are intended to illustrate exemplary functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0054] All illustrative or descriptive terms used in some exemplary embodiments are for the purpose of describing the technical idea in detail only, and the scope of the inventive concept is not limited by the illustrative or descriptive terms unless they are limited by the claims.

[0055] Figure 1 This is a cross-sectional view showing a schematic structure of a capacitor 100 according to at least one exemplary embodiment. (Reference) Figure 1A capacitor 100 according to at least one embodiment includes a first electrode 110, a second electrode 140 facing the first electrode 110, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. In other words, the dielectric layer 130 may be provided between the first electrode 110 and the second electrode 140 facing each other. In the process of manufacturing the capacitor 100, the conductive interface layer 120 may be formed on the upper surface of the first electrode 110, the dielectric layer 130 may be formed on the upper surface of the conductive interface layer 120, and the second electrode 140 may be formed on the upper surface of the dielectric layer 130.

[0056] Dielectric layer 130 may include a dielectric material having a rutile crystal phase. The statement "dielectric layer 130 includes a dielectric material having a rutile crystal phase" means that dielectric layer 130 includes a dielectric material in which the rutile crystal phase is dominant (predominant, controlling). In other words, the entire dielectric material does not need to have a rutile crystal phase, a large portion of the dielectric material may have a rutile crystal phase, and / or the rutile crystal phase may constitute the largest portion of the crystal phase of the material forming the dielectric material. Hereinafter, material having a rutile crystal phase refers to material in which the rutile crystal phase is dominant.

[0057] For example, dielectric layer 130 may comprise titanium oxide (TiO2) having a rutile crystal phase. Titanium oxide has different dielectric constants depending on its phase. While titanium oxide having anatase crystal phase has a dielectric constant of about 40, titanium oxide having rutile crystal phase can have a large dielectric constant of about 80 to about 170, depending on the growth direction of the titanium oxide. Therefore, dielectric layer 130 comprising titanium oxide having a rutile crystal phase can have a dielectric constant of about 80 to about 170. According to at least one exemplary embodiment, because dielectric layer 130 has a high dielectric constant, the thickness of dielectric layer 130 can be reduced and capacitor 100 can be further miniaturized. For example, dielectric layer 130 can have a thickness of about 3 nanometers (nm) to about 7 nm.

[0058] The first electrode 110 may include a conductive metal nitride. Specifically, the first electrode 110 may include a metal nitride that is not easily reduced to a metal during a heat treatment process. In other words, the metal nitride may be thermally stable over a high temperature range applied during the heat treatment process (as discussed in further detail below). For example, the first electrode 110 may include at least one conductive metal nitride selected from titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), cobalt nitride (CoN), and / or any combination thereof. The first electrode 110 may have a thickness of about 5 nm to about 10 nm.

[0059] The second electrode 140 comprises a conductive material. The material of the second electrode 140 is not particularly limited. For example, the second electrode 140 may comprise a conductive material having a single-layer structure and / or a multilayer structure, including metals, metal nitrides, metal oxides, and / or any combination thereof. The second electrode 140 may comprise at least one of, for example, titanium nitride (TiN), molybdenum nitride (MoN), cobalt nitride (CoN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), platinum oxide (PtO), BaRuO3, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), (La,Sr)CoO3 (LSCO), and / or any combination thereof.

[0060] The conductive interface layer 120 may be configured to enable the growth of a dielectric layer 130 having a rutile phase thereon (e.g., by lattice strain induction and / or by preferential lattice growth with crystal alignment) and reduce leakage current. According to at least one exemplary embodiment, the conductive interface layer 120 may include a first conductive interface layer 121 on the upper surface of the first electrode 110 and a second conductive interface layer 122 on the upper surface of the first conductive interface layer 121. The dielectric layer 130 may be provided on the upper surface of the second conductive interface layer 122. Thus, the first conductive interface layer 121 may be provided between the first electrode 110 and the dielectric layer 130, and particularly between the first electrode 110 and the second conductive interface layer 122, and the second conductive interface layer 122 may be provided between the first conductive interface layer 121 and the dielectric layer 130.

[0061] The first conductive interface layer 121 may comprise a conductive metal oxide material having a stable crystal structure in a rutile phase, such that a dielectric layer 130 having a rutile phase can be grown on the conductive interface layer 120. Furthermore, the first conductive interface layer 121 may comprise a conductive metal oxide material that is not easily reduced to a metal during heat treatment processes. The first conductive interface layer 121 may also comprise a conductive metal oxide material that exhibits almost no degradation in film quality and has a relatively high work function during crystallization processes (e.g., 450°C or higher, as discussed further in detail below). The first conductive interface layer 121 may comprise, for example, molybdenum oxide (MoO2) doped with tin (Sn). In other words, the first conductive interface layer 121 may comprise both molybdenum oxide (MoO2) and tin oxide (SnO2). Therefore, the first conductive interface layer 121 may also be referred to as a "Sn-doped molybdenum oxide (MoO2) layer" provided between the first electrode 110 and the dielectric layer 130.

[0062] Like the first conductive interface layer 121, the second conductive interface layer 122 may include a conductive metal oxide material having a stable crystal structure in the rutile crystal phase. In addition, the second conductive interface layer 122 may include a conductive metal oxide material having a relatively high conduction band offset (CBO) with the dielectric layer 130 to reduce leakage current. For example, the material of the second conductive interface layer 122 may be selected such that the CBO between the second conductive interface layer 122 and the dielectric layer 130 is greater than the CBO between the first conductive interface layer 121 and the dielectric layer 130. The second conductive interface layer 122 may include, for example, tin oxide (SnO2), germanium oxide (GeO2), and / or a mixture of tin oxide and germanium oxide ((Sn x Ge 1-x )O2, 0 < x < 1). Thus, the second conductive interface layer 122 may also be referred to as an "interface layer including tin oxide and / or germanium oxide" provided between the "MoO2 layer doped with Sn" and the dielectric layer 130.

[0063] Figure 2 is a schematic energy band diagram showing an example of the CBO between the second conductive interface layer 122 and the dielectric layer 130 in the capacitor 100 shown in Figure 1 . Figure 2 (a) of shows an example of the CBO between the second conductive interface layer 122 and the dielectric layer 130, and Figure 2 (b) of shows an example of the CBO between the first conductive interface layer 121 and the dielectric layer 130 in the absence of the second conductive interface layer 122 for comparison. In Figure 2 , the conduction band of the first conductive interface layer 121 is represented by a thick solid line. Referring to Figure 2 , the CBO between the second conductive interface layer 122 and the dielectric layer 130 may be greater than about 1 eV. For example, the CBO between the second conductive interface layer 122 and the dielectric layer 130 may be about 1.4 eV, and / or about 1.4 eV or greater and about 1.5 eV or less. On the other hand, the CBO between the first conductive interface layer 121 and the dielectric layer 130 may be about 1 eV, which is less than the CBO between the second conductive interface layer 122 and the dielectric layer 130.

[0064] Figures 3A to 3D is a cross-sectional view schematically showing the process of forming the conductive interface layer 120 of the capacitor 100 shown in Figure 1 .

[0065] Referring to Figure 3A , an amorphous molybdenum oxide (MoO xThe first material layer 121'. The first material layer 121' can be formed by, for example, pulsed laser deposition (PLD) or atomic layer deposition (ALD). Alternatively, the first material layer 121' can be formed by other deposition methods, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0066] Reference Figure 3B , a second material layer 121" including tin oxide (SnO2) can be formed on the upper surface of the first material layer 121'. For example, the second material layer 121" can be formed by ALD.

[0067] Reference Figure 3C , the first material layer 121' can be crystallized by post-metallization annealing (PMA). PMA can be performed at a temperature of, for example, about 450 °C or higher and / or about 600 °C or lower. Amorphous molybdenum oxide (MoO x ) can be crystallized to form crystalline molybdenum oxide (MoO2). In this process, the tin oxide (SnO2) of the second material layer 121" on the first material layer 121' can be mixed in the crystal structure of the crystalline molybdenum oxide (MoO2). Thus, a first conductive interface layer 121 including Sn-doped crystalline molybdenum oxide (MoO2) and / or including both crystalline molybdenum oxide (MoO2) and crystalline tin oxide (SnO2) can be formed on the upper surface of the first electrode 110. The first conductive interface layer 121 can have a thickness of about 0.3 nm or greater and about 4 nm or less, and / or about 0.3 nm or greater and about 3 nm or less.

[0068] Reference Figure 3D , a second conductive interface layer 122 can be formed on the first conductive interface layer 121. In this way, the conductive interface layer 120 can be completed. For example, the second conductive interface layer 122 can be formed by growing crystalline tin oxide (SnO2), crystalline germanium oxide (GeO2), or a mixture of crystalline tin oxide and crystalline germanium oxide ((Sn x Ge 1-x )O2, 0 < x < 1) on the first conductive interface layer 121 via ALD. The second conductive interface layer 122 can have a thickness of about 0.3 nm or greater and about 1 nm or less, and / or about 0.3 nm or greater and about 0.6 nm or less. For example, in at least some example embodiments, the thickness of the second conductive interface layer 122 can be such that the lattice structure of the first conductive interface layer 121 constrains the lattice structure of the second conductive interface layer 122, thereby enabling the structure of the first conductive interface layer 121 to affect the structure of the dielectric layer 130 through (through) the second conductive interface layer 122.

[0069] In Figure 3DFollowing the process, a dielectric layer 130 can be formed on the conductive interface layer 120, particularly the second conductive interface layer 122, and a second electrode 140 can be formed on the dielectric layer 130. In this way, a capacitor 100 can be manufactured. For example, the dielectric layer 130 can be formed by ALD deposition of titanium oxide (TiO2). The dielectric layer 130, including titanium oxide (TiO2) having a rutile crystal phase, can be implemented by ALD deposition of titanium oxide (TiO2) on the conductive interface layer 120 having a stable crystal structure in the rutile crystal phase.

[0070] According to at least one exemplary embodiment, in the process of forming the first conductive interface layer 121, the amorphous molybdenum oxide (MoO) can be formed by... x Sn is doped during crystallization to mitigate the degradation of the molybdenum oxide (MoO2) film quality. Therefore, the conductive interface layer 120 can have a relatively uniform thickness of about 4 nm or less, and the surface roughness of the conductive interface layer 120 can be relatively small. In this case, the dielectric layer 130 can be homogeneously formed on the conductive interface layer 120, and leakage current can be reduced.

[0071] Figure 4 This image shows a high-resolution transmission electron microscope (HR-TEM) image of an actual capacitor manufactured according to an embodiment. A first electrode 110 is formed of titanium nitride (TiN), a conductive interface layer 120 is formed of molybdenum oxide (MoO2) and tin oxide (SnO2) doped with Sn, a dielectric layer 130 is formed of titanium oxide (TiO2) having a rutile crystal phase, and a second electrode 140 is formed of platinum (Pt). Although not clearly visible in the image, the conductive interface layer 120 may include both a first conductive interface layer 121 and a second conductive interface layer 122. The first electrode 110, conductive interface layer 120, and dielectric layer 130 are grown by ALD. The second electrode 140 is formed by an evaporator. Reference Figure 4 The conductive interface layer 120 according to at least one embodiment has a relatively uniform thickness. Therefore, in the case of the conductive interface layer 120 according to the embodiment, the film quality degradation of molybdenum oxide (MoO2) is mitigated due to the doping of Sn into molybdenum oxide (MoO2). Therefore, the dielectric layer 130 on the conductive interface layer 120 can also have a relatively uniform thickness.

[0072] Figure 5 This is a diagram showing an example of ultraviolet (UV) photoelectron spectroscopy (UPS) spectrum obtained by UPS measurement for the first conductive interface layer 121. Figure 5The UPS spectrum shown is obtained by forming a 3 nm thick first conductive interface layer 121 on a 10 nm thick first electrode 110 made of titanium nitride (TiN) and irradiating the first conductive interface layer 121 with UV light of approximately 21.22 eV in the vertical direction. Figure 5 In the graph, the horizontal axis represents the binding energy, and the vertical axis represents the intensity or kinetic energy of the electrons emitted through the photoelectric effect. The work function of the sample can be derived from the equation for... Figure 5 The difference between the X intercept of the differential value of the UPS spectrum shown in the figure and 21.22 eV is obtained.

[0073] For example, the work function of the first conductive interface layer according to the comparative example, which is undoped with Sn, is about 5.12 eV. Furthermore, the work function of the first conductive interface layer 121 according to the embodiment, which is doped with Sn at a concentration of about 1.5 atomic percent, is about 5.02 eV, and the work function of the first conductive interface layer 121 according to the embodiment, which is doped with Sn at a concentration of about 3.0 atomic percent, is about 5.03 eV. Therefore, the work function of the first conductive interface layer 121 according to the embodiment, which is doped with Sn, is slightly lower than the work function of the first conductive interface layer according to the comparative example, which is undoped with Sn.

[0074] Figure 6 This is a graph comparing the leakage current characteristics of a capacitor 100 including a conductive interface layer 120 according to an embodiment with that of a capacitor including a conductive interface layer according to a comparative example. Figure 6 In the diagram, the horizontal axis represents the equivalent oxide thickness of the dielectric layer, and the vertical axis represents the leakage current of the capacitor. Figure 6 And the description below Figure 7 , 9 In Figures 10 and 11, the values ​​for equivalent oxide thickness and leakage current on the horizontal and vertical axes are normalized to show only relative characteristics. (Reference) Figure 6 The capacitor (▲) according to Comparative Example 1, which includes only a first conductive interface layer formed of MoO2 doped with Sn at a concentration of 1.5 atomic percent and does not include a second conductive interface layer, has the largest leakage current and the largest equivalent oxide thickness. The capacitor (■) according to Comparative Example 2, which includes a first conductive interface layer formed of MoO2 without Sn doping and a second conductive interface layer formed of SnO2, has a smaller leakage current and equivalent oxide thickness than the capacitor according to Comparative Example 1. In addition, the capacitor 100 (●) according to the embodiment, which includes both a first conductive interface layer 121 formed of MoO2 doped with Sn at a concentration of 1.5 atomic percent and a second conductive interface layer 122 formed of SnO2, has the smallest leakage current and equivalent oxide thickness.

[0075] Figure 7This is a graph comparing the leakage current characteristics of capacitors 100 based on the Sn content in the first conductive interface layer 121. (Reference) Figure 7 When the Sn doping concentration in the first conductive interface layer 121 is about 1.5 atomic% (●), the leakage current and equivalent oxide thickness of the capacitor 100 are minimized. The leakage current and equivalent oxide thickness of the capacitor 100 (◆) with a Sn doping concentration of about 3.0 atomic% in the first conductive interface layer 121 are slightly greater than those of the capacitor 100 with a Sn doping concentration of about 1.5 atomic% in the first conductive interface layer 121, but less than those of the capacitor according to the comparative example (■). On the other hand, the leakage current and equivalent oxide thickness of the capacitor 100 (▲) with a Sn doping concentration of about 4.5 atomic% in the first conductive interface layer 121 are greater than those of the capacitor according to the comparative example.

[0076] When taking into account the following: Figures 5 to 7 When observing variations in various characteristics based on changes in the Sn doping concentration in the first conductive interface layer 121, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic% or greater and about 5.0 atomic% or less. Alternatively, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic% or greater and about 4.0 atomic% or less, about 0.1 atomic% or greater and about 3.0 atomic% or less, about 0.5 atomic% or greater and about 3.0 atomic% or less, or about 1.5 atomic% or greater and about 3.0 atomic% or less. The Sn doping concentration in the first conductive interface layer 121 can be the ratio of the number of Sn atoms to the total number of metal atoms in the first conductive interface layer 121. In other words, the Sn doping concentration in the first conductive interface layer 121 can be "100 × the number of Sn atoms / (the number of Sn atoms + the number of Mo atoms)".

[0077] As described above, in the case of capacitor 100 according to the exemplary embodiment, a dielectric layer 130 comprising a dielectric material having a rutile crystal phase can be formed via ALD using a first conductive interface layer 121 doped with Sn. Therefore, the disclosed capacitor 100 can be miniaturized and has high capacitance. Furthermore, because the material of the first electrode 110 is chemically stable, it is unlikely that the material of the first electrode 110 will be reduced to a metal in subsequent processes. Additionally, leakage current can be reduced by using a second conductive interface layer 122 having a sufficiently large CBO with the dielectric layer 130.

[0078] Refer again Figure 1The dielectric layer 130 includes a first intermediate layer 131 and a second intermediate layer 132 provided therein. Titanium oxide (TiO2) having a rutile phase has a relatively high dielectric constant, but a relatively small band gap of about 3.0 eV and exhibits electric n-type characteristics, which can lead to leakage current. The first intermediate layer 131 may comprise an oxide of a doped metal having electric p-type characteristics. For example, the first intermediate layer 131 may comprise an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and scandium (Sc). The first intermediate layer 131 having electric p-type characteristics is configured to reduce leakage current by lowering the Fermi level of the dielectric layer 130. However, because the first intermediate layer 131 does not have a rutile phase, as the amount of the first intermediate layer 131 increases, the titanium oxide (TiO2) of the dielectric layer 130 may grow into anatase instead of rutile. By taking this into account, the content of the dopant metal in the first intermediate layer 131 of the dielectric layer 130 can be, for example, greater than 0 atomic% and about 20 atomic% or less. The content of the dopant metal can be the ratio of the number of dopant metal atoms to the total number of metal atoms in the dielectric layer 130, including the metal of the second intermediate layer 132 described below.

[0079] The second intermediate layer 132 may comprise an oxide of a Group IVA metal element that may have a rutile crystalline phase. For example, the second intermediate layer 132 may comprise an oxide of at least one of germanium (Ge), silicon (Si), and / or tin (Sn). Germanium oxide (GeO2), silicon oxide (SiO2), and tin oxide (SnO2) may have thermodynamically stable properties in a rutile crystalline phase. In particular, germanium oxide (GeO2) may have the largest band gap (e.g., about 4.63 eV) among oxides having a rutile crystalline phase, which can compensate for the relatively small band gap of titanium oxide (TiO2). The second intermediate layer 132 can help the dielectric layer 130 grow into a rutile crystalline phase. Furthermore, the second intermediate layer 132 can reduce the number of oxygen vacancies in the dielectric layer 130 by trapping oxygen vacancies present in the dielectric layer 130. Therefore, leakage current can be further reduced by suppressing Fermi-level pinning at the interface between the conductive interface layer 120 and the dielectric layer 130, which is caused by a large number of oxygen vacancies distributed in the dielectric layer 130.

[0080] The first intermediate layer 131 and the second intermediate layer 132 can be grown via ALD during the process of growing the dielectric layer 130. For example, the lower portion of the dielectric layer 130 can be grown via ALD, and the second intermediate layer 132 can be grown via ALD. Subsequently, the dielectric layer 130 can be partially grown again on the second intermediate layer 132, the first intermediate layer 131 can be grown on the dielectric layer 130 via ALD, and then the upper portion of the dielectric layer 130 can be grown on the first intermediate layer 131. The thickness of the first intermediate layer 131 and the second intermediate layer 132 can vary depending on the content of the first intermediate layer 131 and the second intermediate layer 132 in the dielectric layer 130.

[0081] Figure 8 An example showing grazing incidence X-ray diffraction (GI-XRD) measurements comparing the crystallinity between dielectric layers grown in multiple layered structures. Reference Figure 8 Titanium oxide (TiO2) grown on titanium nitride (TiN) primarily exhibits anatase crystal phase. On the other hand, when a conductive interface layer including molybdenum oxide (MoO2) exists between titanium nitride (TiN) and dielectric layer 130, titanium oxide (TiO2) with a rutile crystal phase can be well grown even when dielectric layer 130 includes a first intermediate layer 131 and a second intermediate layer 132. In particular, when tin oxide (SnO2) is further added to molybdenum oxide (MoO2) serving as the conductive interface layer, the orientation along the c-axis, which has a relatively high dielectric constant, increases.

[0082] Figure 9 This is a graph comparing the leakage current characteristics of capacitors with varying amounts of materials used in the first intermediate layer 131 and the second intermediate layer 132. The dielectric layer 130 uses titanium oxide (TiO2) with a rutile phase and a thickness of 5 nm; the first intermediate layer 131 uses aluminum oxide (Al2O3); and the second intermediate layer 132 uses germanium oxide (GeO2). The first electrode 110 uses titanium nitride (TiN); the first conductive interface layer 121 uses molybdenum oxide (MoO2) doped with Sn; and the second conductive interface layer 122 uses tin oxide (SnO2). Figure 9In the diagram, "A" indicates the characteristics when dielectric layer 130 includes only the second intermediate layer 132 and not the first intermediate layer 131; "B1", "B2", "B3", "B4", "B5", and "B6" indicate the characteristics when dielectric layer 130 includes only the first intermediate layer 131 and not the second intermediate layer 132; and "C1", "C2", "C3", and "C4" indicate the characteristics when dielectric layer 130 includes both the first intermediate layer 131 and the second intermediate layer 132. Furthermore, the content of the first intermediate layer 131 increases from "B1" to "B6", and the content of the second intermediate layer 132 increases from "C1" to "C4". The contents of the first intermediate layer 131 in dielectric layer 130 for "B1", "B2", "B3", "B4", "B5", and "B6" are 0 atoms, 2.5 atoms, 5 atoms, 7.5 atoms, 10 atoms, and 12.5 atoms, respectively. In the case of "B1", it can be assumed that dielectric layer 130 does not include both the first intermediate layer 131 and the second intermediate layer 132. The content of "C1", "C2", "C3" and "C4" in the first intermediate layer 131 of dielectric layer 130 is 10 atomic%, and the content of "C1", "C2", "C3" and "C4" in the second intermediate layer 132 of dielectric layer 130 is 3 atomic%, 4.5 atomic%, 6 atomic% and 7.5 atomic%, respectively. In addition, the gap between conductive interface layer 120 and the first intermediate layer 131 is 50% of the thickness of dielectric layer 130, and the gap between conductive interface layer 120 and the second intermediate layer 132 is 25% of the thickness of dielectric layer 130.

[0083] refer to Figure 9 Even when germanium oxide (GeO2) is provided alone in dielectric layer 130, an improvement in leakage current (LKG) can be observed. However, compared to the case where germanium oxide (GeO2) is provided alone, when aluminum oxide (Al2O3) is provided alone in dielectric layer 130, the leakage current decreases with increasing aluminum oxide (Al2O3) content. However, when aluminum oxide (Al2O3) is provided alone in dielectric layer 130, the leakage current characteristics improve with increasing aluminum oxide (Al2O3) content, but the equivalent oxide thickness (T) remains the same. oxeq The leakage current characteristics can be degraded. On the other hand, when aluminum oxide (Al2O3) and germanium oxide (GeO2) are provided together in the dielectric layer 130, the leakage current characteristics can be further improved. Furthermore, when aluminum oxide (Al2O3) and germanium oxide (GeO2) are provided together in the dielectric layer 130, the slope of the degradation of the equivalent oxide thickness characteristics can be relatively reduced compared to the slope of the improvement in leakage current characteristics.

[0084] Figure 10 This is a graph comparing the leakage current characteristics of capacitors based on the thickness of the second intermediate layer 132. Additionally, Figure 11This is a graph showing a comparison of the leakage current characteristics of the capacitors at the location of the second intermediate layer 132. (See figure.) Figure 9 Just like in the middle, in Figure 10 and 11 In this structure, dielectric layer 130 uses titanium oxide (TiO2) with a rutile crystal phase and a thickness of 5 nm, first intermediate layer 131 uses aluminum oxide (Al2O3), and second intermediate layer 132 uses germanium oxide (GeO2). First electrode 110 uses titanium nitride (TiN), first conductive interface layer 121 uses molybdenum oxide (MoO2) doped with Sn, and second conductive interface layer 122 uses tin oxide (SnO2).

[0085] exist Figure 10 In the text, "Ref" indicates a case where the first intermediate layer 131 is provided alone, without the second intermediate layer 132. (See reference.) Figure 10 Compared to the case where only the first intermediate layer 131 is provided, the leakage current characteristics are improved when the thickness of the second intermediate layer 132 is 0.2 nm (2 Å). Furthermore, as the thickness of the second intermediate layer 132 increases from 0.2 nm (2 Å) to 0.3 nm (3 Å), the leakage current characteristics are further improved. Compared to the case where the thickness of the second intermediate layer 132 is 0.3 nm (3 Å), a slight improvement in leakage current is observed when the thickness of the second intermediate layer 132 is 0.4 nm (4 Å), but the equivalent oxide thickness characteristics deteriorate. When the thickness of the second intermediate layer 132 is 0.5 nm (5 Å), the leakage current characteristics are similar to those when the thickness of the second intermediate layer 132 is 0.2 nm (2 Å), and the equivalent oxide thickness characteristics deteriorate further.

[0086] Taking these characteristics into account, the thickness of the second intermediate layer 132 can be about 0.1 nm (1 Å) or greater and about 0.5 nm (5 Å) or less, about 0.1 nm (1 Å) or greater and about 0.4 nm (4 Å) or less, about 0.1 nm (1 Å) or greater and about 0.3 nm (3 Å) or less, about 0.2 nm (2 Å) or greater and about 0.5 nm (5 Å) or less, about 0.2 nm (2 Å) or greater and about 0.4 nm (4 Å) or less, or about 0.2 nm (2 Å) or greater and about 0.3 nm (3 Å) or less. The thickness of the second intermediate layer 132 can be less than the thickness of the first intermediate layer 131. The thickness of the first intermediate layer 131 can be about 1 nm (10 Å) or less.

[0087] Furthermore, the metal content of the second intermediate layer 132 having the aforementioned thickness in the dielectric layer 130 may be about 0.1 atomic% or more and about 10 atomic% or less. The metal content of the second intermediate layer 132 may be the ratio of the number of metal atoms in the second intermediate layer 132 to the total number of metal atoms in the dielectric layer 130 including the dopant metal of the first intermediate layer 131.

[0088] refer to Figure 11 Depending on the location of the second intermediate layer 132 or the gap between the conductive interface layer 120 and the second intermediate layer 132 (see...). Figure 1 The equivalent oxide thickness characteristics were observed by g). The second intermediate layer 132 uses germanium oxide (GeO2) with a thickness of 0.2 nm. For example, when the gap g between the conductive interface layer 120 and the second intermediate layer 132 is 20% and 25% of the thickness of the dielectric layer 130, almost identical characteristics are observed. However, when the second intermediate layer 132 is too close to the conductive interface layer 120, the equivalent oxide thickness characteristics can deteriorate. For example, compared to the case where the gap g between the conductive interface layer 120 and the second intermediate layer 132 is 20% or more of the thickness of the dielectric layer 130, the leakage current characteristics can be similar when the gap g between the conductive interface layer 120 and the second intermediate layer 132 is 12.5% ​​of the thickness of the dielectric layer 130, but the equivalent oxide thickness can increase. Taking this into account, the gap g between the conductive interface layer 120 and the second intermediate layer 132 can be 20% or more of the thickness of the dielectric layer 130, or 25% or more of the thickness of the dielectric layer 130. For example, the gap g between the conductive interface layer 120 and the second intermediate layer 132 may be about 0.5 nm (5 Å) or greater. When the gap g between the conductive interface layer 120 and the second intermediate layer 132 is about 0.5 nm (5 Å) or greater, the second intermediate layer 132 may be provided at any location in the dielectric layer 130.

[0089] Figure 12 This is a cross-sectional view showing a schematic structure of a capacitor 100a according to at least one exemplary embodiment. Although Figure 1 The diagram shows a second intermediate layer 132 provided within the dielectric layer 130 between the first intermediate layer 131 and the conductive interface layer 120, but the location of the second intermediate layer 132 is not limited thereto. (See reference...) Figure 12 In the case of capacitor 100a according to at least one example embodiment, a first intermediate layer 131 may be provided between a second intermediate layer 132 and a conductive interface layer 120 within a dielectric layer 130. In this case, the gap g between the conductive interface layer 120 and the second intermediate layer 132 may be greater than the gap g' between the conductive interface layer 120 and the first intermediate layer 131.

[0090] Alternatively, although not shown, the first intermediate layer 131 and the second intermediate layer 132 may be provided to overlap each other in the dielectric layer 130. In this case, the gap g between the conductive interface layer 120 and the second intermediate layer 132 may be equal to the gap g' between the conductive interface layer 120 and the first intermediate layer 131.

[0091] Furthermore, although for convenience, Figure 1 and 12 The dielectric layer 130, and the first intermediate layer 131 and the second intermediate layer 132 provided in the dielectric layer 130 are clearly distinguished. However, in the actual manufactured capacitors 100 and 100a, the materials of the dielectric layer 130 and the first intermediate layer 131 and the second intermediate layer 132 may be mixed in the dielectric layer 130, and therefore may not be clearly distinguishable. In this respect, the dielectric layer 130 may be said to comprise a first metal oxide, a second metal oxide, and a third metal oxide.

[0092] The first metal oxide may be, for example, titanium oxide (TiO2) having a rutile crystal phase. The second metal oxide may be the material of the first intermediate layer 131. For example, the second metal oxide may include an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), and / or scandium (Sc). The third metal oxide may be the material of the second intermediate layer 132. For example, the third metal oxide may include an oxide of a Group IVA metal element. For example, the third metal oxide may include an oxide of at least one metal selected from germanium (Ge), silicon (Si), and tin (Sn).

[0093] The metal content of the first metal oxide in dielectric layer 130 may be the highest among the first, second, and third metal oxides, and the metal content of the second metal oxide may differ from that of the third metal oxide. For example, the ratio of metal atoms of the first metal oxide to the total number of metal atoms in dielectric layer 130 may be about 70 atomic% or more. Furthermore, the ratio of metal atoms of the second metal oxide to the total number of metal atoms in dielectric layer 130 may be greater than 0 atomic% and about 20 atomic% or less. The ratio of metal atoms of the third metal oxide to the total number of metal atoms in dielectric layer 130 may be about 0.1 atomic% or greater and about 10 atomic% or less. Furthermore, the above-described configuration, such as the thickness and position of the first intermediate layer 131 and the second intermediate layer 132, can also be applied to the second and third metal oxides.

[0094] When in Figure 3DWhen forming the dielectric layer 130 on the second conductive interface layer 122 following the process shown, titanium oxide (TiO2) as the first metal oxide can be partially deposited via ALD. Then, the second and third metal oxides can be deposited sequentially, or the third and second metal oxides can be deposited sequentially, or the second and third metal oxides can be deposited simultaneously via ALD. Furthermore, the first metal oxide can be deposited together with the second or third metal oxide. After depositing the second and third metal oxides, the first metal oxide can be further deposited if necessary. In this way, a dielectric layer 130 comprising the first, second, and third metal oxides can be formed on the second conductive interface layer 122.

[0095] On the other hand, reference Figures 5 to 7 The Sn doping concentration in the first conductive interface layer 121 described does not take into account the leakage current reduction effect through the first intermediate layer 131 and the second intermediate layer 132. When the first intermediate layer 131 and the second intermediate layer 132 are provided together in the dielectric layer 130, the range of Sn doping concentration in the first conductive interface layer 121 can be further extended. For example, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic% or greater and about 10 atomic% or less. Alternatively, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic% or greater and about 8 atomic% or less, or about 0.1 atomic% or greater and about 6 atomic% or less.

[0096] As described above, in the cases of capacitors 100 and 100a according to some exemplary embodiments, the dielectric layer 130 comprising a dielectric material having a rutile phase can be formed via ALD using a first conductive interface layer 121 doped with Sn, for example, as a seed layer. Therefore, the disclosed capacitors 100 and 100a can be miniaturized and have high capacitance. Furthermore, because the material of the first electrode 110 is chemically stable, it is unlikely that the material of the first electrode 110 will be reduced to a metal in subsequent processes. Additionally, leakage current can be reduced by using a second conductive interface layer 122 having a sufficiently large CBO with the dielectric layer 130. Furthermore, leakage current can be further reduced by inserting a first intermediate layer 131 and a second intermediate layer 132 into the dielectric layer 130.

[0097] Capacitors are used in a variety of electronic devices. They can be used together with transistors as dynamic random access memory (DRAM). Additionally, capacitors can be used as part of the electronic circuitry of an electronic device, in conjunction with other circuit elements.

[0098] Figure 13It is a circuit diagram used to describe the schematic circuit configuration and operation of an electronic device 1000 including a capacitor according to some exemplary embodiments.

[0099] The circuit diagram of electronic device 1000 is for one cell of DRAM, and electronic device 1000 includes a transistor TR, a capacitor CA, a word line WL, and a bit line BL. The capacitor CA can be used as a reference. Figures 1 to 12 The capacitors 100 and 100a are described.

[0100] The method for writing data to DRAM is as follows. After applying a high gate voltage to the gate electrode through the word line WL to turn on the transistor TR (“on” state), VDD (hereinafter, high voltage) or 0 (hereinafter, low voltage), which is the data voltage value to be input, is applied to the bit line BL. When a high voltage is applied to both the word line WL and the bit line BL, the capacitor CA is charged, i.e., data “1” is written. When a high voltage is applied to the word line WL and a low voltage is applied to the bit line BL, the capacitor CA is discharged, i.e., data “0” is written.

[0101] During data reading, a high voltage is applied to the word line WL to turn on the DRAM transistor TR, and a voltage of VDD / 2 is applied to the bit line BL. When the DRAM data is "1", that is, when the voltage across capacitor CA is VDD, the charge stored in capacitor CA slowly moves to the bit line BL, and the voltage of bit line BL becomes slightly higher than VDD / 2. In contrast, when the data across capacitor CA is "0", the charge in bit line BL moves to capacitor CA, and the voltage of bit line BL becomes slightly lower than VDD / 2. A sense amplifier senses and amplifies the potential difference between the bit lines and determines whether the data is "0" or "1".

[0102] Figure 14 This is a schematic diagram illustrating an electronic device 1001 according to at least one exemplary embodiment.

[0103] refer to Figure 14 Electronic device 1001 may include a structure in which capacitor CA1 and transistor TR are electrically connected to each other via contact 20. Capacitor CA1 may include a first electrode 110, a second electrode 140, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. Capacitor CA1 may be a reference. Figures 1 to 12 The capacitors described are 100 and 100A. Since this has already been described above, its detailed description is omitted.

[0104] A transistor TR can be a field-effect transistor. A transistor TR includes a semiconductor substrate (SU) and a gate stack GS. The semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU and faces the channel region CH. The gate stack GS includes a gate insulating layer GI and a gate electrode GA.

[0105] The channel region CH is the region between the source region SR and the drain region DR, and is electrically connected to both the source region SR and the drain region DR. The source region SR may be electrically connected to one end of the channel region CH or in contact with one end of the channel region CH, and the drain region DR may be electrically connected to the other end of the channel region CH or in contact with the other end of the channel region CH. The channel region CH can be defined as the substrate region between the source region SR and the drain region DR in the semiconductor substrate SU.

[0106] The semiconductor substrate SU may include semiconductor materials. The semiconductor substrate SU may include, for example, semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Furthermore, the semiconductor substrate SU may include a silicon-on-insulator (SOI) substrate.

[0107] In at least some exemplary embodiments, the source region SR, drain region DR, and channel region CH can each be formed independently by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, channel region CH, and drain region DR can each include a substrate material as a base material. The source region SR and drain region DR can each include a conductive material. In this case, the source region SR and drain region DR can each include, for example, a metal, a metal compound, or a conductive polymer.

[0108] In at least some exemplary embodiments, the channel region CH may be implemented as a separate material layer (thin film), unlike its illustrated counterpart. In this case, for example, the channel region CH may include at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots (QDs), organic semiconductors, and / or the like. For example, oxide semiconductors may include InGaZnO, 2D materials may include transition metal dichalcogenides (TMDs) or graphene, and QDs may include colloidal QDs or nanocrystalline structures.

[0109] The gate electrode GA can be disposed on the semiconductor substrate SU and can be separated from the semiconductor substrate SU while facing the channel region CH. The gate electrode GA can include at least one of a metal, a metal nitride, a metal carbide, and polysilicon. For example, the metal can include at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride can include at least one of titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide can include at least one of aluminum-doped (or aluminum-containing) metal carbides and silicon-doped (or silicon-containing) metal carbides. Specific examples of metal carbides can include TiAlC, TaAlC, TiSiC, or TaSiC.

[0110] The gate electrode GA may have a structure in which multiple materials are stacked. For example, the gate electrode GA may have a structure in which metal nitride layers and metal layers are stacked (e.g., TiN / Al), or a structure in which metal nitride layers, metal carbide layers and metal layers are stacked (e.g., TiN / TiAlC / W). However, the above materials are merely examples.

[0111] The gate insulating layer GI may be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may comprise a paraelectric material or a high-k dielectric material and may have a dielectric constant of about 20 to about 70.

[0112] The gate insulating layer GI may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, and / or the like, and / or may include 2D insulators such as hexagonal boron nitride (h-BN). For example, the gate insulating layer GI may include silicon oxide (SiO2), silicon nitride (SiNx), and / or the like, or may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbSc) 0.5 Ta 0.5 O3), lead zinc niobate (PbZnNbO3), etc. Furthermore, the gate insulating layer GI may include metal oxynitrides (e.g., aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), etc.), silicates (e.g., ZrSiON, HfSiON, YSiON, LaSiON, etc.), and / or aluminates (e.g., ZrAlON, HfAlON, etc.). Additionally, the gate insulating layer GI may form a gate stack together with the gate electrode GA.

[0113] One of the first electrode 110 and the second electrode 140 of capacitor CA1 is electrically connected to one of the source region SR and the drain region DR of transistor TR via contact 20. Contact 20 may comprise a suitable conductive material, such as tungsten, copper, aluminum, or polysilicon.

[0114] The arrangement of capacitor CA1 and transistor TR can be modified in various ways. For example, capacitor CA1 can be arranged on semiconductor substrate SU, or it can be embedded in semiconductor substrate SU.

[0115] Figure 14 The electronic device 1001 shown includes a capacitor CA1 and a transistor TR, but this is only an example, and the electronic device 1001 may include multiple capacitors and multiple transistors.

[0116] Figure 15 This is a schematic diagram illustrating an electronic device 1002 according to at least one exemplary embodiment.

[0117] refer to Figure 15 The electronic device 1002 may include a structure in which a capacitor CA2 and a transistor TR are electrically connected to each other via a contact 21. The transistor TR includes a semiconductor substrate SU and a gate stack GS. The semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU, facing the channel region CH, and includes a gate insulating layer GI and a gate electrode GA.

[0118] An interlayer insulating layer 25 may be disposed on a semiconductor substrate SU to cover the gate stack GS. The interlayer insulating layer 25 may include an insulating material. For example, the interlayer insulating layer 25 may include Si oxide (e.g., SiO2), Al oxide (e.g., Al2O3), or a high-k material (e.g., HfO2). A contact 21 passes through the interlayer insulating layer 25 to electrically connect the transistor TR to the capacitor CA2.

[0119] The capacitor CA2 includes a first electrode 110, a second electrode 140, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The first electrode 110 and the second electrode 140 are provided in a shape that maximizes the contact area with the dielectric layer 130, and the material of the capacitor CA2 is similar to that of a reference electrode. Figures 1 to 12 The capacitors 100 and 100a described are made of the same and / or substantially similar materials.

[0120] Figure 16 This is a plan view showing an electronic device 1003 according to at least one exemplary embodiment.

[0121] refer to Figure 16Electronic device 1003 may include a structure in which multiple capacitors and multiple field-effect transistors are repeatedly arranged. Electronic device 1003 may include field-effect transistors, contact structures 20', and capacitor CA3. The field-effect transistors include a semiconductor substrate 11' and a gate stack 12, the semiconductor substrate 11' including a source, a drain, and a channel. Contact structures 20' are disposed on the semiconductor substrate 11' so as not to overlap with the gate stack 12. Capacitor CA3 is disposed on contact structures 20'. Electronic device 1003 may further include bit line structures 13 electrically connecting the field-effect transistors to each other.

[0122] although Figure 16 The contact structure 20' and capacitor CA3 are shown to be arranged repeatedly in the X and Y directions, but the present disclosure is not limited thereto. For example, the contact structure 20' may be arranged in the X and Y directions, and the capacitor CA3 may be hexagonal in shape, such as in a honeycomb structure.

[0123] Figure 17 It is along Figure 16 The cross-sectional view of electronic device 1003 taken by line A-A'.

[0124] refer to Figure 17 The semiconductor substrate 11' may have a shallow trench isolation (STI) structure including a device isolation layer 14. The device isolation layer 14 may be a single layer including one type of insulating layer, or a multilayer including a combination of two or more types of insulating layers. The device isolation layer 14 may include device isolation trenches 14T in the semiconductor substrate 11', and the device isolation trenches 14T may be filled with an insulating material. The insulating material may include at least one of fluorinated silicate glass (FSG), undoped silicate glass (USG), borosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), and tonnen silazene (TOSZ), but this disclosure is not limited thereto.

[0125] The semiconductor substrate 11' may further include a channel region CH defined by a device isolation layer 14, and a gate trench 12T extending in the X direction parallel to the upper surface of the semiconductor substrate 11'. The channel region CH may have a relatively long island shape having a minor axis and a major axis. The major axis of the channel region CH may be arranged in the D3 direction parallel to the upper surface of the semiconductor substrate 11', such as... Figure 16 As shown in the image.

[0126] The gate trench 12T can be arranged to intersect the channel region CH at a certain depth from the upper surface of the semiconductor substrate 11', or it can be arranged within the channel region CH. The gate trench 12T can also be arranged within the device isolation trench 14T. The gate trench 12T within the device isolation trench 14T can have a bottom surface that is lower than the bottom surface of the gate trench 12T in the channel region CH. The first source / drain 11'ab and the second source / drain 11"ab can be arranged in the upper portion of the channel region CH located on both sides of the gate trench 12T.

[0127] The gate stack 12 can be disposed within the gate trench 12T. Specifically, the gate insulating layer 12a, the gate electrode 12b, and the gate capping layer 12c can be sequentially disposed within the gate trench 12T. The gate insulating layer 12a and the gate electrode 12b can be the same as described above, and the gate capping layer 12c can include at least one of the following: silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c can be disposed on the gate electrode 12b to fill the remaining portion of the gate trench 12T.

[0128] Bit line structure 13 may be disposed on the first source / drain 11'ab. Bit line structure 13 may be arranged parallel to the upper surface of semiconductor substrate 11' and extend in the Y direction. Bit line structure 13 may be electrically connected to the first source / drain 11'ab and may include bit line contacts 13a, bit lines 13b, and bit line capping layers 13c sequentially stacked on semiconductor substrate 11'. For example, bit line contacts 13a may include polysilicon, bit lines 13b may include a metallic material, and bit line capping layers 13c may include an insulating material, such as silicon nitride or silicon oxynitride.

[0129] although Figure 17 The bit line contact 13a is shown to have a bottom surface at the same level as the upper surface of the semiconductor substrate 11', but this is merely an example and the present disclosure is not limited thereto. For example, in at least one exemplary embodiment, a recess formed at a certain depth from the upper surface of the semiconductor substrate 11' may be further provided. The bit line contact 13a may extend into said recess such that the bottom surface of the bit line contact 13a is lower than the upper surface of the semiconductor substrate 11'.

[0130] The bit line structure 13 may further include a bit line interlayer (not shown) between the bit line contact 13a and the bit line 13b. The bit line interlayer may include a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride. Additionally, bit line spacers (not shown) may be further formed on the sidewalls of the bit line structure 13. The bit line spacers may have a single-layer or multi-layer structure and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. Furthermore, the bit line spacers may further include an air space (not shown).

[0131] Contact structure 20' may be disposed on second source / drain 11"ab. Contact structure 20' and bit line structure 13 may be disposed on different sources / drains on semiconductor substrate 11'. Contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on second source / drain 11"ab. Contact structure 20' may further include a barrier layer (not shown) surrounding the side and bottom surfaces of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metallic material, and the barrier layer may include a conductive metal nitride.

[0132] A capacitor CA3 may be disposed on a semiconductor substrate 11' and electrically connected to a contact structure 20'. Specifically, the capacitor CA3 includes: a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The first electrode 110 may have a cup shape or a cylindrical shape having an internal space with a closed bottom. The second electrode 140 may have a comb shape, having comb teeth extending into the internal space formed by the first electrode 110 and in the region between adjacent first electrodes 110. Additionally, the dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 140 parallel to the surfaces of the first electrode 110 and the second electrode 140. The conductive interface layer 120 may be disposed between the first electrode 110 and the dielectric layer 130 parallel to the surfaces of the first electrode 110 and the dielectric layer 130. Because the materials of the first electrode 110, conductive interface layer 120, dielectric layer 130, and second electrode 140 constituting capacitor CA3 are similar to those of the reference electrode... Figures 1 to 12 The capacitors 100 and 100a described are essentially the same, so their detailed description is omitted.

[0133] An interlayer insulating layer 15 may be further disposed between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating layer 15 may be disposed in the space between the capacitor CA3 and the semiconductor substrate 11' where no other structures are disposed. Specifically, the interlayer insulating layer 15 may be disposed to cover wiring and / or electrode structures, such as bit line structures 13, contact structures 20', and gate stacks 12 on the semiconductor substrate 11'. For example, the interlayer insulating layer 15 may surround the wall of the contact structure 20'. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contact 13a, and a second interlayer insulating layer 15b covering the side surfaces and / or top surfaces of the bit line 13b and the bit line capping layer 13c.

[0134] The first electrode 110 of capacitor CA3 may be disposed on interlayer insulating layer 15, particularly on second interlayer insulating layer 15b. Furthermore, when multiple capacitors CA3 are disposed, the bottom surfaces of the multiple first electrodes 110 may be separated from each other by an etch stop layer 16. In other words, the etch stop layer 16 may include an opening 16T, and the bottom surfaces of the first electrodes 110 of capacitor CA3 may be disposed within the opening 16T. As shown, the first electrode 110 may have a cup shape or a cylindrical shape having an internal space with a closed bottom. Capacitor CA3 may further include a support (not shown) to prevent the first electrode 110 from tilting or collapsing. The support may be disposed on the sidewall of the first electrode 110.

[0135] Figure 18 This is a cross-sectional view showing an electronic device 1004 according to at least one exemplary embodiment.

[0136] The cross-sectional view of the electronic device 1004 according to this embodiment corresponds to along... Figure 16 The cross-sectional view taken by line A-A', and Figure 18 Electronic devices 1004 and Figure 17 The electronic device 1003 differs only in the shape of the capacitor CA4. The capacitor CA4 is disposed on the semiconductor substrate 11' and electrically connected to the contact structure 20'. The capacitor CA4 includes: a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The materials of the first electrode 110, the conductive interface layer 120, the dielectric layer 130, and the second electrode 140 are consistent with reference to... Figures 1 to 12 The capacitors described, 100 and 100a, are essentially the same.

[0137] The first electrode 110 may have a cylindrical shape, such as a cylinder, square cylinder, or polygonal cylinder, extending in the vertical direction (Z direction). The second electrode 140 may have a comb shape, having comb teeth extending into the region between adjacent first electrodes 110. A dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 140, parallel to the surfaces of the first electrode 110 and the second electrode 140. A conductive interface layer 120 may be disposed between the first electrode 110 and the dielectric layer 130, parallel to the surfaces of the first electrode 110 and the dielectric layer 130.

[0138] The capacitors and electronic devices described in the above examples can be applied to a variety of application areas. For example, the electronic devices described in some examples can be used as logic devices or memory devices. The electronic devices described in some examples can be used for arithmetic operations, program execution, temporary data retention, etc., in devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices. Furthermore, the electronic devices described in some examples are useful for devices where large amounts of data are transmitted continuously.

[0139] Figure 19 and 20 It is a conceptual diagram schematically illustrating a device architecture that can be applied to a device according to at least one example implementation.

[0140] refer to Figure 19 The electronic device architecture 1100 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, ALU 1020, and control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1100 may be implemented as a single chip including the memory unit 1010, ALU 1020, and control unit 1030.

[0141] The storage unit 1010, ALU 1020, and control unit 1030 can be interconnected on-chip via metal wires for direct communication. The storage unit 1010, ALU 1020, and control unit 1030 can be integrated onto a single substrate to form a single chip. Input / output device 2000 can be connected to electronic device architecture (chip) 1100. Additionally, the storage unit 1010 may include both main memory and cache memory. Electronic device architecture (chip) 1000 may be an on-chip memory processing unit. The storage unit 1010 may include the capacitors described above and the electronic devices including them. The ALU 1020 or control unit 1030 may also include the aforementioned capacitors.

[0142] refer to Figure 20 The cache memory 1510, ALU 1520, and control unit 1530 may constitute a central processing unit (CPU) 1500. The cache memory 1510 may include static random access memory (SRAM). Separately from the CPU 1500, main memory 1600 and auxiliary memory 1700 may be provided. Main memory 1600 may be DRAM and may include the aforementioned capacitors. In some cases, the electronic device architecture may be implemented in a form where computing unit elements and storage unit elements are adjacent to each other on a single chip without being distinguished by sub-units.

[0143] The above examples and implementation methods can be summarized as follows, but are not limited thereto.

[0144] (1) A capacitor according to at least one example embodiment may include a first electrode, a second electrode facing the first electrode, a dielectric layer between the first electrode and the second electrode, and a conductive interface layer between the first electrode and the dielectric layer, wherein the dielectric layer may include a dielectric material having a rutile crystal phase, the dielectric layer may include a first intermediate layer and a second intermediate layer provided in the dielectric layer, the first intermediate layer may include an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In) and scandium (Sc), and the second intermediate layer includes an oxide of a group IVA metal element having a rutile crystal phase.

[0145] (2) The dielectric layer may include, for example, titanium oxide (TiO2) having a rutile crystal phase.

[0146] (3) The metal content of the first intermediate layer in the dielectric layer can be greater than 0 atomic% and about 20 atomic% or less.

[0147] (4) The second intermediate layer may include an oxide of at least one of germanium (Ge), silicon (Si) or tin (Sn).

[0148] (5) The metal content of the second intermediate layer in the dielectric layer may be, for example, about 0.1 atomic% or more and about 10 atomic% or less.

[0149] (6) The second intermediate layer may have a thickness of, for example, about 0.1 nm or greater and about 0.5 nm or less.

[0150] (7) The thickness of the second intermediate layer can be less than the thickness of the first intermediate layer.

[0151] (8) The gap between the conductive interface layer and the second intermediate layer may be, for example, 0.5 nm or greater.

[0152] (9) In one instance, a second intermediate layer may be provided in the dielectric layer between the first intermediate layer and the conductive interface layer.

[0153] (10) In another instance, the first intermediate layer may be provided in the dielectric layer between the second intermediate layer and the conductive interface layer.

[0154] (11) The conductive interface layer may include a first conductive interface layer between the first electrode and the dielectric layer, and a second conductive interface layer between the first conductive interface layer and the dielectric layer. The first conductive interface layer may include a conductive metal oxide material having a stable crystal structure in the rutile phase, and the conduction band offset between the second conductive interface layer and the dielectric layer may be greater than the conduction band offset between the first conductive interface layer and the dielectric layer.

[0155] (12) The first conductive interface layer may include molybdenum oxide (MoO2) doped with tin (Sn).

[0156] (13) The Sn doping concentration in the first conductive interface layer may be, for example, about 0.1 atomic% or more and about 10 atomic% or less.

[0157] (14) The first conductive interface layer may have a thickness of, for example, about 0.3 nm or more and about 4 nm or less.

[0158] (15) The second conductive interface layer may include a conductive metal oxide material having a stable crystal structure in the rutile phase.

[0159] (16) The second conductive interface layer may include tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (SnO2). x Ge 1-x O2, 0 <x<1)。

[0160] (17) The second conductive interface layer may have a thickness of, for example, about 0.3 nm or more and about 1 nm or less.

[0161] (18) The first electrode may include at least one conductive metal nitride selected from titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN) and cobalt nitride (CoN) or any combination thereof.

[0162] (19) An electronic device according to at least one example embodiment may include a transistor and a capacitor electrically connected to the transistor, wherein the capacitor may include a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer may include a dielectric material having a rutile crystal phase, the dielectric layer may include a first intermediate layer and a second intermediate layer provided in the dielectric layer, the first intermediate layer may include an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In) and scandium (Sc), and the second intermediate layer may include an oxide of a group IVA metal element having a rutile structure.

[0163] (20) An electronic device according to at least one example embodiment may include a transistor and a capacitor electrically connected to the transistor, wherein the capacitor may include a first electrode, a second electrode facing the first electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer may include a first metal oxide, a second metal oxide and a third metal oxide, the first metal oxide may include titanium oxide having a rutile phase, the second metal oxide may include an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In) and scandium (Sc), and the third metal oxide may include an oxide of at least one metal selected from germanium (Ge), silicon (Si) and tin (Sn).

[0164] (21) The contents of the second metal oxide and the third metal oxide in the dielectric layer can be different from each other.

[0165] (22) A method of manufacturing a capacitor according to at least one example embodiment may include: forming a conductive interface layer on a first electrode; forming a dielectric layer on the conductive interface layer, the dielectric layer including a first metal oxide, a second metal oxide and a third metal oxide; and forming a second electrode on the dielectric layer, wherein the first metal oxide may include titanium oxide having a rutile phase, the second metal oxide may include an oxide of at least one metal selected from aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In) and scandium (Sc), and the third metal oxide may include an oxide of at least one metal selected from germanium (Ge), silicon (Si) and tin (Sn).

[0166] In the case of the disclosed capacitor, the dielectric material of the rutile phase with a high dielectric constant can be formed by forming a conductive interface layer with a multilayer structure on a first electrode, and then forming a dielectric layer on the conductive interface layer. Therefore, the disclosed capacitor can be miniaturized and has high capacitance. Furthermore, according to some of the disclosed exemplary embodiments, leakage current can be reduced by using a conductive interface layer with a multilayer structure.

[0167] Furthermore, because the dielectric layer of the capacitor according to some exemplary embodiments includes an intermediate layer capable of trapping oxygen vacancies in the dielectric layer, leakage current can be further reduced by suppressing Fermi level pinning.

[0168] It should be understood that some exemplary embodiments have been described herein, and these embodiments should be considered in a descriptive sense only and are not intended to be limiting. The descriptions of features or aspects within each embodiment should typically be considered applicable to other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Capacitors, including: First electrode; The second electrode facing the first electrode; A dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a dielectric material having a rutile crystal phase; as well as A conductive interface layer between the first electrode and the dielectric layer The dielectric layer includes a first intermediate layer and a second intermediate layer in the dielectric material. The first intermediate layer comprises an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and The second intermediate layer comprises oxides of group IVA metals having a rutile crystal phase.

2. The capacitor according to claim 1, wherein the dielectric material of the dielectric layer comprises titanium oxide (TiO2) having a rutile crystal phase.

3. The capacitor according to claim 1, wherein the metal content of the first intermediate layer in the dielectric layer is greater than 0 atomic percentage (atomic %) and 20 atomic % or less.

4. The capacitor of claim 1, wherein the oxide of the second intermediate layer comprises at least one of germanium (Ge), silicon (Si), or tin (Sn).

5. The capacitor of claim 4, wherein the metal content of the second intermediate layer in the dielectric layer is 0.1 atomic percentage (atomic %) or greater and 10 atomic % or less.

6. The capacitor of claim 4, wherein the second intermediate layer has a thickness of 0.1 nanometers (nm) or greater and 0.5 nm or less.

7. The capacitor according to claim 4, wherein the thickness of the second intermediate layer is less than the thickness of the first intermediate layer.

8. The capacitor of claim 4, wherein the gap between the conductive interface layer and the second intermediate layer is 0.5 nanometers (nm) or greater.

9. The capacitor of claim 1, wherein the second intermediate layer is located between the first intermediate layer and the conductive interface layer, or The first intermediate layer is located between the second intermediate layer and the conductive interface layer.

10. The capacitor according to claim 1, wherein The conductive interface layer includes a first conductive interface layer between the first electrode and the dielectric layer, and a second conductive interface layer between the first conductive interface layer and the dielectric layer. The first conductive interface layer comprises a conductive metal oxide material having a stable crystal structure in the rutile phase, and The conduction band offset (CBO) between the second conductive interface layer and the dielectric layer is greater than the conduction band offset between the first conductive interface layer and the dielectric layer.

11. The capacitor of claim 10, wherein the first conductive interface layer comprises molybdenum oxide (MoO2) doped with tin (Sn).

12. The capacitor of claim 11, wherein the Sn doping concentration in the first conductive interface layer is 0.1 atomic% or greater and 10 atomic% or less.

13. The capacitor of claim 10, wherein the first conductive interface layer has a thickness of 0.3 nanometers (nm) or greater and 4 nm or less.

14. The capacitor of claim 10, wherein the second conductive interface layer comprises tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (SnO2). x Ge 1-x O2, 0 <x<1)。 15. The capacitor of claim 10, wherein the second conductive interface layer has a thickness of 0.3 nanometers (nm) or greater and 1 nm or less.

16. The capacitor of claim 1, wherein the first electrode comprises titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), cobalt nitride (CoN), or a combination thereof.

17. Electronic devices, including: transistor; and The capacitor electrically connected to the transistor, The capacitors mentioned above include First electrode, The second electrode facing the first electrode, and A dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a first metal oxide, a second metal oxide, and a third metal oxide. The first metal oxide includes titanium oxide having a rutile crystal phase. The second metal oxide includes an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and The third metal oxide includes an oxide of at least one of germanium (Ge), silicon (Si), or tin (Sn) having a rutile crystal phase.

18. The electronic device of claim 17, wherein the contents of the second metal oxide and the third metal oxide in the dielectric layer are different from each other.

19. The electronic device of claim 17, wherein the capacitor is as defined in any one of claims 1 to 16.

20. A method of manufacturing a capacitor, the method comprising: A conductive interface layer is formed on the first electrode; A dielectric layer is formed on the conductive interface layer, the dielectric layer comprising a first metal oxide, a second metal oxide, and a third metal oxide; and A second electrode is formed on the dielectric layer. The first metal oxide includes titanium oxide having a rutile crystal phase. The second metal oxide includes an oxide of at least one of aluminum (Al), gallium (Ga), yttrium (Y), lanthanum (La), boron (B), indium (In), or scandium (Sc), and The third metal oxide includes an oxide of at least one of germanium (Ge), silicon (Si), or tin (Sn).

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