Leakage protection device and electrical switching device

Abstract

The application discloses an electric leakage protection device and an electric switch device. The electric leakage protection device comprises an amplifier, a comparator and a pulse sequence generator. The amplifier is used for amplifying an input electric leakage signal to generate an amplified signal. The comparator is used for comparing the amplified signal with a preset reference signal to generate a comparison signal. The pulse sequence generator is used for outputting a pulse sequence signal. The pulse sequence signal comprises M pulse signals, and the duration of the pulse sequence signal is greater than the tripping time of a later-stage tripping device. The above scheme can accurately and stably trigger the tripping device to perform a tripping action, thereby improving the power supply safety.

Description

Technical Field

[0001] This invention relates to the field of leakage current protection technology, and in particular to a leakage current protection device and an electrical switching device. Background Technology

[0002] Residual current devices (RCDs) and electrical switching devices that include RCDs are widely used in household power supply circuits. When a leakage occurs in the power supply, the RCD promptly cuts off the power supply to prevent electric shock accidents.

[0003] A residual current device (RCD) typically consists of a magnetic core with windings and a control circuit. The windings sense the magnetic flux passing through them and generate an induced signal. The control circuit receives this induced signal and uses it to determine if a leakage current has occurred. Taking a typical household power supply as an example, under normal circumstances, the current in the live wire and the neutral wire is equal, the magnetic flux through the windings is zero, no induced signal is generated, and the control circuit does not operate. When a leakage current occurs, the current in the live wire and the neutral wire is unequal, the magnetic flux through the windings is not zero, thus generating an induced signal (leakage signal). The control circuit receives this leakage signal and controls the electrical switch to cut off the power supply to prevent accidents.

[0004] In practical applications, the duration of the control signal generated by the control circuit may be too short, making it impossible for the downstream tripping device (such as an electromagnetic relay switch) to trip accurately and stably, or even failing to trigger the downstream tripping device to perform the tripping action. In some cases, the duration of the control signal may be too long, causing the downstream tripping device (such as an electromagnetic relay switch) to perform the tripping operation for an extended period, reducing the product's lifespan, and possibly even burning out the tripping device. Summary of the Invention

[0005] The present invention aims to provide at least one leakage current protection device, comprising: an amplifier for amplifying an input leakage current signal to generate an amplified signal; a comparator for comparing the amplified signal with a preset reference signal to generate a comparison signal; and a pulse sequence generator adapted to output a pulse sequence signal, wherein the pulse sequence signal comprises M pulse signals, and the duration of the pulse sequence signal is greater than the tripping time of the subsequent tripping device; M is a positive integer and M≥2.

[0006] The comparator compares the amplified signal with the reference signal, and the resulting comparison signal is input to the pulse sequence generator. Based on the input comparison signal, the pulse sequence generator generates a pulse sequence signal and outputs it to the subsequent tripping device. The duration of the pulse sequence signal output by the pulse sequence generator is longer than the tripping time of the subsequent tripping device. Driven by the pulse sequence signal, the tripping device generates a continuous tripping impact force, accelerating the tripping process. This ensures accurate and stable triggering of the tripping device in the event of leakage. Furthermore, by setting the value of M, the duration of the pulse sequence signal can be precisely controlled, preventing damage to the tripping device due to excessively long pulse sequence signal duration.

[0007] Optionally, the pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N D flip-flops, wherein: the first input of the OR gate is coupled to the first output of the Nth D flip-flop, the second input of which receives the comparison signal, and the output of the OR gate is coupled to the first input of the first AND gate; the second input of the first AND gate receives a clock signal, and the output of the first AND gate is coupled to the clock signal input of the first D flip-flop; the data input of the i-th D flip-flop is coupled to its second output, and its first output is coupled to the clock signal input of the (i+1)-th D flip-flop; i is a positive integer and 1≤i≤N-1; the first input of the second AND gate is coupled to the first output of the Nth D flip-flop, the second input of the second AND gate is coupled to the first output of the first D flip-flop, and the output of the pulse sequence signal.

[0008] Optionally, the pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N T flip-flops, wherein: the first input of the OR gate is coupled to the first output of the Nth T flip-flop, the second input of which receives the comparison signal, and the output of the OR gate is coupled to the first input of the first AND gate; the second input of the first AND gate receives a clock signal, and the output of the first AND gate is coupled to the clock signal input of the first T flip-flop; the control input of the i-th T flip-flop is set to a high level, and the first output of the i+1-th T flip-flop is coupled to the clock signal input of the i-th T flip-flop; i is a positive integer and 1≤i≤N-1; the first input of the second AND gate is coupled to the first output of the Nth T flip-flop, the second input of the second AND gate is coupled to the first output of the first AND flip-flop, and the output of the pulse sequence signal.

[0009] Optionally, the pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N JK flip-flops, wherein: the first input of the OR gate is coupled to the first output of the Nth JK flip-flop, the second input of which receives the comparison signal, and the output of the OR gate is coupled to the first input of the first AND gate; the second input of the first AND gate receives a clock signal, and the output of the first AND gate is coupled to the clock signal input of the first JK flip-flop; the first input of the i-th JK flip-flop is coupled to its second input and set to a high level, and the first output of the i+1-th JK flip-flop is coupled to the clock signal input of the i-th JK flip-flop; i is a positive integer and 1≤i≤N-1; the first input of the second AND gate is coupled to the first output of the Nth JK flip-flop, the second input of the second AND gate is coupled to the first output of the first JK flip-flop, and the output of the pulse sequence signal.

[0010] Optionally, the pulse sequence generator is also adapted to not respond to a new comparison signal output by the comparator during the output of the pulse sequence signal.

[0011] Optionally, the pulse sequence signal is a current signal or a voltage signal.

[0012] Optionally, the pulse width of the pulse signal is equal to the pulse width of the comparison signal.

[0013] Optionally, the leakage protection device further includes: a rectifier, which receives the amplified signal at its input terminal and rectifies the amplified signal to generate a rectified signal; a filter, which receives the rectified signal at its input terminal and outputs a filtered signal to the comparator at its output terminal; the comparator is adapted to compare the filtered signal with the reference signal to generate the comparison signal.

[0014] Secondly, the present invention also provides an electrical switching device, including any of the leakage protection devices described above. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a leakage current protection device according to an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the structure of a pulse sequence generator according to an embodiment of the present invention;

[0017] Figure 3 yes Figure 2 The timing diagram of the pulse sequence generator provided in the document;

[0018] Figure 4 This is a schematic diagram of another pulse sequence generator in an embodiment of the present invention;

[0019] Figure 5 yes Figure 4 The timing diagram of the pulse sequence generator provided in the document;

[0020] Figure 6 This is a schematic diagram of another leakage current protection device in an embodiment of the present invention. Detailed Implementation

[0021] In existing residual current devices (RCDs), the pulse width of the control signal is proportional to the pulse width of the comparison signal. However, in practical applications, the waveform of the residual current signal is uncertain and varies considerably, leading to significant differences in the pulse width of the comparison signal. When the pulse width of the comparison signal is too small, it may prevent the downstream tripping device from performing a tripping action, creating a safety hazard.

[0022] In this embodiment of the invention, the comparison signal generated by the comparator is input to the pulse sequence generator. Based on the input comparison signal, the pulse sequence generator generates a pulse sequence signal and outputs it to the subsequent tripping device. The duration of the pulse sequence signal output by the pulse sequence generator is greater than the tripping time of the subsequent tripping device. Driven by the pulse sequence signal, the tripping device generates a continuous tripping impact force, accelerating the tripping process. This ensures that the tripping device can be accurately and stably triggered to perform the tripping action in the event of leakage. Furthermore, by setting the value of M, the duration of the pulse sequence signal can be precisely controlled, preventing the tripping device from being damaged due to an excessively long pulse sequence signal duration.

[0023] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] This invention provides a leakage current protection device, referring to... Figure 1 .

[0025] In this embodiment of the invention, the leakage current protection device includes an amplifier 11, a comparator 12, and a pulse sequence generator 13. The amplifier 11, comparator 12, and pulse sequence generator 13 can be integrated on the same chip, or they can be separately disposed on different chips.

[0026] In a specific implementation, a leakage signal is input to the input terminal of amplifier 11, and the output terminal of amplifier 11 is coupled to one input terminal of comparator 12; amplifier 11 can amplify the input leakage signal to generate an amplified signal.

[0027] The leakage signal input to amplifier 11 can originate from winding 15 wound around a toroidal iron core 14. The power supply line passes through the iron core 14. When leakage occurs, the magnetic flux through winding 15 changes, generating a leakage signal which is input to amplifier 11. Amplifier 11 amplifies the leakage signal to produce an amplified signal.

[0028] In some embodiments, amplifying the leakage signal may refer to amplifying the voltage value of the leakage signal.

[0029] In specific implementations, the amplifier 11 mentioned above can be a feedback amplifier circuit structure based on an operational amplifier, or other devices or circuits capable of amplification.

[0030] Comparator 12 may include two input terminals, one of which is a reference signal and the other is an amplified signal; comparator 12 compares the reference signal and the amplified signal and outputs a comparison signal.

[0031] In practice, the aforementioned reference signal (also known as a reference signal) can be a voltage signal with a fixed voltage value, generated and output by a preset reference voltage generating device.

[0032] The pulse sequence generator 13 takes a comparison signal as input and outputs a pulse sequence signal when the comparison signal indicates that the amplified signal is greater than the reference signal (i.e., there is leakage current). The pulse sequence signal includes M pulse signals, and the duration of the pulse sequence signal is greater than the tripping time of the tripping device. M is a positive integer and M≥2.

[0033] In practical implementation, the aforementioned tripping device can be coupled to the output terminal of the pulse sequence generator 13. The tripping time of the tripping device can refer to the time required for the tripping device to go from the on state to the off state. That is to say, during the duration of the pulse sequence signal, the tripping device generates a continuous tripping impact force under the drive of the pulse sequence signal, which accelerates the tripping process, makes the tripping process more stable, and realizes leakage protection for downstream loads.

[0034] In this embodiment of the invention, the duration of the pulse sequence signal can be greater than or equal to at least half a cycle of the power supply signal, and covers half a cycle of the tripping device. Taking a 50Hz AC power supply as an example, the tripping action usually occurs during the positive half cycle of the power supply, so the duration of the pulse sequence signal can be greater than 10ms, and covers the positive half cycle of the power supply signal.

[0035] The duration of the pulse sequence signal can be less than a preset value. For example, the duration of the pulse sequence signal can be preset to be less than or equal to two cycles of the power signal. Alternatively, the duration of the pulse sequence signal can be preset to be less than or equal to one cycle of the power signal. These preset values ​​can also be set based on the actual application scenario.

[0036] In some embodiments, the duration of the pulse sequence signal is 20 ms. In other embodiments, the duration of the pulse sequence signal is 40 ms.

[0037] In specific implementations, the aforementioned pulse sequence signal can be a voltage signal or a current signal. The pulse width of the aforementioned pulse sequence signal can be equal to or unequal to the pulse width of the comparison signal.

[0038] In this embodiment of the invention, if the pulse sequence generator 13 receives a new comparison signal output by the comparator 12 during the output of the pulse sequence signal, the pulse sequence generator 13 may not respond to the new comparison signal to ensure the stability of a single tripping process.

[0039] In this embodiment of the invention, the pulse sequence generator 13 may include an OR gate, a first AND gate, a second AND gate, and a digital counter. The input terminal of the digital counter can receive a clock signal, and the digital counter can be used to count the number of cycles of the clock signal.

[0040] In practical implementation, a counting threshold can be preset. When the count value of the digital counter has not reached the counting threshold, the output terminal of the digital counter outputs a high level; when the count value of the digital counter reaches the counting threshold, the output terminal of the digital counter outputs a low level. When the output terminal of the digital counter outputs a high level, the pulse sequence generator 13 continuously outputs a pulse sequence signal; when the output terminal of the digital counter outputs a low level, the pulse sequence generator 13 stops outputting the pulse sequence signal.

[0041] In other words, the duration of the pulse sequence signal is determined by a preset counting threshold and the period of the clock signal. Specifically, the duration of the pulse sequence signal is the product of the counting threshold and the period of the clock signal.

[0042] Therefore, the duration of the pulse sequence signal can be adjusted by adjusting the counting threshold and / or the period of the clock signal.

[0043] In practice, the aforementioned clock signal can be provided by a preset oscillator (such as a crystal oscillator or an RC oscillator). By adjusting the relevant parameters of the oscillator (such as adjusting the resistance and capacitance of the RC oscillator), the period of the output clock signal can be adjusted, thereby adjusting the duration of the pulse sequence signal.

[0044] In practical implementation, a digital counter can consist of N flip-flops. The counting threshold is 2. N -1. By setting the number of triggers N, the corresponding counting threshold can be obtained, thus enabling the adjustment of the counting threshold.

[0045] The pulse sequence generator 13 provided in the embodiments of the present invention will be described in detail below.

[0046] In a specific implementation, the pulse sequence generator 13 may include: an OR gate circuit, a first AND gate circuit, a second AND gate circuit, and N D flip-flops connected in series; wherein:

[0047] The first input terminal of the OR gate is coupled to the first output terminal of the Nth D flip-flop, and the second input terminal of the OR gate is coupled to the output terminal of comparator 12 to input a comparison signal. The output terminal of the OR gate is coupled to the first input terminal of the first AND gate.

[0048] The clock signal is input to the second input terminal of the first AND gate circuit, and the output terminal of the first AND gate circuit is coupled to the clock signal input terminal of the first D flip-flop.

[0049] The data input terminal D of the i-th D flip-flop is coupled to its second output terminal Qn, and the first output terminal Q of the i-th D flip-flop is coupled to the clock signal input terminal of the (i+1)-th D flip-flop; i is a positive integer and 1≤i≤N-1; for the N-th D flip-flop, its first output terminal Q is coupled to the first input terminal of the second AND gate circuit.

[0050] The second input terminal of the second AND gate circuit is coupled to the first output terminal of the first D flip-flop, and the output terminal of the second AND gate circuit outputs a pulse sequence signal.

[0051] A digital counter is constructed using N D flip-flops. The input of the digital counter is the clock signal CLK, and the output of the digital counter is the first output of the Nth D flip-flop.

[0052] Reference Figure 2 A schematic diagram of the structure of a pulse sequence generator 13 in an embodiment of the present invention is provided. Figure 2In this example, N=8, the first D flip-flop is DFF0, the second D flip-flop is DFF1, ..., the eighth D flip-flop is DFF7. These eight D flip-flops form a digital counter with a counting range of 0 to 255. The digital counter counts from 0 to 255 and then resets to zero. After resetting, the output signal of the digital counter is low.

[0053] The first input terminal of OR gate OR1 is coupled to the first output terminal Q7 of DFF7, the second input terminal of OR gate OR1 receives the comparison signal IN, and the output terminal of OR gate OR1 is coupled to the output terminal of the first AND gate AND1.

[0054] The second input terminal of the first AND gate AND1 receives the clock signal CLK, and the output terminal of the first AND gate AND1 is coupled to the clock signal input terminal clk of DFF0.

[0055] The first output terminal Q of DFF0 is coupled to the clock signal input terminal clk of DFF1, and the output signal is Q0; the second output terminal Qn of DFF0 is coupled to the data input terminal D of DFF0.

[0056] The first output terminal Q of DFF1 outputs a signal Q1, which is coupled to the clock signal input terminal clk of DFF2; the second output terminal Qn of DFF1 is coupled to the data input terminal Q of DFF1; the connection relationship of DFF2 to DFF6 can be referred to the connection of DFF1.

[0057] Correspondingly, the clock signal input terminal clk of DFF7 is coupled to the first output terminal of DFF6, and the second output terminal Qn of DFF7 is coupled to the data input terminal D of DFF7; the first output terminal Q of DFF1 outputs a signal Q7, which is coupled to the first input terminal of the second AND gate circuit AND2.

[0058] The second input terminal of the second AND gate AND2 is coupled to the first input terminal Q of DFF0, and the input is Q0; the output OUT of the second AND gate AND2 is the pulse sequence signal.

[0059] The aforementioned D flip-flops may also include a reset terminal, Reset. When the reset signal Reset is input, each flip-flop is reset.

[0060] The following is a summary of the above. Figure 2 The working principle and process of the pulse sequence generator 13 provided in the document are explained. (Refer to...) Figure 3 It gave Figure 2 The timing diagram of the pulse sequence generator provided is shown below. Figure 2 and Figure 3 Please provide an explanation.

[0061] When the comparison signal IN transitions from low to high, the output of OR gate OR1 becomes high. The second input of the first AND gate AND1 receives the clock signal CLK, which is then input to the clock signal input clk of DFF0 via the output of AND1. When the rising edge of clock signal CLK arrives, the output voltages of the Q terminals of DFF0 through DFF7 sequentially become high, and the digital counter begins counting. Before the count value reaches the preset counting threshold, the high level of Q7 keeps the output of OR gate OR1 high, ensuring continuous input of clock signal CLK to the digital counter, which continues counting.

[0062] During continuous counting, the output signal Q0 of the first output terminal of DFF0 is input to the second AND gate circuit AND2. Q0 and Q7 are ANDed to output a pulse sequence signal.

[0063] When the count value of the digital counter reaches the preset count threshold, the output signal Q7 of the first output terminal of DFF7 goes low, or the output of gate OR1 goes low, and the output of the first AND gate AND1 remains low. At the same time, the low level output of Q7 keeps the output of the second AND gate AND2 low.

[0064] Thus, the pulse sequence generator 13 described above can output M pulse signals.

[0065] In a specific implementation, the aforementioned digital counter can be composed of N T flip-flops. Correspondingly, the pulse sequence generator 13 may include: an OR gate, a first AND gate, a second AND gate, and N T flip-flops, wherein:

[0066] The first input terminal of the OR gate is coupled to the first output terminal of the Nth T flip-flop, and the second input terminal of the OR gate receives the comparison signal. The output terminal of the OR gate is coupled to the first input terminal of the first AND gate.

[0067] The clock signal is input to the second input terminal of the first AND gate circuit, and the output terminal of the first AND gate circuit is coupled to the clock signal input terminal of the first T flip-flop.

[0068] The control input of the i-th T flip-flop is set to high level, and the first output of the i-th T flip-flop is coupled to the clock signal input of the (i+1)-th T flip-flop; i is a positive integer and 1≤i≤N-1;

[0069] The first input terminal of the second AND gate is coupled to the first output terminal of the Nth T flip-flop, the second input terminal of the second AND gate is coupled to the first output terminal of the 1st T flip-flop, and the output terminal of the second AND gate outputs a pulse sequence signal.

[0070] Reference Figure 4 The present invention provides a schematic diagram of another pulse sequence generator 13 in an embodiment of the present invention. Figure 4 In this configuration, N=8, the first T flip-flop is TFF0, the second T flip-flop is TFF1, ..., the eighth T flip-flop is TFF7. The control input terminal T of TFF0 to TFF7 is all input with a high level "1".

[0071] The first input terminal of OR gate OR1 is coupled to the first output terminal Q7 of TFF7, the second input terminal of OR gate OR1 receives the comparison signal IN, and the output terminal of OR gate OR1 is coupled to the output terminal of the first AND gate AND1.

[0072] The second input terminal of the first AND gate AND1 receives the clock signal CLK, and the output terminal of the first AND gate AND1 is coupled to the clock signal input terminal clk of TFF0.

[0073] The first output terminal Q of TFF0 is coupled to the clock signal input terminal clk of TFF1, and the output signal is Q0; the second output terminal Qn of TFF0 is set to empty.

[0074] The first output terminal Q of TFF1 outputs a signal Q1, which is coupled to the clock signal input terminal clk of TFF2; the second output terminal Qn of TFF1 is set to empty; the connection relationship of TFF2 to TFF6 can be referred to the connection of TFF1.

[0075] Correspondingly, the clock signal input terminal clk of TFF7 is coupled to the first output terminal of TFF6, and the second output terminal Qn of TFF7 is set to empty; the first output terminal Q of TFF1 outputs a signal of Q7, which is coupled to the first input terminal of the second AND gate circuit AND2.

[0076] The second input terminal of the second AND gate AND2 is coupled to the first input terminal Q of TFF0, and the input is Q0; the output OUT of the second AND gate AND2 is the pulse sequence signal.

[0077] The aforementioned T flip-flops may also include a reset terminal (Reset). When the reset signal (Reset) is input, each flip-flop is reset.

[0078] The following is a summary of the above. Figure 4 The working principle and process of the pulse sequence generator 13 provided in the document are explained. (Refer to...) Figure 5 It gave Figure 4 The timing diagram of the pulse sequence generator provided is shown below. Figure 4 and Figure 5 Please provide an explanation.

[0079] When the comparison signal IN transitions from low to high, the output of OR gate OR1 is high. The second input of the first AND gate AND1 receives the clock signal CLK, which is then input to the clock signal input clk of TFF0 via the output of AND1. When the rising edge of clock signal CLK arrives, the output voltages of the Q terminals of TFF0 to TFF7 sequentially become high, and the digital counter begins counting. Before the count value reaches the preset counting threshold, the high level of Q7 keeps the output of OR gate OR1 high, and clock signal CLK continues to be input to the digital counter, allowing it to continue counting.

[0080] During continuous counting, the output signal Q0 of the first output terminal of TFF0 is input to the second AND gate circuit AND2. Q0 and Q7 are ANDed to output a pulse sequence signal.

[0081] When the count value of the digital counter reaches the preset count threshold, the output signal Q7 of the first output terminal of TFF7 goes low, or the output of gate OR1 goes low, and the output of the first AND gate AND1 remains low. At the same time, the low level output of Q7 keeps the output of the second AND gate AND2 low.

[0082] Thus, the pulse sequence generator 13 described above can output M pulse signals.

[0083] In a specific implementation, the pulse sequence generator 13 described above can also be composed of N JK flip-flops. The first input terminal (J terminal) of the N JK flip-flops can be connected to the second input terminal (K terminal) to make the JK flip-flops serve as the aforementioned T flip-flops, with both the first input terminal (J terminal) and the second input terminal (K terminal) of the JK flip-flops receiving a high level input.

[0084] Specifically, the first input terminal of the OR gate is coupled to the first output terminal of the Nth JK flip-flop, the second input terminal of the OR gate receives the comparison signal, and the output terminal of the OR gate is coupled to the first input terminal of the first AND gate.

[0085] The clock signal is input to the second input terminal of the first AND gate circuit, and the output terminal of the first AND gate circuit is coupled to the clock signal input terminal of the first JK flip-flop.

[0086] The first input terminal of the Nth JK flip-flop is connected to the second input terminal and both are set to high level. The first output terminal of the i-th JK flip-flop is coupled to the clock signal input terminal of the (i+1)-th JK flip-flop. i is a positive integer and 1≤i≤N-1.

[0087] The first input terminal of the second AND gate is coupled to the first output terminal of the Nth JK flip-flop, the second input terminal of the second AND gate is coupled to the first output terminal of the 1st JK flip-flop, and the output terminal of the second AND gate outputs a pulse sequence signal.

[0088] Specifically, the working principle and process of the pulse sequence generator 13, which is composed of JK flip-flops and T flip-flops, can be referred to the pulse sequence generator 13, which is composed of T flip-flops and digital counters, as described above. It will not be repeated here.

[0089] In this embodiment of the invention, the leakage current protection device may further include a rectifier 16 and a filter 17. (See reference...) Figure 6 Another leakage protection device is provided in the embodiments of the present invention.

[0090] In a specific implementation, the input terminal of rectifier 16 is coupled to the output terminal of amplifier 11, and the output terminal of rectifier 16 is coupled to the input terminal of filter 17, which is suitable for rectifying the input amplified signal to obtain a rectified signal.

[0091] The output of filter 17 is coupled to one input of comparator 12 to filter the rectified signal and obtain the filtered signal.

[0092] The other input of comparator 12 is a reference signal, which is compared with the filtered signal to obtain a comparison signal.

[0093] In practical implementation, the rectifier 16 can be used to rectify the amplified signal, adjust the waveform and voltage amplitude range of the amplified signal, and generate a rectified signal.

[0094] Filter 17 can filter the rectified signal to remove interference noise.

[0095] In practical implementation, the residual current device (RCD) may also include a driver. A pulse sequence signal is input to the driver, which generates a drive signal, which then drives the subsequent tripping device. The driver can be a current driver or a voltage driver.

[0096] In practical implementation, the leakage current protection device may also include a time delay device, which delays the comparison signal before inputting it into the pulse sequence generator.

[0097] This invention also provides an electrical switching device, including the leakage protection device provided in any of the above embodiments.

[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A leakage current protection device, characterized in that, include: An amplifier amplifies the input leakage signal to generate an amplified signal. A comparator compares the amplified signal with a preset reference signal to generate a comparison signal; A pulse sequence generator is adapted to output a pulse sequence signal, the pulse sequence signal comprising M pulse signals, and the duration of the pulse sequence signal being longer than the tripping time of the subsequent tripping device; M is a positive integer and M≥2.

2. The leakage current protection device as described in claim 1, characterized in that, The pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N D flip-flops, wherein: the first input terminal of the OR gate is coupled to the first output terminal of the Nth D flip-flop, the second input terminal of the OR gate receives the comparison signal, and the output terminal is coupled to the first input terminal of the first AND gate; the second input terminal of the first AND gate receives a clock signal, and the output terminal is coupled to the clock signal input terminal of the first D flip-flop; The i-th D flip-flop has its data input coupled to its second output, and its first output coupled to the clock signal input of the (i+1)-th D flip-flop; i is a positive integer and 1≤i≤N-1; The second AND gate circuit has its first input terminal coupled to the first output terminal of the Nth D flip-flop, its second input terminal coupled to the first output terminal of the 1st D flip-flop, and its output terminal outputting the pulse sequence signal.

3. The leakage current protection device as described in claim 1, characterized in that, The pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N T flip-flops, wherein: the first input terminal of the OR gate is coupled to the first output terminal of the Nth T flip-flop, the second input terminal of the OR gate receives the comparison signal, and the output terminal is coupled to the first input terminal of the first AND gate; the second input terminal of the first AND gate receives a clock signal, and the output terminal is coupled to the clock signal input terminal of the first T flip-flop; The i-th T flip-flop has its control input set to high level, and its first output is coupled to the clock signal input of the (i+1)-th T flip-flop; i is a positive integer and 1≤i≤N-1; The second AND gate circuit has its first input terminal coupled to the first output terminal of the Nth T flip-flop, its second input terminal coupled to the first output terminal of the 1st T flip-flop, and its output terminal outputting the pulse sequence signal.

4. The leakage current protection device as described in claim 1, characterized in that, The pulse sequence generator includes: an OR gate, a first AND gate, a second AND gate, and N JK flip-flops, wherein: the first input terminal of the OR gate is coupled to the first output terminal of the Nth JK flip-flop, the second input terminal of the OR gate receives the comparison signal, and the output terminal is coupled to the first input terminal of the first AND gate; the second input terminal of the first AND gate receives a clock signal, and the output terminal is coupled to the clock signal input terminal of the first JK flip-flop; The i-th JK flip-flop has its first input terminal coupled to its second input terminal and set to a high level, and its first output terminal coupled to the clock signal input terminal of the (i+1)-th JK flip-flop; i is a positive integer and 1≤i≤N-1; the second AND gate has its first input terminal coupled to the first output terminal of the N-th JK flip-flop, its second input terminal coupled to the first output terminal of the 1st JK flip-flop, and its output terminal outputs the pulse sequence signal.

5. The leakage current protection device as described in claim 1, characterized in that, The pulse sequence generator is also adapted not to respond to a new comparison signal output by the comparator during the output of the pulse sequence signal.

6. The leakage current protection device as described in claim 1, characterized in that, The pulse sequence signal is a current signal or a voltage signal.

7. The leakage current protection device as described in claim 1, characterized in that, The pulse width of the pulse signal is equal to the pulse width of the comparison signal.

8. The leakage current protection device as described in any one of claims 1 to 6, characterized in that, Also includes: A rectifier receives the amplified signal at its input terminal and rectifies the amplified signal to generate a rectified signal; a filter receives the rectified signal at its input terminal and outputs a filtered signal to the comparator at its output terminal; the comparator is adapted to compare the filtered signal with the reference signal to generate the comparison signal.

9. An electrical switching device, characterized in that, include: The leakage current protection device as described in any one of claims 1 to 8.

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