A predictive control method and device for a voltage source type three-phase AC-DC converter

Abstract

The present application relates to the field of power electronic converter, especially to a kind of voltage source type three-phase AC-DC converter's prediction control method and device, method is by in the kth prediction step sampling input voltage, grid current, output voltage, and obtains the switching vector sequence of the k+1th prediction step, realized the prediction of the k+1th prediction step output voltage and grid current;By constructing the switching vector sequence to be measured, in combination with the k+1th prediction step output voltage and grid current, realize the prediction of the k+2th prediction step grid current and output voltage corresponding to the switching vector sequence to be measured, on this basis, in combination with the cost function constructed in advance, the switching vector sequence to be measured obtained by construction is screened, and the optimal switching vector sequence is obtained, and the optimal voltage vector is applied to the target converter in the next control cycle, improve the control precision of target converter, improve the dynamic response performance of converter.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter technology, and in particular to a predictive control method and apparatus for a voltage source type three-phase AC / DC converter. Background Technology

[0002] With the development of renewable energy systems such as offshore wind power, the demand for high-power-density and high-reliability power conversion devices is becoming increasingly urgent. Among them, isolated AC-DC converters are the core equipment of such systems. Traditional solutions adopt a two-stage structure of "three-phase rectifier + isolated DC-DC converter". The intermediate DC bus requires a large-capacity electrolytic capacitor to suppress power ripple, but the electrolytic capacitor is precisely the weak link in the system reliability.

[0003] To eliminate electrolytic capacitors and achieve single-stage power conversion, isolated matrix converters (IAMCs) have become a research hotspot. IAMCs achieve electrical isolation and voltage matching through high-frequency transformers (HFTs), eliminating the need for intermediate DC energy storage. However, traditional IAMC topologies commonly employ bidirectional power switches (typically composed of two anti-parallel MOSFETs or IGBTs), which introduces additional conduction losses. Furthermore, to prevent open-circuit or short-circuit faults during commutation, the extremely complex four-step commutation problem needs to be addressed. To mitigate these problems as much as possible, appropriate control strategies are required for IAMCs. Existing technologies improve the hardware topology to decouple the circuit, thereby avoiding the complex commutation problems caused by bidirectional power switches. However, their control strategies still employ traditional linear control methods, resulting in limited dynamic response performance and low control accuracy. Summary of the Invention

[0004] This invention provides a predictive control method and apparatus for a voltage source three-phase AC / DC converter, which solves the technical problems of limited dynamic response performance and low control accuracy in existing control methods.

[0005] This invention provides a predictive control method for a voltage source type three-phase AC / DC converter, comprising:

[0006] S1. Obtain the input voltage of the target converter in the synchronous coordinate system, the grid current at the kth prediction step, and the switching vector sequence at the (k+1)th prediction step; and obtain the output voltage of the target converter at the kth prediction step.

[0007] S2. Determine the output voltage and grid current of the (k+1)th prediction step based on the output voltage of the kth prediction step, the grid current of the kth prediction step, the input voltage, and the switching vector sequence;

[0008] S3. Obtain the switching state corresponding to each voltage vector of the target converter, determine the target voltage vector pair of the target converter based on the switching state corresponding to each voltage vector and the grid current of the (k+1)th prediction step, and form a target vector set from each target voltage vector pair;

[0009] S4. Select a pair of target voltage vectors from the target vector set, and construct a corresponding test switch vector sequence using the target voltage vector pair and the zero vector of the target converter;

[0010] S5. Based on the vector sequence of the switch to be tested, the input voltage, the output voltage of the (k+1)th prediction step, and the grid current of the (k+1)th prediction step, determine the grid current of the (k+2)th prediction step and the output voltage of the (k+2)th prediction step.

[0011] S6. Input the grid current and the output voltage of the (k+2)th prediction step into the pre-constructed cost function to obtain the cost function value;

[0012] S7. Jump to execute S4 to S7 until the cost function values ​​corresponding to all the switch vector sequences to be tested have been calculated. Output the switch vector sequence to be tested corresponding to the minimum cost function value among all cost function values ​​as the optimal switch vector sequence, and apply the optimal switch vector sequence to the target converter of the (k+2)th prediction step.

[0013] Optionally, the switch vector sequence includes multiple sub-intervals ordered according to a preset time sequence, each sub-interval corresponding to a switch state, and S2 includes:

[0014] S21. Read the switch status of one of the sub-intervals in sequence;

[0015] S22. Input the output voltage of the kth prediction step into a preset first mapping relationship to obtain the first reconstructed output voltage; and input the input voltage, the output voltage of the kth prediction step, and the switching state of the sub-interval into a preset second mapping relationship to obtain the first reconstructed grid voltage.

[0016] S23. Input the first recombined output voltage, the input voltage, and the grid current at the kth prediction step into a preset third mapping formula to obtain the second recombined output voltage; and input the second recombined output voltage into the first mapping formula to perform an inverse operation to obtain the second output voltage.

[0017] S24. Input the first reconstructed grid voltage and the grid current at the kth prediction step into the preset fourth mapping formula to obtain the second grid current;

[0018] S25. Replace the second output voltage with the output voltage of the kth prediction step size, and replace the second grid current with the grid current of the kth prediction step size;

[0019] S26. Jump to execute S21 to S25 until the switch status of all sub-intervals has been read. Output the second output voltage as the output voltage of the (k+1)th prediction step size, and output the second grid current as the grid current of the (k+1)th prediction step size.

[0020] Optionally, determining the target voltage vector pair of the target converter based on the switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step includes:

[0021] The switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step are input into the preset output current relationship to obtain each output current value.

[0022] The output current value that is not less than zero among the aforementioned output current values ​​shall be taken as the target current value;

[0023] The voltage vector corresponding to the target current value is taken as the target voltage vector;

[0024] According to the preset combination rules, the target voltage vectors are combined in pairs to obtain target voltage vector pairs.

[0025] Optionally, the switch vector sequence to be tested includes multiple sub-intervals to be tested ordered according to a preset time sequence, each sub-interval to be tested corresponding to a switch state, and S5 includes:

[0026] S51. Read the switch status of one of the sub-intervals to be tested in sequence;

[0027] S52. Input the output voltage of the (k+1)th prediction step and the switching state of the sub-interval to be tested into a preset first mapping relationship to obtain the fifth reconstructed output voltage; and input the input voltage, the output voltage of the (k+1)th prediction step and the switching state of the sub-interval to be tested into a preset second mapping relationship to obtain the fifth reconstructed grid voltage.

[0028] S53. Input the fifth recombined output voltage, the input voltage, and the grid current at the (k+1)th prediction step into a preset third mapping formula to obtain the sixth recombined output voltage; and input the sixth recombined output voltage into the first mapping formula to perform an inverse operation to obtain the sixth output voltage.

[0029] S54. Input the fifth reconstructed grid voltage and the grid current at the (k+1)th prediction step into the preset fourth mapping formula to obtain the sixth grid current.

[0030] S55. Replace the sixth output voltage with the output voltage of the (k+1)th prediction step, and replace the sixth grid current with the grid current of the (k+1)th prediction step;

[0031] S56. Jump to execute S51 to S55 until the switch status of all sub-intervals under test has been read. Output the sixth output voltage as the output voltage of the (k+2)th prediction step size, and output the sixth grid current as the grid current of the (k+2)th prediction step size.

[0032] Optionally, constructing the corresponding switch vector sequence under test using the target voltage vector pair and the zero vector of the target converter includes:

[0033] The duration of the zero vector and the duration of each voltage vector in the target voltage vector pair are determined and used as the test sub-intervals of the switch vector sequence to be tested;

[0034] The order of action of each voltage vector in the zero vector and target voltage vector pair of the target converter is obtained, and each sub-interval to be tested is sorted in turn according to the order of action to obtain the sequence of switch vectors to be tested.

[0035] Optionally, the third mapping relation and the fourth mapping relation constitute the decoupled discrete state-space model of the target transformer; wherein, the construction process of the decoupled discrete state-space model includes:

[0036] Construct the initial mathematical model and power model of the target converter in the synchronous coordinate system;

[0037] Construct the first mapping relation and the second mapping relation;

[0038] Based on the power model, the first mapping relationship, and the second mapping relationship, the initial mathematical model is simplified to obtain the target mathematical model;

[0039] The forward Euler method is used to convert the target mathematical model into a discrete state-space model;

[0040] Eliminating the coupling terms in the discrete state-space model yields a decoupled discrete state-space model.

[0041] Optionally, the cost function is:

[0042] ;

[0043] Where g is the cost function value, and λ1 is the first weight coefficient. i is the reference value for the d-axis component of the grid current. d(k+2) represents the d-axis component of the grid current with a prediction step size of k+2. i is the reference value for the q-axis component of the grid current. q (k+2) represents the q-axis component of the grid current with a prediction step size of k+2, and λ2 is the second weighting coefficient. u is the reference value for the DC output voltage. o (k+2) represents the output voltage with a prediction step size of k+2.

[0044] Optionally, the first mapping relationship is:

[0045] ;

[0046] u is the recombined output voltage of the target converter, u o 2 The square of the output voltage of the target converter.

[0047] Optionally, the second mapping relationship is:

[0048] ;

[0049] Among them, U d To reconstruct the d-axis component of the grid voltage, U q To reconstruct the q-axis component of the grid voltage, u d u is the d-axis component of the input voltage of the target converter. o u is the output voltage of the target converter. q s is the q-axis component of the input voltage of the target converter. d For the d-axis component of the switching state of the target converter, s q The q-axis component represents the switching state of the target converter.

[0050] Another aspect of the present invention provides a predictive control device for a voltage source type three-phase AC / DC converter, the predictive control device comprising a processor and a memory:

[0051] The memory is used to store program code and transmit the program code to the processor;

[0052] The processor is used to execute the method described above according to the instructions in the program code.

[0053] As can be seen from the above technical solutions, the present invention has the following advantages:

[0054] In the predictive control method for a voltage source type three-phase AC / DC converter provided by this invention, in this embodiment, the output voltage and grid current of the target converter at the k-th prediction step are determined by acquiring and based on the output voltage of the target converter at the k-th prediction step, the input voltage of the target converter in the synchronous coordinate system, the grid current at the k-th prediction step, and the switching vector sequence at the k+1-th prediction step, thus realizing the prediction of the output voltage and grid current at the k+1-th prediction step. Furthermore, by using the grid current at the k+1-th prediction step and the switching states corresponding to each voltage vector of the target converter, each voltage vector is filtered, improving the prediction speed and reducing the computational cost. The target voltage vector pairs are determined by combining the filtered results, and each target voltage vector pair is combined into a target vector set, thus realizing the determination of the target voltage vector pairs and the target vector set, thereby improving the accuracy and efficiency of prediction. To improve the control accuracy of the target controller, a pair of target voltage vectors is selected from the target vector set. Using the target voltage vector pair and the zero vector of the target converter, a corresponding sequence of switch vectors to be tested is constructed, thus realizing the construction of the switch vector sequence. Based on the switch vector sequence, combined with the output voltage and grid current at the (k+1)th prediction step, the grid current and output voltage at the (k+2)th prediction step are predicted. On this basis, combined with a pre-constructed cost function, the switch vector sequence to be tested is filtered to obtain the optimal switch vector sequence at the (k+2)th prediction step. The optimal voltage vector is then used to control the target converter during the switching cycle corresponding to the (k+2)th prediction step, improving the control accuracy of the target converter and enhancing its dynamic response performance. This solves the technical problems of limited dynamic response performance and low control accuracy in existing control methods. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the structure of a traditional IAMC;

[0057] Figure 2 A schematic diagram of the improved VF-MC circuit topology;

[0058] Figure 3 This is a schematic diagram showing the positional relationship of each voltage vector in the vector space of the VSC.

[0059] Figure 4This is a schematic diagram of the current, voltage, and switching state waveforms in the first sector of the improved VF-MC during one switching cycle.

[0060] Figure 5 This is a topology diagram of a single VSC provided in an embodiment of the present invention;

[0061] Figure 6 A schematic diagram illustrating the principle of the feedforward decoupling control strategy provided in an embodiment of the present invention;

[0062] Figure 7 A schematic diagram illustrating the principle of predictive control and its application process provided in an embodiment of the present invention;

[0063] Figure 8 A schematic diagram illustrating the control principle of the predictive control method provided in this embodiment of the invention;

[0064] Figure 9 A flowchart illustrating a predictive control method for a voltage source type three-phase AC / DC converter provided in an embodiment of the present invention;

[0065] Figure 10 A flowchart illustrating a predictive control method for a voltage source type three-phase AC / DC converter, provided in another embodiment of the present invention;

[0066] Figure 11 A flowchart illustrating a predictive control method for a voltage source type three-phase AC / DC converter, provided as an application example of the present invention;

[0067] Figure 12 A schematic diagram of the input and output voltage and current waveforms at an output power of 1000W is provided as a simulation application example of the present invention.

[0068] Figure 13 A schematic diagram of the total harmonic distortion rate waveform of the phase current at an output power of 1000W, provided as a simulation application example of the present invention.

[0069] Figure 14 A schematic diagram of the current and voltage waveforms across the HFT provided as a simulation application example of the present invention;

[0070] Figure 15 The diagram shows the input and output voltage and current waveforms when the output power is reduced from 1000W to 500W, which is provided as a simulation application example of the present invention. Detailed Implementation

[0071] To address the complex four-step commutation problem inherent in traditional IAMC topologies, existing technologies propose a bidirectional power switch-free isolated matrix AC-DC converter based on a voltage source converter. This topology cleverly decouples the original matrix converter, effectively transforming it into two alternating VSCs (positive and negative VSCs). Therefore, modulation methods specific to VSC topologies can be used, avoiding bidirectional switching and its associated complex commutation problems. However, the control strategies of this improved isolated AC-DC matrix converter still largely rely on traditional linear control methods, often employing dual-loop PI control strategies based on space vector modulation (SVM), such as dual-loop proportional-integral (PI) control based on SVM. While SVM+PI control technology is mature, its dynamic response speed is limited by the bandwidth of the PI regulator, resulting in inherent latency. Furthermore, its modulation strategy is separated from the control loop, failing to fully utilize the discrete characteristics of the system and limiting performance when handling nonlinear and time-varying systems. Additionally, the commutation safety of the high-frequency transformer leakage inductance current in this topology still requires careful arrangement of voltage vectors in the SVM and the reservation of a fixed time window for leakage inductance charging and discharging, increasing the complexity of the control algorithm.

[0072] In recent years, Finite Control Set Model Predictive Control (FCS-MPC) has been increasingly applied to AC / DC matrix converters. FCS-MPC is a control method based on a discrete system model. It directly selects the optimal switch combination from a finite set of switch states by online rolling optimization of a pre-designed cost function, demonstrating significant advantages in multi-objective constraints and dynamic response. However, most FCS-MPC algorithms are based on non-isolated AC / DC matrix converter topologies. Due to the large number of switch states and the complexity of the IAMC model, it is difficult to directly apply to isolated AC / DC matrix converter topologies, posing new challenges to the design and implementation of the cost function for FCS-MPC in isolated AC / DC matrix converter topologies. Therefore, current technology lacks a finite control set model predictive control method applicable to isolated AC / DC matrix converter topologies.

[0073] Based on the above, it can be seen that the existing control strategies for AC / DC matrix converters have the following problems.

[0074] 1) Mathematical Modeling Problems of Complex Models: Traditional IAMC modulation strategies borrow from the power transfer principle of DAB, resulting in high-frequency sinusoidal oscillations at both ends of the high-frequency transformer, making it difficult to model using simple linearization or piecewise linearization. More importantly, during dynamic processes such as load changes, input disturbances, or operating mode switching, the system deviates from steady state. During this transient period, the aforementioned high-frequency oscillations undergo strong nonlinear coupling with the dynamic response of the main power loop, producing severe damped oscillations (ringing). It is this highly nonlinear and time-varying oscillatory behavior exhibited during transient processes that poses a significant challenge to traditional MPC methods based on accurate mathematical models.

[0075] 2) Modeling issues of complex commutation operations: Traditional IAMC topologies using bidirectional switches require complex multi-step commutation strategies (such as four-step commutation) to ensure safety, placing extremely high demands on the real-time performance and reliability of the controller, and posing a risk of commutation failure. In the improved VF-MC topology without bidirectional switches mentioned in the background section, time needs to be reserved for the leakage inductance to charge and discharge in order to solve the commutation problem of high-frequency transformer leakage current. The current changes during this period also increase the complexity of system modeling.

[0076] 3) Limited dynamic response performance: SVM-based PI control is a linear and continuous control method. Its dynamic response speed is limited by the tuning of the PI controller parameters, resulting in an inherent response delay. When dealing with conditions such as sudden load changes and input voltage fluctuations, the system recovery time is relatively long, making it difficult to achieve instantaneous optimal control.

[0077] 4) Commutation failure caused by variable duty cycle: Traditional SVM strategy relies on variable duty cycle to change voltage amplitude, which inevitably generates narrow pulses. Commutation operation requires a certain amount of time, and the conflict between the two will lead to commutation failure.

[0078] 5) Current coupling problem of VSC: Traditional VSC control strategies often use feedforward decoupling control to eliminate current coupling, but this strategy needs to be implemented in the current PI loop. If it is to be implemented in FCS-MPC, a new decoupling method needs to be found.

[0079] Therefore, in order to solve at least one of the problems of the prior art mentioned above, embodiments of the present invention provide a predictive control method and apparatus for a voltage source three-phase AC / DC converter.

[0080] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0081] The predictive control method for a voltage source three-phase AC / DC converter provided by this invention is applied to a voltage source three-phase AC / DC converter. Specifically, the voltage source three-phase AC / DC converter is a voltage source three-phase isolated AC / DC matrix converter.

[0082] like Figure 1 As shown, Figure 1 The left side shows the structure of a traditional IAMC, where G is the generator. ia, ib, and ic represent the three-phase currents a, b, and c, respectively. Sap1, Sbp1, Scp1, San1, Sbn1, Scn1, Sap2, Sbp2, Scp2, San2, Sbn2, and Scn2 are all switches, connected in pairs to form a bidirectional switch. For example, Sap1 and Sap2 form a bidirectional switch. Figure 1 As shown on the right, the bidirectional switches of a traditional IAMC can be divided into two groups to form two equivalent VSC circuits. The group of switches with the last digit of the number being 1 (i.e., Sap1, Sbp1, Scp1, San1, Sbn1, Scn1) adds a positive half-cycle switching signal Sp to control the output of the positive half-cycle voltage. The group of switches with the last digit of the number being 2 adds a negative half-cycle switching signal Sn to control the output of the negative half-cycle voltage.

[0083] according to Figure 1 As shown in the topology on the right, during the high-frequency conversion process, the switches numbered p (i.e., Sap1, Sbp1, Scp1, Sap2, Sbp2, Scp2) control the forward conduction of the voltage source converter VSC voltage. Furthermore, their body diodes all serve as freewheeling current during the leakage inductance current commutation process. Therefore, this group of switches can be combined (Sap1 and Sap2, Sbp1 and Sbp2, Scp1 and Scp2), and the original two high-frequency transformers can be replaced with a center-tapped transformer connected to ISOP, thus achieving parallel connection of the two VSCs, resulting in the following... Figure 2 The improved VF-MC circuit topology shown is the voltage source type three-phase isolated AC / DC matrix converter provided in the embodiment of the present invention.

[0084] like Figure 2As shown, the complete circuit topology of the voltage source type three-phase isolated AC / DC matrix converter includes five parts: three-phase AC input terminal, matrix converter, high-frequency transformer HFT, full-bridge rectifier, and DC output terminal. Figure 2 In the middle, the grid voltage input at the AC terminal is a three-phase stable sine wave. , , , and These are the filter inductor and the inductor resistor, respectively. , , This represents the grid-side current. The matrix converter consists of 11 switches, where switches Sn, San2, Sbn2, Scn2 and Sp, San1, Sbn1, Scn1 control the negative and positive half-cycle voltage outputs, respectively, while Sap, Sbp, and Scp simultaneously control the positive voltage vectors of both positive and negative VSCs. A high-frequency transformer provides current isolation and voltage matching between the AC and DC links. and This refers to the leakage inductance of the transformer. The full-bridge rectifier circuit consists of switches S1, S2, S3, and S4. S1 and S4 handle the positive half-cycle rectification, while S2 and S3 handle the negative half-cycle rectification. The DC output is connected to the load. and filter capacitor composition, and These are the DC output current and DC output voltage, respectively.

[0085] based on Figure 2 It can be seen that the improved VF-MC circuit topology can be viewed as two independent sets of positive and negative VSCs operating alternately. Therefore, the switching function of the traditional VSC can also be analogized to this topology. Define the binary switching function S. xyz As shown in equation (1).

[0086] (1)

[0087] According to the binary switching function shown in formula (1), the voltage vector and switching state of the converter VSC can be obtained as shown in Table 1.

[0088] Table 1

[0089]

[0090] The above is an introduction to the voltage source type three-phase AC / DC converter circuit topology and modulation involved in this invention. The following will describe in detail a predictive control method for a voltage source type three-phase AC / DC converter provided by an embodiment of this invention, in conjunction with the voltage source type three-phase AC / DC converter circuit topology and modulation.

[0091] The present invention provides a predictive control method for a voltage source type three-phase AC / DC converter, which includes two stages in each control cycle: a predictive calculation stage and a vector application stage.

[0092] Prediction Calculation Phase: Based on the sampled data at the current time (the end of the k-th prediction step) and the switching states determined and applied in the previous cycle (k+1-th prediction step), the state at the future time (the end of the k+2-th prediction step) is predicted using the established discrete model. Then, through traversal optimization, the optimal voltage vector (i.e., the voltage vector in the optimal switching vector sequence) for the next cycle (k+2-th prediction step) is selected from the finite control set. The discrete model describes a switching cycle T. s Within a given period, when a switching sequence consisting of specific voltage vectors (including active and zero vectors) is applied in a fixed time interval, the system state (grid current, output voltage) changes from the beginning to the end of the cycle. In the predictive calculation, the "switching state" serves as the input to this discrete model, essentially representing the time-interval voltage vector sequence to be applied in the next switching cycle. By inputting the switching state representing the future vector sequence into the model, the system state after the sequence has completed (i.e., the end of the (k+1)th prediction step) can be predicted.

[0093] Vector application phase: The predicted optimal voltage vector is actually applied to the converter within the following complete switching cycle (from the end of the (k+1)th prediction step to the end of the (k+2)th prediction step). Each optimal switching vector sequence corresponds to a sequence of two active vectors and two zero vectors, applied according to a preset, fixed time ratio and order (e.g., ...). Figure 4 The switching sequence shown is used to construct the circuit. In application, the controller strictly follows this sequence, outputting the corresponding drive signals sequentially in time intervals within the switching cycle to synthesize the desired optimal output voltage. The duty cycle of this sequence is fixed, fundamentally avoiding the risk of narrow pulses caused by the variable duty cycle in traditional SVPWM.

[0094] Data closed loop: The actual switching state output during the vector application phase will be recorded and used as the known input "switching state of the (k+1)th prediction step" for the prediction calculation in the next control cycle, thereby realizing the closed loop of prediction and control.

[0095] Please see Figure 9 The present invention provides a predictive control method for a voltage source type three-phase AC / DC converter, comprising:

[0096] S1. Obtain the input voltage of the target converter in the synchronous coordinate system, the grid current at the kth prediction step, and the switching vector sequence at the (k+1)th prediction step; and obtain the output voltage of the target converter at the kth prediction step.

[0097] It should be noted that the target converter in this embodiment is as follows: Figure 2 The diagram shows an improved voltage source isolated AC / DC matrix converter (VF-MC). This converter operates within one switching cycle T. s Internally, two voltage source converters (VSCs), one positive and one negative, operate alternately to jointly achieve three-phase AC to DC conversion. Since the topology, mathematical model, and control laws of these two VSCs are identical, this embodiment uses a single VSC as an example to illustrate the predictive control flow. In actual operation, simply alternating the control flow of a single VSC in time is sufficient to control the entire converter. Therefore, the target converter in this embodiment refers to the entire improved VF-MC converter.

[0098] The input voltage is specifically the AC input voltage of the power grid for this prediction period. Since the switching frequency fs is 20kHz, and the input voltage u... s (k) is 50Hz, and within one switching cycle, u s (k) changes very little and can be considered constant. In the predictive control operation of one cycle in this embodiment, u s (k)= u s (k+n), therefore, in one prediction process of this embodiment, u s (k) is set to a constant. The input voltage for this step is u. s (k) Input voltage after dq axis transformation.

[0099] The grid current and output voltage at the k-th prediction step are the AC input current and DC output voltage at the end of the k-th prediction step (i.e., the end of the previous prediction cycle and the start of the current prediction cycle). k is a constant. k+1 represents the current at the start of the current prediction cycle, after a further prediction step. The time of prediction. Here, the grid current at the k-th prediction step is the grid current after dq-axis transformation. The DC output voltage at the k-th prediction step is obtained by real-time sampling. Here, the prediction step size... Equal to the switching period T s .

[0100] The (k+1)th prediction step size of the switching vector sequence refers to the optimal switching vector sequence predicted in the previous prediction cycle and applied between k and k+1. This switching vector sequence records the action order and timing of each voltage vector, as well as the switching state of the target converter when the voltage vectors are applied. During application, the voltage vectors in this switching vector sequence are applied to the target converter between k and k+1 in time-sequenced intervals. As shown in Table 1, there is a correspondence between the voltage vectors and the switching states of the target converter. Therefore, the voltage vectors in the switching vector sequence will cause the target converter to exhibit the corresponding switching state. This step obtains the (k+1)th prediction step size of the switching vector sequence in the synchronous coordinate system. Based on this, the switching states corresponding to each voltage vector in the synchronous coordinate system are obtained.

[0101] Therefore, the input voltage, grid current, and switch state in this step all contain d-axis and q-axis components, respectively, that is, the d-axis component u of the AC grid input voltage. d (k) q-axis component u of the AC input voltage of the power grid q (k) d-axis component i of the grid current d (k) q-axis component i of the grid current q (k) d-axis component s of the switch state d (k+1), q-axis component s of the switching state q (k+1).

[0102] S2. Based on the output voltage of the kth prediction step, the grid current of the kth prediction step, the input voltage, and the switching vector sequence, determine the output voltage of the (k+1)th prediction step and the grid current of the (k+1)th prediction step.

[0103] It should be noted that, as mentioned above, each voltage vector in the switching vector sequence acts sequentially on the target converter, adjusting its switching state accordingly, thereby adjusting the system's output voltage and grid current. Based on the timing relationship, the output voltage and grid current at the k-th prediction step are the output voltage and grid current corresponding to the start of this prediction cycle. Based on this, combined with the first voltage vector acting in the switching vector sequence, the switching state of its corresponding target converter is determined. Using this switching state and the output voltage and grid current at the k-th prediction step, the system's output voltage and grid current after the first voltage vector acts can be determined. Using this output voltage and grid current as the basis for prediction, the switching state of the target converter corresponding to the second voltage vector acting in the switching vector sequence is then used to predict the system's output voltage and grid current after the second voltage vector acts. This process continues, using all the switching states in the switching vector sequence for prediction, ultimately obtaining the output voltage and grid current at the (k+1)-th prediction step.

[0104] S3. Obtain the switching state corresponding to each voltage vector of the target converter. Based on the switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step, determine the target voltage vector pair of the target converter. Then, form a target vector set from each target voltage vector pair.

[0105] It should be noted that, in order to reduce the computational burden on the model for the optimal switching vector sequence, this embodiment pre-selects each voltage vector using the grid current at the (k+1)th prediction step and the corresponding switching state of each voltage vector, and combines the selected voltage vectors according to a preset combination rule to obtain the target voltage vector pair.

[0106] Specifically, the target converter has 6 active voltage vectors and 2 zero vectors. As shown in Table 1 above, each voltage vector has a corresponding switching state and a corresponding output current. The output current value can be calculated from the switching state and the grid current. Based on this principle, this step determines the output current value corresponding to each voltage vector, and selects the required voltage vectors by combining the screening condition that the output current is not less than 0. Then, the selected voltage vectors are combined in pairs according to the preset combination rules to obtain the target voltage vector pairs.

[0107] In one embodiment, determining the target voltage vector pair of the target converter in S3 based on the switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step includes the following sub-steps:

[0108] S31. Input the switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step into the preset output current relationship to obtain each output current value.

[0109] It should be noted that the preset output current relationship is shown in equation (2):

[0110] (2)

[0111] in, For output current; s d For the d-axis component of the switching state, s q For the q-axis component of the switching state, i d Let i be the d-axis component of the grid current. q This represents the q-axis component of the grid current.

[0112] In this step, the switching state corresponding to the voltage vector in the three-phase coordinate system is predetermined, and the switching state in the three-phase coordinate system is transformed to the synchronous coordinate system to obtain the corresponding d-axis and q-axis components. The d-axis and q-axis components of the grid current at the (k+1)th prediction step (i.e., ...) are then used. and Substituting into the above formula, we obtain the corresponding output current i3(k+1). It can be understood that in this step, performing this process for each voltage vector will yield the corresponding output current value.

[0113] Based on the correspondence between each voltage vector and the switching state shown in Table 1, the binary switching function of the switching state can be determined, and the three-phase coordinates corresponding to each switching state can be obtained based on the binary switching function. By converting the three-phase coordinates into dq coordinates, the dq components of the switching state can be obtained.

[0114] S32. Take the output current value that is not less than zero among all output current values ​​as the target current value;

[0115] S33. Take the voltage vector corresponding to the target current value as the target voltage vector.

[0116] It should be noted that the output current value corresponding to each voltage vector is compared with 0, and the target voltage vector with an output current value greater than 0 is selected. That is, the voltage vector that makes i3(k+1)≥0 is taken as the target voltage vector.

[0117] S34. According to the preset combination rules, the target voltage vectors are combined in pairs to obtain the target voltage vector pairs.

[0118] It should be noted that the preset combination rule is as follows: according to the preset action time ratio, the target voltage vector is combined with itself to obtain the target voltage vector pair. And / or, according to a preset action time ratio, each target voltage vector is combined with its adjacent target voltage vectors based on their positional relationship in the vector space, to obtain a target voltage vector pair. It is understandable that, in practical applications, the two voltage vectors in the target voltage vector pair in this embodiment will act on the target converter sequentially according to a preset action order, based on the action time ratio corresponding to the action time, causing the target converter to be in the corresponding switching state. In one example, according to the definition of vector synthesis, Indicates two Applying time t respectively is equivalent to Since it acts alone for 2t, the actual effect of the target voltage vector pair obtained by combining the same voltage vectors can be regarded as the effect of a single real voltage vector, which can be directly realized by a single switching state in hardware. express and The two voltage vectors are applied for time t respectively. Different switching states need to be applied at each time t. They cannot be directly represented by a single real vector. They cannot be directly implemented in hardware. Therefore, in this embodiment, the target voltage vector pair composed of different voltage vectors is defined as a virtual voltage vector.

[0119] Understandably, in order to clearly explain the principle of voltage vector synthesis and the working principle of the virtual voltage vector in this embodiment, the following explanation will combine the virtual voltage vector composed of the original unfiltered voltage vectors of the target converter and the traditional SVPWM control.

[0120] As shown in Table 1, VSC has a total of 6 active vectors ( ~ ) and two zero vectors ( , The positional relationships of each voltage vector in vector space are as follows: Figure 3 As shown. Using traditional SVPWM control, the vector space can be divided into 6 sectors (i.e., I, II, III, IV, V, VI) based on these 8 voltage vectors. The target output voltage of each sector is synthesized by the two active vectors and two zero vectors at both ends of the sector. The target voltage is obtained by controlling the duration of the two active vectors within one switching cycle. Its general expression is:

[0121] (3)

[0122] In the formula, Indicates one switching cycle. , , Represents vector , , The operating time within a switching cycle is a variable duty cycle modulation strategy.

[0123] To prevent the filter capacitor from short-circuiting due to simultaneous conduction of the upper and lower bridge arms during commutation, a commutation strategy is often introduced. Traditional SVPWM typically employs a four-step commutation method, while the improved VF-MC utilizes DC voltage... The basic idea behind commutation of the auxiliary leakage inductance current is: when the effective voltage vector changes from zero vector... During the transition to an active vector converter, the rectifier bridge switches are not changed initially, while the positive VSC switch S to which the transition is to is simultaneously turned on. p During this process, Zero vector switch and S ap S bp S cp The body diode forms a circuit, and the reverse voltage provided by the rectifier bridge charges the leakage inductor through the HFT to generate leakage current, thereby avoiding voltage spikes caused by voltage mismatch across the HFT.

[0124] Figure 4 This demonstrates a switching cycle T of the first sector of the improved VF-MC. s The current, voltage, and switching state waveforms within the circuit, such as Figure 4 As shown, the voltage vectors used are V1, V2, V7, and V8, and their corresponding durations are T. x / 2、T y / 2, T0 / 4, T0 / 4, in the first positive half-cycle T s Within / 2, the order of action is V8, V1, V2, V7.

[0125] To achieve the charging and discharging process of the leakage inductor, it is necessary to ensure The charging time of the leakage inductance current. As shown in formula (4).

[0126] (4)

[0127] in, / This is the HFT turns ratio.

[0128] As can be seen from the attached diagram and the above, both the traditional four-step commutation method and the improved VF-MC commutation method require a delay time. To complete commutation, modulation methods using variable duty cycle inevitably produce narrow pulses. When the pulse width is less than... This will lead to commutation failure. However, this embodiment constructs a virtual voltage vector with a fixed duty cycle and combines it with real vectors to build a vector set, providing basic support for subsequent steps to select the optimal switching vector sequence. Thus, when using the target control voltage corresponding to the optimal switching vector sequence to control the VSC, the risk of commutation failure can be reduced.

[0129] Specifically, the expression for the virtual voltage vector is shown in equation (5):

[0130] (5)

[0131] Where d1 is the first proportionality coefficient and d2 is the second proportionality coefficient. It is understandable that the expression for the virtual voltage vector is not a summation operation in conventional mathematics, but rather indicates the duration of the combined voltage vector's action and the type of voltage vector. Here, d1 represents the voltage vector V. n The time ratio occupied, d2 is used for voltage vector V n+1 This indicates the proportion of time occupied. In this embodiment, it is set... = =0.5, indicating that during the total duration of the virtual voltage vector, the voltage vector V n With voltage vector V n+1 Each occupies half, that is, when the virtual voltage vector is applied to the target converter, within one switching cycle, the voltage vector V in the virtual voltage vector occupies half. n With voltage vector V n+1 The duration of their effects is equal.

[0132] Traditional SVPWM achieves instantaneous synthesis and approximation of the reference voltage vector by continuously adjusting the duty cycles of two active vectors within a single switching cycle. However, the model predictive control method employed in this embodiment applies a complete, fixed-waveform switching sequence within each switching cycle. By traversing a pre-generated set of voltage vector pairs, it selects the optimal sequence that minimizes the cost function. In other words, the ideal control effect in this embodiment is not achieved through precise synthesis within a single cycle, but rather through rolling optimization of the optimal sequence over multiple cycles, gradually approaching the global optimum.

[0133] Using the target voltage vector pair in the vector sequence of the switch under test as the virtual voltage vector, and Figure 4 Taking the control sequence and range of voltage vectors V1, V2, V7, and V8 as an example, assuming the selected virtual voltage vector is V... 1,2 Then the virtual voltage vector V 1,2 It can be divided into V1 and V2, where the duration of action of V1 is T. x Equal to the duration T of V2 y V 1,2V1 replacement with a fixed duty cycle Figure 4 V1 with an indefinite duty cycle will V 1,2 V2 replacement with a fixed duty cycle Figure 4 V2 has a variable duty cycle, while other voltage vectors remain unchanged. Based on this, in the first half of the cycle, after voltage vector V8 has acted for T0 / 4, V1 acts for T... x / 2, then V2 acts on T x / 2, and so on for the second half of the cycle.

[0134] Therefore, according to the above combination rules, the two voltage vectors that make up a voltage vector pair equally divide the total action time of the voltage vector pair. Based on this, if the obtained voltage vector pair is composed of two identical voltage vectors, then the voltage vector pair is equivalent to that voltage vector; if the obtained voltage vector pair is composed of two different voltage vectors, then the voltage vector pair is a virtual voltage vector. Therefore, after combining the 6 active vectors and 2 zero vectors in pairs, the obtained voltage vector pairs include the 12 virtual voltage vectors shown in Table 2, the 6 active vectors (V1~V6) in Table 1, and the 2 zero vectors (V7, V8) in Table 1. Table 2 is shown below.

[0135] Table 2

[0136]

[0137] Understandably, the prediction accuracy of the FCS-MPC algorithm usually depends on the 4E8E sampling frequency and the completeness of the control set. If the control set has few members, a higher sampling frequency is required to achieve accurate prediction, while if the control set has too many members, it will increase the computational cost of the model. However, by using the target vector set constructed as described above in this application as the control set, both the prediction accuracy and computational cost of the algorithm can be balanced.

[0138] S4. Select a pair of target voltage vectors from the target vector set, and use the target voltage vector pair and the zero vector of the target converter to construct the corresponding switch vector sequence to be tested.

[0139] It should be noted that the test switch vector sequence in this embodiment consists of two zero vectors and a pair of target voltage vectors. The order and timing of the action of each voltage vector in the test switch voltage vector sequence are fixed; the difference lies in the fact that the target voltage vector pair in the test switch vector sequence constructed each time S4 ​​is executed is different.

[0140] In one embodiment, the step S4 of constructing the corresponding switch vector sequence under test using the target voltage vector pair and the zero vector of the target converter includes the following sub-steps:

[0141] S41. Determine and respectively use the action time of the zero vector and the action time of each voltage vector in the target voltage vector pair as the test sub-intervals of the switch vector sequence to be tested;

[0142] S42. Obtain the action order of each voltage vector in the zero vector and target voltage vector pair of the target converter, and sort each sub-interval to be tested in sequence according to the action order to obtain the vector sequence of the switch to be tested.

[0143] It should be noted that in this embodiment, during one switching cycle T s Within the test switch vector sequence, the order and duration of each voltage vector are as follows: V8 (duration is T). s / 20), V x (The duration of action is T) s / 5), V y (The duration of action is T) s / 5), V7 (action time is T) s / 10), V x (The duration of action is T) s / 5), V y (The duration of action is T) s / 5), V8 (action time is T) s / 20). Among them, V x V y Let V be the two voltage vectors in the target voltage vector pair. Either voltage vector in the target voltage vector pair can be considered as V. x It can also be used as V y For example: the target voltage vector pair is V 5,6 Then V5 is V x V6 is V y Or, V5 is V y V6 can be V x In one example, the voltage vector with the smallest subscript number in the target voltage vector pair can be taken as V. x .

[0144] Based on the above, in this embodiment, the switching period is divided according to the action time of each voltage vector in the test switch vector sequence to obtain each test sub-interval. For example, the voltage vector corresponding to the first test sub-interval is the zero vector V8, and the switching state corresponding to the first test sub-interval is the switching state of the target converter when voltage vector V8 acts on the target converter, and so on. Then, the test sub-intervals are sorted according to the action order of each voltage vector in the test switch vector sequence to obtain the corresponding test switch vector sequence.

[0145] S5. Based on the vector sequence of the switch to be tested, the input voltage, the output voltage at the (k+1)th prediction step, and the grid current at the (k+1)th prediction step, determine the grid current at the (k+2)th prediction step and the output voltage at the (k+2)th prediction step.

[0146] It should be noted that this step predicts the (k+2)th prediction step size. The prediction principle is similar to S2. That is, the output voltage and grid current of the (k+1)th prediction step size are used as the prediction starting point, and the switching state corresponding to the first voltage vector in the test switch vector sequence is determined. The output voltage and grid current after the voltage vector is applied are determined based on the switching state. The output voltage and grid current after the voltage vector is applied are then used as the new starting point. The output voltage and grid current after the voltage vector is applied are predicted based on the switching state corresponding to the second voltage vector in the test switch vector sequence. The switching states corresponding to the voltage vectors in the test switch vector sequence are iterated sequentially to finally obtain the grid current and the output voltage of the (k+2)th prediction step size.

[0147] In this embodiment, the switch states corresponding to the switch vectors used and the switch states of the switch vector sequence to be tested are both switch states in the synchronous coordinate system.

[0148] As can be seen from the above, in this embodiment, when the switch vector sequence begins to act at the starting point of the (k+1)th prediction step, the output voltage and grid current of the kth prediction step corresponding to the starting point, as well as the switching state corresponding to the voltage vector in the switch vector sequence, can be used to predict the output voltage and grid current at the end of the (k+1)th prediction step, thereby accelerating the acquisition of the output voltage and grid current at the end of the (k+1)th prediction step. Using the output voltage and grid current at the end of the (k+1)th prediction step as the starting point of the (k+2)th prediction step, and combining this with the switch vector sequence to be tested, the output voltage and grid current at the end of the (k+2)th prediction step are predicted. Therefore, by adopting the predictive control method provided in this embodiment, the output voltage and grid current at the end of the (k+2)th prediction step after the switch vector sequence to be tested has been completed can be obtained more quickly, thereby improving the prediction speed of the optimal switch vector sequence, enhancing the control accuracy and efficiency of the target converter, and improving the dynamic response performance of the converter.

[0149] S6. Input the grid current and the output voltage of the (k+2)th prediction step into the pre-constructed cost function to obtain the cost function value.

[0150] It should be noted that the cost function is composed of the error term obtained by subtracting the reference value and the predicted value of the control quantity. By setting different weights for the control quantities, the degree of importance that the cost function attaches to different control quantities can be controlled. In the process of selecting the switch vector sequence to be tested, the switch vector sequence to be tested that minimizes the cost function value is the optimal switch vector sequence to be applied to the next switching cycle (i.e., the k+2 prediction step).

[0151] As mentioned above, the test switch vector sequence constructed in S4 has multiple types. Each test switch vector sequence has a corresponding predicted grid current and output voltage at the (k+2)th prediction step, and thus has a corresponding cost function value.

[0152] In one embodiment, the cost function is constructed according to the following principle:

[0153] In predictive control applied to an improved VF-MC topology, a DC output voltage is used. and AC input grid current As the control variable of the cost function, the cost function can be expressed as:

[0154] (6)

[0155] In the formula, For grid current The reference value of the d-axis component (i.e., active current). For grid current The reference value of the q-axis component (i.e., reactive current). This is a reference value for the DC output voltage. It can be calculated from the rated power and load. g is the cost function value, λ1 is the first weighting coefficient, λ2 is the second weighting coefficient, and i d (k+1) represents the d-axis component of the grid current with a prediction step size of k+1, i q (k+1) represents the q-axis component of the grid current with a prediction step size of k+1, u o (k+1) represents the output voltage with a prediction step size of k+1.

[0156] And for , Since the reactive power input to the grid is expected to be 0, the active current reference value is... and reactive current reference value The calculation formula is as follows:

[0157] (7)

[0158] In the formula, The active component of the sampled AC input voltage (i.e., the active component of the input voltage at the k-th prediction step) is used. Since the change in AC input current and voltage is small within a switching cycle, as shown in Equation (8), the future current reference value is obtained by extrapolation.

[0159] (8)

[0160] It should be noted that, in the control process of this embodiment, sampling and prediction for the next cycle are typically completed in the first switching cycle. The prediction result is applied in the next switching cycle. The predictive control and application process is as follows: Figure 7 As shown.

[0161] Due to the delay in the control process, it is necessary to introduce delay compensation into the cost function, which is to predict the current and voltage values ​​at the (k+2)th prediction step. The cost function with delay compensation can be expressed as:

[0162] (9)

[0163] In the formula, For grid current The reference value of the d-axis component (i.e., active current). For grid current The reference value of the q-axis component (i.e., reactive current). This is a reference value for the DC output voltage. It can be calculated from the rated power and load. g is the cost function value, λ1 is the first weighting coefficient, λ2 is the second weighting coefficient, and i d (k+2) represents the d-axis component of the grid current with a prediction step size of k+2, i q (k+2) represents the q-axis component of the grid current with a prediction step size of k+2, u o (k+2) represents the output voltage with a prediction step size of k+2.

[0164] Therefore, in this embodiment, by inputting the grid current and output voltage of the (k+2)th prediction step into the above cost function, the corresponding cost function value can be obtained.

[0165] S7. Jump to execute S4 to S7 until the cost function values ​​corresponding to all the switch vector sequences to be tested have been calculated. Output the switch vector sequence to be tested corresponding to the minimum cost function value among all cost function values ​​as the optimal switch vector sequence, and apply the optimal switch vector sequence to the target converter of the (k+2)th prediction step.

[0166] It should be noted that in this embodiment, for each switch vector sequence to be tested constructed in S4, S5-S6 is executed once, and the cost function value of each switch vector sequence to be tested is recorded until the cost function values ​​corresponding to all switch vector sequences to be tested constructed in S4 have been calculated. The cost function values ​​corresponding to each switch vector sequence to be tested are compared, and the switch vector sequence to be tested with the minimum cost function value is taken as the optimal switch vector sequence and applied to the switching period corresponding to the (k+2)th prediction step.

[0167] In this embodiment, the input voltage of the target converter in the synchronous coordinate system, the grid current at the k-th prediction step, and the switching vector sequence at the (k+1)-th prediction step are obtained. The output voltage at the k-th prediction step of the target converter is also obtained. Based on the output voltage, input voltage, grid current, and switching vector sequence at the k-th prediction step, the output voltage and grid current at the (k+1)-th prediction step are determined, thus achieving the prediction of the output voltage and grid current at the (k+1)-th prediction step. Furthermore, by using the grid current at the (k+1)-th prediction step and the switching states corresponding to each voltage vector of the target converter, each voltage vector is filtered, improving the prediction speed and reducing computational cost. The filtered results are then used to determine target voltage vector pairs, and these target voltage vector pairs are combined to form a target vector set, thus achieving the determination of both the target voltage vector pairs and the target vector set, thereby improving the accuracy and efficiency of prediction. To improve the control accuracy of the target controller, a pair of target voltage vectors is selected from the target vector set. Using the target voltage vector pair and the zero vector of the target converter, a corresponding sequence of switch vectors to be tested is constructed, thus realizing the construction of the switch vector sequence. Based on the switch vector sequence, combined with the output voltage and grid current at the (k+1)th prediction step, the grid current and output voltage at the (k+2)th prediction step are predicted. On this basis, combined with a pre-constructed cost function, the switch vector sequence to be tested is filtered to obtain the optimal switch vector sequence at the (k+2)th prediction step. The target converter is then controlled using the optimal voltage vector in the switching cycle corresponding to the (k+2)th prediction step, improving the control accuracy of the target converter and enhancing its dynamic response performance. This solves the technical problems of limited dynamic response performance and low control accuracy in existing control methods.

[0168] In one embodiment, based on the above embodiment, the steps of S2 are described as follows. As described above, the switching vector sequence includes multiple sub-intervals ordered according to a preset timing sequence, each sub-interval corresponding to a switching state. The sub-interval refers to the duration of the voltage vector in the switching vector sequence, for example: Figure 4 For example, suppose the switching vector sequence consists of voltage vectors V8, V1, V2, and V7, and in the first positive half-cycle T... sWithin / 2, the order of action is V8, V1, V2, V7, corresponding to subintervals T0 / 4 and T... x / 2、T y / 2, T0 / 4, in the latter negative half-cycle T s Within / 2, the order of action is V7, V1, V2, V8, corresponding to subintervals T0 / 4 and T... x / 2、T y / 2、T0 / 4.

[0169] Please see Figure 10 S2 includes the following sub-steps:

[0170] S21. Read the switch status of a sub-interval in sequence.

[0171] It should be noted that each sub-interval has a corresponding voltage vector, and each voltage vector has a corresponding switching state. Therefore, each sub-interval has a corresponding switching state. This step reads the switching states corresponding to one sub-interval sequentially according to the order recorded in the switching vector sequence. The switching states obtained in this step are the switching states in the synchronous coordinate system.

[0172] The output voltage, input voltage, and grid current at the k-th prediction step are the same as the output voltage, input voltage, and grid current at the starting point of the (k+1)-th prediction step. In other words, the first voltage vector in the switching vector sequence will be based on the output voltage, input voltage, and grid current at the starting point of the (k+1)-th prediction step to adjust the current and voltage of the target converter.

[0173] Taking the above example, the voltage vector corresponding to the first sub-interval of the switch vector sequence is V8. Therefore, this step reads the switch state s corresponding to voltage vector V8. d (k+T0 / 4), s q (k+T0 / 4).

[0174] S22. Input the output voltage of the kth prediction step into the preset first mapping relationship to obtain the first reconstructed output voltage; and input the input voltage, the output voltage of the kth prediction step, and the switching state of the sub-interval into the preset second mapping relationship to obtain the first reconstructed grid voltage.

[0175] It should be noted that the first mapping relationship contains a mapping relationship with the output voltage of the target converter as the independent variable and the recombined output voltage of the target converter as the dependent variable; the second mapping relationship contains a mapping relationship with the output voltage of the target converter, the input voltage of the target converter in the synchronous rotating coordinate system, and the switching state as the independent variables and the recombined grid voltage of the target converter as the dependent variable.

[0176] Therefore, in this embodiment, the first reconstructed output voltage is obtained by inputting the output voltage of the kth prediction step into the first mapping formula; the first reconstructed grid voltage corresponding to the sub-interval is obtained by inputting the input voltage, the output voltage of the kth prediction step, and the switching state of the sub-interval into the second mapping formula.

[0177] Taking the example above, this step will predict the output voltage u of the k-th prediction step. o (k) Input the first mapping relationship to obtain the first recombined output voltage u(k), and then input the voltage u d (k), u q (k), u o (k), s d (k+T0 / 4), s q (k+T0 / 4) is input into the second mapping relationship to obtain the first reorganized grid voltage U. d (k+T0 / 4), U q (k+T0 / 4).

[0178] S23. Input the first recombined output voltage, the input voltage, and the grid current at the kth prediction step into the preset third mapping relationship to obtain the second recombined output voltage; and input the second recombined output voltage into the first mapping relationship to perform the inverse operation to obtain the second output voltage.

[0179] It should be noted that the third mapping formula contains an embedded mapping relationship with the first recombined output voltage, input voltage, and grid current as dependent variables, and the second recombined output voltage as the independent variable. In this embodiment, the first recombined output voltage, input voltage, and grid current at the k-th prediction step are input into the preset third mapping formula to obtain the second recombined output voltage. The second recombined output voltage is then input into the first mapping formula and inversely calculated to obtain the corresponding second output voltage. The second output voltage obtained at this time is the output voltage corresponding to the end point of the sub-interval read in S21.

[0180] Taking the above example as an example, this step will combine the first recombined output voltage u(k) and input voltage u d (k), u q (k), the grid current i at the k-th prediction step d (k), i q (k) Input the second recombined output voltage u(k+T0 / 4) into the third mapping equation, and then input the second recombined output voltage u(k+T0 / 4) into the first mapping equation and perform the inverse operation to obtain the second output voltage u. o (k+T0 / 4).

[0181] S24. Input the first reconstructed grid voltage and the grid current at the kth prediction step into the preset fourth mapping relationship to obtain the second grid current.

[0182] It should be noted that the fourth mapping relationship contains an embedded mapping relationship with the first reconstructed grid voltage and grid current as independent variables and the second grid current as the dependent variable. Therefore, in this embodiment, the first reconstructed grid voltage and the grid current at the k-th prediction step are input into the preset fourth mapping relationship to obtain the second grid current. The second grid current at this time is the grid current corresponding to the end point of the sub-interval read in S21.

[0183] Taking the above example as an example, this step will reassemble the first grid voltage U d (k+T0 / 4), U q (k+T0 / 4), the grid current i at the k-th prediction step. d (k), i q (k) Input the fourth mapping relation to obtain the second grid current i d (k+T0 / 4), i q (k+T0 / 4). Therefore, the second grid current i is finally obtained in this example. d (k+T0 / 4), i q (k+T0 / 4) represents the system input current when the predicted voltage vector V8 has completed its action in the first sub-interval, and the resulting second output voltage u. o (k+T0 / 4) is the predicted output current of the system when the voltage vector V8 has finished acting in the first sub-interval. Based on this, the prediction of the input current and output voltage at the end of the first sub-interval in the switching vector sequence is completed.

[0184] S25. Replace the second output voltage with the output voltage of the kth prediction step, and replace the second grid current with the grid current of the kth prediction step.

[0185] It should be noted that, in this embodiment, the above steps need to be performed on each sub-interval in the switch vector sequence to obtain the grid current and output voltage at the end of the (k+1)th prediction step. Therefore, in this step, the obtained second output voltage replaces the output voltage of the kth prediction step in S21 to S24, and the obtained second grid current replaces the grid current of the kth prediction step, as the basis for predicting the grid current and output voltage of the next sub-interval.

[0186] S26. Jump to execute S21 to S25 until the switching status of all sub-intervals has been read. Output the second output voltage as the output voltage of the (k+1)th prediction step size, and output the second grid current as the grid current of the (k+1)th prediction step size.

[0187] It should be noted that after executing S21 to S25 once, if there are still unread sub-intervals of switch states in the switch vector sequence, then jump to S21 again and repeat the above steps to obtain the grid current and output voltage at the end of the (k+1)th prediction step.

[0188] Based on the above example, after obtaining the grid current i in the first sub-interval... d (k+T0 / 4), i q (k+T0 / 4) and output voltage u o After (k+T0 / 4), using this as a reference, read the switch state corresponding to the second sub-interval, such as... Figure 4 As shown, the voltage vector corresponding to the second sub-interval is V1, then the read switch state is the switch state corresponding to V1, that is, s d (k+T0 / 4+T x / 2), s q (k+T0 / 4+T x / 2). The output voltage u o The input (k+T0 / 4) is used in the first mapping relationship to obtain the first recombined output voltage u(k+T0 / 4). Since the input voltage can remain constant by default during a prediction process, the input voltage used in each sub-interval is u. d (k), u q (k), at this time, the input voltage u d (k), u q (k), Output voltage u o (k+T0 / 4), the switching state s corresponding to the second sub-interval d (k+T0 / 4+T x / 2), s q (k+T0 / 4+T x / 2), in the second mapping relationship, the first reorganized grid voltage U is obtained. d (k+T0 / 4+T) x / 2), U q (k+T0 / 4+T) x / 2). Then, the first recombined output voltage u(k+T0 / 4) and input voltage u d (k), u q (k), grid current i d (k+T0 / 4), i q (k+T0 / 4) is input into the third mapping relationship to obtain the second recombined output voltage u(k+T0 / 4+T). x / 2), and the second recombined output voltage u(k+T0 / 4+T) x / 2) Input the first mapping relationship into the first equation and perform the inverse operation to obtain the second output voltage u. o(k+T0 / 4+T x / 2). Finally, the first reorganized grid voltage U d (k+T0 / 4+T) x / 2), U q (k+T0 / 4+T) x / 2), grid current i d (k+T0 / 4), i q Inputting (k+T0 / 4) into the fourth mapping equation yields the second grid current i. d (k+T0 / 4+T x / 2), i q (k+T0 / 4+T x / 2). Based on this, the grid current i at the end of the second sub-interval was calculated. d (k+T0 / 4+T x / 2), i q (k+T0 / 4+T x / 2) Output voltage u o (k+T0 / 4+T x The predictions for / 2) are calculated, and the predictions for other sub-intervals are calculated similarly.

[0189] It is understandable that this example takes the voltage vector corresponding to the second sub-interval as the real voltage vector. If the voltage vector corresponding to the second sub-interval is a virtual voltage vector, then the switch state corresponding to the two voltage vectors that make up the number of virtual voltages can be read sequentially.

[0190] The above is a detailed description of S2. Based on the above embodiments, the construction process of the first mapping relation, the second mapping relation, the third mapping relation, and the fourth mapping relation involved in the embodiments of the present invention will be described below. It can be understood that in this embodiment, the first mapping relation, the second mapping relation, the third mapping relation, and the fourth mapping relation used in the (k+1)th prediction step will be used as examples, and the (k+2)th prediction step can refer to the (k+1)th prediction step.

[0191] In one embodiment, the third and fourth mapping relations constitute the decoupled discrete state-space model of the target transformer. The discrete state-space model can be obtained by modeling the VCS, and the first and second mapping relations can be obtained during the modeling process. The construction process of the decoupled discrete state-space model includes:

[0192] 10. Construct the initial mathematical model and power model of the target converter in the synchronous coordinate system;

[0193] 20. Construct the first and second mapping relationships;

[0194] 30. Based on the power model, the first mapping relationship, and the second mapping relationship, simplify the initial mathematical model to obtain the target mathematical model;

[0195] 40. Use the forward Euler method to convert the target mathematical model into a discrete state-space model;

[0196] 50. Eliminate coupling terms in the discrete state-space model to obtain the decoupled discrete state-space model.

[0197] The first mapping relation is:

[0198] ;

[0199] u is the recombined output voltage of the target converter, u o 2 The square of the output voltage of the target converter.

[0200] The second mapping relation is:

[0201] ;

[0202] Among them, U d To reconstruct the d-axis component of the grid voltage, U q To reconstruct the q-axis component of the grid voltage, u d u is the d-axis component of the input voltage of the target converter. o u is the output voltage of the target converter. q s is the q-axis component of the input voltage of the target converter. d For the d-axis component of the switching state of the target converter, s q The q-axis component represents the switching state of the target converter.

[0203] It should be noted that, based on the aforementioned topology description of the improved VF-MC converter, the improved VF-MC converter can be considered as two VSCs, one positive and one negative, acting on the front. and after After passing through the rectifier bridge, the output current and voltage of the two improved VSCs are the same. Therefore, when modeling, a single VSC can be modeled first, and then repeated twice to predict the entire switching cycle of the VF-MC converter. The topology of a single VSC is as follows: Figure 5 As shown, during modeling, for Figure 5 Model a single VSC in the VSC and then repeat the process twice.

[0204] The modeling process is as follows:

[0205] Assumption The AC input voltage of the power grid (i.e., the input voltage in this embodiment). If the grid current is given, then the three-phase coordinates of both can be expressed as:

[0206] (10)

[0207] a, b, and c represent phase a, phase b, and phase c, respectively, and T represents transpose.

[0208] Through Park transformation, the AC input voltage of the power grid is converted... Transform to the synchronous coordinate system to obtain its dq coordinates:

[0209] (11)

[0210] Where u0 is the zero-sequence component of the AC input voltage of the grid after Park transformation. Since the converter is set to operate in a three-phase balanced grid, u0 can be ignored. d u is the d-axis component of the AC input voltage of the power grid. q This represents the q-axis component of the AC input voltage of the power grid. This is the angular frequency of the grid voltage.

[0211] Similarly, the expression for the grid current in the synchronous coordinate system is: Where i0 is the zero-sequence component of the grid current after the Park transformation, i d Let i be the d-axis component of the grid current. q i0 is the q-axis component of the grid current. In this embodiment, i0 can be ignored.

[0212] According to the binary switching function (1), the vector expression of the switching state in three-phase coordinates can be obtained as follows:

[0213] (12)

[0214] Referring to the transformation of the AC input voltage of the reference grid, the switch state is transformed to the synchronous coordinate system, and the dq coordinates of the switch state s are obtained as follows:

[0215] (13)

[0216] Where s0 is the zero-sequence component of the switch state after the Park transformation, s d For the d-axis component of the switching state, s q For the q-axis component of the switching state, s0 can be ignored in this embodiment.

[0217] Using KVL and KCL to... Figure 5 Analyzing the VSC circuit shown, we can obtain the mathematical model of VSC in the dq coordinate system (i.e., the initial mathematical model in this embodiment):

[0218] (14)

[0219] For filtering capacitors, and These are the DC output current and the DC output voltage, respectively. and These are the filter inductor and the inductor resistor, respectively.

[0220] In modeling, the VSC is usually considered to have no self-loss, and its AC input power is equal to its DC output power. Transforming the AC input power to the synchronous coordinate system, the resulting dq coordinates are:

[0221] (15)

[0222] Among them, P in For AC input power, P out For DC output power, R L The load is represented by formula (15), which is the power model in this embodiment.

[0223] Due to the dq component of the grid current , With DC output voltage There is a non-linear relationship between them. To simplify the model and facilitate control over a single variable, three new variables are defined as follows:

[0224] (16)

[0225] From top to bottom, the first equation in formula (16) is the first mapping relation, and the second to third equations are the second mapping relations.

[0226] By combining the initial mathematical model equation (14) and the power model equation (15) and substituting them into the new variable formula (16), the simplified VSC mathematical model (i.e., the target mathematical model in this embodiment) can be obtained as follows:

[0227] (17)

[0228] Using the forward Euler method, the discrete differential equation (i.e., discrete state-space model) of VSC can be obtained as follows:

[0229] (18)

[0230] In the formula, , , , , , and The current and voltage state in the VSC circuit at time k (i.e., the end point of the k prediction step in this embodiment) can be obtained by sampling calculation. To predict the step size, , and This indicates that time k+1, or time k, has elapsed since then. The voltage and current state at time (i.e., the end point of the k+1 prediction step in this embodiment) is predicted by the above formula (18). k is a constant.

[0231] According to formula (18), and In a coupled state, such a coupled prediction formula will pose a significant obstacle when the cost function attempts to control the alternating current. For example, at a certain moment, a desired active current... Increase, reactive current While the target steady-state value can be reduced, the coupling terms in the prediction formula cause both to increase and decrease simultaneously, making it difficult to obtain the target steady-state value. Therefore, traditional VSC converters typically employ a feedforward decoupling control strategy (such as...). Figure 6 As shown in the figure, the basic idea is to introduce current coupling terms of equal magnitude and opposite sign at the output terminals of the d-axis and q-axis current regulators respectively, so as to achieve the purpose of feedforward decoupling.

[0232] By analogy with the feedforward decoupling control strategy, eliminating the decoupling terms in the discrete differential equations allows for the prediction of the decoupled state. and The decoupled discrete differential equation (i.e., the decoupled discrete state-space model) is shown in equation (19).

[0233] (19)

[0234] Based on formula (19), the third and fourth mapping relations were constructed.

[0235] The third mapping relation is:

[0236] ;

[0237] The fourth mapping relation is:

[0238] ;

[0239] Where u(k+1) is the recombined output voltage with a prediction step size of k+1, i d (k+1) represents the d-axis component of the grid current with a prediction step size of k+1, i q (k+1) represents the q-axis component of the grid current with a prediction step size of k+1. u(k) represents the recombined output voltage with a prediction step size of k, and i d(k) represents the d-axis component of the grid current with a prediction step size of k, i q (k) represents the q-axis component of the grid current with a prediction step size of k.

[0240] The above explains the construction process of the first, second, third, and fourth mapping relationships involved in the (k+1)th prediction step. The following will explain the prediction process for the grid current and output voltage at the (k+2)th prediction step.

[0241] In one embodiment, the switch vector sequence to be tested includes multiple sub-intervals to be tested ordered according to a preset timing sequence, and each sub-interval to be tested corresponds to a switching state. It is understood that the principle of the switch vector sequence to be tested is similar to that of the switch vector sequence in the previous embodiment, and the sub-intervals to be tested are similar to the sub-intervals in the switch vector sequence. Therefore, the switch vector sequence to be tested in this embodiment can participate in the switch vector sequence in the above embodiments, and will not be described again here.

[0242] S5 includes:

[0243] S51. Read the switch status of one sub-interval to be tested in sequence;

[0244] S52. Input the output voltage of the (k+1)th prediction step into the preset first mapping relationship to obtain the fifth recombined output voltage; and input the input voltage, the output voltage of the (k+1)th prediction step, and the switching state of the sub-interval to be measured into the preset second mapping relationship to obtain the fifth recombined grid voltage.

[0245] S53. Input the fifth recombined output voltage, input voltage, and grid current at the (k+1)th prediction step into the preset third mapping relationship to obtain the sixth recombined output voltage; and input the sixth recombined output voltage into the first mapping relationship to perform the inverse operation to obtain the sixth output voltage.

[0246] S54. Input the fifth recombined grid voltage and the grid current at the (k+1)th prediction step into the preset fourth mapping relationship to obtain the sixth grid current.

[0247] S55. Replace the sixth output voltage with the output voltage of the (k+1)th prediction step, and replace the sixth grid current with the grid current of the (k+1)th prediction step.

[0248] S56. Jump to execute S51 to S55 until the switch status of all sub-intervals under test has been read. Output the sixth output voltage as the output voltage of the (k+2)th prediction step and output the sixth grid current as the grid current of the (k+2)th prediction step.

[0249] It should be noted that the prediction principles of S51 to S56 are similar to those of S21 to S26. The difference lies in that S21 to S26 use the grid current, output voltage, input voltage, and switch vector sequence at the k-th prediction step to predict the grid current and output voltage at the (k+1)-th prediction step, while S51 to S56 use the grid current, output voltage, input voltage, and the switch vector sequence under test at the (k+1)-th prediction step to predict the grid current and output voltage at the (k+2)-th prediction step corresponding to that switch vector sequence. It can be understood that in one prediction process (i.e., the end point of the k-th prediction step - the end point of the (k+1)-th prediction step), the input voltage can remain unchanged by default. Therefore, the input voltage used in S51 to S56 is still u. d (k), u q (k). Based on this, the explanations of S51 to S56 can be found in S21 to S26, and will not be repeated here.

[0250] In one application example, combining Figure 8 and Figure 11 The flowchart of the predictive control method for a voltage source type three-phase AC / DC converter provided by the present invention is described. Figure 8 This is a block diagram illustrating the control principle of the predictive control method of the present invention.

[0251] The prediction process for completing one prediction is as follows: Figure 11 As shown, it includes:

[0252] Initially, sample us(k), is(k), uo(k), and switch states s1(k+1), s2(k+1), then perform dq coordinate transformation; then, calculate u(k), Ud(k), Uq(k) according to formula (16); then calculate is_ref according to formula (7); S5, calculate i according to formula (19). d (k+1), i q (k+1), u(k+1); then select n vectors from the 6 active vectors and 2 zero vectors that make i3(k+1)≥0; then refer to Table 2, combine the vectors in Table 1 pairwise and record their numbers to form a vector set; then select N vectors in the vector set that contain the previously pre-selected numbers; then for i=1:N; then perform dq transformation on the voltage vector vec(i) and calculate U. d (k+1), U q (k+1); then calculate i according to equation (19). d (k+2), i q(k+2), u(k+2); then substitute the predicted value and the reference value into the cost function, i.e., formula (9), to calculate g; then set i=i+1; then determine whether i is equal to 20. If yes, select the minimum cost g and the corresponding label i, and select the minimum cost g and the corresponding label i. Otherwise, jump to execute for i=1:N.

[0253] Since the improved VF-MC can be regarded as two VSCs operating alternately in positive and negative directions, and the predictive control process of each VSC is similar, the difference lies in the different switching state values ​​used. Therefore, s1(k+1) and s2(k+1) are used to represent the switching states of the two VSCs respectively.

[0254] As can be seen from the above process, this application example samples at the end of step k. Based on the current and voltage state at that time and the switching state vector to be used in step k+1, the current and voltage state at the end of step k+1 can be predicted. Then, the optimal switching vector sequence that minimizes the cost function in the control set is selected by the FCS-MPC algorithm and applied to the circuit.

[0255] In a simulation application example, the predictive control method of a voltage source type three-phase AC / DC converter provided in the aforementioned embodiment was simulated and verified. The simulation parameters are shown in Table 3.

[0256] Table 3

[0257]

[0258] Simulation results are as follows Figures 12 to 15 And as shown in Table 4. Among them, Figure 12 The input and output voltage and current waveforms at 1000W output power are shown. Figure 12 It can be seen that the target control quantity can quickly reach the steady-state value, and the DC output voltage can accurately track the voltage reference value. It can also be seen that the AC input voltage and current are in phase, and the power factor is 0.9997 in steady state. Figure 13 The results showed that the total harmonic distortion (THD) of the phase current was only 3.16% at a 1000W output power, meeting the grid THD requirement of <5%. Figure 13 In the figure, the fundamental amplitude at 50 Hz is 11.63, and the vertical axis represents the percentage relative to the fundamental frequency. Figure 14 The current and voltage waveforms at both ends of the HFT were displayed. The commutation was successfully completed within the reserved time without any voltage spikes caused by voltage mismatch at both ends of the transformer. Figure 15 The input and output voltage and current waveforms are shown when the output power is reduced from 1000W to 500W, and a new steady state can be reached in just 0.004s. Table 4 shows the changes in various system parameters under different output powers.

[0259] Table 4

[0260]

[0261] In summary, this invention provides a predictive control method for a voltage source type three-phase AC / DC converter, used for the improved VF-MC finite control set model predictive control, realizing the establishment of the discrete state-space model of the converter. Furthermore, in the simplification steps of the discrete state-space model, the coupling term between the d-axis and q-axis currents is eliminated, achieving decoupled prediction. Moreover, by using a vector set with a fixed duty cycle consisting of 6 active vectors, 2 zero vectors, and 12 virtual voltage vectors for predictive control, the risk of commutation failure is effectively reduced. Furthermore, by constructing a cost function for selecting the optimal voltage vector, and considering the tracking errors of the AC input current and DC output voltage in the cost function, the control accuracy is improved. Simultaneously, compared to the traditional SVM+PI control which requires tuning multiple PI controller parameters, resulting in a cumbersome and complex tuning process, this invention mainly tunes the weight parameters in the cost function, requiring fewer tuning parameters and greatly simplifying the debugging process. Furthermore, simulation verification shows that the predictive control method provided by this invention improves the state response speed of the model, requiring only about 0.004s to reach steady state again after load shedding, significantly enhancing the response speed. Moreover, the predictive control scheme provided by this invention applies FCS-MPC to isolated AC / DC matrix converters, breaking the technical bias that CS-MPC algorithms are all based on non-isolated AC / DC matrix converter topologies. Due to the numerous switching states and complex models of IAMCs, they are difficult to apply to isolated AC / DC matrix converter topologies. Furthermore, the predictive control method provided by this invention, when applied to isolated AC / DC matrix converters, also improves the operational safety of isolated AC / DC matrix converters.

[0262] The present invention also provides a predictive control device for a voltage source type three-phase AC / DC converter, the predictive control device including a processor and a memory:

[0263] The memory is used to store program code and transfer the program code to the processor;

[0264] The processor is used to execute the methods of any of the above embodiments according to instructions in the program code.

[0265] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0266] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A predictive control method for a voltage source type three-phase AC / DC converter, characterized in that, include: S1. Obtain the input voltage of the target converter in the synchronous coordinate system, the grid current at the kth prediction step, and the switching vector sequence at the (k+1)th prediction step; and obtain the output voltage of the target converter at the kth prediction step. S2. Determine the output voltage and grid current of the (k+1)th prediction step based on the output voltage of the kth prediction step, the grid current of the kth prediction step, the input voltage, and the switching vector sequence; S3. Obtain the switching state corresponding to each voltage vector of the target converter, and determine the target voltage vector pair of the target converter based on the switching state corresponding to each voltage vector and the grid current of the (k+1)th prediction step. And the target voltage vector pairs are combined into a target vector set; S4. Select a pair of target voltage vectors from the target vector set, and construct a corresponding test switch vector sequence using the target voltage vector pair and the zero vector of the target converter; S5. Based on the vector sequence of the switch to be tested, the input voltage, the output voltage of the (k+1)th prediction step, and the grid current of the (k+1)th prediction step, determine the grid current of the (k+2)th prediction step and the output voltage of the (k+2)th prediction step. S6. Input the grid current and the output voltage of the (k+2)th prediction step into the pre-constructed cost function to obtain the cost function value; S7. Jump to execute S4 to S7 until the cost function values ​​corresponding to all the switch vector sequences to be tested have been calculated. Output the switch vector sequence to be tested corresponding to the minimum cost function value among all cost function values ​​as the optimal switch vector sequence, and apply the optimal switch vector sequence to the target converter of the (k+2)th prediction step.

2. The predictive control method according to claim 1, characterized in that, The switch vector sequence includes multiple sub-intervals ordered according to a preset time sequence, each sub-interval corresponding to a switch state, and S2 includes: S21. Read the switch status of one of the sub-intervals in sequence; S22. Input the output voltage of the kth prediction step into a preset first mapping relationship to obtain the first reconstructed output voltage; and input the input voltage, the output voltage of the kth prediction step, and the switching state of the sub-interval into a preset second mapping relationship to obtain the first reconstructed grid voltage. S23. Input the first recombined output voltage, the input voltage, and the grid current at the kth prediction step into a preset third mapping formula to obtain the second recombined output voltage; and input the second recombined output voltage into the first mapping formula to perform an inverse operation to obtain the second output voltage. S24. Input the first reconstructed grid voltage and the grid current at the kth prediction step into the preset fourth mapping formula to obtain the second grid current; S25. Replace the second output voltage with the output voltage of the kth prediction step size, and replace the second grid current with the grid current of the kth prediction step size; S26. Jump to execute S21 to S25 until the switch status of all sub-intervals has been read. Output the second output voltage as the output voltage of the (k+1)th prediction step size, and output the second grid current as the grid current of the (k+1)th prediction step size.

3. The predictive control method according to claim 2, characterized in that, The step of determining the target voltage vector pair of the target converter based on the switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step includes: The switching state corresponding to each voltage vector and the grid current at the (k+1)th prediction step are input into the preset output current relationship to obtain each output current value. The output current value that is not less than zero among the aforementioned output current values ​​shall be taken as the target current value; The voltage vector corresponding to the target current value is taken as the target voltage vector; According to the preset combination rules, the target voltage vectors are combined in pairs to obtain target voltage vector pairs.

4. The predictive control method according to claim 3, characterized in that, The test switch vector sequence includes multiple test sub-intervals ordered according to a preset timing sequence, each test sub-interval corresponding to a switch state, and S5 includes: S51. Read the switch status of one of the sub-intervals to be tested in sequence; S52. Input the output voltage of the (k+1)th prediction step and the switching state of the sub-interval to be tested into a preset first mapping relationship to obtain the fifth reconstructed output voltage; and input the input voltage, the output voltage of the (k+1)th prediction step and the switching state of the sub-interval to be tested into a preset second mapping relationship to obtain the fifth reconstructed grid voltage. S53. Input the fifth recombined output voltage, the input voltage, and the grid current at the (k+1)th prediction step into a preset third mapping formula to obtain the sixth recombined output voltage; and input the sixth recombined output voltage into the first mapping formula to perform an inverse operation to obtain the sixth output voltage. S54. Input the fifth reconstructed grid voltage and the grid current at the (k+1)th prediction step into the preset fourth mapping formula to obtain the sixth grid current. S55. Replace the sixth output voltage with the output voltage of the (k+1)th prediction step, and replace the sixth grid current with the grid current of the (k+1)th prediction step; S56. Jump to execute S51 to S55 until the switch status of all sub-intervals under test has been read. Output the sixth output voltage as the output voltage of the (k+2)th prediction step size, and output the sixth grid current as the grid current of the (k+2)th prediction step size.

5. The predictive control method according to claim 4, characterized in that, The step of constructing the corresponding switch vector sequence under test using the target voltage vector pair and the zero vector of the target converter includes: The duration of the zero vector and the duration of each voltage vector in the target voltage vector pair are determined and used as the test sub-intervals of the switch vector sequence to be tested; The order of action of each voltage vector in the zero vector and target voltage vector pair of the target converter is obtained, and each sub-interval to be tested is sorted in turn according to the order of action to obtain the sequence of switch vectors to be tested.

6. The predictive control method according to claim 5, characterized in that, The third and fourth mapping relationships constitute the decoupled discrete state-space model of the target transformer; wherein, the construction process of the decoupled discrete state-space model includes: Construct the initial mathematical model and power model of the target converter in the synchronous coordinate system; Construct the first mapping relation and the second mapping relation; Based on the power model, the first mapping relationship, and the second mapping relationship, the initial mathematical model is simplified to obtain the target mathematical model; The forward Euler method is used to convert the target mathematical model into a discrete state-space model; Eliminating the coupling terms in the discrete state-space model yields a decoupled discrete state-space model.

7. The predictive control method according to claim 6, characterized in that, The cost function is: ； Where g is the cost function value, and λ1 is the first weight coefficient. i is the reference value for the d-axis component of the grid current. d (k+2) represents the d-axis component of the grid current with a prediction step size of k+2. i is the reference value for the q-axis component of the grid current. q (k+2) represents the q-axis component of the grid current with a prediction step size of k+2, and λ2 is the second weighting coefficient. u is the reference value for the DC output voltage. o (k+2) represents the output voltage with a prediction step size of k+2.

8. The predictive control method according to claim 7, characterized in that, The first mapping relationship is: ； u is the recombined output voltage of the target converter, u o 2 The square of the output voltage of the target converter.

9. The predictive control method according to claim 8, characterized in that, The second mapping relationship is: ； Among them, U d To reconstruct the d-axis component of the grid voltage, U q To reconstruct the q-axis component of the grid voltage, u d u is the d-axis component of the input voltage of the target converter. o u is the output voltage of the target converter. q s is the q-axis component of the input voltage of the target converter. d For the d-axis component of the switching state of the target converter, s q The q-axis component represents the switching state of the target converter.

10. A predictive control device for a voltage source type three-phase AC / DC converter, characterized in that, The predictive control device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is configured to execute the method as described in any one of claims 1-9 according to instructions in the program code.

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