A pair of two wireless energy transmission system with adaptive power allocation and implementation method thereof

Abstract

The application discloses a pair of two wireless energy transmission systems with adaptive power distribution and an implementation method thereof, which comprises a transmitting resonant circuit, two receiving resonant circuits and two receiving chips with different coupling coefficients. The transmitting resonant circuit is used for transmitting wireless energy. The two receiving resonant circuits are connected with the transmitting resonant circuit and are used for receiving the wireless energy. Each of the two receiving resonant circuits comprises a detuning capacitor and a switch tube, so as to introduce a detuning rectification mode and a detuning idle mode. The two receiving chips with different coupling coefficients are connected with the two receiving resonant circuits and a load respectively and are used for converting the wireless energy into direct-current electric energy. Each of the two receiving chips comprises a current sampling circuit, an amplitude detection circuit and a control circuit, which are used for acquiring power information of the other receiving chip and realizing inter-receiving communication. The application can realize adaptive power distribution and stable output voltage and can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a one-to-two wireless power transfer system with adaptive power distribution and its implementation method. Background Technology

[0002] A one-to-two wireless power transfer system can flexibly power multiple portable smart devices simultaneously. In receiver chip design, traditional single-stage rectification and regulation architectures can achieve high energy conversion efficiency, but their impedance switching can lead to incorrect power distribution in a one-to-two wireless power transfer system, resulting in unstable output voltage and high load regulation. Furthermore, differences in coupling coefficients between different receiver chips can also cause uneven power distribution, leading to unstable output voltage. Summary of the Invention

[0003] To address the aforementioned technical problems, the purpose of this application is to provide a one-to-two wireless power transmission system with adaptive power distribution and its implementation method, thereby achieving adaptive power distribution and stable output voltage.

[0004] To achieve the above objectives, one aspect of this application proposes a one-to-two wireless power transfer system with adaptive power allocation, comprising: A transmitting resonant circuit is used to transmit wireless energy; Both receiving resonant circuits are connected to the transmitting resonant circuit for receiving the wireless energy. Each circuit includes a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. Two receiving chips with different coupling coefficients are respectively connected to the two receiving resonant circuits and the load to convert the wireless energy into DC power. Each chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit to obtain the power information of the other receiving chip and realize communication between the receivers.

[0005] In some embodiments, the transmitting resonant circuit includes a transmitting inductor and a transmitting capacitor. One end of the transmitting inductor is connected to one end of the transmitting circuit, and the other end of the transmitting inductor is connected to one end of the transmitting capacitor. The other end of the transmitting capacitor is connected to the other end of the transmitting circuit, and the transmitting circuit is used to drive the transmitting resonant circuit.

[0006] In some embodiments, the receiving resonant circuit further includes a receiving inductor and a receiving capacitor. One end of the receiving inductor is connected to the receiving chip through the receiving capacitor, and the other end of the receiving inductor is connected to the receiving chip through the detuning capacitor. The gate of the switching transistor is connected to the receiving chip. One end of the receiving inductor and one end of the detuning capacitor are both connected to the drain of the switching transistor. The source of the switching transistor is connected between the detuning capacitor and the receiving chip.

[0007] In some embodiments, the receiving chip further includes: A single-stage rectifier bridge, connected to the receiving resonant circuit, the control circuit, and the load, is used to convert the wireless energy into DC power to supply power to the load. A driving circuit, connected to the receiving resonant circuit and the control circuit, is used to control the switching transistor to be turned on or off. A feedback circuit, connected to the control circuit, is used to detect the output voltage and achieve voltage regulation control.

[0008] In some embodiments, the control circuit includes: An output detection circuit is connected to the feedback circuit; A hysteresis voltage regulator circuit, connected to the feedback circuit and the output detection circuit, is used to generate a hysteresis voltage regulator control signal, which is used to control the single-stage rectifier bridge to achieve rectification or idling. A time-division multiplexing enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit, and is used to generate a square wave clock signal, which is used for time-division multiplexing control. An amplitude detection enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit, and is used to drive the amplitude detection circuit. The AND gate has its first input connected to the hysteresis voltage regulator circuit, its second input connected to the time-division multiplexing enable circuit, and its output connected to the drive circuit. It is used to generate a switching transistor control signal, which is used to control the switching transistor to turn on or off.

[0009] In some embodiments, the time-division multiplexing enable circuit includes a first positive pulse generating circuit, a second positive pulse generating circuit, a third positive pulse generating circuit, an SR flip-flop, a first OR gate, a second OR gate, and a clock generating circuit. One end of the first positive pulse generating circuit is connected to the amplitude detection circuit, and the other end of the first positive pulse generating circuit is connected to the first pin of the SR flip-flop. One end of the second positive pulse generating circuit is connected to the hysteresis voltage regulator circuit, and the other end of the second positive pulse generating circuit is connected to the first input of the first OR gate. One end of the third positive pulse generating circuit is connected to the output detection circuit, and the other end of the third positive pulse generating circuit is connected to the second input of the first OR gate. The output of the first OR gate is connected to the second pin of the SR flip-flop. The third pin of the SR flip-flop is connected to one end of the clock generating circuit, and the other end of the clock generating circuit is connected to the first input of the second OR gate. The third pin of the SR flip-flop is also connected to the second input of the second OR gate, and the output of the second OR gate is connected to the second input of the AND gate.

[0010] In some embodiments, the clock generation circuit includes an oscillator, a fourth positive pulse generation circuit, a first D flip-flop, a second D flip-flop, and a NOR gate. One end of the oscillator is connected to the third pin of the SR flip-flop, and the other end of the oscillator is connected to one end of the fourth positive pulse generation circuit. The other end of the fourth positive pulse generation circuit is connected to one end of the first D flip-flop, and the other end of the first D flip-flop is connected to one end of the second D flip-flop. The first input terminal of the NOR gate is connected to the first D flip-flop, and the second input terminal of the NOR gate is connected to the second D flip-flop.

[0011] In some embodiments, the output terminal of the current sampling circuit is connected to the input terminal of the amplitude detection circuit, and the amplitude detection circuit is connected to the control circuit.

[0012] In some embodiments, the amplitude detection circuit includes a diode, a transistor, a Schmitt trigger, two capacitors, two resistors, two operational amplifiers, and two AND gates.

[0013] To achieve the above objectives, another aspect of this application proposes a method for implementing a one-to-two wireless power transfer system with adaptive power allocation, comprising the following steps: Transmit wireless energy through a transmitting resonant circuit; The wireless energy is received through two receiving resonant circuits, each of which includes a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. The wireless energy is converted into DC power by two receiving chips with different coupling coefficients. Each receiving chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit. The power information of the other receiving chip is obtained through the current sampling circuit, the amplitude detection circuit, and the control circuit, thereby realizing communication between the receivers.

[0014] The beneficial effects of this application are as follows: This application discloses a one-to-two wireless power transmission system with adaptive power distribution and its implementation method, comprising a transmitting resonant circuit, two receiving resonant circuits, and two receiving chips with different coupling coefficients. The transmitting resonant circuit is used to transmit wireless energy; the receiving resonant circuit is used to receive wireless energy, and both include a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode; the receiving chips are used to convert wireless energy into DC power, and both include a current sampling circuit, an amplitude detection circuit, and a control circuit to obtain the power information of the other receiving chip and realize communication between the receivers. This application adds a switching transistor and a detuned capacitor to the traditional single-stage rectification and voltage regulation architecture, and introduces a detuned rectification mode and a detuned idling mode on top of the original rectification mode and idling mode. In these two detuned modes, the detuned capacitor reduces the reflection impedance of the corresponding receiving chip, solving the power distribution problem of the traditional single-stage rectification and voltage regulation architecture; and by obtaining the power information of each other's receiving chips through the current sampling circuit, amplitude detection circuit, and control circuit, the power distribution problem caused by the coupling coefficient is solved, achieving adaptive power distribution and stabilizing the output voltage. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of a one-to-two wireless power transfer system with adaptive power allocation provided in one embodiment of this application; Figure 2 This is a circuit block diagram of a one-to-two wireless power transfer system with adaptive power allocation provided in one embodiment of this application; Figure 3 This is a schematic flowchart illustrating mistuning control according to one embodiment of this application; Figure 4 A circuit block diagram of a control circuit provided in one embodiment of this application; Figure 5 A circuit block diagram of a time-division multiplexing enable circuit and a clock generation circuit provided in one embodiment of this application; Figure 6 A circuit block diagram of an amplitude detection circuit provided in one embodiment of this application; Figure 7 A flowchart illustrating the workflow of a one-to-two wireless power transfer system with adaptive power allocation provided in one embodiment of this application; Figure 8 A schematic diagram of the working waveforms of a one-to-two wireless power transfer system with adaptive power allocation provided in one embodiment of this application; Figure 9 A schematic diagram of a one-to-two wireless power transfer system with adaptive power allocation provided in one embodiment of this application; Figure 10 This is a comparison diagram of steady-state test waveforms provided in one embodiment of this application; Figure 11 This is a load regulation test curve provided in one embodiment of the present application; Figure 12 This is a schematic diagram illustrating the steps of an implementation method for a one-to-two wireless power transfer system with adaptive power allocation, provided in one embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0018] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0019] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0020] A one-to-two wireless power transfer system can flexibly power multiple portable smart devices simultaneously. However, traditional one-to-two wireless power transfer systems have the following shortcomings: I. In a traditional single-stage rectifier and voltage regulator architecture, the receiver exhibits low reflected impedance and low received power when in rectification mode supplying power to the output; however, it exhibits high reflected impedance and high received power when in idle mode supplying no power to the output. Therefore, in a one-to-two wireless power transmission system, the receiver chip in rectification mode receives insufficient power, resulting in unstable output voltage and high load regulation; while the receiver chip in idle mode receives high received power, leading to power waste.

[0021] Second, different distances between the receiving and transmitting coils result in different coupling coefficients, and the reflected impedance and received power are positively correlated with the coupling coefficient. Therefore, in a one-to-two wireless power transfer system, the receiving chip with a low coupling coefficient receives insufficient power, leading to unstable output voltage and high load regulation.

[0022] Third, a fully integrated communication circuit between receivers has not yet been proposed, so the receiver chips cannot obtain each other's received power information, making it impossible to further achieve adaptive power allocation.

[0023] In view of this, this application proposes a one-to-two wireless power transmission system with adaptive power distribution, including a transmitting resonant circuit, two receiving resonant circuits, and two receiving chips with different coupling coefficients. The transmitting resonant circuit is used to transmit wireless energy; the receiving resonant circuit is used to receive wireless energy, and both include a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. The receiving chips are used to convert wireless energy into DC power, and both include a current sampling circuit, an amplitude detection circuit, and a control circuit to obtain the power information of the other receiving chip and realize communication between the receivers. This application adds a switching transistor and a detuned capacitor to the traditional single-stage rectification and voltage regulation architecture, and introduces a detuned rectification mode and a detuned idling mode on top of the original rectification mode and idling mode. In these two detuned modes, the detuned capacitor reduces the reflection impedance of the corresponding receiving chip, solving the power distribution problem of the traditional single-stage rectification and voltage regulation architecture; and by obtaining the power information of each other's receiving chips through the current sampling circuit, amplitude detection circuit, and control circuit, the power distribution problem caused by the coupling coefficient is solved, realizing adaptive power distribution and stabilizing the output voltage.

[0024] Reference Figure 1 , Figure 1 This is a structural block diagram of a one-to-two wireless power transfer system with adaptive power allocation according to an embodiment of this application. The embodiment of this application proposes a one-to-two wireless power transfer system with adaptive power allocation, comprising: A transmitting resonant circuit is used to transmit wireless energy; Both receiving resonant circuits are connected to the transmitting resonant circuit for receiving wireless energy. Both circuits include detuned capacitors and switching transistors to introduce detuned rectification mode and detuned idling mode. Two receiver chips with different coupling coefficients are connected to two receiver resonant circuits and a load, respectively, to convert wireless energy into DC power. Each chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit to obtain the power information of the other receiver chip and realize communication between the receivers.

[0025] Reference Figure 2 , Figure 2 The circuit block diagram of a one-to-two wireless power transfer system with adaptive power distribution provided in one embodiment of this application is shown. As an optional implementation, the output terminal of the current sampling circuit is connected to the input terminal of the amplitude detection circuit, and the amplitude detection circuit is connected to the control circuit.

[0026] Specifically, such as Figure 1 As shown, the circuit architecture of this embodiment includes a transmitting resonant circuit, two receiving resonant circuits, and two receiving chips with different coupling coefficients. The receiving resonant circuit includes a detuning capacitor C. DT and switching transistor M N The receiving chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit.

[0027] It should be noted that, on the one hand, the embodiments of this application add a switching transistor M to the traditional single-stage rectification and regulation architecture. N With detuned capacitor C DT In addition to the existing rectification and idling modes, detuned rectification and detuned idling modes are introduced. In these two detuned modes, the detuned capacitor reduces the reflection impedance of the receiving chip, solving the power distribution problem of the traditional single-stage rectification and voltage regulation architecture, thus enabling appropriate power distribution in a one-to-two wireless power transmission system. Furthermore, the current sampling circuit, amplitude detection circuit, and output detection circuit in the control circuit of this embodiment constitute an inter-receiver communication circuit. This inter-receiver communication circuit detects the magnitude of the received current to obtain the received power information of each chip, and works in conjunction with the time-division multiplexing circuit in the control circuit to solve the power distribution problem caused by the coupling coefficient.

[0028] Reference Figure 2 As an optional implementation, the transmitting resonant circuit includes a transmitting inductor and a transmitting capacitor. One end of the transmitting inductor is connected to one end of the transmitting circuit, the other end of the transmitting inductor is connected to one end of the transmitting capacitor, and the other end of the transmitting capacitor is connected to the other end of the transmitting circuit. The transmitting circuit is used to drive the transmitting resonant circuit.

[0029] Specifically, in the external portion, the transmitting inductor L TX and emitter capacitance C TXIt forms a transmitting resonant circuit, driven by the transmitting circuit, to realize wireless power transmission.

[0030] Reference Figure 2 As an optional implementation, the receiving resonant circuit further includes a receiving inductor and a receiving capacitor. One end of the receiving inductor is connected to the receiving chip through the receiving capacitor, and the other end of the receiving inductor is connected to the receiving chip through the detuning capacitor. The gate of the switching transistor is connected to the receiving chip. One end of the receiving inductor and one end of the detuning capacitor are both connected to the drain of the switching transistor. The source of the switching transistor is connected between the detuning capacitor and the receiving chip.

[0031] Specifically, the receiving inductor L RX Receiver capacitor C RX Detuned capacitor C DT and switching transistor M N It forms a receiving resonant circuit to receive wireless energy and power subsequent receiving chips and loads.

[0032] Reference Figure 2 As an optional implementation, the receiving chip further includes: A single-stage rectifier bridge, connected to the receiving resonant circuit, control circuit, and load, is used to convert wireless energy into DC power to supply power to the load. The driving circuit, connected to the receiving resonant circuit and the control circuit, is used to control the switching transistor to be turned on or off. The feedback circuit, connected to the control circuit, is used to detect the output voltage and achieve voltage regulation control.

[0033] Specifically, the receiving chip includes a single-stage rectifier bridge, a current sampling circuit, an amplitude detection circuit, a control circuit, a drive circuit, and a feedback circuit. The single-stage rectifier bridge is used for AC-DC energy conversion to drive the load; the control circuit generates relevant control signals for hysteresis regulation, detuning control, and time-division multiplexing control; and the drive circuit controls the switching transistor M. N Turning on and off, when the switching transistor M N Short-circuit detuning capacitor C when turned on DT The output detection, current sampling circuit, and amplitude detection circuit are used to achieve communication between receivers; the feedback circuit is used to detect the output voltage V. O This achieves voltage stabilization control.

[0034] In some alternative embodiments, such as Figure 3 The diagram shown illustrates the detuning control process. The idling and rectification modes are the same as the traditional single-stage rectifier and voltage regulator architecture. In this case, the switching transistor M... N Turn on, detuned capacitor C DT Short-circuited. In idling mode, the two rectifier input nodes V... X and V YThe total receiving impedance Z is connected to ground via two N-type power transistors. RX R is the on-resistance of the two power transistors. ON Added together, i.e., 2R ON Based on the reflection impedance Z RL With the receiving impedance Z RX Relationship, Z RL Represented as ω 2 M 2 / (2R ON ), where ω is the resonant angular frequency of the wireless power transfer system, and M is the L TX With L RX The mutual inductance coefficient, and M is positively correlated with the coupling coefficient.

[0035] In rectification mode, the receiving impedance is the equivalent input resistance R of the full-bridge rectification. RECT Corresponding to Z RL For ω 2 M 2 / (2R RECT Furthermore, the detuning control proposed in this application introduces additional detuning idling mode and detuning rectification mode. At this time, the switching transistor M... N Turn off, via series detuning capacitor C DT Z RX It will increase a detuning impedance Z DT This reduces Z RL In the detuning control proposed in the embodiments of this application, the detuning capacitor C DT The value is 1 / 2C RX Corresponding to Z DT ≈jωL RX +3 / (jωC RX ).

[0036] When time division multiplexing control is not activated, the receiving chip only switches between rectification mode and detuned idling mode. Because the reflection impedance is higher in rectification mode, the receiving chip receives more power, while the detuned idling mode receives only a small amount of useless power, thus achieving appropriate power distribution.

[0037] It should be noted that the time-division multiplexing control method of this application can eliminate the influence of the coupling coefficient in a one-to-two wireless power transmission system, achieving adaptive power allocation. After communication is completed, the receiving chip with a high coupling coefficient will switch between rectification and detuned rectification modes. When the receiving chip with a high coupling coefficient is in rectification mode, its reflection impedance is higher, and it obtains most of the received power; when the receiving chip with a high coupling coefficient is in detuned rectification mode, its reflection impedance will decrease, allowing the other receiving chip with a low coupling coefficient to obtain most of the received power, thus achieving adaptive power allocation.

[0038] Reference Figure 2 and 4 , Figure 4 The circuit block diagram of the control circuit provided in one embodiment of this application is shown. Further, as an optional implementation, the control circuit includes: The output detection circuit is connected to the feedback circuit. The hysteresis voltage regulator circuit, connected to the feedback circuit and the output detection circuit, is used to generate a hysteresis voltage regulator control signal. The hysteresis voltage regulator control signal is used to control the single-stage rectifier bridge to achieve rectification or idling. The time-division multiplexing enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit. It is used to generate a square wave clock signal, which is used for time-division multiplexing control. An amplitude detection enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit, and is used to drive the amplitude detection circuit. The AND gate has its first input connected to a hysteresis voltage regulator circuit, its second input connected to a time-division multiplexing enable circuit, and its output connected to a driver circuit. It is used to generate a switching transistor control signal, which is used to control the switching transistor to turn on or off.

[0039] Specifically, the hysteresis voltage regulator circuit outputs a hysteresis voltage regulation control signal V. RM This circuit controls a single-stage rectifier bridge to perform rectification or idling. It includes a negative pulse generation circuit composed of delay units and NAND gates, which generates a low-level signal for a certain duration upon detecting a rising edge. The time-division multiplexing enable circuit outputs a square wave clock signal V with a 25% duty cycle. CLK Used to start time-division multiplexing control; amplitude detection enable circuit is used to start amplitude detection circuit; AND gate output switch control signal V DTU Used to control the switching transistor M N The on / off states constitute the four operating modes in detuning control; the output detection and amplitude detection circuits in the control circuit enable communication between the receivers, generating a signal V. DBLK .

[0040] Reference Figure 4As a further optional implementation, the time-division multiplexing enable circuit includes a first positive pulse generating circuit, a second positive pulse generating circuit, a third positive pulse generating circuit, an SR flip-flop, a first OR gate, a second OR gate, and a clock generating circuit. One end of the first positive pulse generating circuit is connected to the amplitude detection circuit, and the other end of the first positive pulse generating circuit is connected to the first pin of the SR flip-flop. One end of the second positive pulse generating circuit is connected to the hysteresis regulator circuit, and the other end of the second positive pulse generating circuit is connected to the first input of the first OR gate. One end of the third positive pulse generating circuit is connected to the output detection circuit, and the other end of the third positive pulse generating circuit is connected to the second input of the first OR gate. The output of the first OR gate is connected to the second pin of the SR flip-flop. The third pin of the SR flip-flop is connected to one end of the clock generating circuit, and the other end of the clock generating circuit is connected to the first input of the second OR gate. The third pin of the SR flip-flop is also connected to the second input of the second OR gate, and the output of the second OR gate is connected to the second input of the AND gate.

[0041] The first positive pulse generation circuit, the second positive pulse generation circuit, and the third positive pulse generation circuit are used to generate a high level for a certain period of time when a rising edge is detected.

[0042] Reference Figure 5 , Figure 5 The present invention provides a circuit block diagram of a time-division multiplexing enable circuit and a clock generation circuit according to one embodiment. As an optional implementation, the clock generation circuit includes an oscillator, a fourth positive pulse generation circuit, a first D flip-flop, a second D flip-flop, and a NOR gate. One end of the oscillator is connected to the third pin of the SR flip-flop, and the other end of the oscillator is connected to one end of the fourth positive pulse generation circuit. The other end of the fourth positive pulse generation circuit is connected to one end of the first D flip-flop, and the other end of the first D flip-flop is connected to one end of the second D flip-flop. The first input terminal of the NOR gate is connected to the first D flip-flop, and the second input terminal of the NOR gate is connected to the second D flip-flop.

[0043] The fourth positive pulse generation circuit is used to generate a high level for a certain period of time when a falling edge is detected.

[0044] Reference Figure 6 , Figure 6 The present invention provides a circuit block diagram of an amplitude detection circuit according to one embodiment. Further, as an optional implementation, the amplitude detection circuit includes a diode, a transistor, a Schmitt trigger, two capacitors, two resistors, two operational amplifiers, and two AND gates.

[0045] Among them, the Schmitt trigger is an inverter with a hysteresis voltage window.

[0046] In summary, as Figure 7The diagram shows the workflow of a one-to-two wireless power transfer system with adaptive power allocation. Figure 8 The diagram shows the working waveforms of a one-to-two wireless power transfer system with adaptive power allocation.

[0047] Reference Figure 7 In stage I, when the uneven power distribution caused by the coupling coefficient is not significant, receiver chips 1 and 2 switch between rectification and detuning idling modes, and achieve adaptive power distribution through reflection impedance.

[0048] In stage II, due to the low coupling coefficient of receiver chip 1, the receiving current i RX1 Insufficient. At this time, although receiver chip 1 is operating in rectification mode (V... HY =1), low receiving current i RX1 It still cannot drive the load, causing the output voltage V to... O decline.

[0049] In Phase III, through Figure 4 The output detection circuit shown outputs a voltage V. O1 Below the threshold voltage V TH1 At that time, signal V DVO It will be set high, generating a negative pulse signal V of <10μs. BLK1 And temporarily set V to zero RM This causes receiver chip 1 to briefly enter idle mode. Idle mode has a higher reflective impedance, resulting in reduced received power and current i. RX1 Increase, and thus reduce, the receiving power and current i of receiver chip 2 with high coupling coefficient. RX2 Subsequently, receiver chip 1 will return to rectification mode. The amplitude detection circuit of receiver chip 2 will detect i RX2 The amplitude of the sampled signal V decreases, causing it to drop. AVG2 Below the threshold voltage V TH4 Generates a positive pulse signal V DBLK This completes the communication between receivers.

[0050] In phase IV, signal V DBLK The rising edge will set the signal V high. C2 This enables the clock, thus achieving time-division multiplexing control. When the square wave clock signal V... CLK When it is at a high level, signal V DTU The voltage is high, and receiver chip 2 is in rectification mode. Although both receiver chip 1 and receiver chip 2 are in rectification mode, receiver chip 2 has a higher coupling coefficient and therefore a higher reflection impedance. Thus, most of the power will flow to receiver chip 2. When the square wave clock signal V... CLK When it is at a low level, signal V DTUWhen the voltage is low, receiver chip 2 enters detuned rectification mode, reducing the reflection impedance. At this time, most of the power will flow to receiver chip 1, thus achieving adaptive power allocation. Square wave clock signal V CLK The duty cycle is 25% to ensure that the receiver chip 1 with insufficient power can receive power for a long time, thereby achieving stable output voltage and high load regulation.

[0051] In stage V, there are two outputs V. O1 and V O2 Both are charged to the target value and switched to detuned idling mode, and receiver chip 2 will turn off time division multiplexing control until the next inter-received communication circuit is started.

[0052] The structure, working principle, and workflow of the adaptive power distribution one-to-two wireless power transfer system according to the embodiments of this application have been described above. It can be recognized that the embodiments of this application have the following advantages compared with the traditional single-stage rectification and voltage regulation architecture: First, a detuning control method is proposed. Based on the traditional single-stage rectifier and voltage regulator architecture, a detuned rectification mode and a detuned idling mode are introduced. By introducing additional detuning capacitors, these two modes reduce the reflection impedance of the receiving chip, thus solving the problems of high reflection impedance and high received power in the idling mode. In a one-to-two wireless power transmission system, the reflection impedance of the detuned idling mode is lower than that of the rectification mode, allowing the receiving chip to achieve appropriate power distribution.

[0053] Second, a communication method between receivers is proposed. The communication circuit between receivers consists of a current sampling circuit, an amplitude detection circuit, and an output detection circuit. The receiving current is detected by this circuit, so that the receiving chips can obtain each other's receiving power information. In addition, the time-division multiplexing circuit is used to solve the power distribution problem caused by the coupling coefficient, so as to realize a fully integrated design.

[0054] Third, a time-division multiplexing control method is proposed. After obtaining power information through the inter-receiver communication circuit, the receiver chip with a high coupling coefficient generates a clock signal, causing the receiver chip to switch between rectification mode and detuned rectification mode. In a one-to-two wireless power transmission system, the influence of the coupling coefficient can be eliminated, and adaptive power allocation can be achieved.

[0055] The effectiveness of the adaptive power allocation one-to-two wireless power transfer system of this application is illustrated below with specific examples.

[0056] like Figure 9 The diagram shows the structure of the one-to-two wireless power transfer system with adaptive power allocation proposed in this application. When the coupling coefficient k2 = 0.28 is greater than k1 = 0.14, adaptive power allocation is achieved through the detuning control and time-division multiplexing control proposed in this application, as well as inter-receiver communication, resulting in a stable output voltage V. O1 and VO2 Optimize load regulation rate.

[0057] like Figure 10 The image shown is a comparison of steady-state test waveforms. Figure 10 As can be seen, the detuning control and time-division multiplexing control proposed in this application can effectively achieve power distribution and 4V regulated output, ensuring system stability and expanding the application range. Figure 11 The figure shown is a load regulation rate test curve. Figure 11 As can be seen, the detuning and time-division multiplexing control proposed in this application greatly optimizes the load regulation rate, especially for the receiver chip 1 with low coupling coefficient, reducing it from 1.27mV / mA ​​to 0.07mV / mA, thus expanding the load range of the one-to-two wireless power transmission system.

[0058] Furthermore, in addition to the circuit structure and method mentioned in the above embodiments, the present application can also make the following modifications: 1. Detuned capacitor C DT The value of is not limited to 1 / 2C RX It can also be set according to actual needs, as long as the magnitude of the reflection impedance meets the actual system requirements.

[0059] 2. The clock period and duty cycle can be designed independently to meet the power distribution requirements under different coupling coefficients.

[0060] 3. Based on detuning control and time-division multiplexing control, adaptive power allocation can be achieved in a one-to-many wireless power transfer system by extending inter-receiver communication from dual-receiver chips to multiple-receiver chips.

[0061] Reference Figure 12 This application provides a method for implementing a one-to-two wireless power transfer system with adaptive power allocation, which is used to implement the aforementioned one-to-two wireless power transfer system with adaptive power allocation, including the following steps S101 to S103: Step S101: Transmit wireless energy through a transmitting resonant circuit; Step S102: Receive wireless energy through two receiving resonant circuits. Each receiving resonant circuit includes a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. Step S103: Wireless energy is converted into DC power through two receiving chips with different coupling coefficients. Each receiving chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit. The power information of the other receiving chip is obtained through the current sampling circuit, amplitude detection circuit, and control circuit to realize communication between the receivers.

[0062] The contents of the above-described adaptive power allocation one-to-two wireless power transfer system embodiments are all applicable to the implementation method embodiments. The specific functions implemented in the implementation method embodiments are the same as those in the above-described adaptive power allocation one-to-two wireless power transfer system embodiments, and the beneficial effects achieved are also the same as those achieved in the above-described adaptive power allocation one-to-two wireless power transfer system embodiments.

[0063] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0064] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0065] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A self-adapting power allocation pair-to-two wireless power transfer system, characterized by, include: A transmitting resonant circuit is used to transmit wireless energy; Both receiving resonant circuits are connected to the transmitting resonant circuit for receiving the wireless energy. Each circuit includes a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. Two receiving chips with different coupling coefficients are respectively connected to the two receiving resonant circuits and the load to convert the wireless energy into DC power. Each chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit to obtain the power information of the other receiving chip and realize communication between the receivers.

2. The system according to claim 1, characterized in that, The transmitting resonant circuit includes a transmitting inductor and a transmitting capacitor. One end of the transmitting inductor is connected to one end of the transmitting circuit, and the other end of the transmitting inductor is connected to one end of the transmitting capacitor. The other end of the transmitting capacitor is connected to the other end of the transmitting circuit. The transmitting circuit is used to drive the transmitting resonant circuit.

3. The system according to claim 1, characterized in that, The receiving resonant circuit further includes a receiving inductor and a receiving capacitor. One end of the receiving inductor is connected to the receiving chip through the receiving capacitor, and the other end of the receiving inductor is connected to the receiving chip through the detuning capacitor. The gate of the switching transistor is connected to the receiving chip. One end of the receiving inductor and one end of the detuning capacitor are both connected to the drain of the switching transistor. The source of the switching transistor is connected between the detuning capacitor and the receiving chip.

4. The system according to claim 1, characterized in that, The receiving chip also includes: A single-stage rectifier bridge, connected to the receiving resonant circuit, the control circuit, and the load, is used to convert the wireless energy into DC power to supply power to the load. A driving circuit, connected to the receiving resonant circuit and the control circuit, is used to control the switching transistor to be turned on or off. A feedback circuit, connected to the control circuit, is used to detect the output voltage and achieve voltage regulation control.

5. The system according to claim 4, characterized in that, The control circuit includes: An output detection circuit is connected to the feedback circuit; A hysteresis voltage regulator circuit, connected to the feedback circuit and the output detection circuit, is used to generate a hysteresis voltage regulator control signal, which is used to control the single-stage rectifier bridge to achieve rectification or idling. A time-division multiplexing enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit, and is used to generate a square wave clock signal, which is used for time-division multiplexing control. An amplitude detection enable circuit is connected to the amplitude detection circuit, the output detection circuit, and the hysteresis voltage regulator circuit, and is used to drive the amplitude detection circuit. The AND gate has its first input connected to the hysteresis voltage regulator circuit, its second input connected to the time-division multiplexing enable circuit, and its output connected to the drive circuit. It is used to generate a switching transistor control signal, which is used to control the switching transistor to turn on or off.

6. The system according to claim 5, characterized in that, The time-division multiplexing enable circuit includes a first positive pulse generation circuit, a second positive pulse generation circuit, a third positive pulse generation circuit, an SR flip-flop, a first OR gate, a second OR gate, and a clock generation circuit. One end of the first positive pulse generation circuit is connected to the amplitude detection circuit, and the other end of the first positive pulse generation circuit is connected to the first pin of the SR flip-flop. One end of the second positive pulse generation circuit is connected to the hysteresis voltage regulator circuit, and the other end of the second positive pulse generation circuit is connected to the first input of the first OR gate. One end of the third positive pulse generation circuit is connected to the output detection circuit, and the other end of the third positive pulse generation circuit is connected to the second input of the first OR gate. The output of the first OR gate is connected to the second pin of the SR flip-flop. The third pin of the SR flip-flop is connected to one end of the clock generation circuit, and the other end of the clock generation circuit is connected to the first input of the second OR gate. The third pin of the SR flip-flop is also connected to the second input of the second OR gate, and the output of the second OR gate is connected to the second input of the AND gate.

7. The system according to claim 6, characterized in that, The clock generation circuit includes an oscillator, a fourth positive pulse generation circuit, a first D flip-flop, a second D flip-flop, and a NOR gate. One end of the oscillator is connected to the third pin of the SR flip-flop, and the other end of the oscillator is connected to one end of the fourth positive pulse generation circuit. The other end of the fourth positive pulse generation circuit is connected to one end of the first D flip-flop, and the other end of the first D flip-flop is connected to one end of the second D flip-flop. The first input terminal of the NOR gate is connected to the first D flip-flop, and the second input terminal of the NOR gate is connected to the second D flip-flop.

8. The system according to claim 1, characterized in that, The output terminal of the current sampling circuit is connected to the input terminal of the amplitude detection circuit, and the amplitude detection circuit is connected to the control circuit.

9. The system according to claim 1, characterized in that, The amplitude detection circuit includes a diode, a transistor, a Schmitt trigger, two capacitors, two resistors, two operational amplifiers, and two AND gates.

10. A method for implementing a one-to-two wireless power transfer system with adaptive power allocation, used to implement it through a one-to-two wireless power transfer system with adaptive power allocation as described in any one of claims 1 to 9, characterized in that, Includes the following steps: Transmit wireless energy through a transmitting resonant circuit; The wireless energy is received through two receiving resonant circuits, each of which includes a detuned capacitor and a switching transistor to introduce a detuned rectification mode and a detuned idling mode. The wireless energy is converted into DC power by two receiving chips with different coupling coefficients. Each receiving chip includes a current sampling circuit, an amplitude detection circuit, and a control circuit. The power information of the other receiving chip is obtained through the current sampling circuit, the amplitude detection circuit, and the control circuit, thereby realizing communication between the receivers.

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