A high power density digital ac constant current source

Abstract

The application relates to a high-power-density digital AC constant-current source, which comprises a single-phase 220V AC input end, a PFC circuit, an LLC circuit and an inverter circuit connected in sequence, voltage and current detection nodes are arranged at the PFC circuit and the inverter circuit, a phase control circuit obtains a voltage fluctuation amplitude and a load change rate through voltage and current waveforms output by the voltage and current detection nodes, determines an offset compensation coefficient, and if the offset compensation coefficient exceeds a preset threshold value, obtains a target phase offset value according to temperature data of the circuit; according to the target phase offset value and switch device state information, a control signal is determined, the control signal is used to adjust a conduction timing of the switch device, and the system maintains high-power-density output.

Description

Technical Field

[0001] This invention relates to the field of power supply system technology, and in particular to a digital AC constant current source that achieves high power density after being converted from a single-phase 220V AC input by a PFC (Power Factor Correction) and LLC circuit. Background Technology

[0002] Traditional constant current power supply systems typically use a single-phase 220V AC input, first converting the AC to 400V DC via a PFC stage, then inverting it to 200V AC, and finally using a step-up transformer to obtain the required high-current AC constant current. This approach has some drawbacks: The use of step-up transformers increases the size and weight of the entire power system, which is not conducive to the miniaturization and portability of equipment and is limited in some application scenarios with demanding space requirements.

[0003] The presence of magnetic components such as transformers makes it difficult to further increase the power density of the power supply system, reducing the overall performance and energy efficiency of the system, and resulting in poor performance in applications requiring high power density.

[0004] Therefore, developing a constant current power supply system that can eliminate the need for a step-up transformer, reduce size, and increase power density is of great practical significance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings in the above-mentioned background technology and provide a high power density digital AC constant current source. This system eliminates the key component of the current booster transformer while achieving the same constant current output function, effectively reducing the system size, increasing the power density, and improving the overall performance.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a high power density digital AC constant current source, comprising a single-phase 220V AC input terminal, a PFC circuit, an LLC circuit, and an inverter circuit connected in sequence, wherein: The PFC circuit is used to rectify and correct the power factor of single-phase 220V AC power and output a stable 400V DC voltage. The LLC circuit receives the 400V DC voltage output by the PFC circuit and converts it into low-voltage DC through resonance transformation. The inverter circuit inverts the low-voltage DC voltage output by the LLC circuit to generate a constant current power supply with a large AC current output. Voltage and current detection nodes are set at the PFC circuit and the inverter circuit. The voltage and current detection nodes are connected to the phase control circuit. The phase control circuit obtains the voltage fluctuation amplitude and load change rate through the voltage waveform and current waveform output by the voltage and current detection nodes. The offset compensation coefficient is determined according to the voltage fluctuation amplitude and the load change rate. If the offset compensation coefficient exceeds a preset threshold, the target phase offset value is obtained according to the temperature data of the circuit. The control signal is determined according to the target phase offset value and the state information of the switching devices in the PFC circuit and the LLC circuit. The control signal is used to adjust the conduction timing of the switching devices in the LLC circuit so that the system maintains high power density output.

[0007] Optionally, the PFC circuit rectifies and corrects the power factor of the input AC power, the LLC circuit efficiently steps down the 400V high-voltage DC power to a low-voltage DC power, the inverter circuit converts 30V DC power into a high-current AC constant current power output by controlling the on and off of the inverter switching device, and the phase control circuit includes one or more FPGAs.

[0008] Optionally, a voltage detection node is set at the input terminal of the PFC circuit and a current detection node is set at the output terminal of the inverter circuit. The voltage detection node detects the input voltage waveform, and the current detection node detects the output current waveform. The voltage fluctuation amplitude is obtained based on the input voltage waveform, and the load change rate is obtained based on the output current waveform.

[0009] Optionally, based on the voltage fluctuation amplitude and the load change rate, the phase offset value between the PFC circuit and the LLC circuit is determined by a lookup table method, and the offset compensation coefficient is obtained by normalizing the difference between the phase offset value and the current system phase offset value.

[0010] Optionally, the temperature data includes the temperature of the PFC circuit and the temperature of the LLC circuit. The total thermal concern of the system is calculated based on the temperature of the PFC circuit and the temperature of the LLC circuit. The performance concern is calculated based on the offset compensation coefficient. The adjustment priority order is determined based on the temperature of the PFC circuit, the temperature of the LLC circuit, the total thermal concern of the system, and the performance concern to obtain the target phase offset value.

[0011] Optionally, if the temperature of the PFC circuit is greater than the switching transistor warning temperature, or the temperature of the LLC circuit is greater than the switching transistor warning temperature, or the total thermal concern of the system is greater than the first thermal concern threshold, then the priority order is adjusted to thermal balance, efficiency, and dynamic response, and the target phase offset value is set to a preset cooling phase offset value. If the performance concern is greater than the first performance concern threshold and the total system thermal concern is less than the second thermal concern threshold, then the priority order is adjusted to dynamic response, efficiency, and thermal balance, and the target phase offset value is determined by looking up a table based on the load change rate. If the total thermal concern of the system is less than the third thermal concern threshold and the performance concern is less than the second performance concern threshold, then the priority order is adjusted to efficiency, dynamic response, and thermal balance. The target phase offset value is determined by looking up a table based on the current input voltage and output current.

[0012] Optionally, the switching device status information in the PFC circuit and the LLC circuit includes the maximum allowable switching speed of the switching device; If the difference between the target phase offset value and the current system phase offset value is less than a preset change threshold, then the conduction timing path is to directly switch from the current system phase offset value to the target phase offset value. If the difference between the target phase offset value and the current system phase offset value is not less than a preset change threshold, then the phase adjustment speed is determined based on the maximum allowable switching speed of the switching device. The total path time is calculated from the phase adjustment speed and the difference between the target phase offset value and the current system phase offset value. The conduction timing path is obtained from the phase adjustment speed, the current system phase offset value, and the total path time. Φ(t) = Φ C + ΔΦ * [ (1 - cos(π * t / T)) / 2 ] In the formula, Φ(t) is the conduction timing path, Φ C ΔΦ represents the current phase offset of the system, ΔΦ represents the phase adjustment speed, t represents time, and T represents the total path time.

[0013] Optionally, the turn-on timing path outputs the control signal of the LLC circuit through the PWM generator of the FPGA.

[0014] Compared with traditional solutions, the present invention has the following significant advantages: Eliminating the step-up transformer: Traditional solutions rely on step-up transformers to increase current, while this invention, through an optimized combination of PFC and LLC, directly reduces the 400V DC voltage to a low-voltage DC voltage in the LLC stage. Subsequent inversion can then produce a high-current AC constant current power supply, eliminating the need for the large and heavy step-up transformer. This significantly reduces the size of the entire power supply system, making it easier to integrate into various small devices and meeting the miniaturization and lightweight requirements of modern electronic equipment.

[0015] Increased power density: By eliminating the current-boosting transformer, the magnetic components that originally occupied a large space can be optimized, allowing more power conversion core components to be accommodated in the same volume. This significantly increases the power density of the power supply system, improving the energy transmission and conversion capacity per unit volume. It is more competitive in high-performance, high-power-density applications, such as industrial automation equipment and consumer electronics products where power supply size and weight are sensitive, and can better leverage its advantages. Intelligent circuit control: By setting up a phase control circuit, the optimal phase offset between the PFC stage and LLC stage is calculated and output in real time. The system continuously monitors input voltage fluctuations, output load change rate, and circuit temperature, and dynamically adjusts the phase offset command. This enables the system to make a proactive and coordinated response to grid fluctuations and load changes. By controlling the working phase of the PFC and LLC circuits in real time, the system effectively solves core problems such as two-stage loop coupling interference, high thermal management pressure, and limited soft switching range of the PFC and LLC circuits. While ensuring high reliability, the power density, conversion efficiency, and dynamic performance of the power supply are improved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, obtaining other drawings based on these drawings without creative effort still falls within the scope of the present invention.

[0017] Figure 1 A structural diagram of a high power density digital AC constant current source provided in an embodiment of the present invention; Figure 2 A PFC circuit diagram provided for an embodiment of the present invention; Figure 3 An LLC circuit provided in an embodiment of the present invention; Figure 4 This is an inverter circuit diagram provided for an embodiment of the present invention. Detailed Implementation

[0018] The high power density digital AC constant current source of the present invention will be further described in detail below with reference to the accompanying drawings: like Figure 1 As shown, the high power density digital AC constant current source includes a single-phase 220V AC input terminal, a PFC circuit, an LLC circuit, and an inverter circuit connected in sequence. After the single-phase 220V AC power is connected from the input terminal, it first enters the PFC circuit. Figure 2As shown, the PFC circuit adopts a mature power factor correction topology. It uses a power factor correction chip and related peripheral components to rectify and correct the input AC power, so that the output 400V DC voltage has high stability and good power factor, which meets the power supply requirements of subsequent circuits.

[0019] The 400V DC voltage, after PFC processing, is input to the LLC circuit. For example... Figure 3 As shown, the LLC circuit, based on the LLC resonant converter principle, efficiently steps down 400V high-voltage DC to low-voltage DC by rationally designing parameters such as the resonant inductor and resonant capacitor. This circuit features soft-switching characteristics, enabling zero-voltage switching (ZVS) or zero-current switching (ZCS) over a wide load range, effectively reducing switching losses and improving power conversion efficiency.

[0020] Subsequently, low-voltage direct current is fed into the inverter circuit. For example... Figure 4 As shown, the inverter circuit employs a specific inverter topology, converting DC power into a high-current AC constant-current power output by controlling the on and off states of the inverter switching devices. During the inverter process, precise control algorithms and circuit design ensure the stability of the output current, waveform quality, and dynamic response performance, meeting the constant-current power requirements of different loads.

[0021] Because this invention eliminates the step-up transformer, the system exposes problems that are not present or not prominent in traditional solutions: In traditional solutions, the transformer decouples the front and rear stages to some extent, and the loop design is relatively independent. However, in this invention, the PFC, LLC, and inverter are directly connected in series, and any disturbance at any stage will propagate throughout the entire system. To ensure system stability, traditional control sacrifices response speed, resulting in slow output current recovery and large overshoot when the load changes abruptly. In traditional solutions, the step-up transformer is the largest heat source and the biggest contributor to volume. However, after eliminating the transformer in this invention, the losses are more concentrated on the semiconductor switching transistors, and local hot spots become the primary bottleneck limiting output power and reliability. In traditional solutions, the transformer itself is a relatively stable component, while the accuracy of the entire system in this invention depends entirely on the accuracy and stability of the electronic components, and the gain and bias of these components will drift with temperature and time.

[0022] Therefore, in order to further solve the problems caused by the combination of PFC and LLC and the elimination of the current booster transformer, this invention sets up a phase control circuit and voltage and current detection nodes to achieve rapid response to disturbances, efficient circuit thermal management, and ensure power density of the power supply.

[0023] Voltage and current sensing nodes are set in the PFC circuit and inverter circuit. The voltage and current sensing nodes are connected to the phase control circuit, which includes one or more FPGAs. The phase control circuit obtains the voltage fluctuation amplitude and load change rate by using the voltage and current waveforms output by the voltage and current sensing nodes. The offset compensation coefficient is determined based on the voltage fluctuation amplitude and load change rate. If the offset compensation coefficient exceeds the preset threshold, the target phase offset value is obtained based on the circuit's temperature data. The control signal is determined based on the target phase offset value and the state information of the switching devices in the PFC circuit and LLC circuit. The control signal is used to adjust the conduction timing of the switching devices in the LLC circuit so that the system maintains high power density output.

[0024] like Figure 1 As shown, a voltage detection node is set at the input end of the PFC circuit, and a current detection node is set at the output end of the inverter circuit. The voltage detection node detects the input voltage waveform, and the current detection node detects the output current waveform. The voltage fluctuation amplitude is obtained from the input voltage waveform, and the load change rate is obtained from the output current waveform.

[0025] Among them, the fluctuation of the input voltage directly affects the working state of the PFC stage and the stability of the DC bus voltage input to the LLC stage, while the rate of change of the output current is the most direct and fastest reflection of the change in load demand.

[0026] This invention employs an ADC to sample the input voltage and output current at a fixed frequency. For the voltage fluctuation amplitude, a filter is used to preprocess the voltage waveform, a sliding window is created, and the standard deviation of the voltage values ​​within the sliding window is calculated. This standard deviation is then output as the voltage fluctuation amplitude, which is: In the formula, ΔV is the voltage fluctuation amplitude, N is the total number of data points in the window, V(i) is the i-th input voltage value in the window, and μ is the average value of all voltage values ​​in the window.

[0027] For the load change rate, calculate the instantaneous rate of change of current: In the formula, dI(n) is the instantaneous rate of change of current, I(n) is the current value at the current moment, I(nk) is the current value at the kth sampling point, and T is the sampling period.

[0028] Then, a smoothing process is performed to obtain the load change rate: In the formula, (dI) load / dt)(n) represents the current load change rate, (dI) load / dt)(n-1) is the load change rate at the previous moment, dI(n) is the instantaneous change rate of the current, and β is the filter coefficient (0<β<1).

[0029] Based on the voltage fluctuation amplitude and load change rate, the phase offset between the PFC circuit and the LLC circuit is determined by looking up a table.

[0030] This invention establishes a lookup table, which includes voltage fluctuation amplitude, load change rate, and corresponding phase offset value. The correspondence between voltage fluctuation amplitude, load change rate, and corresponding phase offset value in the lookup table was obtained during the research and development process through experiments, historical data, expert experience, simulation, and modeling. The optimal phase offset value is determined using the lookup table method under the current voltage fluctuation amplitude and load change rate.

[0031] The phase offset value is the phase difference or time difference between the drive signal of the PFC circuit and the drive signal of the LLC circuit. Adjusting the phase offset value directly controls the timing and intensity at which the LLC circuit draws energy from the PFC circuit. A smaller phase offset value allows energy to flow more efficiently, enabling zero-voltage switching of the LLC circuit's switching devices with low losses. This allows for faster energy delivery when the load requires a rapid increase in power. Conversely, a larger phase offset value reduces energy flow efficiency but can suppress excessive current, protecting the circuit from overheating or handling sudden load reduction.

[0032] The offset compensation coefficient is obtained by normalizing the difference between the phase offset value and the current system's phase offset value. In the formula, k p Φ is the offset compensation coefficient. offset Φ is the phase offset value. current k represents the phase offset value of the current system. max This represents the maximum value of the phase offset.

[0033] If the offset compensation coefficient exceeds the preset threshold, the target phase offset value is obtained based on the circuit's temperature data.

[0034] The purpose of setting this preset threshold in this invention is to avoid unnecessary frequent adjustments and prevent over-control and system oscillation. Because of factors such as sensor noise and sampling errors, the calculated phase offset value may fluctuate slightly around the true optimal value. Without a preset threshold, the system would continuously make tiny phase adjustments, leading to constant slight phase fluctuations. This not only fails to improve performance but also introduces additional ripple and noise, and may even cause instability and oscillation in the control loop.

[0035] Therefore, the system will only perform further processing if the offset compensation coefficient exceeds the preset threshold. If the offset compensation coefficient does not exceed the preset threshold, the system will maintain the status quo and will not adjust the phase offset value.

[0036] This invention obtains the target phase offset value based on the temperature data of the circuit.

[0037] The temperature data of the circuit includes the temperature T of the PFC circuit. PFC and the temperature T of the LLC circuit LLC According to the temperature T of the PFC circuit PFC and the temperature T of the LLC circuit LLC Calculate PFC popularity H PFC and LLC's popularity H LLC : H PFC =max(0,( T PFC -T w ) / ( T C -T w )) H LLC =max(0,( T LLC -T w ) / ( T C -T w )) Among them, H PFC For PFC, H LLC For LLC's high level of attention, T w T is the critical temperature of the switching transistor. C T is the warning temperature for the switching transistor. PFC T represents the temperature of the PFC circuit. LLC The temperature of the LLC circuit.

[0038] According to PFC popularity H PFC and LLC's popularity H LLC Determine the total system heat of concern H s : H S =max(H PFC H LLC ) In the formula, H PFC For PFC, H LLC For LLC's high level of attention, H s This represents the total system attention level.

[0039] Simultaneously, based on the offset compensation coefficient and the preset threshold, the performance concern P is calculated: P=min(1,K / (2*Φ T )) In the formula, P represents performance concern, K represents the offset compensation coefficient, and Φ represents the offset compensation coefficient. T This is a preset threshold.

[0040] In this invention, the value of thermal concern is between 0 and 1, with the value closer to 1 indicating a higher risk of circuit overheating; the value of performance concern is between 0 and 1, with the value closer to 1 indicating a higher demand for performance.

[0041] Then, based on the temperature of the PFC circuit, the temperature of the LLC circuit, the total system thermal concern, and the performance concern, the adjustment priority order is determined as follows: (1) If the temperature T of the PFC circuit PFC Greater than the switching transistor warning temperature T C Or the temperature T of the LLC circuit LLC Greater than the switching transistor warning temperature T C or the total system attention H s If the value exceeds the first heat attention threshold (e.g., 0.7), the priority order is adjusted to thermal balance, efficiency, and dynamic response, and the target phase offset value is set to the preset cooling phase offset value.

[0042] Among them, thermal balance represents the balance between the generation and dissipation of heat within the power supply system, with the goal of preventing components from being damaged or having their lifespan reduced due to overheating; efficiency represents the ratio of output power to input power, with the goal of ensuring the conversion efficiency of electrical energy from the input end to the output end and reducing losses; dynamic response represents the system's reaction speed and stability to external disturbances, with the goal of ensuring that the system can quickly support the current and suppress overshoot and drop when there are external disturbances, such as load changes.

[0043] At this time, the system is in an overheated state. The system prioritizes cooling down and sets the target phase offset value to a preset cooling phase offset value. This preset cooling phase offset value is a phase offset value designed to reduce the temperature of a specific device.

[0044] (2) If the performance concern P is greater than the first performance concern threshold (e.g., 0.8) and the total system thermal concern H s If the value is less than the second heat concern threshold (e.g., 0.4), the priority order is adjusted to dynamic response, efficiency, and thermal balance. The target phase offset value is determined by looking up a table based on the load change rate.

[0045] Among them, a lookup table is established using the load change rate and phase offset value. The correspondence between the load change rate and phase offset value in the lookup table is obtained through experiments, historical data, expert experience, simulation and modeling during the research and development process.

[0046] At this point, the system uses a phase point with the fastest dynamic response. This phase point can ensure that energy can be replenished as quickly as possible when the load changes suddenly, and suppress output current overshoot.

[0047] (3) If the total heat of concern of the system H s If the thermal attention threshold is less than the third thermal attention threshold (e.g., 0.3) and the performance attention threshold P is less than the second performance attention threshold (e.g., 0.5), then the priority order is adjusted to efficiency, dynamic response, and thermal balance. The target phase offset value is determined by looking up a table based on the current input voltage and output current.

[0048] A lookup table is established using input voltage, output current, and phase offset value. The phase offset value is the phase offset value that achieves the highest efficiency under different load currents and input voltages.

[0049] At this point, the system does not have the risk of overheating or sudden load changes. The system focuses on finding and locking onto the phase offset value with the highest efficiency to achieve optimal efficiency under normal conditions.

[0050] Based on the target phase offset value and the state information of the switching devices in the PFC circuit and LLC circuit, the control signal is determined, and the conduction timing of the switching devices in the LLC circuit is adjusted using the control signal to enable the system to maintain high power density output.

[0051] The status information of the switching devices in the PFC circuit and LLC circuit includes the maximum allowable switching speed of the switching devices.

[0052] If the difference between the target phase offset value and the current system phase offset value is less than a preset change threshold, the conduction timing path is to switch directly from the current system phase offset value to the target phase offset value.

[0053] The turn-on timing path is a sequence of phase offset values ​​that change according to a predetermined pattern over time during the transition from the current phase offset value to the target phase offset value. The turn-on timing path is a time-defined action plan that clearly specifies how to safely, smoothly, and efficiently transition from the current phase state to the target phase state. If no turn-on timing path is set, and the phase offset value is directly switched to the target phase offset value, the rapidly changing current flowing through the parasitic inductance of the PCB traces will generate a huge voltage spike. This spike voltage may exceed the rated withstand voltage of the switching transistor, causing it to be instantly damaged. Furthermore, the abrupt phase jump is a strong disturbance that will impact the voltage loop of the PFC and the current loop of the inverter. These control loops cannot respond to such drastic changes instantaneously, resulting in output oscillations and instability.

[0054] The conduction timing path includes the current phase offset value, the target phase offset value, the total path time, and the phase offset values ​​corresponding to different times within the total path time. For example, [(Φ0,t0), (Φ1,t1),..., (Φ n ,t n )).

[0055] This invention employs different adjustment strategies for different target phase offset values ​​to achieve a balance between accuracy, speed, and stability. When the difference between the target phase offset value and the current system's phase offset value is less than a preset change threshold, it indicates that the target phase offset value is very close to the current system's phase offset value, meaning that the system is already operating in a relatively optimal state and only requires a minor adjustment. Introducing a conduction timing path at this point would introduce unnecessary control delays, potentially causing the system to fail to respond promptly to rapidly changing loads. Moreover, a small-amplitude, direct phase offset value switch can more quickly and accurately lock onto the final target value, reducing steady-state errors during the transition process.

[0056] If the difference between the target phase offset value and the current system phase offset value is not less than the preset change threshold, the phase adjustment speed is determined according to the maximum allowable switching speed of the switching device.

[0057] The maximum permissible switching speed of a switching device is an inherent physical property determined by the switching transistor itself, the gate drive circuit, and the PCB layout. It represents the maximum rate of change in voltage and current that a single switching transistor can withstand during turn-on and turn-off. Phase adjustment speed, on the other hand, is the rate of change of the relative phase difference between the PFC and LLC circuits. When the phase changes, the amplitude and phase of the resonant current in the circuit change. These changing currents flow through the switching devices in the circuit. The faster the phase adjustment speed, the faster the required rate of current change in the switching devices. Therefore, setting the phase adjustment speed requires ensuring that the rate of change of voltage and current in the switching devices does not exceed the safe operating area.

[0058] The maximum permissible switching speed of a switching transistor refers to the fastest switching action rate it can achieve while ensuring safe and stable operation. It is measured by dv / dt (rate of change of voltage) and di / dt (rate of change of current), with units of V / μs and A / μs, respectively.

[0059] The maximum phase adjustment speed is determined based on the maximum permissible switching speed of the switching device, and the phase adjustment speed is set to be less than the maximum phase adjustment speed. The maximum phase adjustment speed is the product of the safety factor and the maximum permissible switching speed. In the formula, (dΦ / dt) max The maximum phase adjustment speed is given by α, where α is the safety factor (di / dt). max This represents the maximum permissible switching speed.

[0060] This invention sets the conduction timing path as an S-shaped function to plan the phase change over time, ensuring a smooth phase switching process.

[0061] The total path time is calculated from the phase adjustment velocity and the difference between the target phase offset value and the current system phase offset value. The conduction timing path is obtained from the phase adjustment velocity, the current system phase offset value, and the total path time. Φ(t) = Φ C + ΔΦ * [ (1 - cos(π * t / T)) / 2 ] In the formula, Φ(t) is the conduction timing path, Φ C ΔΦ represents the current phase offset of the system, ΔΦ represents the phase adjustment speed, t represents time, and T represents the total path time.

[0062] The turn-on timing path outputs control signals for the LLC circuit through the FPGA's PWM generator. PWM is the final command signal that directly controls the switching transistor's turn-on and turn-off. It is automatically generated in real time by a dedicated hardware module, the PWM generator, based on target parameters (including phase offset, duty cycle, etc.) calculated by a software algorithm.

[0063] The LLC circuit is a DC-DC converter stage, and its transmitted power is directly and sensitively related to its phase. By changing its phase, the power transmitted to the output is directly and immediately affected, thereby achieving a fast dynamic response. Therefore, this invention converts the conduction timing path into a control signal to control the LLC circuit, thereby ensuring that the phase offset between the LLC circuit and the PFC circuit is in the target state, achieving a fast system response to disturbances, efficient circuit thermal management, and ensuring the power density of the power supply.

[0064] This invention achieves efficient conversion from single-phase 220V AC power to high-current AC constant current power supply through the coordinated operation of the above-mentioned circuit components. At the same time, thanks to the innovative design of eliminating the current-boosting transformer and designing a phase control circuit, the size of the power supply system is greatly reduced and the power density is significantly increased. It has broad application prospects and practical value in many constant current power supply application scenarios.

Claims

1. A high power density digital AC constant current source, characterized in that, It includes a single-phase 220V AC input terminal, a PFC circuit, an LLC circuit, and an inverter circuit connected in sequence, wherein: The PFC circuit is used to rectify and correct the power factor of single-phase 220V AC power and output a stable 400V DC voltage. The LLC circuit receives the 400V DC voltage output by the PFC circuit and converts it into low-voltage DC through resonance transformation. The inverter circuit inverts the low-voltage DC voltage output by the LLC circuit to generate a constant current power supply with a large AC current output. Voltage and current detection nodes are set at the PFC circuit and the inverter circuit. The voltage and current detection nodes are connected to the phase control circuit. The phase control circuit obtains the voltage fluctuation amplitude and load change rate through the voltage waveform and current waveform output by the voltage and current detection nodes. The offset compensation coefficient is determined according to the voltage fluctuation amplitude and the load change rate. If the offset compensation coefficient exceeds a preset threshold, the target phase offset value is obtained according to the temperature data of the circuit. The control signal is determined according to the target phase offset value and the state information of the switching devices in the PFC circuit and the LLC circuit. The control signal is used to adjust the conduction timing of the switching devices in the LLC circuit so that the system maintains high power density output.

2. The high power density digital AC constant current source according to claim 1, characterized in that, The PFC circuit rectifies and corrects the power factor of the input AC power. The LLC circuit efficiently steps down the 400V high-voltage DC power to a low-voltage DC power. The inverter circuit converts 30V DC power into a high-current AC constant-current power output by controlling the on and off of the inverter switching device. The phase control circuit includes one or more FPGAs.

3. The high power density digital AC constant current source according to claim 1, characterized in that, A voltage detection node is set at the input terminal of the PFC circuit, and a current detection node is set at the output terminal of the inverter circuit. The voltage detection node detects the input voltage waveform, and the current detection node detects the output current waveform. The voltage fluctuation amplitude is obtained from the input voltage waveform, and the load change rate is obtained from the output current waveform.

4. The high power density digital AC constant current source according to claim 1, characterized in that, Based on the voltage fluctuation amplitude and the load change rate, the phase offset value between the PFC circuit and the LLC circuit is determined by a lookup table method. The offset compensation coefficient is obtained by normalizing the difference between the phase offset value and the current system phase offset value.

5. The high power density digital AC constant current source according to claim 1, characterized in that, The temperature data are the temperatures of the PFC circuit and the LLC circuit. The total thermal concern of the system is calculated based on the temperatures of the PFC circuit and the LLC circuit. The performance concern is calculated based on the offset compensation coefficient. The adjustment priority order is determined based on the temperatures of the PFC circuit, the LLC circuit, the total thermal concern of the system, and the performance concern to obtain the target phase offset value.

6. The high power density digital AC constant current source according to claim 5, characterized in that, If the temperature of the PFC circuit is greater than the switching transistor warning temperature, or the temperature of the LLC circuit is greater than the switching transistor warning temperature, or the total thermal concern of the system is greater than the first thermal concern threshold, then the priority order is adjusted to thermal balance, efficiency, dynamic response, and the target phase offset value is set to a preset cooling phase offset value. If the performance concern is greater than the first performance concern threshold and the total system thermal concern is less than the second thermal concern threshold, then the priority order is adjusted to dynamic response, efficiency, and thermal balance, and the target phase offset value is determined by looking up a table based on the load change rate. If the total thermal concern of the system is less than the third thermal concern threshold and the performance concern is less than the second performance concern threshold, then the priority order is adjusted to efficiency, dynamic response, and thermal balance. The target phase offset value is determined by looking up a table based on the current input voltage and output current.

7. The high power density digital AC constant current source according to claim 1, characterized in that, The status information of the switching devices in the PFC circuit and the LLC circuit includes the maximum allowable switching speed of the switching devices; If the difference between the target phase offset value and the current system phase offset value is less than a preset change threshold, then the conduction timing path is to directly switch from the current system phase offset value to the target phase offset value. If the difference between the target phase offset value and the current system phase offset value is not less than a preset change threshold, then the phase adjustment speed is determined based on the maximum allowable switching speed of the switching device. The total path time is calculated from the phase adjustment speed and the difference between the target phase offset value and the current system phase offset value. The conduction timing path is obtained from the phase adjustment speed, the current system phase offset value, and the total path time. Φ(t) = Φ C + ΔΦ * [ (1 - cos(π * t / T)) / 2 ] In the formula, Φ(t) is the conduction timing path, Φ C ΔΦ represents the current phase offset of the system, ΔΦ represents the phase adjustment speed, t represents time, and T represents the total path time.

8. The high power density digital AC constant current source according to claim 7, characterized in that, The turn-on timing path outputs the control signal of the LLC circuit through the PWM generator of the FPGA.

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