A power balance modulation method suitable for an n-cell cascaded H-bridge multilevel inverter
By employing a carrier reconfiguration method for cascaded H-bridge inverters, the problems of power imbalance and insufficient harmonic cancellation performance are solved, achieving power balance and fast response across the entire modulation ratio range, reducing control complexity, and making it suitable for photovoltaic grid-connected power generation, energy storage technology, and power electronic transformers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANHUI UNIV OF SCI & TECH
- Filing Date
- 2026-03-11
- Publication Date
- 2026-06-05
AI Technical Summary
Existing modulation strategies for cascaded H-bridge multilevel inverters suffer from power imbalance, insufficient harmonic cancellation performance, and control complexity. In particular, high-frequency modulation leads to increased thermal stress imbalance between modules, increased filtering difficulty, and limited dynamic response performance.
Reconstruction is performed using n carriers with the same frequency and amplitude. By periodically cyclically translating in the time domain, a PWM signal for controlling the H-bridge unit is generated to ensure that the power of each unit is balanced within one carrier cycle and that the harmonics are mainly concentrated near the nth harmonic of the carrier frequency.
It achieves power equalization across the entire modulation ratio range, reduces digital implementation complexity, responds quickly to dynamic load changes, maintains excellent harmonic cancellation performance, and facilitates filter design.
Smart Images
Figure CN122159709A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of PWM technology for multilevel converters, specifically relating to a power equalization modulation method suitable for cascaded H-bridge (CHB) multilevel inverters, which can be widely used in power electronic equipment such as photovoltaic grid-connected power generation, energy storage technology, and power electronic transformers. Background Technology
[0002] Multilevel inverters have been widely used in medium- and high-voltage high-power conversion fields due to their advantages such as low output voltage stress and low electromagnetic interference. Among them, cascaded H-bridge inverters, with their high degree of modularity and ease of expansion and maintenance, are gradually being applied to fields such as photovoltaic grid-connected power generation, energy storage technology, and power electronic transformers.
[0003] Modulation strategy is a core technology that determines the output waveform quality, switching losses, and system reliability of a cascaded H-bridge inverter. Existing modulation strategies can be mainly divided into two categories: high-frequency modulation and low-frequency modulation. While low-frequency modulation has lower switching losses, it results in higher harmonic content in the output voltage waveform. In high-frequency modulation, carrier phase-shift modulation can achieve natural power balance among power modules, but its line voltage harmonic distribution is more dispersed, increasing the difficulty of filtering. While carrier in-phase cascade modulation has the best line voltage harmonic suppression capability, it suffers from problems such as fixed switching states of power units and uneven output power among modules. Long-term operation will lead to thermal stress imbalance between modules, affecting the overall lifespan of the system.
[0004] To address the aforementioned power imbalance problem, existing technologies typically employ a periodic pulse switching strategy, whereby each unit alternates between different switching states to achieve average power balance within a certain timeframe. However, this method suffers from a long power balancing time, and the required balancing period increases further with the number of cascaded units, limiting dynamic response performance. While some improved strategies can enhance power balancing, they introduce problems such as increased difficulty in digital control, higher total harmonic distortion (THD), or inconsistent switching frequencies of the switching transistors, impacting system reliability and lifespan.
[0005] Therefore, there is an urgent need for a modulation method that can balance power equalization, harmonic elimination performance, and control implementation difficulty. Summary of the Invention
[0006] 1. Technical problem to be solved: To address the contradiction between power equalization and harmonic suppression performance in existing modulation strategies for cascaded H-bridge multilevel inverters, as well as the problems of long equalization time and complex control implementation, this invention proposes a novel power equalization modulation method. This method aims to achieve power equalization across the entire modulation ratio range, while maintaining the excellent harmonic suppression performance of IPD-PWM and reducing the difficulty of digital implementation.
[0007] 2. Technical Solution: To solve the above problems, the present invention adopts the following technical solution.
[0008] A power equalization modulation method for n-unit cascaded H-bridge multilevel inverters, applied to an inverter composed of n cascaded H-bridge units with equal DC-side voltages, includes the following steps: There are n carriers, the number of which is equal to the number of H-bridge units, and each carrier has the same frequency and amplitude. During the positive half-cycle of the modulation wave, the modulation wave is compared with each of the n carrier waves, and a first PWM signal for controlling the left arm of each H-bridge unit is generated based on the comparison results. During the negative half-cycle of the modulation wave, the modulation wave is compared with each of the n carrier waves, and a second PWM signal is generated based on the comparison results to control the right arm of each H-bridge unit. The carrier cycles periodically in the time domain according to a preset rule, and the correspondence between each H-bridge unit and each carrier changes periodically during each cycle of the carrier, so as to balance the output power of each H-bridge unit.
[0009] Furthermore, the carrier is a reconstructed carrier obtained by reconstructing a triangular carrier based on in-phase stacked modulation IPD-PWM. The reconstruction method is as follows: taking half a period of the triangular carrier as a reconstruction unit, the triangular carrier is translated in the vertical direction in each half carrier period. After several translations, a reconstruction cycle is completed. The translated reconstruction units are connected in sequence to form the reconstructed carrier.
[0010] In a preferred embodiment, when n=3, the rule for constructing the reconstructed carrier is as follows: The first-layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, 2, 1, 1, 2, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 2, 0, 1, 1, 0, 2.
[0011] The second-layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, -1, 1, 1, -1, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 0, 1, -1, -1, 1, 0.
[0012] The third carrier wave has the following translation sequence during the positive half-cycle of the modulation wave: 0, -1, -2, -2, -1, 0; and during the negative half-cycle of the modulation wave: -2, -1, 0, 0, -1, -2.
[0013] The unit of translation is the DC-side voltage value E of the H-bridge unit.
[0014] Furthermore, the distribution of the n carriers satisfies the following: at the same time, different regions of any carrier do not overlap, and the same regions of different carriers do not overlap, so as to ensure that the conduction time of each unit is balanced within a reconstruction cycle.
[0015] During the positive half-cycle of the modulation wave, when the instantaneous value of the modulation wave is greater than the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a positive level; when the instantaneous value of the modulation wave is less than or equal to the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a zero level. During the negative half-cycle of the modulation wave, when the instantaneous value of the modulation wave is less than the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a negative level; when the instantaneous value of the modulation wave is greater than or equal to the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a zero level.
[0016] Within one cycle of the carrier, the average output power of each H-bridge unit is equal, thereby achieving power equalization.
[0017] The output voltage harmonics of the inverter are mainly distributed near the nth harmonic of the carrier frequency, which facilitates filtering.
[0018] The n is an integer greater than or equal to 2.
[0019] Within one cycle of the carrier, the average output power of each H-bridge unit is balanced.
[0020] 3. Beneficial effects: Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) The present invention can achieve power balance of each level unit in the full modulation ratio range, and the output power ratio of each unit is close to 1:1:1, which effectively solves the power imbalance problem of IPD modulation strategy.
[0021] (2) The present invention maintains the excellent harmonic elimination characteristics of the IPD modulation strategy. The output voltage THD value is comparable to that of the IPD modulation strategy. The harmonics are mainly concentrated near the nth harmonic of the carrier frequency, which is easy to filter and can reduce the size of the filter.
[0022] (3) Without changing the switching frequency, output waveform and power equalization performance, the present invention only requires n carriers, which reduces the number of carriers and reduces the complexity of digital implementation.
[0023] (4) This invention can be directly extended to cascaded H-bridge multilevel inverters with any n units, and is suitable for different power levels and application scenarios, making it highly practical.
[0024] (5) The present invention can achieve power balancing within one reconfiguration carrier cycle, has a fast response speed, and can adapt to dynamic operating conditions such as load changes.
[0025] It should be noted that the structures not described in this invention are not related to the design points and improvement directions of this invention, and are the same as or can be implemented using existing technologies, so they will not be elaborated here. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a three-unit cascaded H-bridge topology.
[0027] Figure 2 This is a graph of the switching function.
[0028] Figure 3 The image shows a comparison of carrier reconstruction, where (a) is before carrier reconstruction and (b) is after carrier reconstruction.
[0029] Figure 4 This is a schematic diagram of the periodic principle.
[0030] Figure 5 This is a schematic diagram of the output voltage during the positive half-cycle of the modulation strategy.
[0031] Figure 6 This is a schematic diagram of a four-unit modulation strategy.
[0032] Figure 7 The output voltage harmonic spectrum analysis diagrams are shown, where (a) is the IPD output voltage harmonic spectrum analysis and (b) is the modulation strategy spectrum analysis of the present invention.
[0033] Figure 8 The diagram shows the output power of the three units, where (a) represents the IPD power and (b) represents the modulation strategy power of this invention.
[0034] Figure 9 The power diagram of the modulation strategy of this invention is shown for four units.
[0035] Figure 10 The results are from a dynamic performance simulation, where (a) represents the inverter's output voltage (u) when the load changes from a resistive-inductive load to a resistive load (M=0.9). o i o Waveform, (b) is u when M changes from 0.3 to 0.9. o i o The waveform.
[0036] Figure 11 The output voltage waveform and Fourier analysis diagram of the modulation strategy of this invention are shown.
[0037] Figure 12 This is a diagram showing the output power distribution of the three units of the modulation strategy of this invention.
[0038] Figure 13 This is a diagram showing the output power distribution of the four units of the modulation strategy of this invention. Detailed Implementation
[0039] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. The specific embodiments described are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0040] Example 1: Three-unit cascaded H-bridge inverter This embodiment uses a three-unit cascaded H-bridge inverter as an example to explain in detail the implementation process of the present invention.
[0041] 1. Circuit Topology Figure 1 A topology diagram of a three-unit CHB inverter is given. The main circuit consists of three cascaded H-bridge units (H1, H2, H3). The midpoint of the right half of bridge H1 is connected to the midpoint of the left half of bridge H2, and the midpoint of the right half of bridge H2 is connected to the midpoint of the left half of bridge H3. The AC voltage is output between the midpoint of the left arm of bridge H1 and the midpoint of the right arm of bridge H3. The DC-side voltages of each unit are independent and equal, i.e., u... o1 =u o2 =u o3 =E. Each H-bridge unit consists of four switching transistors (IGBT and freewheeling diode connected in parallel), and can output three voltage levels: -E, 0, and E.
[0042] Inverter total output voltage u o The sum of the output voltages of each unit is expressed as: u o = u o1 + u o2 + u o3 (1) Output current i o It can be represented as: i o = I m sin(ωt - φ) (2) Where I m ω is the output current amplitude, ω is the output voltage angular frequency, and φ is the output impedance angle.
[0043] 2. Carrier Reconfiguration Method This invention reconstructs the carrier wave based on IPD-PWM technology. Let the period of the original triangular carrier wave be T. c With the half-cycle T of the triangular carrier c / 2 is the basic reconstruction unit.
[0044] Figure 3 The comparison presents the distribution characteristics of the switching function before and after carrier reconstruction. Figure 3 (a) is the switching function of traditional IPD-PWM, which includes 7 states: 111, 011, 001, 000, 00-1, 0-1-1, -1-1-1, which correspond to 7 levels of the output voltage: 3E, 2E, E, 0, -E, -2E, -3E.
[0045] Figure 3 (b) is the switching function after carrier reconstruction. When the output voltage is at one of the four intermediate levels (2E, E, -E, -2E), eight sets of redundant switching states are introduced: 101, 110, 100, 010, -100, 0-10, -10-1, and -1-10. The introduction of these redundant states only changes the switching timing within the cascaded unit and does not affect the output voltage u. o The waveform.
[0046] For a three-unit system, the rules for constructing the reconfigured carrier are as follows: The first-layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, 2, 1, 1, 2, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 2, 0, 1, 1, 0, 2.
[0047] The second-layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, -1, 1, 1, -1, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 0, 1, -1, -1, 1, 0.
[0048] The third carrier wave has the following translation sequence during the positive half-cycle of the modulation wave: 0, -1, -2, -2, -1, 0; and during the negative half-cycle of the modulation wave: -2, -1, 0, 0, -1, -2.
[0049] The unit for translation is E.
[0050] The modulated wave is a unipolar segmented modulated wave, with its positive half being a sine wave and its negative half being obtained by shifting the negative half-cycle of the sine wave upwards by 3E. Its expression is v. ref for: (3) Figure 4 This is a schematic diagram of the periodic principle. As shown in the diagram, the reconstructed carrier period T... c ′ and the original triangular carrier period T c The relationship is: T c = 3T c (4) Accordingly, the relationship between the angular frequencies before and after carrier reconstruction is as follows: ω c ′ = ω c / 3 (5) 3. PWM signal generation The sinusoidal modulation wave vref The signal is compared with the reconstructed carrier wave to generate a PWM control signal. During the positive half-cycle of the modulated wave, when v ref When the voltage is greater than the corresponding carrier wave, the corresponding H-bridge unit is controlled to output a positive level (+E); when v ref When the value is less than or equal to the corresponding carrier wave, the output level is zero (0).
[0051] During the negative half-cycle of the modulated wave, when v ref When the voltage is less than the corresponding carrier wave, the corresponding H-bridge unit is controlled to output a negative level (-E); when v ref When the value is greater than or equal to the corresponding carrier wave, the output level is zero (0).
[0052] In each H-bridge unit, the upper and lower switches of the same bridge arm are complementary and conduction is performed, and a dead time is set to avoid shoot-through.
[0053] Figure 5 A schematic diagram of the output voltage during the positive half-cycle of the modulation strategy is given, with the inverter output voltage in the range of [E, 2E] as an example for illustration.
[0054] 4. Analysis of Power Balancing Principle To illustrate the power equalization principle of this invention, the output characteristics of the cascaded units within the reconstructed carrier period are analyzed. Assume the reconstructed carrier frequency f... c The frequency f of the sinusoidal modulation wave is much greater than that of the sinusoidal modulation wave. s Then, within one reconstructed carrier cycle, the modulated wave v can be... ref With inverter output current i o It is considered a constant value.
[0055] Let t Hi+ To reconstruct u within the carrier period Hi =The duration of E, then t Hi + can be represented as: (6) The average value u of the output voltage of each H-bridge unit during the reconstructed carrier cycle. H1+ u H2+ u H3+ They are respectively: (7) Since the H-bridge units of each stage are connected in series, the output current is equal and constant. Combined with the carrier reconstruction strategy to balance the conduction time of each unit, the average output power of each unit is: (8) Due to the symmetry of carrier reconstruction, the power factor cosφ only affects the power magnitude and does not change the distribution relationship. Therefore, during the reconstructed carrier period, the average output power of each cascaded unit is equal, i.e.: (9) The principle of the negative half-cycle and positive half-cycle of the inverter output is the same, and will not be elaborated further. Therefore, based on IPD-PWM technology, by changing the arrangement of the carrier in the vertical direction to perform carrier reconstruction, the average output voltage of each cascade unit can be made equal during the reconstruction carrier cycle, thereby ensuring that the average output power of each cascade unit is equal and the time required for power balancing is only one reconstruction carrier cycle.
[0056] 5. Harmonic Performance Analysis Using a dual Fourier series analysis method combined with multi-carrier PWM technology, u o-IPD Harmonic expression: (10) Among them B p (m,n) and C p (m,n) are the harmonic amplitude coefficients, J n Let M be an nth-order Bessel function, and M be the modulation ratio.
[0057] Substituting equation (5) into equation (10), we can see that, under the same physical switching frequency, the equivalent switching frequency of this modulation strategy is increased to n times the original frequency, and the harmonics are mainly concentrated near the nth harmonic of the carrier frequency.
[0058] Example 2: Four-unit cascaded H-bridge inverter To verify the topology scalability of the present invention, it was extended to a four-unit CHB inverter. Figure 6 A schematic diagram of the four-unit modulation strategy is presented. The carrier distribution satisfies the following: at any given time, different regions of any carrier do not overlap, and the same regions of different carriers do not overlap; that is, a single carrier does not repeat in different regions, and different carriers do not repeat in the same region. This distribution ensures that each unit achieves power balance within one carrier cycle.
[0059] Simulation verification: A simulation platform was built using Matlab / Simulink to verify the method of this invention. The simulation parameters were set as follows: DC side voltage E = 100V, load resistance R = 25Ω, filter inductance L = 5.6mH, and fundamental frequency f. s =50Hz, triangular carrier frequency f c =1000Hz.
[0060] Figure 7 The output voltage harmonic spectrum analysis diagram is shown, where (a) is the traditional IPD modulation strategy and (b) is the modulation strategy of the present invention. The comparison shows that the strategy of the present invention concentrates the harmonics in the high-frequency band of the third harmonic of the carrier frequency (3000Hz), almost suppressing low-order harmonics at 1000Hz and below, and the fundamental amplitude is basically consistent with that of IPD.
[0061] Figure 8 The diagram shows the output power of the three units, where (a) represents the IPD modulation strategy and (b) represents the modulation strategy of this invention. Under IPD modulation, the output power of each unit is significantly unbalanced, while under the strategy of this invention, the output power of the three units is completely consistent.
[0062] Figure 9 The power diagram of the modulation strategy of the present invention for four units shows that, with modulation ratios M=0.3, 0.6, and 0.9, the average output power ratio of each unit approaches 1:1:1:1, verifying the topological scalability of the strategy.
[0063] Figure 10 The results are from dynamic performance simulations, where (a) represents the value of u when the load abruptly changes from an RL load to a purely resistive load (M=0.9). o i o Waveform (b) shows the waveform when the modulation ratio M abruptly changes from 0.3 to 0.9. o i o Waveform. It can be seen that the output voltage and current can respond quickly to changes, exhibiting good dynamic performance.
[0064] Experimental verification: A CHB seven-level inverter experimental platform was built for verification. The controller used an FPGA (model: ALINX Black Gold AX7010), and the DC voltage of each unit was set to 24V (E). The load parameters were consistent with the simulation.
[0065] Figure 11 The output voltage waveform of the inverter under the modulation strategy of this invention and its Fourier analysis show that the output voltage successfully achieves seven levels, and the harmonics are mainly concentrated near the third harmonic of the carrier frequency, which is consistent with the simulation results.
[0066] Figure 12 The output power distribution of the modulation strategy of this invention on the three-unit experimental prototype (M=0.6 and M=0.9) shows that the average voltage of each unit is basically the same, thus achieving power balance.
[0067] Figure 13 The output power distribution of the four-unit experimental prototype (M=0.6 and M=0.9) also achieved power balance among the units at each level, verifying the correctness of the power balance promotion scheme.
[0068] The general case of extending to n units: For an n-unit CHB-type inverter, the method of this invention can be naturally extended. In this case, n carrier waves, each with positive polarity, are required. crn+ The carrier distribution must meet the following requirements; Within any reconstructed carrier cycle, the vertical offsets of each carrier layer are unequal within the same half-cycle, and the vertical offset of the same carrier layer does not repeat in different half-cycles. Specifically, the carrier distribution satisfies: (11) Each unit achieves power equalization within one reconfiguration carrier cycle.
[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A power equalization modulation method applicable to an n-unit cascaded H-bridge multilevel inverter, applied to an inverter composed of n cascaded H-bridge units with equal DC-side voltages, characterized in that, Includes the following steps: There are n carriers, the number of which is equal to the number of H-bridge units, and each carrier has the same frequency and amplitude. During the positive half-cycle of the modulation wave, the modulation wave is compared with each of the n carrier waves, and a first PWM signal for controlling the left arm of each H-bridge unit is generated based on the comparison results. During the negative half-cycle of the modulation wave, the modulation wave is compared with each of the n carrier waves, and a second PWM signal is generated based on the comparison results to control the right arm of each H-bridge unit. The carrier cycles periodically in the time domain according to a preset rule, and the correspondence between each H-bridge unit and each carrier changes periodically during each cycle of the carrier, so as to balance the output power of each H-bridge unit.
2. The power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, The carrier is a reconstructed carrier obtained by reconstructing a triangular carrier based on in-phase stacked modulation IPD-PWM. The reconstruction method is as follows: taking half a period of the triangular carrier as the reconstruction unit, each layer of triangular carrier is translated in the vertical direction within each half carrier period. After a predetermined number of translations, a reconstruction cycle is completed. The translated reconstruction units are connected in sequence to form the reconstructed carrier, so that the conduction time of each H-bridge unit is evenly distributed within a reconstruction cycle.
3. The power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 2, characterized in that, When n=3, the rule for constructing the reconstructed carrier is: The first layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, 2, 1, 1, 2, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 2, 0, 1, 1, 0, 2. The second-layer carrier shift sequence during the positive half-cycle of the modulation wave is: 0, -1, 1, 1, -1, 0; and the shift sequence during the negative half-cycle of the modulation wave is: 0, 1, -1, -1, 1, 0. The third carrier wave has the following translation sequence during the positive half-cycle of the modulation wave: 0, -1, -2, -2, -1, 0; and during the negative half-cycle of the modulation wave: -2, -1, 0, 0, -1, -2.
4. The power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, The vertical distribution of the n carriers satisfies the following: at the same time, the different level intervals of any one carrier do not overlap, and the same level intervals of different carriers do not overlap.
5. A power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, The modulation wave is a unipolar segmented modulation wave, with the positive half-segment being a sine wave and the negative half-segment being obtained by shifting the negative half-cycle of the sine wave upwards by 3E.
6. The power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, During the positive half-cycle of the modulation wave, when the instantaneous value of the modulation wave is greater than the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a positive level; when the instantaneous value of the modulation wave is less than or equal to the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a zero level. During the negative half-cycle of the modulation wave, when the instantaneous value of the modulation wave is less than the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a negative level; when the instantaneous value of the modulation wave is greater than or equal to the instantaneous value of the carrier wave, the corresponding H-bridge unit is controlled to output a zero level.
7. A power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, Within one cycle of the carrier, the output power of each H-bridge unit is balanced.
8. A power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 7, characterized in that, Within one cycle of the carrier, the average output power of each H-bridge unit is equal.
9. A power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to claim 1, characterized in that, The output voltage harmonics of the inverter are mainly distributed around the nth harmonic of the carrier frequency.
10. A power equalization modulation method for an n-unit cascaded H-bridge multilevel inverter according to any one of claims 1 to 9, characterized in that, n is an integer greater than or equal to 2.