Multi-core series resonant oscillator and array thereof

Abstract

The application provides a multi-core series resonant oscillator and an array thereof. The multi-core series resonant oscillator comprises a plurality of core units, each of which comprises an oscillation core, a drain end inductance and a drain end capacitance, the plurality of oscillation cores are arranged in a ring shape, the drain end capacitance is integrated in the oscillation core, each oscillation core has a first drain end, a second drain end and a first capacitance end and a second capacitance end connected with the drain end capacitance, and the drain end inductance comprises a first drain end inductance and a second drain end inductance. Wherein the first drain end of each oscillation core is connected with the second capacitance end of an adjacent oscillation core through the first drain end inductance; the second drain end of each oscillation core is connected with the first capacitance end of another adjacent oscillation core through the second drain end inductance; and the first drain end inductance of each core unit is cross-coupled with the second drain end inductance of an adjacent core unit; and the second drain end inductance of each core unit is cross-coupled with the first drain end inductance of another adjacent core unit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a multi-core series resonant oscillator and its array. Background Technology

[0002] Ultra-low phase noise microwave signal sources play a crucial role in quantum computing, precision measurement, and high-end communication systems. Existing solutions, such as dielectric resonator oscillators and frequency divider synthesizers, offer excellent performance but are bulky, costly, and power-consuming, making them unsuitable for large-scale integrated systems.

[0003] CMOS (Complementary Metal-Oxide-Semiconductor) voltage-controlled oscillators (VCOs) are an ideal alternative due to their low cost and high integration, but their performance is limited by the low quality factor of passive devices. While existing multi-core coupled oscillators theoretically reduce phase noise through coupling, their actual performance falls far short of theoretical expectations due to issues such as inter-core mismatch, waveform distortion caused by parasitic capacitance, and common-mode noise interference. Furthermore, as process dimensions shrink, transistor driving capability decreases, while increasing device size significantly increases the gate-drain capacitance C. gd Parasites cause the output waveform slope to slow down and distortion to increase, thereby deteriorating the phase noise performance. Summary of the Invention

[0004] The purpose of this application is to provide a multi-core series resonant oscillator and its array, which can effectively solve at least one of the technical problems mentioned in the prior art.

[0005] One aspect of this application provides a multi-core series resonant oscillator. The multi-core series resonant oscillator includes multiple core units, each core unit including an oscillation core, a drain inductor, and a drain capacitor. The multiple oscillation cores are arranged in a ring. The drain capacitor is integrated within the oscillation core. Each oscillation core has a first drain terminal, a second drain terminal, and a first capacitor terminal and a second capacitor terminal connected to the drain capacitor. The drain inductor includes a first drain inductor and a second drain inductor. Specifically, the first drain terminal of each oscillation core is connected to the second capacitor terminal of an adjacent oscillation core via the first drain inductor; the second drain terminal of each oscillation core is connected to the first capacitor terminal of another adjacent oscillation core via the second drain inductor; and the first drain inductor of each core unit is cross-coupled with the second drain inductor of an adjacent core unit; the second drain inductor of each core unit is also cross-coupled with the first drain inductor of another adjacent core unit.

[0006] Furthermore, the number of the plurality of said oscillation cores is an even number.

[0007] Furthermore, each core unit includes a gate inductor and a gate capacitor, and each oscillation core has a first gate and a second gate. The gate inductor and the gate capacitor are connected in parallel between the first gate and the second gate. The multi-core series resonant oscillator also includes a split coupling network, and the first gate and the second gate of each oscillation core are both connected in parallel to the split coupling network.

[0008] Furthermore, the multiple oscillation cores are evenly arranged in a ring direction with the sub-coupling network as the center.

[0009] Furthermore, the gate inductance of each core unit is arranged in a ring around the sub-coupling network, and the gate inductance of each core unit is cross-coupled with the gate inductance of other core units.

[0010] Furthermore, the gate inductor is located in the annular region between the drain inductor and the decoupled network.

[0011] Furthermore, the number of the plurality of oscillation cores is four, and the four gate inductors corresponding to the four oscillation cores all have the same layout structure.

[0012] Furthermore, each gate inductor includes a first gate inductor, a second gate inductor, a third gate inductor, and a fourth gate inductor connected in sequence to each other, wherein the first gate inductor is connected to the first gate, and the fourth gate inductor is connected to the second gate.

[0013] Furthermore, the first gate inductor and the second gate inductor are connected by a first connection portion; the second gate inductor and the third gate inductor are connected by a second connection portion; and the third gate inductor and the fourth gate inductor are connected by a third connection portion. Each gate inductor's first, second, third, and fourth gate inductors are located on the same metal layer, and the first, second, and third connection portions are located on metal layers different from those of the first, second, third, and fourth gate inductors.

[0014] Furthermore, the four oscillation cores sequentially include a first oscillation core, a second oscillation core, a third oscillation core, and a fourth oscillation core. The first oscillation core and the third oscillation core are arranged opposite to each other, and the first oscillation core, the second oscillation core, and the fourth oscillation core are arranged adjacent to each other. Specifically, the first connection portion of the gate inductor connected to the first oscillation core is cross-coupled with the third gate inductor connected to the third oscillation core; the second and third connection portions of the gate inductor connected to the first oscillation core are cross-coupled with the third gate inductor connected to the fourth oscillation core and the first gate inductor connected to the fourth oscillation core, respectively; the first gate inductor connected to the first oscillation core is cross-coupled with the third connection portion of the gate inductor connected to the second oscillation core; and the third gate inductor connected to the first oscillation core is cross-coupled with the second connection portion of the gate inductor connected to the second oscillation core and the first connection portion of the third oscillation core.

[0015] Another aspect of this application provides a multi-core series resonant oscillator array. The multi-core series resonant oscillator array includes a total coupling network and a plurality of multi-core series resonant oscillators as described above, wherein the sub-coupling networks of the plurality of multi-core series resonant oscillators are all connected in parallel to the total coupling network.

[0016] Furthermore, the plurality of said multi-core series resonant oscillators are uniformly arranged in a ring direction with the total coupling network as the center.

[0017] The multi-core series resonant oscillator and its array in one or more embodiments of this application adopt a cooperative enhancement ring-coupled topology. Each core unit is equivalently coupled through a resistive and magnetic mutual inductance network to form a unified normalized resistance channel, so that the coupling strength between any two core units remains consistent. In differential mode operation, the currents of each core are superimposed in the same direction to form a spatially uniform magnetic field, thereby enhancing the amplitude of the differential mode signal and suppressing mode aliasing and frequency pulling effects. This structure not only improves the equivalent resonance quality factor, but also improves the consistency of multi-core phase synchronization, so that the oscillator maintains a low mismatch when expanded to more cores.

[0018] The multi-core series resonant oscillator and its array of one or more embodiments of this application introduce two key technologies—magnetically enhanced feedforward waveform shaping and implicit common-mode noise suppression—into the CMOS oscillator structure. These technologies achieve the synergistic effect of waveform distortion compensation, power supply noise suppression, and multi-core coupling optimization, solving problems such as waveform distortion, common-mode interference, and multi-core mismatch in traditional silicon-based oscillators. This results in low-noise, high-robustness, and scalable oscillation performance. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a multi-core series resonant oscillator according to an embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the layout structure of a gate inductor according to an embodiment of this application.

[0021] Figure 3 for Figure 2 The diagram shown illustrates the working principle of the gate inductor.

[0022] Figure 4 This application presents an embodiment of a magnetically enhanced feedforward waveform shaping circuit structure and its equivalent model.

[0023] Figure 5 This is a schematic diagram of the implicit common-mode noise suppression mechanism of one embodiment of this application.

[0024] Figure 6 This is a schematic diagram of a multi-core series resonant oscillator array according to an embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0026] The multi-core series resonant oscillator and its array of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Figure 1 A schematic diagram of a multi-core series resonant oscillator 100 according to one embodiment of this application is shown. Figure 1 As shown, a multi-core series resonant oscillator 100 according to one embodiment of this application includes multiple core units. Each core unit includes an oscillation core 110, a drain inductor 120, and a drain capacitor (not shown). The multiple oscillation cores 110 are arranged in a ring, and each oscillation core 110 includes a pair of cross-coupled MOS transistors. The drain capacitor is integrated within the oscillation core 110. Each oscillation core 110 has a first drain terminal D1, a second drain terminal D2, and a first capacitor terminal C1 and a second capacitor terminal C2 connected to the drain capacitor. The drain inductor 120 includes a first drain inductor 121 and a second drain inductor 122.

[0028] The first drain terminal D1 of each oscillating core 110 is connected to the second capacitor terminal C2 of an adjacent oscillating core 110 through a first drain inductor 121; the second drain terminal D2 of each oscillating core 110 is connected to the first capacitor terminal C1 of another adjacent oscillating core 110 through a second drain inductor 122; and the first drain inductor 121 of each core unit is cross-coupled with the second drain inductor 122 of an adjacent core unit.

[0029] The number of multiple oscillation cores 110 is even. In the illustrated embodiment, the multi-core series resonant oscillator 100 includes four core units. Accordingly, the four core units have four oscillation cores 110, for example, the four oscillation cores 110 sequentially include a first oscillation core 111, a second oscillation core 112, a third oscillation core 113, and a fourth oscillation core 114. The first oscillation core 111 and the third oscillation core 113 are arranged opposite each other, and the second oscillation core 112 and the fourth oscillation core 114 are arranged opposite each other. The first oscillation core 111, the second oscillation core 112, and the fourth oscillation core 114 are arranged adjacent to each other.

[0030] For example, for the first oscillation core 111, its first drain terminal D1 is connected to the second capacitor terminal C2 of the adjacent fourth oscillation core 114 via a first drain inductor 121; its second drain terminal D2 is connected to the first capacitor terminal C1 of the adjacent second oscillation core 112 via a second drain inductor 122. Furthermore, the first drain inductor 121 of the first oscillation core 111 is cross-coupled with the second drain inductor 122 of the adjacent fourth oscillation core 114. The second drain inductor 122 of the first oscillation core 111 is also cross-coupled with the first drain inductor 121 of the adjacent second oscillation core 112. The first oscillation core 111 is connected in series with the corresponding third oscillation core 113; and the second oscillation core 112 is connected in series with the corresponding fourth oscillation core 114.

[0031] For the second oscillating core 112, its first drain terminal D1 is connected to the second capacitor terminal C2 of the adjacent first oscillating core 111 via a first drain inductor 121; its second drain terminal D2 is connected to the first capacitor terminal C1 of the adjacent third oscillating core 113 via a second drain inductor 122. Furthermore, the first drain inductor 121 of the second oscillating core 112 is cross-coupled with the second drain inductor 122 of the adjacent first oscillating core 111; and the second drain inductor 122 of the second oscillating core 112 is cross-coupled with the first drain inductor 121 of the adjacent third oscillating core 113.

[0032] Each core unit includes a gate inductor 130 and a gate capacitor (not shown). Each oscillating core 110 has a first gate G1 and a second gate G2. The gate inductor 130 and the gate capacitor are connected in parallel between the first gate G1 and the second gate G2.

[0033] In some embodiments, the multi-core series resonant oscillator 100 further includes a split-coupling network 140. The first gate terminal G1 and the second gate terminal G2 of each oscillation core 110 are connected in parallel to the split-coupling network 140.

[0034] Optionally, multiple oscillation cores 110 are evenly arranged in a ring direction with the split coupling network 140 as the center.

[0035] In some embodiments, the gate inductance 130 of each core unit in the multi-core series resonant oscillator 100 of this application is arranged in a ring around the split coupling network 140, and the gate inductance 130 of each core unit is cross-coupled with the gate inductance 130 of other core units.

[0036] Optionally, the gate inductor 130 is located in the annular region between the drain inductor 120 and the decoupled network 140.

[0037] Figure 2 A schematic diagram of the layout structure of a gate-end inductor 130 according to one embodiment of this application is shown. Figure 2 As shown, when there are four oscillation cores 110, the four gate inductors 130 connected to the four oscillation cores 110 have the same layout structure. In some embodiments, each gate inductor 130 includes a first gate inductor 131, a second gate inductor 132, a third gate inductor 133, and a fourth gate inductor 134 connected to each other in sequence, wherein the first gate inductor 131 is connected to the first gate G1, and the fourth gate inductor 134 is connected to the second gate G2.

[0038] In some embodiments, the first gate inductor 131 and the second gate inductor 132 can be connected by a first connection portion 135; the second gate inductor 132 and the third gate inductor 133 can be connected by a second connection portion 136; and the third gate inductor 133 and the fourth gate inductor 134 can be connected by a third connection portion 137. The first gate inductor 131, the second gate inductor 132, the third gate inductor 133, and the fourth gate inductor 134 of each gate inductor 130 are all located on the same metal layer, while the first connection portion 135, the second connection portion 136, and the third connection portion 137 are located on a different metal layer than the first gate inductor 131, the second gate inductor 132, the third gate inductor 133, and the fourth gate inductor 134.

[0039] In some embodiments, the first connection portion 135 of the gate inductor 130 connected to the first oscillation core 111 is cross-coupled with the third gate inductor 133 connected to the third oscillation core 113; the second connection portion 136 and the third connection portion 137 of the gate inductor 130 connected to the first oscillation core 111 are cross-coupled with the third gate inductor 133 and the first gate inductor 131 connected to the fourth oscillation core 114, respectively. The first gate inductor 131 connected to the first oscillation core 111 is cross-coupled with the third connection portion 137 of the gate inductor 130 connected to the second oscillation core 112; the third gate inductor 133 connected to the first oscillation core 111 is cross-coupled with the second connection portion 136 of the gate inductor 130 connected to the second oscillation core 112 and the first connection portion 135 connected to the third oscillation core 113. Thus, the gate inductor 130 of the first oscillation core 111 can be cross-coupled with the gate inductors 130 of the second oscillation core 112, the third oscillation core 113, and the fourth oscillation core 114.

[0040] It is understood that the first oscillation core 111, the second oscillation core 112, the third oscillation core 113 and the fourth oscillation core 114 mentioned above are only distinguished by name for the convenience of description, and are not used to limit the specific position of the oscillation core 110 in the annular direction.

[0041] Figure 3 Revealed Figure 2 The diagram shown illustrates the working principle of the gate inductor 130. Figure 3 As shown, through Figure 2 The layout design of the four gate inductors 130 shown allows each core cell's gate inductor 130 to have the same inductance value L and line resistance Rs. Furthermore, each core cell's gate inductor 130 can be cross-coupled with the gate inductors 130 of its adjacent core cells and the gate inductors 130 of the opposite core cell. For example, each core cell's gate inductor 130 has a magnetic coupling coefficient k1 with the gate inductors 130 of its adjacent core cells, and each core cell's gate inductor 130 has a magnetic coupling coefficient k2 with the gate inductor 130 of the opposite core cell.

[0042] The multi-core series resonant oscillator 100 of this application realizes a cooperative enhancement type ring-coupled transformer topology through the structural design of the gate inductor 130 and the drain inductor 120. A magnetic coupling transformer network is introduced at the gate and drain of each oscillation core 110, which can be used to realize magnetic enhancement feedforward waveform shaping. Figure 4 The present application discloses the structure and equivalent model of a magnetically enhanced feedforward waveform shaping circuit according to one embodiment. Figure 4 The diagram shows the transformer network topology of a single core unit, such as... Figure 4 As shown, each core unit has a drain inductance with an inductance value of L.D The inductance value of the gate inductor is L G The drain inductor includes a first drain inductor and a second drain inductor, and the first drain inductor and the second drain inductor have the same inductance value L. D / 2, the first drain inductance and the second drain inductance are cross-coupled with each other, having a coupling coefficient K D The drain inductance and the gate inductance are coupled to each other, with a coupling coefficient K. GD C D C represents the drain capacitance. G This represents the gate capacitance. Figure 4 The magnetic coupling coefficient K in the transformer network D K GD Transformed into mutual inductance, resulting in Figure 4 The equivalent model shown is where M1 represents the magnetic coupling coefficient K. GD The resulting mutual inductance, M2, represents the mutual inductance obtained from the magnetic coupling coefficient K. D The mutual inductance obtained can be used to obtain Figure 4 The equivalent model shown includes the electrical coupling gains A and FD, where A = L. G / M1, FD=L D / (2×M2).

[0043] When the gate-drain parasitic capacitance (C) of the MOS transistor in the oscillation core 110 gd When a portion of the input signal is injected into the drain, causing voltage sag and waveform distortion, the negative output signal, after being filtered by an LC network, is coupled to the positive input via the transformer's magnetic flux, forming reverse current compensation. This compensation current is related to C. gd The injected currents have similar amplitudes and opposite phases, thus canceling out the waveform distortion caused by parasitic injection, making the output voltage edges steeper and closer to an ideal square wave. By adjusting the mutual inductance, the compensation effect can be precisely controlled according to the device size and parasitic parameters, thereby effectively improving waveform linearity and phase noise performance.

[0044] The multi-core series resonant oscillator 100 of this application adopts a cooperative enhancement ring-coupled topology, in which each core unit is equivalently coupled through a resistive and magnetic mutual inductance network to form a unified normalized resistance channel, so that the coupling strength between any two core units remains consistent.

[0045] The multi-core series resonant oscillator 100 of this application establishes an implicit mutual inductance path between the gate inductor 130 and the drain inductor 120 by arranging both the drain inductor 120 and the gate inductor 130 in a ring around the coupling network 140, with the gate inductor 130 located in the ring region between the drain inductor 120 and the coupling network 140. This forms an implicit common-mode noise suppression mechanism, which can further improve the oscillator's ability to suppress power supply disturbances. Figure 5A schematic diagram illustrating the implicit common-mode noise suppression mechanism of one embodiment of this application is shown. Figure 5 The diagram shows the transformer network topology of a single core unit, such as... Figure 5 As shown, Figure 5 The four inductors at the top are one-quarter of the drain inductance, and their inductance value is L. D / 4, the two lower inductors are half the gate inductance, and their inductance value is L. G / 2, red represents common-mode noise, and black represents differential-mode signal. Common-mode noise flows in simultaneously from both drain DP and drain DN; differential-mode signal flows in from drain DP and out from drain DN. Figure 5 The flow of common-mode noise and differential-mode signals in the image shows that when common-mode noise occurs in the power supply or bias network, currents in opposite directions are generated in the coupling coils, and the mutual inductance fluxes cancel each other out, thus significantly reducing the degree of power supply noise injected into the resonant cavity and achieving the effect of suppressing common-mode noise. Since this mechanism utilizes the self-balancing characteristics of electromagnetic mutual coupling to achieve noise cancellation, no additional detection and feedback circuits are required, making it simple to implement, requiring no additional power consumption, and highly robust. This implicit suppression structure allows the oscillator to maintain excellent phase stability under standard CMOS power supply conditions. In differential-mode operation, the currents of each core unit are superimposed in the same direction, forming a spatially uniform magnetic field, thereby enhancing the differential-mode signal amplitude and suppressing mode aliasing and frequency pulling effects. This structure not only improves the equivalent resonance quality factor but also improves the consistency of multi-core phase synchronization, enabling the oscillator to maintain low mismatch even when expanded to more cores.

[0046] In summary, the multi-core series resonant oscillator 100 of this application achieves the synergistic effect of waveform distortion compensation, power supply noise suppression and multi-core coupling optimization by introducing two key technologies, magnetic enhancement feedforward waveform shaping and implicit common-mode noise suppression, into the CMOS oscillator structure. This solves the problems of waveform distortion, common-mode interference and multi-core mismatch in traditional silicon-based oscillators, and achieves low noise, high robustness and scalable oscillation performance.

[0047] The multi-core series resonant oscillator 100 of this application does not require an additional low-noise regulator or external high-Q device. It can achieve stable oscillation in the frequency range of 7.15-7.95 GHz under standard CMOS process. The measured phase noise reaches -146.72dBc / Hz@1MHz offset, and the FoM (Figure of Merit) is 190.6dBc / Hz. It significantly breaks through the performance limit of existing silicon-based oscillators, has the advantage of easy integration, and can be widely used in quantum measurement, precision instruments and high-frequency communication systems.

[0048] This application also provides a multi-core series resonant oscillator array 200. Figure 6A schematic diagram of a multi-core series resonant oscillator array 200 according to one embodiment of this application is shown. Figure 6 As shown, a multi-core series resonant oscillator array 200 according to one embodiment of this application includes a total coupling network 240 and a plurality of multi-core series resonant oscillators 100 as described above. The sub-coupling networks 140 of the plurality of multi-core series resonant oscillators 100 are all connected in parallel to the total coupling network 240.

[0049] In some embodiments, multiple multi-core series resonant oscillators 100 are uniformly arranged in a ring direction with the total coupling network 240 as the center. Thus, each core unit forms a ring array structure through magnetic mutual inductance and a normalized resistance network to achieve multi-core synchronous oscillation.

[0050] Compared with existing CMOS oscillators, the multi-core series resonant oscillator 100 and its array 200 of this application have at least one of the following beneficial technical effects: (1) Ultra-low phase noise is achieved by magnetically enhanced feedforward waveform shaping to realize square wave-like output, which improves waveform transition steepness and pulse sensitivity function; (2) Robust common-mode noise suppression: Implicit common-mode noise cancellation technology significantly enhances the ability to resist power supply disturbances; (3) The highly scalable and low-mismatch multi-core synchronization network and cooperative coupling topology ensure inter-core consistency and mode stability, and can be migrated to other frequencies; (4) High performance indicators achieve ultra-low phase noise under CMOS process, breaking the performance record of silicon-based oscillators, suitable for integrated precision instruments and quantum measurement systems.

[0051] The multi-core series resonant oscillator and its array provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the multi-core series resonant oscillator and its array in the embodiments of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the spirit and principles of this application, and these improvements and modifications should all fall within the protection scope of the appended claims.

Claims

1. A multi-core series resonant oscillator, characterized in that, The system comprises multiple core units, each core unit including an oscillation core, a drain inductor, and a drain capacitor. The multiple oscillation cores are arranged in a ring. The drain capacitor is integrated within each oscillation core. Each oscillation core has a first drain terminal, a second drain terminal, and a first capacitor terminal and a second capacitor terminal connected to the drain capacitor. The drain inductor includes a first drain inductor and a second drain inductor. The first drain terminal of each oscillating core is connected to the second capacitor terminal of an adjacent oscillating core via the first drain inductor; the second drain terminal of each oscillating core is connected to the first capacitor terminal of another adjacent oscillating core via the second drain inductor; and... The first drain inductor of each core unit is cross-coupled with the second drain inductor of an adjacent core unit; the second drain inductor of each core unit is cross-coupled with the first drain inductor of another adjacent core unit.

2. The multi-core series resonant oscillator as described in claim 1, characterized in that, The number of the multiple oscillation cores is an even number.

3. The multi-core series resonant oscillator as described in claim 2, characterized in that, Each core unit includes a gate inductor and a gate capacitor. Each oscillation core has a first gate and a second gate. The gate inductor and the gate capacitor are connected in parallel between the first gate and the second gate. The multi-core series resonant oscillator also includes a split coupling network, in which the first gate terminal and the second gate terminal of each oscillation core are connected in parallel to the split coupling network.

4. The multi-core series resonant oscillator as described in claim 3, characterized in that, The multiple oscillation cores are evenly arranged in a ring direction with the sub-coupling network as the center.

5. The multi-core series resonant oscillator as described in claim 3, characterized in that, The gate inductance of each core unit is arranged in a ring around the sub-coupling network, and the gate inductance of each core unit is cross-coupled with the gate inductance of other core units.

6. The multi-core series resonant oscillator as described in claim 5, characterized in that, The gate inductor is located in the annular region between the drain inductor and the decoupled network.

7. The multi-core series resonant oscillator as described in claim 5, characterized in that, The number of the multiple oscillation cores is four, and the four gate inductors corresponding to the four oscillation cores all have the same layout structure.

8. The multi-core series resonant oscillator as described in claim 7, characterized in that, Each gate inductor includes a first gate inductor, a second gate inductor, a third gate inductor, and a fourth gate inductor connected in sequence to each other, wherein the first gate inductor is connected to the first gate, and the fourth gate inductor is connected to the second gate.

9. The multi-core series resonant oscillator as described in claim 8, characterized in that, The first gate terminal inductor and the second gate terminal inductor are connected by a first connection portion; The second gate inductor and the third gate inductor are connected by a second connection portion; The third gate inductor and the fourth gate inductor are connected by a third connection portion. In this configuration, the first gate inductor, the second gate inductor, the third gate inductor, and the fourth gate inductor of each gate inductor are all located on the same metal layer, while the first connection portion, the second connection portion, and the third connection portion are located on a different metal layer than the first gate inductor, the second gate inductor, the third gate inductor, and the fourth gate inductor.

10. The multi-core series resonant oscillator as described in claim 9, characterized in that, The four oscillation cores sequentially include a first oscillation core, a second oscillation core, a third oscillation core, and a fourth oscillation core. The first oscillation core and the third oscillation core are arranged opposite each other, and the first oscillation core, the second oscillation core, and the fourth oscillation core are arranged adjacent to each other. The first connection portion of the gate inductor connected to the first oscillation core is cross-coupled with the third gate inductor connected to the third oscillation core; the second and third connection portions of the gate inductor connected to the first oscillation core are cross-coupled with the third gate inductor and the first gate inductor connected to the fourth oscillation core, respectively. The first gate inductor connected to the first oscillation core is cross-coupled with the third connection portion of the gate inductor connected to the second oscillation core; the third gate inductor connected to the first oscillation core is cross-coupled with the second connection portion of the gate inductor connected to the second oscillation core and the first connection portion of the third oscillation core.

11. A multi-core series resonant oscillator array, characterized in that, It includes a total coupling network and a plurality of multi-core series resonant oscillators as described in any one of claims 1 to 10, wherein the sub-coupling networks of the plurality of multi-core series resonant oscillators are all connected in parallel to the total coupling network.

12. The multi-core series resonant oscillator array as described in claim 11, characterized in that, Multiple multi-core series resonant oscillators are uniformly arranged in a ring direction with the total coupling network as the center.

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