A multi-channel synchronous trigger sampling system and method

Abstract

The application provides a multi-channel synchronous trigger sampling system and method, relates to the technical field of data transmission, and comprises an encoding module, a sampling module, a synchronization module, a decoding module and a trigger module; wherein the encoding module is configured to encode an original trigger signal and a PRBS code stream by using an XOR algorithm to obtain an initial transmission sequence; the sampling module is configured to sample and serial-parallel convert the initial transmission sequence to generate a multi-channel parallel intermediate transmission sequence; the synchronization module is configured to generate a PRBS reference sequence and a PRBS reverse sequence which are the same as the PRBS code stream in the intermediate transmission sequence; the PRBS reference sequence, the PRBS reverse sequence and the intermediate transmission sequence are subjected to correlation operation to determine the time delay and polarity of the initial transmission sequence, obtain a phase-aligned synchronous transmission sequence and a target PRBS code stream for decoding, and then the original trigger signal is recovered after decoding.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a multi-channel synchronous triggering sampling system and method. Background Technology

[0002] In current scientific research and engineering applications, such as high-energy physics experiments, high-speed communication system testing, radar signal processing, and biomedical imaging, the testing scenarios for coherent systems place extremely stringent requirements on the synchronous triggering of multi-channel acquisition systems. The core objective of synchronous triggering of multi-channel acquisition systems is to ensure that each acquisition channel can initiate data acquisition at precisely the same moment, thereby guaranteeing accurate temporal correlation between the acquired signals and providing a reliable data foundation for subsequent signal analysis, processing, and decision-making.

[0003] However, achieving high-precision synchronous triggering in multi-channel acquisition systems faces numerous challenges in practical applications. One key factor is the characteristics of the trigger source. Practical trigger sources are often low-speed trigger signals, which inherently have limited time resolution and cannot directly provide the time information required for high-precision synchronous triggering. For example, in some traditional testing systems, the trigger signal may be generated by a simple mechanical switch or low-frequency electronic circuit, resulting in significant jitter on its rising or falling edges, making it impossible to provide accurate trigger timing indication for multi-channel acquisition systems. Summary of the Invention

[0004] In view of this, the present invention proposes a multi-channel synchronous triggering sampling system and method.

[0005] The technical solution of this invention is implemented as follows: The first aspect of this invention provides a multi-channel synchronous trigger sampling system, comprising: an encoding module, a sampling module, a synchronization module, a decoding module, and a triggering module; wherein, The encoding module includes an XOR gate structure, configured to use an XOR algorithm to encode the original trigger signal and the PRBS code stream to obtain an initial transmission sequence; The sampling module includes a multi-channel structure and is configured to sample and convert the initial transmission sequence into a serial-to-parallel sequence to generate a multi-channel parallel intermediate transmission sequence. The synchronization module is configured to generate a PRBS reference sequence identical to the PRBS code stream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence; and to perform correlation operations using the PRBS reference sequence, the PRBS inversion sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, thereby obtaining a phase-aligned synchronized transmission sequence and a target PRBS code stream for decoding. The decoding module is configured to decode the synchronous transmission sequence using the target PRBS bitstream to generate a decoded signal; The triggering module is configured to recover the original triggering signal based on the decoded signal.

[0006] Based on the above technical solutions, preferably, the sampling module, the synchronization module, the decoding module and the triggering module are composed of FPGA internal circuits.

[0007] Based on the above technical solutions, preferably, the synchronization module includes a PRBS synchronization submodule, a PRBS generator, and an inverter; wherein... The PRBS generator is configured to receive the intermediate transmission sequence and generate a PRBS reference sequence that is identical to the PRBS code stream in the intermediate transmission sequence. The inverter is configured to reverse the polarity of the PRBS reference sequence to generate a PRBS inverted sequence. The PRBS synchronization submodule is configured to perform correlation operations using the PRBS reference sequence, the PRBS inverted sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, perform phase alignment of the initial transmission sequence based on the delay and polarity to obtain a synchronized transmission sequence, and determine the target PRBS bitstream for decoding from the PRBS reference sequence and the PRBS inverted sequence.

[0008] Based on the above technical solutions, preferably, the original trigger signal includes at least one of edge triggering, level triggering, and pulse width triggering.

[0009] More preferably, a second aspect of the present invention provides a multi-channel synchronous triggering sampling method, applied to the multi-channel synchronous triggering sampling system described in the first aspect, comprising: The original trigger signal and PRBS code stream are encoded using the XOR algorithm to obtain the initial transmission sequence; The initial transmission sequence is sampled and converted from serial to parallel to generate a multi-channel parallel intermediate transmission sequence; Generate a PRBS reference sequence identical to the PRBS bitstream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence; use the PRBS reference sequence, the PRBS inversion sequence, and the intermediate transmission sequence to perform calculations to determine the delay and polarity of the initial transmission sequence, and obtain a phase-aligned synchronous transmission sequence and a target PRBS bitstream for decoding; The synchronous transmission sequence is decoded using the target PRBS bitstream to generate a decoded signal; The original trigger signal is recovered based on the decoded signal.

[0010] Based on the above technical solutions, preferably, the step of generating a PRBS reference sequence identical to the PRBS codestream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence, includes: The polarity of the PRBS reference sequence is reversed to generate the corresponding PRBS inverted sequence; The PRBS reference sequence and the PRBS inverted sequence of each channel are shifted by the FPGA internal cyclic shifting process to generate multiple PRBS reference sequences and PRBS inverted sequences of different bits.

[0011] Based on the above technical solutions, preferably, the step of using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal to perform calculations to determine the delay and polarity of the initial transmission sequence, and to obtain a phase-aligned synchronous transmission sequence and a target PRBS code stream for decoding, includes: The delay and polarity of the initial transmission sequence are determined by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal. The initial transmission sequence is phase-aligned based on the delay and polarity to obtain a synchronous transmission sequence, and the target PRBS bitstream for decoding is determined from the PRBS reference sequence and the PRBS inverted sequence.

[0012] Based on the above technical solutions, preferably, the step of determining the delay and polarity of the initial transmission sequence by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal includes: The intermediate transmission sequence is truncated to obtain a transmission subsequence of the same length as the PRBS reference sequence; By simultaneously and in parallel performing correlation operations with the transmitted subsequence using the PRBS reference sequence and the PRBS inverted sequence, multiple correlation operation results are obtained; The delay and polarity of the initial transmission sequence are determined based on the maximum value of the relevant calculation results.

[0013] More preferably, a third aspect of the present invention provides a multi-channel synchronous trigger sampling device, including the multi-channel synchronous trigger sampling system described in the first aspect.

[0014] More preferably, a fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the multi-channel synchronous trigger sampling method described in the second aspect.

[0015] The multi-channel synchronous triggering sampling system and method of the present invention have the following advantages over the prior art: 1. By using an XOR algorithm to encode the original low-speed trigger signal and the PRBS code stream, the rich timing information of the PRBS code stream is embedded into the original trigger signal, greatly improving the signal's temporal resolution and enabling the signal to carry more precise timing information. Based on this, an intermediate transmission sequence is used to generate a PRBS reference sequence identical to the PRBS code stream within it, as well as a corresponding PRBS inversion sequence. Correlation operations are performed based on these three sequences to determine the delay and polarity of the initial transmission sequence, ensuring precise time synchronization of the trigger signals across all channels. This solves the problem of inaccurate synchronization triggering caused by inconsistent delays and polarities between channels, providing a crucial guarantee for high-precision synchronous triggering in multi-channel acquisition systems.

[0016] 2. By using the FPGA's internal cyclic shifting mechanism to shift the PRBS reference sequence and PRBS inverted sequence of each channel, multiple PRBS reference sequences and PRBS inverted sequences of different bits are generated. Then, truncation and XOR operations are performed on the PRBS reference sequences, PRBS inverted sequences, and the original trigger signal to determine the delay and polarity of the initial transmission sequence. This increases the signal redundancy and improves the reliability and stability of the system.

[0017] 3. By truncating the intermediate transmission sequence, a transmission subsequence of the same length as the PRBS reference sequence is obtained. Due to the good autocorrelation of the PRBS sequence, the correlation result reaches its maximum value when the transmission subsequence is perfectly aligned with the PRBS reference sequence in time. By performing parallel correlation operations at multiple different time points and finding the maximum value of the correlation result, the time delay of the transmission subsequence relative to the PRBS reference sequence is determined, thereby determining the time delay of the initial transmission sequence. This provides an accurate basis for subsequent phase alignment, ensuring that the trigger signals of each channel are strictly synchronized in time, effectively solving the problem of inaccurate synchronization caused by time delay differences. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a multi-channel synchronous triggering sampling system provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the working principle of a multi-channel synchronous triggering sampling system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structural correspondence provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the type of the original trigger signal provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating a multi-channel synchronous triggering sampling method provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] In some embodiments, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a multi-channel synchronous trigger sampling system provided by an embodiment of the present invention; the multi-channel synchronous trigger sampling system provided by the present invention includes: an encoding module, a sampling module, a synchronization module, a decoding module, and a triggering module; wherein, The encoding module, including an XOR gate structure, is configured to use an XOR algorithm to encode the original trigger signal and the PRBS code stream to obtain the initial transmission sequence.

[0022] The sampling module, including a multi-channel structure, is configured to sample and convert the initial transmission sequence into a serial-to-parallel sequence to generate a multi-channel parallel intermediate transmission sequence.

[0023] The synchronization module is configured to generate a PRBS reference sequence identical to the PRBS bitstream in the intermediate transmission sequence, as well as a PRBS inverted sequence corresponding to the PRBS reference sequence; it performs correlation operations using the PRBS reference sequence, the PRBS inverted sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, thereby obtaining a phase-aligned synchronized transmission sequence and a target PRBS bitstream for decoding.

[0024] The decoding module is configured to decode the synchronous transmission sequence using the target PRBS bitstream to generate a decoded signal.

[0025] The trigger module is configured to recover the original trigger signal based on the decoded signal.

[0026] In this embodiment, the system receives a raw trigger signal. The encoding module uses an XOR gate structure to perform an XOR operation between the raw trigger signal and the serial PRBS (pseudo-random binary sequence) code stream to generate the encoded trigger signal, i.e., the initial transmission sequence. Combining the raw trigger signal with the PRBS code stream increases the signal complexity and anti-interference capability. The sampling module has a multi-channel structure and can include multiple sampling sub-modules, such as sampling module 1 to sampling module N, to sample the initial transmission sequence. Each sampling module is followed by a 1:Mbit serial-to-parallel conversion. In the sampling module, the serial signal is converted into a multi-channel parallel intermediate transmission sequence, with each channel responsible for sampling a portion of the data. Based on this, the serial-to-parallel conversion is completed to obtain the intermediate transmission sequence. The synchronization module can independently generate a PRBS reference sequence and a corresponding PRBS inverse sequence based on the same algorithm. Correlation operations are performed using the generated PRBS reference sequence, PRBS inverse sequence, and intermediate transmission sequence. Through these operations, the system can determine the delay and polarity of the initial transmission sequence, thereby achieving phase alignment and obtaining a synchronized transmission sequence and a target PRBS code stream for decoding. The decoding module uses the target PRBS bitstream provided by the synchronization module to decode the synchronization transmission sequence. Through XOR operation or other appropriate decoding algorithms, it restores the encoded signal to the original logic signal, generating a decoded signal. The triggering module recovers the original trigger signal based on the decoded signal.

[0027] In some embodiments, the sampling module, synchronization module, decoding module, and triggering module are composed of internal circuitry of the FPGA.

[0028] In this embodiment, please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram illustrating the working principle of a multi-channel synchronous triggering sampling system provided in an embodiment of the present invention; Figure 3This diagram illustrates the structural correspondence of an embodiment of the invention. The initial transmission sequence is obtained by XORing the original trigger signal with the serial PRBS code stream using an XOR gate in the encoding module. The synchronization module includes PRBS synchronization and a PRBS generator structure. On one hand, a PRBS reference sequence identical to the PRBS code stream is generated through the PRBS synchronization mechanism; on the other hand, a PRBS inverted sequence corresponding to this PRBS reference sequence is generated. Correlation operations are performed using the generated PRBS reference sequence, the PRBS inverted sequence, and the received intermediate transmission sequence to detect the similarity between signals. By calculating the correlation values ​​under different delays, the delay and polarity of the initial transmission sequence are determined. After computation and processing, phase alignment of the signals in each channel is achieved, resulting in a synchronized transmission sequence, and the target PRBS code stream for decoding is determined. Here, RX represents the receiver and TX represents the transmitter. The FPGA structure at the bottom of the diagram contains a PRBS generator that produces a parallel PRBS code stream, which is output after PRBS synchronization processing, providing the necessary PRBS code stream support for the encoding and synchronization process of the entire system.

[0029] In some embodiments, the synchronization module includes a PRBS synchronization submodule, a PRBS generator, and an inverter; wherein... A PRBS generator is configured to receive an intermediate transmission sequence and generate a PRBS reference sequence that is identical to the PRBS bitstream in the intermediate transmission sequence. An inverter, configured to reverse the polarity of a PRBS reference sequence to generate a PRBS inverted sequence; The PRBS synchronization submodule is configured to perform correlation operations using the PRBS reference sequence, the PRBS inverted sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, perform phase alignment of the initial transmission sequence based on the delay and polarity to obtain the synchronization transmission sequence, and determine the target PRBS bitstream for decoding from the PRBS reference sequence and the PRBS inverted sequence.

[0030] In this embodiment, the initial transmission sequence can be represented as: .

[0031] in, This is the encoded initial transmission sequence. It is a high-speed PRBS bitstream. The digital signal obtained after the original trigger signal is acquired. This is an XOR operation.

[0032] The initial transmission sequence is sampled and converted from serial to parallel using a multi-channel structure to generate a multi-channel parallel intermediate transmission sequence. .

[0033] Let the PRBS reference sequence generated within each channel and the inverted PRBS sequence be as follows: ; Taking the k-th channel as an example, its internally generated PRBS sequence and its inverted sequence are as follows: . Sequences are generated by cyclic shifting within the FPGA. ,in, Subtract 1 from the length of the PRBS code.

[0034] Will Simultaneous parallel and Perform relevant calculations, among which, This indicates a truncation operation. for The length is truncated to and Sequences of the same length. The relevant operation results are: , , , ... , .

[0035] according to The maximum value among the results of the correlation calculations determines the delay and polarity of the initial transmission sequence, and the target PRBS bitstream used for subsequent decoding is selected accordingly.

[0036] For example, if If the maximum value is found, the delay is L. Simultaneously, the polarity of this frame in the high-speed signal stream is negative; therefore, the optimal value is selected. The target PRBS bitstream is used for decoding. If If the maximum value is found, the delay is H. Simultaneously, the polarity of this frame in the high-speed signal stream is positive; therefore, the optimal value is selected. The target PRBS bitstream is used for decoding.

[0037] The decoding module can be constructed from the internal XOR gates of N FPGAs. When a PRBS sequence is selected for decoding... or Then, an XOR decoding operation is performed internally. The decoded signal flow can then be represented as... or Since the synchronization operation has been completed at this point, or Considering the associative law of the XOR operation, the decoded signal flow can be expressed as follows: or The synchronization and decoding process is illustrated using the k-th channel as an example. However, the decoded signal is independent of the time delay of different channels and the polarity of the received signal; the decoded signal is always the result of the trigger signal being truncated. Therefore, it can be used for precise synchronous triggering of N-channel sampling systems.

[0038] In some embodiments, the original trigger signal includes at least one of edge triggering, level triggering, and pulse width triggering.

[0039] In this embodiment, please refer to Figure 4 , Figure 4 This diagram illustrates the types of original trigger signals provided in this embodiment of the invention. Edge triggering focuses on the transition edges of signal levels, such as rising or falling edges. In high-speed data acquisition systems, edge triggering ensures timely sampling at the moment of signal change, preventing the loss of critical data, especially for capturing transient signals. Level triggering determines whether to trigger based on the signal's level state. Sampling is triggered when the signal level reaches or remains at a specific value. Pulse width triggering can identify pulse signals with a specific width and trigger sampling. It can filter out interference pulses with widths that do not meet the requirements, thereby improving the system's anti-interference capability and ensuring the accuracy and reliability of sampling.

[0040] In some embodiments, please refer to Figure 5 , Figure 5 This is a flowchart illustrating a multi-channel synchronous triggering sampling method provided in an embodiment of the present invention; the multi-channel synchronous triggering sampling method is applied to the aforementioned multi-channel synchronous triggering sampling system, and includes: S510 uses an XOR algorithm to encode the original trigger signal and PRBS code stream to obtain the initial transmission sequence.

[0041] S520 samples and performs serial-to-parallel conversion on the initial transmission sequence to generate a multi-channel parallel intermediate transmission sequence.

[0042] S530, generate a PRBS reference sequence identical to the PRBS code stream in the intermediate transmission sequence, and a PRBS inverted sequence corresponding to the PRBS reference sequence; use the PRBS reference sequence, PRBS inverted sequence and intermediate transmission sequence to perform calculations to determine the delay and polarity of the initial transmission sequence, and obtain a phase-aligned synchronous transmission sequence and a target PRBS code stream for decoding.

[0043] The S540 uses the target PRBS bitstream to decode the synchronous transmission sequence and generate a decoded signal.

[0044] The S550 recovers the original trigger signal based on the decoded signal.

[0045] In this embodiment, the original trigger signal can be an edge-triggered, level-triggered, or pulse-width-triggered signal, and its form and parameters are determined according to the specific application scenario. The PRBS code stream is generated by a dedicated PRBS generator. The PRBS generator generates a pseudo-random sequence with good autocorrelation characteristics based on a certain algorithm, such as the linear feedback shift register algorithm. The parameters of the PRBS code stream, such as code length and rate, are set according to system requirements. The original trigger signal and the PRBS code stream are simultaneously input into an XOR gate circuit. Through XOR operation, the original trigger signal and the PRBS code stream are encoded and fused to obtain the encoded initial transmission sequence. The encoded initial transmission sequence is input into a serial-to-parallel converter to convert the serial initial transmission sequence into a multi-channel parallel intermediate transmission sequence. Each channel outputs a portion of data to achieve parallel data transmission and processing. Using a PRBS generator with the same algorithm as the transmitter, a PRBS reference sequence identical to the PRBS code stream in the received intermediate transmission sequence is generated. At the same time, by inverting the PRBS reference sequence, a PRBS inverted sequence corresponding to the PRBS reference sequence is generated. The generated PRBS reference sequence and PRBS inverted sequence are correlated with the intermediate transmission sequence, and the time delay relationship is determined by calculating the similarity between the two sequences at different time delays. When the correlation value reaches its maximum value, the corresponding time delay is the time delay of the initial transmission sequence. Simultaneously, the polarity of the initial transmission sequence is determined by comparing the correlation results between the intermediate transmission sequence and the PRBS reference and PRBS inverted sequences. Based on the determined time delay and polarity, the intermediate transmission sequence is phase-aligned to obtain the synchronous transmission sequence. At the same time, the target PRBS code stream for decoding is determined. In the decoding module, the synchronous transmission sequence and the target PRBS code stream are XORed. The XOR operation eliminates the influence of the PRBS code stream introduced during encoding, restoring the encoded synchronous transmission sequence to its original logical state, generating the decoded signal. The processed decoded signal is the recovered original trigger signal.

[0046] In some embodiments, generating a PRBS reference sequence identical to the PRBS bitstream in the intermediate transmission sequence, and a PRBS inverse sequence corresponding to the PRBS reference sequence, includes: The polarity of the PRBS reference sequence is reversed to generate the corresponding PRBS inverted sequence. The PRBS reference sequence and PRBS inverted sequence of each channel are shifted by the internal cyclic shift of the FPGA to generate multiple PRBS reference sequences and PRBS inverted sequences of different bits.

[0047] Generating multiple PRBS reference sequences and PRBS inverse sequences with different bit values ​​through cyclic shifting is equivalent to detecting at multiple different time delay positions. This allows for a more detailed scan of the entire time delay range, more accurately identifying the point of maximum correlation, and thus accurately determining the signal delay, improving the accuracy of multi-channel synchronization. Furthermore, different channels may have different effects on the signal, including delay spread and phase distortion. Generating multiple sequences better adapts to various channel characteristics, and through correlation operations, accurately extracts useful synchronization information from the channel-affected received signal, ensuring the stability of multi-channel synchronization.

[0048] In some embodiments, calculations are performed using a PRBS reference sequence, a PRBS inverted sequence, and the original trigger signal to determine the delay and polarity of the initial transmission sequence, resulting in a phase-aligned synchronous transmission sequence and a target PRBS bitstream for decoding, including: The delay and polarity of the initial transmission sequence are determined by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal. Phase alignment of the initial transmission sequence is performed based on delay and polarity to obtain a synchronous transmission sequence, and the target PRBS bitstream for decoding is determined from the PRBS reference sequence and the PRBS inverted sequence.

[0049] In some embodiments, the delay and polarity of the initial transmission sequence are determined by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal, including: The intermediate transmission sequence is truncated to obtain a transmission subsequence of the same length as the PRBS reference sequence; By simultaneously performing correlation operations with the transport subsequence using the PRBS reference sequence and the PRBS inverted sequence, multiple correlation operation results are obtained. The delay and polarity of the initial transmission sequence are determined based on the maximum value of the relevant calculation results.

[0050] It should be noted that the multi-channel synchronous trigger sampling method and the multi-channel synchronous trigger sampling system provided in this application are based on the same application concept. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned multi-channel synchronous trigger sampling system, and the repeated parts will not be described again.

[0051] In some embodiments, the multi-channel synchronous trigger sampling device provided in this application includes the multi-channel synchronous trigger sampling system described above.

[0052] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the multi-channel synchronous trigger sampling method described above. This computer-readable medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into that device / apparatus / system. The aforementioned computer-readable medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0053] According to embodiments of this application, a computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wired, optical fiber, radio frequency signals, etc., or any suitable combination thereof.

[0054] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A multi-channel synchronous trigger sampling system, characterized in that, include: The module comprises an encoding module, a sampling module, a synchronization module, a decoding module, and a triggering module; among which, The encoding module includes an XOR gate structure, configured to use an XOR algorithm to encode the original trigger signal and the PRBS code stream to obtain an initial transmission sequence; The sampling module includes a multi-channel structure and is configured to sample and convert the initial transmission sequence into a serial-to-parallel sequence to generate a multi-channel parallel intermediate transmission sequence. The synchronization module is configured to generate a PRBS reference sequence identical to the PRBS code stream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence; and to perform correlation operations using the PRBS reference sequence, the PRBS inversion sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, thereby obtaining a phase-aligned synchronized transmission sequence and a target PRBS code stream for decoding. The decoding module is configured to decode the synchronous transmission sequence using the target PRBS bitstream to generate a decoded signal; The triggering module is configured to recover the original triggering signal based on the decoded signal.

2. The multi-channel synchronous triggering sampling system as described in claim 1, characterized in that, The sampling module, the synchronization module, the decoding module, and the triggering module are composed of FPGA internal circuitry.

3. The multi-channel synchronous triggering sampling system as described in claim 1, characterized in that, The synchronization module includes a PRBS synchronization submodule, a PRBS generator, and an inverter; wherein... The PRBS generator is configured to receive the intermediate transmission sequence and generate a PRBS reference sequence that is identical to the PRBS code stream in the intermediate transmission sequence. The inverter is configured to reverse the polarity of the PRBS reference sequence to generate a PRBS inverted sequence. The PRBS synchronization submodule is configured to perform correlation operations using the PRBS reference sequence, the PRBS inverted sequence, and the intermediate transmission sequence to determine the delay and polarity of the initial transmission sequence, perform phase alignment of the initial transmission sequence based on the delay and polarity to obtain a synchronized transmission sequence, and determine the target PRBS bitstream for decoding from the PRBS reference sequence and the PRBS inverted sequence.

4. The multi-channel synchronous triggering sampling system as described in claim 1, characterized in that, The original trigger signal includes at least one of edge triggering, level triggering, and pulse width triggering.

5. A multi-channel synchronous trigger sampling method, applied to the multi-channel synchronous trigger sampling system according to any one of claims 1 to 4, characterized in that, include: The original trigger signal and PRBS code stream are encoded using the XOR algorithm to obtain the initial transmission sequence; The initial transmission sequence is sampled and converted from serial to parallel to generate a multi-channel parallel intermediate transmission sequence; Generate a PRBS reference sequence identical to the PRBS bitstream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence; use the PRBS reference sequence, the PRBS inversion sequence, and the intermediate transmission sequence to perform calculations to determine the delay and polarity of the initial transmission sequence, and obtain a phase-aligned synchronous transmission sequence and a target PRBS bitstream for decoding; The synchronous transmission sequence is decoded using the target PRBS bitstream to generate a decoded signal; The original trigger signal is recovered based on the decoded signal.

6. The multi-channel synchronous triggering sampling method as described in claim 5, characterized in that, The generation of a PRBS reference sequence identical to the PRBS codestream in the intermediate transmission sequence, and a PRBS inversion sequence corresponding to the PRBS reference sequence, includes: The polarity of the PRBS reference sequence is reversed to generate the corresponding PRBS inverted sequence; The PRBS reference sequence and the PRBS inverted sequence of each channel are shifted by the FPGA internal cyclic shifting process to generate multiple PRBS reference sequences and PRBS inverted sequences of different bits.

7. The multi-channel synchronous triggering sampling method as described in claim 6, characterized in that, The step of using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal to perform calculations to determine the delay and polarity of the initial transmission sequence, and to obtain a phase-aligned synchronous transmission sequence and a target PRBS bitstream for decoding, includes: The delay and polarity of the initial transmission sequence are determined by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal. The initial transmission sequence is phase-aligned based on the delay and polarity to obtain a synchronous transmission sequence, and the target PRBS bitstream for decoding is determined from the PRBS reference sequence and the PRBS inverted sequence.

8. The multi-channel synchronous triggering sampling method as described in claim 7, characterized in that, The step of determining the delay and polarity of the initial transmission sequence by performing truncation and XOR operations using the PRBS reference sequence, the PRBS inverted sequence, and the original trigger signal includes: The intermediate transmission sequence is truncated to obtain a transmission subsequence of the same length as the PRBS reference sequence; By simultaneously and in parallel performing correlation operations with the transmitted subsequence using the PRBS reference sequence and the PRBS inverted sequence, multiple correlation operation results are obtained; The delay and polarity of the initial transmission sequence are determined based on the maximum value of the relevant calculation results.

9. A multi-channel synchronous trigger sampling device, comprising the multi-channel synchronous trigger sampling system according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, It stores a computer program, wherein the computer program, when executed by a processor, implements the multi-channel synchronous trigger sampling method as described in any one of claims 5 to 8.

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