A method, chip, medium and device for dynamic resource configuration of an LDPC decoder

Abstract

The application provides an LDPC decoder dynamic resource configuration method, a chip, a medium and equipment, and the method comprises the following steps: obtaining user decoding performance requirements and to-be-decoded data; determining a decoding resource configuration scheme of the to-be-decoded data based on the user decoding performance requirements; generating a corresponding configuration signal based on the decoding resource configuration scheme and performing iterative decoding processing on the to-be-decoded data to obtain a decoding check result; delivering the decoding check result to a decoding manager and adjusting an iterative decoding processing process based on a current state of a previous buffer, a subsequent buffer and a decoding processor; and obtaining decoded data based on the adjusted LDPC decoder and outputting the decoded data. The application can configure an efficient and stable LDPC decoder for a specific use scenario, while ensuring that the use of hardware resources and power consumption control are within a reasonable range.

Description

Technical Field

[0001] This invention belongs to the technical field of decoders, and in particular relates to a dynamic resource configuration method, system, chip, and device for an LDPC decoder. Background Technology

[0002] In the design of Ethernet physical layer chips, low-density parity check (LDPC) codes are widely used as a forward error correction technique to improve the reliability and efficiency of data transmission. IEEE specifies the use of specific LDPC code types at the physical layer. While the standard specifies the code type, it does not limit the specific implementation of the decoder, providing chip designers with room for innovation: on the one hand, to improve decoding performance, LDPC decoders need to perform multiple iterative calculations; on the other hand, to increase throughput, the decoder needs to complete the iteration process as quickly as possible. There is an inherent contradiction between these two aspects, as high performance often means more iterations, which conflicts with the need to complete decoding quickly.

[0003] In physical layer chips, there are stringent requirements for the throughput and performance of decoders. The IEEE standard specifies that the LDPC code parity-check matrix can be split row-wise, so designers mostly adopt a row-level decoder architecture with high parallelism. To meet these requirements, designers have to increase chip area to balance high throughput and high performance. However, due to the highly parallel architecture of LDPC code decoders and the frequent signal switching during decoding, this significantly increases the power consumption of Ethernet physical layer chips.

[0004] Therefore, how to provide a dynamic resource configuration method for LDPC decoders to solve the above problems has become an urgent problem for those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a dynamic resource configuration method, chip, medium, and device for LDPC decoders, in order to solve the problem of how to optimize the resource allocation and power consumption management of LDPC decoders while adhering to the performance and throughput standards specified by the Ethernet physical layer protocol, reduce chip resource occupation and power consumption, and maintain sufficient flexibility so that users can make personalized adjustments to the decoder according to different application requirements and communication environments.

[0006] In a first aspect, the present invention provides a dynamic resource configuration method for an LDPC decoder, the method comprising the following steps: obtaining user decoding performance requirements and data to be decoded;

[0007] Determine the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements;

[0008] Based on the decoding resource configuration scheme, a corresponding LDPC decoder configuration signal is generated, and the data to be decoded is iteratively decoded to obtain the decoding verification result.

[0009] The decoding verification result is sent to the decoding manager, and the decoding process is adjusted and iterated based on the current state of the front buffer, the back buffer, the decoder core input and output buffer, and the decoding processor.

[0010] The decoded data is obtained and output based on the adjusted LDPC decoder.

[0011] In one implementation of the first aspect, determining the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements includes the following steps:

[0012] Based on the user's decoding performance requirements, the parameter configuration set for the number of iterations, parallelism, and operating frequency corresponding to the data to be decoded is determined through simulation;

[0013] The parameter configuration sets are verified and evaluated respectively, and the group with the best decoding performance is selected as the parameter configuration of the LDPC decoder.

[0014] In one implementation of the first aspect, based on the user's decoding performance requirements, the set of iteration count, parallelism, and operating frequency corresponding to the data to be decoded is determined using the following formula:

[0015]

[0016] Where I represents the number of iterations of the LDPC decoder under the current channel, L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern, N represents the parallelism of the LDPC decoder, and f represents the operating frequency of the LDPC decoder. s f0 represents the throughput of the LDPC decoder; f0 represents the external operating frequency of the LDPC decoder.

[0017] In one implementation of the first aspect, the parallelism N is calculated using the following formula:

[0018]

[0019] Where, N f M represents the number of consecutive error frames. rec Indicates the number of frames recovered; L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern; N s This indicates the maximum number of clock cycles required for the LDPC decoder to decode one frame of data at f0; Iavg Indicates the average number of iterations; I max This indicates the maximum number of iterations.

[0020] In one implementation of the first aspect, generating a corresponding LDPC decoder configuration signal based on the decoding resource configuration scheme and performing iterative decoding processing on the data to be decoded to obtain the decoding verification result includes the following steps:

[0021] Based on the configuration signal, the parameters of the LDPC decoder are set and a corresponding number of data to be decoded are pre-stored;

[0022] The data to be decoded is concatenated, and the concatenated data to be decoded is cached in the previous cache and the decoding entry cache, respectively.

[0023] The data to be decoded is cached in the iterative LLR cache, and the data to be decoded is subjected to the first data processing to obtain the processed first data to be decoded;

[0024] Based on the data node information and verification node information of the first data to be decoded, update the data value of the first data to be decoded;

[0025] The updated first data to be decoded is subjected to second data processing to obtain the processed second data to be decoded and cached in the iterative LLR cache;

[0026] The sign bit of the second data to be decoded is read and it is determined whether the second data to be decoded meets the verification condition. The decoding verification result is obtained and sent to the iterative controller.

[0027] In one implementation of the first aspect, the decoding verification result is sent to the decoding manager, and the iterative decoding process is adjusted based on the current state of the previous buffer, the next buffer, the decoder core input / output buffer, and the decoding processor, including the following steps:

[0028] The subsequent buffer is initialized and the amount of data is pre-stored to a set value;

[0029] When the amount of data cached by the subsequent buffer reaches a set value, the decoding manager enters a normal management state and obtains the decoded data based on the final decoding verification result;

[0030] When the subsequent buffer starts consuming the pre-stored data, the decoder enters a stress-resistant state and terminates the iterative processing based on the states of the preceding and subsequent buffers and obtains the corresponding data.

[0031] When the downstream buffer consumes all the pre-stored data, the decoder enters a recovery state until the downstream buffer restores the pre-stored data to a set value, at which point the decoder returns to the normal management state.

[0032] In one implementation of the first aspect, preprocessing the data to be decoded and caching the preprocessed data to be decoded into a preceding buffer and a decoding processing entry buffer respectively includes the following steps:

[0033] The data to be decoded is received and spliced ​​together according to the internal and external frequency differences, then buffered into the previous buffer.

[0034] After the forward buffer down-clocks the data to be decoded, it caches it in the decoding processing entry cache, waiting for the decoding processor to read it.

[0035] In a second aspect, the present invention provides a dynamic resource configuration chip for an LDPC decoder, the chip comprising a first acquisition module, a resource configuration module, a decoding processing module, a decoding management module, and a second acquisition module;

[0036] The first acquisition module is used to acquire the user's decoding performance requirements and the data to be decoded;

[0037] The configuration resource module is used to determine the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements.

[0038] The decoding processing module is used to generate a corresponding LDPC decoder configuration signal based on the decoding resource configuration scheme and perform iterative decoding processing on the data to be decoded to obtain the decoding verification result;

[0039] The decoding management module is used to send the decoding verification result to the decoding manager, and adjust the iterative decoding process based on the current state of the front buffer, the back buffer, the decoder core input and output buffer, and the decoding processor.

[0040] The second acquisition module is used to acquire and output the decoded data based on the adjusted LDPC decoder.

[0041] Thirdly, the present invention provides an electronic device, the electronic device comprising: a processor and a memory;

[0042] The memory is used to store computer programs;

[0043] The processor is used to execute the computer program stored in the memory, so that the electronic device performs the above-described LDPC decoder dynamic resource configuration method.

[0044] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by an electronic device, implements the above-described dynamic resource configuration method for an LDPC decoder.

[0045] As described above, the LDPC decoder dynamic resource configuration method, system, storage medium, and electronic device of the present invention have the following beneficial effects:

[0046] This invention can significantly improve decoding performance: by real-time monitoring and dynamic adjustment of decoding parameters, this invention can ensure that the LDPC decoder maintains optimal decoding performance under different communication environments and user requirements, thereby reducing the bit error rate and improving the reliability of data transmission.

[0047] This invention can optimize resource utilization: dynamically adjust the allocation of hardware resources, including memory and processor load, according to actual needs, thereby improving resource utilization and reducing unnecessary resource waste; the dynamic resource allocation method helps to reduce overall energy consumption and extend the service life of equipment by optimizing the use of hardware resources while meeting decoding performance requirements.

[0048] This invention enhances system adaptability: by adaptively adjusting parameters such as the number of iterations, parallelism, and operating frequency, this invention enables the LDPC decoder to better adapt to changing channel conditions and data processing requirements, thereby enhancing the system's flexibility and adaptability.

[0049] This invention improves data processing efficiency: By optimizing the data processing flow and sequence, this invention can improve the data processing speed of the LDPC decoder, thereby increasing system throughput and meeting the needs of high-speed communication. Attached Figure Description

[0050] Figure 1 The flowchart shown is an embodiment of the dynamic resource allocation method for the LDPC decoder of the present invention.

[0051] Figure 2 The diagram shows the stress recovery state during the decoding process of the LDPC decoder of the present invention.

[0052] Figure 3 This is a schematic diagram showing the parallelism N in the LDPC parity check matrix;

[0053] Figure 4 This diagram illustrates the process of processing high and low frequency data across the forward buffer of an LDPC decoder.

[0054] Figure 5a The diagram shows a simplified architectural representation of an embodiment of a dynamic resource allocation method for an LDPC decoder.

[0055] Figure 5bThe diagram shows a detailed schematic of the architecture of an embodiment of the dynamic resource allocation method for an LDPC decoder.

[0056] Figure 6 This is a diagram showing the state transitions of the LDPC decoder manager.

[0057] Figure 7 The diagram shown is a structural schematic of the LDPC decoder dynamic resource allocation chip of the present invention in one embodiment;

[0058] Figure 8 The diagram shown is a structural schematic of an embodiment of the electronic device of the present invention. Detailed Implementation

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0060] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0062] like Figure 1 As shown, in one embodiment, the LDPC decoder dynamic resource configuration method of the present invention includes steps S11 to S15.

[0063] Step S11: Obtain the user's decoding performance requirements and the data to be decoded.

[0064] Obtaining the user's decoding performance requirements and the data to be decoded is the first step in the dynamic resource configuration method of the LDPC decoder. This step ensures that subsequent resource configuration and decoding processes can meet the performance requirements of specific application scenarios.

[0065] Specifically, users analyze and determine the key performance indicators of the LDPC decoder based on specific application scenarios, including but not limited to data throughput and operating frequency. Based on scenario analysis, users set the expected number of iterations (average number of iterations and maximum number of iterations), decoding frequency, and parallelism of the LDPC decoder.

[0066] In one embodiment, suppose a wireless communication system exists where the user desires a bit error rate (BER) of no more than 10. -6 The user requires the decoder to operate at a rate of 100 Mbps. The system has strict power consumption limits for the decoder, not exceeding 2 watts. The communication receiver receives an LDPC codeword with a code rate of 1 / 2 and a code length of 1024. After modulation, channel transmission, and matched filtering, the corresponding log-likelihood ratio (LLR) value sequence is obtained. First, clarify the user's requirements: define the user's specific requirements for decoding performance, including bit error rate, processing speed, and power consumption. Second, prepare the data to be decoded: obtain the raw data from the communication receiver. This data is typically a binary sequence that has been converted into LLR values, representing the probability information of each bit being 0 or 1. Third, match requirements with data: match the user's requirements with the acquired data to be decoded to determine the decoder's configuration parameters. For example, if the user requires high throughput, the decoder may need to be configured with higher parallelism. Finally, initialize the decoder: based on the user's requirements and the characteristics of the data to be decoded, initialize the decoder's relevant parameters, such as the number of iterations, parallelism, and operating frequency.

[0067] Step S12: Determine the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements. This specifically includes the following steps:

[0068] Based on the user's decoding performance requirements, the parameter configuration set for the number of iterations, parallelism, and operating frequency corresponding to the data to be decoded is determined through simulation;

[0069] The parameter configuration sets are verified and evaluated respectively, and the group with the best decoding performance is selected as the parameter configuration of the LDPC decoder.

[0070] Specifically, based on the user's specific needs, a simulation environment is set up, including the channel model, signal-to-noise ratio (SNR), and data rate. Initial parameters of the decoder are determined, such as code length, code rate, and parity check matrix structure. The simulation is run, and changes in decoding performance (e.g., bit error rate BER) are observed by varying the number of iterations. The average number of iterations I required to achieve the user's performance requirements (e.g., a specific BER) is determined. avg and the maximum number of iterations I max Among them, the average number of iterations I avgThis represents the average number of iterations required by the decoder to process data under normal conditions, reflecting the decoder's performance under normal operating conditions. Maximum number of iterations I max This represents the maximum number of iterations the decoder can achieve when processing data under extreme conditions. Beyond this number, the performance improvement will no longer be significant, or the benefit will be negligible. Considering decoding speed and hardware resources, a possible range of parallelism N is determined, and the decoding performance and resource consumption under different parallelism levels are evaluated through simulation. Based on the operating frequencies f0 of the preceding and following modules and the decoder's design constraints, a possible range of operating frequencies f is determined. Simulation analysis is performed to analyze the decoding performance and power consumption at different operating frequencies.

[0071] This also includes the number of verification matrix layers L. H The LDPC code type determines the decoder's internal data processing flow and complexity. The external operating frequency f0 is the frequency at which the decoder interacts with upstream and downstream modules, determining the decoder's data throughput. The maximum number of clock cycles N... s : Indicates the maximum number of clock cycles required for the decoder to process one frame of data.

[0072] Furthermore, based on the user's decoding performance requirements, the set of iteration count, parallelism, and operating frequency corresponding to the data to be decoded is determined using the following formula:

[0073]

[0074] Where I represents the number of iterations of the LDPC decoder under the current channel, L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern, N represents the parallelism of the LDPC decoder, and f represents the operating frequency of the LDPC decoder. s This indicates the maximum number of clock cycles required to decode one frame of LDPC data at a specified external decoding clock frequency f0; f0 represents the external operating frequency of the LDPC decoder. This represents the maximum time limit required to decode one frame of data.

[0075] Based on the above formula, the sets of I, N, and f are obtained:

[0076] Number of iterations I <![CDATA[I1]]> <![CDATA[I2]]> <![CDATA[I3]]> … Parallelism N* <![CDATA[N1]]> <![CDATA[N2]]> <![CDATA[N3]]> … Operating frequency f <![CDATA[f1]]> <![CDATA[f2]]> <![CDATA[f3]]> …

[0077] Where * indicates that the LDPC code length multiplied by the parallelism equals the number of units in the LDPC decoding core.

[0078] I∈{I1,I2,I3,…},I≥I avg , f∈{f1,f2,f3,…},f≤f o At the same time, N must satisfy the inequality constraints.

[0079] like Figure 2 As shown, N f It is determined by the channel conditions and is used to ensure the ability to handle continuous data errors. The LDPC decoder guarantees N f All frame data can be iterated I max Next. N rec This is the number of frames required for the cache to recover from a stress state to a normal state, calculated using the following formula:

[0080]

[0081] It is evident that if the channel fluctuation is large, N needs to be increased. f To combat data errors caused by uneven distribution. N rec The smaller the value, the more frequently the decoder can handle consecutive data errors.

[0082] Furthermore, the parameter configuration sets are verified and evaluated respectively, and the group with the best decoding performance is selected as the parameter configuration for the LDPC decoder, including the following steps:

[0083] Obtain the area and power consumption of the LDPC decoder under different configurations in the parameter configuration set;

[0084] The minimum required parallelism is determined based on the area and power consumption of the LDPC decoder.

[0085] The optimal parameter configuration is determined based on the minimum parallelism.

[0086] like Figure 3 As shown, considering P∝I avg Given *f*N and area A∝N, to reduce power consumption, we prioritize reducing the parallelism N. Based on inequalities, we can derive the lower limit of the parallelism N as:

[0087]

[0088] Where, N f N represents the number of consecutive error frames; rec Indicates the number of frames recovered; L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern; N s This indicates the throughput of the LDPC decoder.

[0089] Specifically, computer simulation software is used to simulate the decoding performance of the data to be decoded under different parameter configurations. During the simulation, other conditions are kept constant, only the number of iterations, parallelism, and operating frequency are changed, and the changes in decoding performance are observed. Area, power consumption, resource usage, decoding error rate, and decoding latency are used as evaluation criteria. For each parameter configuration, simulation results are recorded, and the above evaluation metrics are calculated. The evaluation results under different parameter configurations are compared to find the optimal parameter combination that meets the user's decoding performance requirements (such as area, bit error rate, processing speed, and power consumption limitations). The optimal parameter configuration refers to those parameter combinations that achieve the best decoding performance while meeting all performance requirements.

[0090] In one embodiment, a set of parameter configurations is determined based on user requirements, including the following parameters:

[0091] Number of iterations: 5, 10, 15, 20

[0092] Parallelism: 1, 4, 8, 16

[0093] Operating frequencies: 100MHz, 300MHz, 500MHz, 1GHz

[0094] Run simulations for each parameter combination, for example, a configuration with 10 iterations, 8 parallelism channels, and a 500MHz operating frequency. Record the decoding error rate, decoding latency, power consumption, and resource usage for each configuration. Compare these results, and assume that we find that the configuration with 10 iterations, 8 parallelism channels, and a 500MHz operating frequency provides the lowest bit error rate and reasonable decoding latency while meeting power consumption constraints.

[0095] Ultimately, this configuration was chosen as the parameter configuration for the LDPC decoder because it provides optimal decoding performance while meeting all user needs.

[0096] Step S13: Generate the corresponding LDPC decoder configuration signal based on the decoding resource configuration scheme and perform iterative decoding processing on the data to be decoded to obtain the decoding verification result. Specifically, this includes the following steps:

[0097] Based on the configuration signal, the parameters of the LDPC decoder are set and a corresponding number of data to be decoded are pre-stored;

[0098] The data to be decoded is concatenated, and the concatenated data to be decoded is cached in the previous cache and the decoding entry cache, respectively.

[0099] The data to be decoded is cached in the iterative LLR cache, and the data to be decoded is subjected to the first data processing to obtain the processed first data to be decoded;

[0100] Based on the data node information and verification node information of the first data to be decoded, update the data value of the first data to be decoded;

[0101] The updated first data to be decoded is subjected to second data processing to obtain the processed second data to be decoded and cached in the iterative LLR cache;

[0102] The sign bit of the second data to be decoded is read and it is determined whether the second data to be decoded meets the verification condition. The decoding verification result is obtained and sent to the iterative controller.

[0103] Specifically, the register settings parameters of the LDPC decoder of this invention are configured based on optimal settings. The LDPC decoder architecture of this invention belongs to an adjustable layered decoder architecture, which can be used in various LDPC code decoding scenarios, requiring only the adjustment of the configuration registers.

[0104] (1) CFG1: Data width of the previous buffer

[0105] CFG1 determines the data bit width of the preceding buffer and is responsible for transferring data from the high-frequency clock domain to the low-frequency clock domain.

[0106] The data bit width needs to be determined based on the frequency ratio of the high-frequency clock domain to the low-frequency clock domain. This is determined by the time taken to read from the preceding buffer, which is less than the time taken to write a single frame of data. Therefore, the length of the data to be concatenated should be a multiple of the following formula:

[0107]

[0108] Where, N c Indicates the data bit width. For example... Figure 4 As shown, the time to read from the front buffer is less than the time to write a single frame of data, ensuring that the decoding process is not idle while waiting for data, thereby improving throughput.

[0109] (2)CFG2: Minimum depth of the previous buffer.

[0110] CFG2 is used to control the near-full signal of the previous buffer, thereby managing the data flow. Modifying CFG2 controls the near-full signal of the previous buffer; the formula is:

[0111]

[0112] Where n represents the LDPC code length ， N f This represents the number of consecutive error frames. The above formula ensures that the buffer has sufficient depth to store data from the high-frequency clock domain until it can be processed in the low-frequency clock domain.

[0113] (3)CFG3: Minimum depth of the back buffer.

[0114] CFG3 is used to control the near-full signal of the subsequent buffer and manage the output of decoded data. The formula is as follows:

[0115]

[0116] Where k represents the effective data length of the LDPC code, and w0 represents the output bit width. During the pre-data storage stage, the subsequent buffer needs sufficient depth to store N. f Frame data to avoid data loss.

[0117] (4)CFG4: Maximum number of iterations.

[0118] CFG4 is set to the maximum number of iterations I max This is the maximum number of iterations the decoder will attempt to decode. CFG4 determines the maximum effort the decoder can make when dealing with difficult-to-decode data. Exceeding this number of iterations, the decoder will stop trying and may report a decoding failure.

[0119] In one embodiment, taking the LDPC code scenario used in the PCS (Physical Coding Sublayer) of the 802.3bz standard as an example, its design and configuration process is as follows:

[0120] The user's modeling and simulation results show that the average number of iterations I for the LDPC line-level decoder in this channel is... avg ≤2, maximum number of iterations I max After 20 iterations, there is no significant performance gain. The LDPC code can be divided into at least 6 decoding layers. The PCS operates at a frequency of 200MHz, and the throughput requirement for the LDPC code decoder is to output one frame of data (2048 code length) every 128 CLKs.

[0121] Assume the decoder has I iterations, N parallelism, and an actual operating frequency of f. The original operating frequency is f. o The maximum number of CLKs allowed for processing one frame of data is N. s If the number of layers in LDPC is L, then the following formula can be used to obtain:

[0122]

[0123] Substitute N s =128, f o =200, L=6, then the following design combinations that meet the requirements can be listed (only some are listed).

[0124] Number of iterations … 2 5 5 10 5 10 20 20 20 … Parallelism* … 1 0.5 1 1 1 1 1 0.5 0.5 … Operating frequency … 50 100 100 100 200 200 200 200 400 …

[0125] Since the operating frequency significantly increases chip power consumption, combinations where the actual operating frequency is higher than the original operating frequency are not considered. Assume continuous N... f If the frame data needs to be iterated to the maximum number of iterations, the pre-stored data will be consumed during this period. After consumption, the data will be slowly replenished into the FIFO, a process that takes N iterations. f *I max / II avg The frame time. Because the LDPC decoder can only perform I iterations during the data recovery phase, excessively long recovery times risk degrading decoding performance. Therefore, the data recovery time should not exceed 10 frames. Furthermore, to prevent clustered errors, N f ≥2 (If the channel fluctuation is large, N needs to be increased) f If ), then 10 ≥ N f *I max / II avg ≥2*20 / I-2, we can get I≥6.

[0126] Considering power consumption and area under different configurations, given that P∝I avg Given *f*N, the area A∝N. Although the actual composite area decreases as the operating frequency f decreases, these two factors are not linearly related. Therefore, the adjustable adaptive LDPC decoding resource allocation scheme will prioritize reducing the parallelism N.

[0127]

[0128] Substituting into the formula, we get N*f≥56.25, which gives the following combination: In this scenario, a row-level decoder operating at 120MHz frequency, iterating 6 times, with a parallelism of 1 / 2 can be used, which can handle the peak computation of 20 iterations for 2 consecutive frames.

[0129] Finally, the configuration parameters of the adjustable LDPC decoder architecture need to be calculated based on the above scheme.

[0130] CFG1 determines the data bit width of the preceding FIFO. Since this FIFO transfers data from the high-frequency clock domain to the low-frequency clock domain, the time required to read out one frame must be less than N. s / f o Therefore, the length of the concatenated data here should be greater than f of the length of the high-frequency clock domain input LLR data. o / f times. Taking the above scheme as an example, the length of the concatenated data must be at least twice the length of the original information. Assuming the original information length is 16, the data bit width of the FIFO can be set to 32. CFG2 is the minimum depth of the preceding FIFO; modifying CFG2 can control the near-full signal of the preceding FIFO. Under stress conditions, the preceding FIFO needs to store a maximum of N. f For frame data, assuming the LDPC code length of a single frame is n, then a single frame of LLR data requires n / CFG1 addresses, so CFG2 = N. f *n / CFG1. Substitute N f =2, n=2048, CFG1=32, thus we get CFG2=128.

[0131] CFG3 is the minimum depth of the subsequent FIFO; modifying CFG3 controls the near-full signal of the subsequent FIFO. During the pre-data storage phase, the subsequent FIFO needs to store a maximum of N data. f For frame data, given that the LDPC output bit width k = 65 in the 802.3bz system and the total output data size is 1625 bits, then CFG3 = 1625 * N. f / 65 = 50.

[0132] CFG4 is the maximum number of iterations, set to 20 according to the scenario requirements.

[0133] Furthermore, the LDPC decoder architecture pre-stores the corresponding number of LLR information in the subsequent buffer, and consumes the pre-stored data when the decoder core needs to iterate to the maximum number of iterations.

[0134] like Figures 5a to 5b As shown, based on the decoding resource configuration scheme, a corresponding LDPC decoder configuration signal is generated, and this configuration signal is used to iteratively decode the data to be decoded. The decoding execution process includes the following steps:

[0135] Based on the configuration signal, a corresponding number of data to be decoded are pre-stored. The data to be decoded has been converted into LLR values, and the front-end module of the decoder receives the LLR data.

[0136] Because the LDPC decoder operates at a lower frequency than the preceding module, the data to be decoded needs to pass through a bit-width aggregation module to ensure that the data throughput when reading data in the low-frequency region is greater than or equal to the input data throughput in the high-frequency region. The bit-width aggregation module concatenates LLR data based on the frequency difference and writes it to the buffer when the preceding buffer is not full. The bit-width aggregation module monitors the status of the preceding buffer. When the preceding buffer is not full, the module writes the concatenated LLR data to the buffer. This mechanism ensures that the data stream will not be interrupted by a full buffer before entering the decoding process.

[0137] The LDPC decoder manager is responsible for coordinating read operations from the buffers. It follows specific conditions to control data reading: the manager will only read data from the buffers when the current item buffer is not empty (i.e., there is data to be processed) and the decoder entry buffer is free (i.e., the decoder is ready to receive new data).

[0138] Once a complete frame of LLR data has accumulated in the decoding entry buffer, the decoder will read this data into and transfer it to the iterative LLR buffer during its idle processing cycle. This step is crucial for initiating the decoding process, as the data in the iterative LLR buffer will be used for subsequent decoding iterations.

[0139] Once valid LLR data is loaded into the iterative LLR cache, the decoding processor begins executing the iterative decoding algorithm. This algorithm typically includes updating data nodes, updating check nodes, and exchanging information between nodes. After each iteration, the sign check module checks the sign bit of the LLR data to determine if the decoding result meets the predetermined check rules. If the check passes, the iterative controller stops the iteration; if it fails, the iteration process continues until the maximum number of iterations is reached or a specific stopping condition is met.

[0140] The LDPC decoder processor operates at a lower frequency to reduce decoding power consumption and module design complexity. Through this sophisticated data management and control mechanism, the LDPC decoder can perform decoding tasks efficiently and reliably, while optimizing power consumption and resource utilization.

[0141] Furthermore, the addition of the input / output buffers in this invention is to: enable data splicing and splitting, ensuring that the input and output bit widths of the decoder match the bit widths stored in the preceding and following item buffers (FIFOs). When the decoder is performing stress decoding, a frame of data is stored in the decoder's input buffer, which can be immediately input to the decoder after the output, accelerating the data "recovery" process. Utilizing the input / output buffers reduces the probability of timing conflicts between reading / writing to the preceding and following item buffers and between the decoder's input and output. If a conflict occurs, data may remain in the buffer or decoder, affecting data processing efficiency.

[0142] Furthermore, the decoder processor includes an iterative LLR cache module, a data rearrangement module, data nodes, a check node, an LLR data update module, a symbol check module, and an iterative controller.

[0143] The iterative LLR buffer is a buffer used during LDPC decoding to temporarily store information exchanged between data nodes (VNs) and check nodes (CNs). During each iteration, the LLR (log-likelihood ratio) value is updated and stored in this buffer. The data rearrangement module is responsible for rearranging the input data according to the LDPC code's parity-check matrix structure to facilitate correct information exchange between subsequent data nodes and check nodes. The LLR data update module is responsible for calculating and updating the LLR values ​​of data nodes and check nodes in each iteration. After each row is calculated, the symbol check module reads the sign bit of the LLR value from the iterative buffer. It verifies whether the decoded data meets the check conditions based on the parity-check matrix. The check result is fed back to the iterative controller. The iterative controller receives the symbol check result; if all check equations pass, the iteration process stops. The LDPC decoding manager is notified that the data is ready for output.

[0144] The decoding manager allows LDPC decoding to output decoded data when the decoding output buffer is idle. This data is segmented according to the needs of subsequent modules and written to the subsequent buffer when it is not full. The read control of the subsequent buffer is determined by the subsequent modules. The LDPC decoding manager not only monitors the status of the buffers and input / output buffers to control data flow read / write, but also issues forced wait or forced output commands to the iteration controller if it detects any abnormal status in the input / output buffer FIFOs to prevent data errors or loss. The output data is segmented according to the needs of subsequent modules and written to the subsequent buffer when it is not full.

[0145] Figure 5b The LDPC decoder is divided into high-frequency and low-frequency regions. The front buffer converts data from high frequency to low frequency, while the back buffer converts data from low frequency to high frequency. This design ensures that the most complex decoding module in the LDPC decoder operates at a lower frequency, thus significantly reducing power consumption. Because the signal switching rate and parallelism of the decoding module are extremely high during LDPC decoding, reducing its operating frequency not only helps reduce power consumption but also alleviates design complexity, as lower frequencies simplify the implementation of decoding modules containing a large amount of combinational logic.

[0146] Through the above process, the LDPC decoder can effectively perform error correction and output reliable decoded data. This process requires precise coordination and control to ensure the correct processing and transmission of data during decoding.

[0147] Step S14: The decoding verification result is sent to the decoding manager, and the decoding process is adjusted and iterated based on the current state of the previous buffer, the next buffer, the decoder core input / output buffer, and the decoding processor. Specifically, this includes the following steps:

[0148] The subsequent buffer is initialized and the amount of data is pre-stored to a set value;

[0149] When the amount of data cached by the subsequent buffer reaches a set value, the decoding manager enters a normal management state and obtains the decoded data based on the final decoding verification result;

[0150] When the subsequent buffer consumes the amount of pre-stored data, the decoder enters a stress-resistant state and terminates the iterative processing based on the states of the preceding and subsequent buffers and obtains the corresponding data.

[0151] When the subsequent buffer restores the amount of pre-stored data to the set value, the decoder manager returns to the normal management state.

[0152] like Figure 6 As shown, before reading data from the subsequent buffer, an initialization operation is required: the bit width of the input data is adjusted to the width required for decoding processing to facilitate subsequent processing. During initialization, data is written to the preceding buffer as the input buffer for the decoding processor. Data is transferred from the preceding buffer to the decoding processing entry buffer, ready for LDPC decoding. Data undergoes decoding processing in the LDPC decoding processor. The decoded data is temporarily stored in the decoding processing exit buffer. Data is then transferred from the decoding processing exit buffer to the subsequent buffer, awaiting output.

[0153] The amount of pre-stored data cannot exceed the reception and processing delay specified in the protocol to ensure real-time data processing. The larger the amount of pre-stored data, the more iterations the LDPC decoding process has to attempt decoding when encountering frames in the error set, thus improving the decoding success rate.

[0154] Under normal channel conditions, the decoder manager operates in a routine management state. Once the buffered data reaches a set value, the subsequent buffer FIFO begins outputting according to the throughput required by the subsequent modules. Since the number of iterations required for successful decoding is relatively small under normal channel conditions, this scheme allows users to reduce the operating frequency or the computational parallelism of LDPC decoding to achieve decoding functionality, thereby reducing power consumption and chip area. In this state, the decoder manager reports the verification result after successful symbol verification within the decoding process, and then stops iterating, maintaining a dynamic balance between the amount of data in the preceding and following buffers.

[0155] When encountering frames with a high error set, the decoder manager switches to a stress-response state, requiring the decoder processor to perform more iterations for decoding. In stress-response state, because the decoder processor is continuously iterating and decoding without outputting valid data, the subsequent buffer also receives no data during this period. To maintain output throughput, the subsequent buffer consumes the amount of data pre-stored during the initialization phase. Simultaneously, the decoder processor cannot receive input data from the preceding stage during decoding, so the preceding buffer also caches unprocessed data during this period. The decoder manager continuously monitors the status of both buffers. When the preceding buffer is nearing full, or the subsequent buffer is about to exhaust its pre-stored data, the iteration manager forces the decoder to terminate iteration and output data to prevent buffer overflow / underflow that could lead to physical layer receive link errors or data loss.

[0156] After the decoder exits the stress-recovery state, the buffer enters a recovery phase because the pre-stored data in the subsequent buffer has been consumed. During recovery, the preceding buffer stores data that was not processed during the stress-recovery period. As soon as the decoder finishes its iteration and outputs, the decoder's input buffer immediately outputs LLR data for the decoder, while the preceding buffer can continue to read data. Because the iteration time required for LDPC decoding is low under normal channel conditions, data throughput is high, allowing the pre-stored data in the subsequent buffer to be restored. When the subsequent buffer recovers to its initial data level, the stress-recovery state ends, and the decoder returns to its normal management state.

[0157] Through this precise management and control, the LDPC decoder can effectively cope with different channel conditions, ensuring the correctness of data processing and the stability of the system. At the same time, it can reduce power consumption and chip area by adjusting the operating frequency and computational parallelism.

[0158] The dynamic allocation scheme for LDPC decoding resources proposed in this invention achieves adaptation and optimization to performance requirements in different scenarios through the following key points:

[0159] (1) Adding a two-level cache:

[0160] The two-level buffer is designed to introduce an additional buffer in the data stream, which provides some storage space between data input and output, thereby alleviating the throughput pressure caused by fluctuations in data flow.

[0161] By ensuring that the number of iterations in the buffer exceeds the requirements under normal channel conditions, users can select appropriate LDPC decoding parallelism and operating frequency based on actual hardware area and power consumption constraints. This means that with limited hardware resources, a reduction in parallelism or operating frequency can be compensated for by increasing the number of iterations, and vice versa.

[0162] (2) The monitoring function of the decoder manager:

[0163] The decoder manager ensures smooth data transmission during the decoding process by monitoring the status of the two-level buffers, avoiding data flow interruptions caused by full or empty buffers.

[0164] The decoder manager can identify data frames with more errors and dynamically allocate more decoding resources (such as computing power and memory) to process these frames, thereby improving overall decoding performance and reliability.

[0165] (3) Flexible adjustment of the cache:

[0166] The cache's empty and full thresholds can be flexibly set according to actual data traffic and system requirements to optimize cache utilization and system response speed. The amount of data cached during initialization can be adjusted based on specific user needs to adapt to different working scenarios. The decoder's structure and operating frequency can be adjusted according to user requirements, meaning the solution is suitable for different hardware platforms and performance requirements.

[0167] Through the above design, this invention ensures that the LDPC code decoder can be optimized for use in various Ethernet physical layer chips, achieving an optimal balance in terms of performance, power consumption, and hardware resource utilization. This flexibility and adaptability make this invention widely applicable in various communication scenarios.

[0168] The scope of protection of the LDPC decoder dynamic resource configuration method described in this embodiment is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principle of this invention is included within the scope of protection of this invention.

[0169] This invention also provides a dynamic resource configuration system for an LDPC decoder. The dynamic resource configuration system for an LDPC decoder can implement the dynamic resource configuration method for an LDPC decoder described in this invention. However, the implementation apparatus of the dynamic resource configuration system for an LDPC decoder described in this invention includes, but is not limited to, the structure of the dynamic resource configuration system for an LDPC decoder listed in this embodiment. All structural modifications and substitutions of the prior art made in accordance with the principles of this invention are included within the protection scope of this invention.

[0170] like Figure 7 As shown, in one embodiment, the LDPC decoder dynamic resource configuration chip of the present invention includes a first acquisition module 71, a resource configuration module 72, a decoding processing module 73, a decoding management module 74, and a second acquisition module 75.

[0171] The first acquisition module 71 is used to acquire the user's decoding performance requirements and the data to be decoded;

[0172] The configuration resource module 72 is connected to the first acquisition module 71 and is used to determine the decoding resource configuration scheme of the data to be decoded based on the user's decoding performance requirements.

[0173] The decoding processing module 73 is connected to the configuration resource module 72 and is used to generate a corresponding LDPC decoder configuration signal based on the decoding resource configuration scheme and perform iterative decoding processing on the data to be decoded to obtain the decoding verification result.

[0174] The decoding management module 74 is connected to the decoding processing module 73 and is used to send the decoding verification result to the decoding manager and adjust the iterative decoding process based on the current state of the front buffer, the back buffer, the decoder core input and output buffer, and the decoding processor.

[0175] The second acquisition module 75 is connected to the decoder manager module 74 and is used to acquire and output the decoded data based on the adjusted LDPC decoder.

[0176] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0177] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of the present invention, depending on actual needs. For example, the functional modules / units in the various embodiments of the present invention may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0178] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0179] This invention also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. This available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0180] This invention also provides an electronic device. The electronic device includes a processor and a memory.

[0181] The memory is used to store computer programs.

[0182] The memory includes various media capable of storing program code, such as ROM, RAM, magnetic disk, USB flash drive, memory card, or optical disk.

[0183] The processor is connected to the memory and is used to execute the computer program stored in the memory, so that the electronic device performs the above-described LDPC decoder dynamic resource configuration method.

[0184] Preferably, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0185] like Figure 8 As shown, the electronic device of the present invention is embodied in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: one or more processors or processing units 81, a memory 82, and a bus 83 connecting different system components (including the memory 82 and the processing unit 81).

[0186] Bus 83 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0187] Electronic devices typically include a variety of computer-readable media. These media can be any available media that can be accessed by the electronic device, including volatile and non-volatile media, and removable and non-removable media.

[0188] Memory 82 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 821 and / or cache memory 822. The electronic device may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 823 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 8 Not shown; usually referred to as a "hard drive"). Although Figure 8Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 83 via one or more data media interfaces. Memory 82 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0189] A program / utility 824 having a set (at least one) of program modules 8241 may be stored, for example, in memory 82. Such program modules 8241 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 8241 typically perform the functions and / or methods described in the embodiments of the present invention.

[0190] The electronic device can also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). This communication can be performed through input / output (I / O) interface 84. Furthermore, the electronic device can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 85. Figure 8 As shown, network adapter 85 communicates with other modules of the electronic device via bus 83. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0191] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for dynamic resource allocation in an LDPC decoder, characterized in that, The method includes the following steps: Obtain the user's decoding performance requirements and the data to be decoded; Determine the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements; Based on the decoding resource configuration scheme, a corresponding LDPC decoder configuration signal is generated, and the data to be decoded is iteratively decoded to obtain the decoding verification result. The decoding verification result is sent to the decoding manager, and the iterative decoding process is adjusted based on the current state of the previous buffer, the next buffer, and the decoding processor. The decoded data is obtained and output based on the adjusted LDPC decoder.

2. The dynamic resource allocation method for LDPC decoders according to claim 1, characterized in that: Determining the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements includes the following steps: Based on the user's decoding performance requirements, the parameter configuration set for the number of iterations, parallelism, and operating frequency corresponding to the data to be decoded is determined through simulation; The parameter configuration sets are verified and evaluated respectively, and the group with the best decoding performance is selected as the parameter configuration of the LDPC decoder.

3. The dynamic resource allocation method for LDPC decoders according to claim 2, characterized in that: Based on the user's decoding performance requirements, the set of iteration count, parallelism, and operating frequency corresponding to the data to be decoded is determined using the following formula: Where I represents the number of iterations of the LDPC decoder under the current channel, L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern, N represents the parallelism of the LDPC decoder, and f represents the operating frequency of the LDPC decoder. s f0 indicates the maximum number of clock cycles required for the LDPC decoder to decode one frame of data; f0 represents the external operating frequency of the LDPC decoder.

4. The dynamic resource allocation method for LDPC decoders according to claim 3, characterized in that: The parallelism N is calculated using the following formula: Where, N f N represents the number of consecutive error frames. rec Indicates the number of frames recovered; L represents the number of layers in the parity-check matrix corresponding to the LDPC decoder code pattern; N s Indicates the throughput of the LDPC decoder; I avg Indicates the average number of iterations; I max This indicates the maximum number of iterations.

5. The dynamic resource allocation method for LDPC decoders according to claim 1, characterized in that: Based on the decoding resource configuration scheme, a corresponding LDPC decoder configuration signal is generated, and the data to be decoded is iteratively decoded to obtain the decoding verification result, including the following steps: The parameters of the LDPC decoder are set based on the configuration signal; The data to be decoded is preprocessed, and the preprocessed data to be decoded is cached in the front buffer and the decoding processing entry buffer. The data to be decoded is cached in the iterative LLR cache, and the data to be decoded is subjected to the first data processing to obtain the processed first data to be decoded; Based on the data node information and verification node information of the first data to be decoded, update the data value of the first data to be decoded; The updated first data to be decoded is subjected to second data processing to obtain the processed second data to be decoded and cached in the iterative LLR cache; The sign bit of the second data to be decoded is read and it is determined whether the second data to be decoded meets the verification condition. The decoding verification result is obtained and sent to the iterative controller.

6. The dynamic resource allocation method for LDPC decoders according to claim 1, characterized in that: The decoding verification result is sent to the decoding manager, and the iterative decoding process is adjusted based on the current state of the previous buffer, the next buffer, and the decoding processor, including the following steps: The subsequent buffer is initialized and the amount of data is pre-stored to a set value; When the amount of data cached by the subsequent buffer reaches a set value, the decoding manager enters a normal management state and obtains the decoded data based on the final decoding verification result; When the subsequent buffer starts consuming the pre-stored data, the decoder enters a stress-resistant state and terminates the iterative processing based on the states of the preceding and subsequent buffers and obtains the corresponding data. When the downstream buffer consumes all the pre-stored data, the decoder enters a recovery state until the downstream buffer restores the pre-stored data to a set value, at which point the decoder returns to the normal management state.

7. The dynamic resource allocation method for LDPC decoders according to claim 5, characterized in that: Preprocessing the data to be decoded and caching the preprocessed data to be decoded into the preceding buffer and the decoding entry buffer respectively includes the following steps: The data to be decoded is received and spliced ​​together according to the internal and external frequency differences, then buffered into the previous buffer. After the forward buffer down-clocks the data to be decoded, it caches it in the decoding processing entry cache, waiting for the decoding processor to read it.

8. A dynamic resource allocation chip for an LDPC decoder, characterized in that, The chip includes a first acquisition module, a configuration resource module, a decoding processing module, a decoding management module, and a second acquisition module; The first acquisition module is used to acquire the user's decoding performance requirements and the data to be decoded; The configuration resource module is used to determine the decoding resource configuration scheme for the data to be decoded based on the user's decoding performance requirements. The decoding processing module is used to generate a corresponding LDPC decoder configuration signal based on the decoding resource configuration scheme and perform iterative decoding processing on the data to be decoded to obtain the decoding verification result; The decoding management module is used to send the decoding verification result to the decoding manager, and adjust the iterative decoding process based on the current state of the previous buffer, the next buffer, and the decoding processor. The second acquisition module is used to acquire and output the decoded data based on the adjusted LDPC decoder.

9. An electronic device, characterized in that, The electronic device includes: a processor and a memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory to cause the electronic device to perform the LDPC decoder dynamic resource configuration method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by an electronic device, the program implements the LDPC decoder dynamic resource allocation method as described in any one of claims 1 to 7.

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