A low-complexity high-speed LDPC decoder for 5G standards and a control method thereof

Abstract

The application discloses a low-complexity high-speed LDPC decoder facing 5G standards, comprising an input quantization and preprocessing module, a rate recovery module, a parallel conversion module, a core decoding processing module, a parallel recovery module and a code block splicing and CRC checking module, wherein the input quantization and preprocessing module receives soft information from a channel and outputs fixed-point and blocked initial data; the rate recovery module performs deinterleaving and bit recovery operations on the blocked initial data and outputs data after rate recovery; the parallel conversion module dynamically adjusts parallel paths and outputs continuous data streams; the core decoding processing module performs iterative decoding through variable node updating, cyclic shift and check node updating; the parallel recovery module converts data back to decoding completed data in a fixed parallel format; and the code block splicing and CRC checking module outputs final decoding data. The application enables the LDPC decoder to achieve higher throughput at low complexity and has the effects of low power consumption and flexibility.

Description

Technical Field

[0001] This invention belongs to the field of satellite communication technology, specifically relating to a low-complexity, high-speed LDPC decoder for 5G standards and its control method. Background Technology

[0002] Low-Density Parity-Check (LDPC) codes, as a high-performance error correction coding technique approaching the Shannon limit, possess excellent decoding performance, low error level, and strong parallel decoding capability, and have been widely used in wireless communication, satellite communication, data storage, and other fields. In the fifth-generation mobile communication (5G) standard, LDPC codes have been officially adopted as the coding scheme for data channels in enhanced mobile broadband (eMBB) scenarios. They offer advantages such as high throughput, low latency, and high reliability, supporting the ultra-high speed and ultra-high reliability requirements of 5G systems.

[0003] However, LDPC codes in 5G standards typically employ quasi-cyclic structures, supporting various code lengths and rates. Their decoding process is usually based on soft-decision iterative algorithms, such as the Normalized Min-Sum Algorithm (NMSA) or the Offset Min-Sum Algorithm (OMSA). In actual hardware implementations, each iteration requires numerous message updates and storage operations between variable nodes and check nodes, resulting in significant computational complexity and storage overhead. Especially when supporting high-speed data transmission, traditional decoding structures often face issues such as timing constraints, high resource consumption, and high power consumption, making it difficult to achieve high-speed decoding while maintaining low complexity. Therefore, in 5G communication equipment, especially terminals and base stations, designing a low-complexity, high-throughput, and resource-efficient LDPC decoder has become a key issue in improving overall system performance and energy efficiency, and a significant challenge in current 5G communication chip design and implementation. Summary of the Invention

[0004] To address the aforementioned problems in existing technologies, this invention provides a low-complexity, high-speed LDPC decoder and its control method for 5G standards. The technical problem to be solved by this invention is achieved through the following technical solution: One aspect of the present invention provides a low-complexity, high-speed LDPC decoder for 5G standards, comprising an input quantization and preprocessing module, a rate recovery module, a parallel conversion module, a core decoding processing module, a parallel recovery module, and a code block concatenation and CRC check module, wherein... The input quantization and preprocessing module is used to receive soft information from the channel, perform dynamic range quantization, compression and code block segmentation on it, and output fixed-point and block-based initial data. The rate recovery module is used to receive the initial data after it is segmented, and to perform deinterleaving and bit recovery operations on it. The data order is rearranged according to the 5G standard and its length is restored. The data after rate recovery is then output. The parallel conversion module is used to dynamically adjust the number of parallel paths according to the expansion factor required by the current decoding task, reassemble and interleave the data after the rate is restored, and output the reassembled and interleaved continuous data stream as the original variable node information. The core decoding processing module is used to receive the continuous data stream after recombination and interleaving, perform iterative decoding through variable node updates, cyclic shifts and check node updates, and output the parallel data after hard decision of updated variable node information, posterior probability information and hard decision. The parallel recovery module is used to convert the parallel data back into decoded data in a fixed parallel format; The code block concatenation and CRC check module is used to receive the decoding completion data in the fixed parallel format, sequentially concatenate the decoding results of each code block, perform cyclic redundancy check, and output the final decoded data and check status.

[0005] Another aspect of the present invention provides a control method for a low-complexity, high-speed LDPC decoder for 5G standards, executed using the low-complexity, high-speed LDPC decoder for 5G standards, the method comprising: S1: Receive soft information from the channel, perform dynamic range quantization, compression and code block segmentation on it, and output fixed-point and block-based initial data; S2: Receive the initial data after it is divided into blocks, and perform deinterleaving and bit recovery operations on it. Rearrange the data order according to the 5G standard and restore its length. Output the data after the rate is restored. S3: Dynamically adjust the number of parallel paths according to the expansion factor required by the current decoding task, reassemble and interleave the data after the rate recovery, and output the reassembled and interleaved continuous data stream as the original variable node information; S4: Receive the continuous data stream after recombination and interleaving, perform iterative decoding through variable node update, cyclic shift and check node update, and output the updated variable node information and the decoded parallel data; S5: Convert the decoded parallel data back into decoded data in a fixed parallel format; S6: Receive the decoded data in the fixed parallel format, perform hard decision-making and sequential concatenation on the decoding results of each code block, perform cyclic redundancy check, and output the final decoded data and check status.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The LDPC decoder provided by this invention significantly reduces the amount of arithmetic operations and logic gate resources required for each iteration through an optimized normalized minimum sum algorithm and a simplified merging strategy for variable nodes. In particular, it reduces the complexity and latency of the critical path of check node updates and increases decoding performance.

[0007] 2. The LDPC decoder provided by this invention adopts multi-frame interleaving processing. By optimizing the time utilization of the information update of the check node and variable node, it realizes parallel processing of multi-frame data. With only an increase in information storage resources and a small amount of control logic resources, and without an increase in computing resources, it achieves a significant improvement in decoder throughput with lower resource overhead.

[0008] 3. The LDPC decoder provided by this invention adopts an optimized partial expansion factor Zc parallel decoding architecture. This architecture reduces the power consumption loss in the small Zc mode by reducing the maximum number of parallel paths. At the same time, the data can still correspond to the 5G LDPC standard matrix by reducing the parallelism through interleaving. No additional address lookup resource logic is required, which reduces the power consumption of the entire system.

[0009] 4. The LDPC decoder provided by this invention adopts an efficient storage scheme, specifically covering the following aspects: It employs an integrated storage design, merging hard decision results and variable nodes in the same storage unit, thereby reducing storage overhead and saving counter resources; it implements a storage optimization method for the smallest block RAM, adapting the block RAM bit width to make it as close as possible to or equal to the maximum bit width supported by the smallest block RAM or an integer multiple thereof, thereby improving the efficiency of storage resource utilization; furthermore, in FPGA implementations, if block RAM resources are scarce or utilization is low, the external information storage module of the verification node can use distributed RAM to store hard decision information.

[0010] 5. The LDPC decoder provided by this invention adopts a sophisticated 5G standard control method. The overall architecture is optimized for the structural characteristics of 5G standard LDPC codes, with regularized memory addressing and high reusability of processing units. When implemented in FPGA or ASIC, it can achieve a given throughput index with less logic and storage resources, reducing chip cost and area.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the implementation of a low-complexity, high-speed LDPC decoder for 5G standards provided in an embodiment of the present invention. Figure 2This is a schematic diagram illustrating the structure and connection relationship of an input quantization and preprocessing module, a rate recovery module, and a parallel conversion module provided in an embodiment of the present invention. Figure 3 This is a block diagram illustrating the implementation of a 5G-compliant rate matching structure provided in an embodiment of the present invention. Figure 4 This is a matrix transformation principle diagram of an optimized parallel decoding architecture provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the structure and connection relationship of a core decoding processing module, a parallel recovery module, and a code block splicing and CRC verification module provided in an embodiment of the present invention. Figure 6 This is a timing diagram of an improved QSN shift network provided in an embodiment of the present invention; Figure 7 This is an implementation block diagram of a core decoding processing module provided in an embodiment of the present invention. Detailed Implementation

[0013] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a low-complexity high-speed LDPC decoder and its control method for 5G standards proposed according to the present invention.

[0014] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0016] Example 1 Please see Figure 1 , Figure 1This is a block diagram of a low-complexity, high-speed LDPC decoder for 5G standards provided in this embodiment of the invention. The LDPC decoder includes an input quantization and preprocessing module 101, a rate recovery module 102, a parallel conversion module 103, a core decoding processing module 104, a parallel recovery module 105, and a code block concatenation and CRC check module 106. The input quantization and preprocessing module 101 receives soft information from the channel, performs dynamic range quantization, compression, and code block segmentation on it, and outputs fixed-point and segmented initial data. The rate recovery module 102 receives the segmented initial data, performs deinterleaving and bit recovery operations on it, rearranges the data order according to the 5G standard, restores its length, and outputs rate-recovered data. The parallel conversion module 103 is used to adjust the spread factor required by the current decoding task. The system dynamically adjusts the number of parallel paths, reassembles and interleaves the data after rate recovery, and outputs the reassembled and interleaved continuous data stream as the original variable node information. The core decoding processing module 104 receives the reassembled and interleaved continuous data stream, performs iterative decoding through variable node updates, cyclic shifts, and check node updates, and outputs the parallel data after hard decision based on the updated variable node posterior probability information. The parallel recovery module 105 converts the decoded parallel data back into decoded data in a fixed parallel format. The code block splicing and CRC check module 106 receives decoded data in a fixed parallel format, sequentially splices the decoding results of each code block, performs cyclic redundancy check, and outputs the final decoded data and check status.

[0017] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating the structure and connection relationship of an input quantization and preprocessing module, a rate recovery module, and a parallel conversion module provided in an embodiment of the present invention. The input quantization and preprocessing module 101 of this embodiment includes a fixed-point quantization unit, a dynamic range adjustment unit, and a code block segmentation unit. The fixed-point quantization unit receives soft-bit information from the channel demodulator and quantizes the soft-bit information into a signed integer of a preset number of bits to obtain quantized soft-bit information, which is multi-bit LLR (log-likelihood ratio) data. The dynamic range adjustment unit scales the quantized soft-bit information as a whole according to external channel state information to optimize the decoder input dynamic range under different channel conditions. The code block segmentation unit segments the dynamically adjusted soft-bit information into independent LLR data code blocks according to the code block parameters of the 5G LDPC standard through FIFO buffering and counter control.

[0018] Specifically, the fixed-point quantization unit receives multi-bit LLR data from the channel demodulator and quantizes this LLR data into a signed integer of a preset number of bits to obtain quantized LLR data. In this embodiment, the input LLR data is an 8-bit signed integer. The fixed-point quantization unit employs a truncation and saturation processing strategy to quantize it into a 6-bit signed integer. Specifically, the lower 5 significant bits are retained, and when the input value exceeds the range [-32, +31], it is saturated to the boundary value. This design significantly reduces the data bit width and storage overhead of all subsequent processing modules while ensuring controllable decoding performance loss (<0.1 dB).

[0019] Subsequently, the dynamic range adjustment unit, based on external channel state information (signal-to-noise ratio (SNR) estimate), performs overall scaling on the quantized LLR data using a simple 2-bit shifter to optimize the decoder input dynamic range under different channel conditions. The dynamic range referred to here is the span between the maximum and minimum values ​​of the LLR data. A 2-bit shifter is a commonly used simple scaling module in hardware, performing arithmetic shifts to achieve powers of 2 (left shift = amplification, right shift = reduction). Specifically, the dynamic range adjustment unit selects the shift direction and number of bits (0, 1, or 2 bits) based on the SNR estimate, performing an overall arithmetic shift on the 6-bit LLR data (preserving the sign bit and adjusting only the numerical bits) to achieve overall scaling of the dynamic range. The adjusted LLR data remains a 6-bit signed integer.

[0020] Next, the code block segmentation unit divides the dynamically adjusted LLR data into independent LLR data code blocks according to the code block parameters of the 5G LDPC standard through FIFO buffering and counter control. It should be noted that in a 5G NR (New Radio) system, the Transport Block (TB) is the basic data unit for physical layer transmission. While LDPC encoding performs better with longer codes, when the TB is too large (e.g., exceeding the maximum code block length), the TB needs to be divided into multiple code blocks (CBs). Each code block undergoes independent LDPC encoding (basemap selection, parity bit addition), and then is cascaded for transmission after rate matching. In this embodiment, the dynamically adjusted LLR data is stored in a FIFO (First-In-First-Out) buffer, and then the dynamically adjusted LLR is segmented into code blocks according to the number of code blocks and the code block length in the 5G LDPC standard using a counter. The LLR data code blocks are then read from the FIFO buffer. It should be noted that all LLR data code blocks are read sequentially, and the data in each LLR data code block is read out over multiple clock cycles.

[0021] Furthermore, the rate recovery module 102 is a key data path adapter connecting preprocessing and core decoding. It is designed for the rate matching scheme specific to LDPC codes in the 5G NR standard. In this embodiment, the rate recovery module 102 includes a deinterleaving unit and a bit recovery unit. The deinterleaving unit is used to configure the 5G LDPC code parameters (i.e., modulation order) according to the current decoding task. The corresponding deinterleaving address mapping rule is determined, and read and write address control signals are generated in real time according to the deinterleaving address mapping rule. The input LLR data code blocks are scheduled and output to the bit recovery unit according to the parallelism and data arrangement order required by the decoder.

[0022] like Figure 2 As shown, the deinterleaving unit includes buffer registers REG1, REG2, REG3, RAM1, RAM2, RAM3, and a multiplexer MUX1. The inputs of buffer registers REG1, REG2, and REG3 are all connected to the output of the input quantization and preprocessing module 101. The output of buffer register REG1 is connected to the input of RAM1, the output of buffer register REG2 is connected to the input of RAM2, and the output of buffer register REG3 is connected to the input of RAM3. The outputs of buffer registers REG1, REG2, and REG3 are all connected to the multiplexer MUX1. Buffer registers REG1, REG2, and REG3 are all 144 bits, and RAM1, RAM2, and RAM3 have a depth of 1024 and a width of 144.

[0023] Specifically, to achieve high-speed continuous processing of the data stream, a 144-bit sliding window register structure is used in the design. For example, such as Figure 3 As shown, this structure concatenates 72 bits of data from two consecutive clock cycles: at each clock edge, the register performs a shift operation, temporarily storing the data from the previous moment in the lower 72 bits. The entire data is shifted left to the high 72 bits, while the 72 bits of new data input at the current moment are simultaneously... The lower 72 bits are written in parallel, as shown in the diagram: bits 71-66 are written to the higher bits, bits 59-54 are written to the next higher bits, and so on. The specific operation of the entire system is as follows: if the modulation order configured for the current decoding task... Data from the input quantization and preprocessing module 101 does not require deinterleaving and is directly output to the bit recovery unit; if the modulation order... The data from two different clocks from the input quantization and preprocessing module 101 are processed according to... Figure 3The data is concatenated and cached in REG1, then written together into RAM1. When reading, a multiplexer MUX1 is used to first read the data from all addresses sequentially, taking the first 36 bits, then reading the data from all addresses sequentially, taking the last 36 bits. If... The data from the four clocks of the input quantization and preprocessing module 101 are first processed according to... Figure 3 The data is concatenated and cached in REG1 and REG2, then written to RAM1 and RAM2 respectively. When reading, MUX1 is used to first read the data from all addresses in RAM1 sequentially, taking the first 36 bits; then read the data from all addresses in RAM1 sequentially, taking the last 36 bits; then read the data from all addresses in RAM2 sequentially, taking the first 36 bits; finally, read the data from all addresses in RAM2 sequentially, taking the last 36 bits. If... The data from the six clocks in the input quantization and preprocessing module 101 are first processed according to... Figure 3 The data is concatenated and cached into REG1, REG2, and REG3, and then written into RAM1, RAM2, and RAM3 respectively. When reading, MUX1 is used to first read the data of all addresses in RAM1 in sequence and take the first 36 bits, then read the data of all addresses in RAM1 in sequence and take the last 36 bits, then read the data of all addresses in RAM2 in sequence and take the first 36 bits, then read the data of all addresses in RAM3 in sequence and take the last 36 bits, then read the data of all addresses in RAM3 in sequence and take the first 36 bits, and finally read the data of all addresses in RAM3 in sequence and take the last 36 bits.

[0024] Furthermore, the bit recovery unit is used to determine the corresponding bit recovery data length and address according to the 5G LDPC code parameters configured in the current decoding task, and to generate read / write control signals in real time according to the bit recovery data length to store the data input to the bit recovery unit into the corresponding address according to the read / write control signals. Subsequent data exceeding the bit recovery data length is cyclically superimposed onto the stored original data from the beginning. Then, according to the deinterleaving address mapping rules, a read control signal is generated to insert all zero values ​​or positive maximum values ​​into specific positions of the data input to the bit recovery unit, and then output to the parallel conversion module 103.

[0025] Specifically, the bit recovery unit in this embodiment includes a RAM (depth 2112, width 108). Data input to the bit recovery unit is expanded by 3 bits (to prevent addition overflow) and directly stored in the RAM. The length of data stored in the RAM is counted by a counting controller. If the RAM address is about to reach the encoder's set encoding length (three clock cycles in advance) before the input enable ends, data in the RAM is output starting from address zero. The data output from the RAM is added to the current data input of the bit recovery unit and stored in the address where RAM data has been removed, achieving signal superposition. After all data from the deinterleaving unit is stored in the RAM, data is read from address zero, and the length of the read data is counted by the counting controller. When the puncture position set by the 5G LDPC standard is reached, the reading is paused, and the output is set to the maximum positive value. Reading continues until the puncture length is output, and then reading from the RAM continues until all data is read. The read data is then transmitted to the parallel conversion module 103.

[0026] Traditional 5G-LDPC decoders typically fix the maximum internal parallelism at 384 to support all possible scaling factors. However, this design leads to high hardware resource consumption, timing constraints, and limitations in the expansion factor of the 5G-LDPC decoder. Resource utilization is low when the scaling factor is small. Therefore, this embodiment proposes an optimized partially parallel decoding architecture, based on the scaling factor. Numerical dynamic adjustment parallel strategy: when the expansion factor When it is greater than 192, use Due to the evenness of all values, the parity-check matrix of the 5G-LDPC decoder is split and transformed, reducing the decoding parallelism to a certain level. ;when If the value is no more than 192, the matrix remains unchanged, and the parallelism remains the same. .

[0027] Furthermore, in In this case, the original single-level operation can be decomposed into two levels, denoted as follows: and The matrix partitioning method is determined by Figure 4 As shown, the original submatrix is ​​of size The standard cyclic shift matrix is ​​obtained by interleaving the row and column indices (odd-even interleaving). First, a column transformation is performed, placing odd-numbered columns first and even-numbered columns second; then a row transformation is performed, placing odd-numbered rows first and even-numbered rows third. The original matrix is ​​then mapped to... Block matrix structure. It can be observed that each sub-block after decomposition is... A small cyclic shift matrix or an all-zero matrix. Let... The index of the non-zero column in the original parity check matrix. Given the shift values ​​of the non-zero columns of the original parity-check matrix, we can obtain... Layered non-zero column index With cyclic shift coefficient This is obtained from the following relationship:

[0028]

[0029] Layered non-zero column index With cyclic shift coefficient This is obtained from the following relationship:

[0030]

[0031] Furthermore, such as Figure 2 As shown, the parallel conversion module 103 of this embodiment includes shift register 1, shift register 2, FIFO1, FIFO2, and multiplexer MUX2. The inputs of shift register 1 and shift register 2 are connected to the output of the bit recovery unit, the output of shift register 1 is connected to the input of FIFO1, the output of shift register 2 is connected to the input of FIFO2, and the outputs of FIFO1 and FIFO2 are connected to the input of multiplexer MUX2. The output of multiplexer MUX2 serves as the output of parallel conversion module 103. FIFO1 and FIFO2 have a depth of 256 and a width of 1152.

[0032] Specifically, when the expansion factor When the data input to the parallel conversion module 103 is shifted and stored in shift register 1, the length of the data stored in shift register 1 is greater than the input length of the parallel conversion module 103. When using bits, the most significant bit is taken from the valid data. The data of bit is stored in FIFO1; when At that time, the data input to the parallel conversion module 103 is interleaved and shifted into shift register 1 and shift register 2, and the length of the data stored in shift register 1 and shift register 2 is greater than 1 / 2. When the bit is used, the most significant bits are taken from the valid data in both shift registers. The bit data is stored in FIFO1 and FIFO2 respectively. After all the data is stored in the FIFO, the multiplexer MUX2 is used to start reading the data in the FIFO for output, and transmits it as the original variable node information to the core decoding processing module 104.

[0033] Further, please see Figure 5 , Figure 5 This is a schematic diagram illustrating the structure and connection relationship of a core decoding processing module, a parallel recovery module, and a code block splicing and CRC check module provided in an embodiment of the present invention. The core decoding processing module 104 in this embodiment includes a decoding control unit, a variable node processing unit, a cyclic shift unit, a check node update unit, and an iterative early stop unit. The variable node processing unit includes a multiplexer MUX3 and a variable node memory VN RAM. One input of the multiplexer MUX3 is connected to the output of the parallel conversion module 103, and the output of the multiplexer MUX3 is connected to the variable node memory VN RAM. The variable node processing unit is used to select either the original variable node information from the parallel conversion module 103 or the updated variable node information from the check node update unit using the enable signal of the multiplexer MUX3 and store it in the variable node memory VN RAM. Then, according to the read / write control signal issued by the decoding control unit, it reads and outputs data from the corresponding address in the variable node memory VN RAM. The cyclic shift unit is used to control the shift parameters of the variable node memory VN RAM according to the shift parameters of the decoding control unit. The RAM data is cyclically shifted, and the cyclic shift result is output. The verification node update unit uses the cyclic shift result and a dynamic normalized minimum sum algorithm to modulate the normalization parameter through the number of iterations to update the variable node information. The iteration early stop module checks whether the hard decision information of the posterior probability information of the updated variable node satisfies the verification equation. If it does, the iteration is terminated early, and the hard decision information is used as the output of the core decoding processing module to the parallel recovery module. If it does not satisfy the equation, the updated variable node information is transmitted to the multiplexer MUX3 to continue the iteration.

[0034] Furthermore, the verification node update unit in this embodiment includes a verification node memory (V2C RAM), an information memory (C2V RAM), and a verification node update processing subunit. The information memory (C2V RAM) sets all values ​​to zero upon reset. It reads the corresponding C2V information via a read / write address control signal sent by the decoding control unit, subtracts it from the input variable information (i.e., the cyclic shift result) from the cyclic shift unit to obtain V2C information, and stores the updated C2V information into the corresponding address of the information memory (C2V RAM) according to the control signal sent by the decoding unit after the verification node update processing subunit completes the update. Here, C2V information is the information passed from the verification node to the variable node, and V2C information is the information passed from the variable node to the verification node. When obtaining V2C information through subtraction, the verification node memory (V2C RAM) stores the V2C information into the verification node memory (V2C RAM) via a write control signal sent by the decoding unit. After the check node update processing subunit completes the update, the V2C information at the corresponding address in the RAM is read out according to the read control signal sent by the control decoding unit. The check node update processing subunit is used to split the 192 V2C information obtained by subtraction into 16 groups, each with 12 V2C information. The absolute value and sign bit are taken respectively, and the minimum and second smallest absolute values ​​are compared. The position corresponding to the minimum value is recorded. The extracted sign bit is stored in the internal register and the product of the sign bits is calculated. After the calculation is completed, the product of the minimum or second smallest absolute value and the sign bit is determined according to the position corresponding to the minimum absolute value. This product is used as the updated C2V information and then added to the V2C information read from the check node memory V2C RAM to obtain the updated variable node information and transmit it to the multiplexer MUX3.

[0035] The decoding control unit is used to control the read and write operations of the variable node memory VN RAM, the check node memory V2C RAM, the information memory C2V RAM, and the parameter control of the cyclic shift unit 43.

[0036] Specifically, for the read / write control of the variable node memory (VN RAM), when the LDPC decoder has idle time and there are undecoded code blocks in the VN RAM, data should be read from the VN RAM in a timely manner. It should be ensured that all variable node information in the corresponding non-zero column of the parity check matrix is ​​read continuously each time, while ensuring that the updated data value of the read variable node in the previous iteration has been stored in the VN RAM to avoid using outdated values. When the parity check node update unit completes the update, the posterior probability information of the newly generated variable node needs to be stored in the VN RAM. For the read / write control of the parity check node memory (V2C RAM), it should be ensured that the parity check node information is stored in the V2C RAM in a timely manner when it is generated, and the read time should be calculated to ensure that the read parity check node information and the updated parity check node to variable node transmission information (C2V information) are synchronized in one clock cycle. For the read / write control of the information storage C2V RAM passed from the verification node to the variable node, it is necessary to ensure that the output data of C2V RAM is aligned with the clock of the variable node information shift output data when reading data, and the corresponding address in C2V RAM is stored in time when C2V information is updated. For the parameter control of the cyclic shift unit 43, it is necessary to ensure that the shift parameters after matrix splitting are used according to the matrix splitting method shown in the parallel conversion module 103, and to ensure that they are aligned with the clock of the output data of the variable node storage VN RAM to ensure correct shifting. At the same time, the relative shift value after the previous shift of the corresponding node must be calculated for the shift operation.

[0037] Furthermore, the cyclic shift unit is used to cyclically shift data from the variable node memory (VN RAM) according to the shift parameter control signal of the decoding control unit, including three processes: left shift, right shift, and XOR, and then output. It should be noted that when the classic quasi-cyclic LDPC code cyclic network (QSN) is implemented in hardware, for a shift value of up to 192, eight pipeline stages are required, along with 16 registers to store the data shifted left and right in each pipeline stage. This results in significant resource overhead, and the eight-stage pipeline greatly reduces the decoding throughput of the iterative decoding system. Therefore, this invention simplifies the pipeline to a three-stage pipeline based on the QSN. Please refer to [link to relevant documentation]. Figure 6 , Figure 6This is a timing diagram of an improved QSN shift network provided in an embodiment of the present invention. The processing flow begins with the high-level activation of the input enable signal i_en. This enable signal i_en is controlled by the core controller, indicating that the input data in the current clock cycle is valid. iv_data represents the VN node information vector from the VN RAM, serving as the main body to be shifted. iv_lsft / iv_rsft are the displacement control values ​​for left shift (forward alignment) and right shift (backward recovery), respectively, issued by the controller and directly determining the configuration strategy of the shift network.

[0038] The diagram shows the intermediate signals with a stepped change: First-stage coarse-grained shift (reglsft128_64): In the first cycle of the pipeline, the logic circuit performs a large-span data shift of 128 bits or 64 bits based on the highest bit segment of the control word. Second-stage medium-grained shift (reglsft32_8): In the second cycle, based on the result of the previous stage, it performs intermediate-span adjustments of 32 bits, 16 bits, or 8 bits. Third-stage fine-grained shift (reglsft4_1): In the third cycle, it performs fine alignment of 4 bits, 2 bits, and 1 bit. `reglsft` corresponds to left shift, and `reglsft` corresponds to right shift. After both are completed, the left and right results are XORed, and the completed data is output through the `ov_data` port, while the output enable signal `o_en` is pulled high.

[0039] For example, during a left shift, the first-stage pipeline determines the high two bits of the shift parameter, shifting 192 / 128 / 64 / 0 bits of data according to different values; the second-stage pipeline determines the middle three bits of the shift parameter, shifting 56 / 48 / 32 / 24 / 16 / 8 / 0 bits of data according to different values; and the third-stage pipeline determines the last three bits of the shift parameter, shifting 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0 bits of data according to different values. The right shift follows the same principle. After both left and right shifts are completed, the results are XORed together to obtain the final cyclic shift result.

[0040] As described above, the check node update processing subunit is used to split the 192 V2C information obtained by subtraction into 16 groups, with 12 V2C information in each group. The absolute value and sign bit are taken for each group, and the minimum and second smallest absolute values ​​are compared, recording the position corresponding to the minimum value. The extracted sign bit is stored in an internal register, and the product of the sign bits is calculated. After calculation, based on the position corresponding to the minimum absolute value, the product of the minimum or second smallest absolute value and the sign bit is output as the updated C2V information. This updated C2V information is then added to the V2C information read from the check node memory V2C RAM to obtain the updated variable node information, which is then transmitted to the multiplexer MUX3. Specifically... Figure 7As shown, its core lies in adopting a dynamic normalized minimum sum algorithm, which modulates the normalization parameter by the number of iterations, and optimizes the traditional minimum value operation into a hybrid logic of comparison tree and bit operation, and updates the variable node information to pass it to the subsequent modules.

[0041] Specifically, when using the Layered Normalized Min-Sum (LNMS) algorithm for LDPC decoding, traditional algorithms use a fixed normalization factor to correct the overestimation problem of the Min-Sum algorithm. However, in the early stages of decoding, the information reliability is low, and a more conservative (i.e., smaller) normalization factor may be needed to prevent error propagation. In the later stages of decoding, the information gradually becomes more reliable, and using a larger factor can accelerate convergence. Considering both performance and complexity, this invention adopts a two-stage LNMS algorithm: when the number of iterations is less than four, the normalization factor is set to 0.625; when the number of iterations is greater than or equal to four, the normalization factor is set to 0.75. Therefore, for each check node... and all variable nodes connected to it The verification node is passed to the variable node. External information Represented as:

[0042]

[0043] in, Indicates from variable node n Passed to the verification node m Current confidence information, Indicates all nodes related to the verification node A set of connected variable nodes. Represents a set Exclude the current variable node The set after, This indicates the current iteration number.

[0044] Furthermore, the early stopping module in this embodiment is used to check whether the hard decision information of the posterior probability information of the variable node (this information is hard decision data obtained by taking only 1 bit of the sign bit of the updated VN node information) satisfies the verification equation. If it does, the iteration is terminated early. Specifically, the updated variable node information is multiplied by the verification matrix. If the result is all zeros, the verification passes; otherwise, it fails. When the verification passes or the maximum number of iterations is reached, the hard decision information is output by the core decoding processing module to the parallel recovery module.

[0045] In this embodiment, the parallel recovery module 105 corresponds to the parallel conversion module 103, such as... Figure 2 As shown, the parallel recovery module 105 includes a shift register 3 and a FIFO 3. When the input data from the core decoding processing module 104 is stored in shift register 3, and as long as the valid data in shift register 3 is greater than 12 bits, the high 12 bits of the valid data are stored in FIFO 3; when At this time, two consecutive input data are interleaved and stored in shift register 3. As long as the valid data in shift register 3 is greater than 12 bits, the high 12 bits of the valid data are stored in FIFO. After all input data is stored in FIFO3, data is read from FIFO3 and passed to the code block concatenation and CRC check module 106.

[0046] Furthermore, the code block concatenation and CRC check module 106 is used to perform CRC check on the information output after decoding iteration (i.e. the information output by the parallel recovery module 105) according to the 5G LDPC design CB CRC (Code Block Cyclic Redundancy Check) polynomial, and then concatenate the corresponding code blocks output continuously according to their length, and perform CRC check on the concatenated information according to the TB CRC (Transport Block) polynomial and output it.

[0047] In summary, the LDPC decoder provided by this invention significantly reduces the arithmetic operations and logic gate resources required for each iteration through an optimized normalized minimum sum algorithm and a simplified merging strategy for variable nodes. In particular, it reduces the complexity and latency of the critical path of check node updates and increases decoding performance. This invention employs multi-frame interleaving processing, optimizing the time utilization of check node and variable node information updates to achieve parallel processing of multi-frame data. With only an increase in information storage resources and a small amount of control logic resources, and without increasing computational resources, it achieves a significant increase in decoder throughput with lower resource overhead. This invention adopts an optimized partial expansion factor Zc parallel decoding architecture. This architecture reduces the power consumption loss in small Zc mode by reducing the maximum number of parallel paths. Simultaneously, the data is deparallelized through interleaving, allowing it to still correspond to the 5G LDPC standard matrix without requiring additional address lookup resource logic, thus reducing the overall system power consumption.

[0048] The LDPC decoder provided by this invention employs a high-efficiency storage scheme, specifically encompassing the following aspects: It adopts an integrated storage design, merging hard decision results and variable nodes into the same storage unit, thereby reducing storage overhead and saving counter resources; it implements a storage optimization method oriented towards the minimum block RAM, adapting the block RAM bit width to make it as close as possible to or equal to the maximum bit width supported by the minimum block RAM or an integer multiple thereof, thereby improving the efficiency of storage resource utilization; furthermore, in FPGA implementations, if block RAM resources are scarce or utilization is low, the external information storage module for the verification node can use distributed RAM to store hard decision information. The LDPC decoder provided by this invention employs a refined 5G standard control method. The overall architecture is optimized for the structural characteristics of 5G standard LDPC codes, with regularized memory addressing and high processing unit reusability. In FPGA or ASIC implementations, it can achieve a given throughput target with fewer logic and storage resources, reducing chip cost and area.

[0049] Example 2 Based on Embodiment 1, this embodiment provides a control method for a low-complexity, high-speed LDPC decoder oriented towards the 5G standard. The control method includes: S1: Receive soft information from the channel, perform dynamic range quantization, compression and code block segmentation on it, and output fixed-point and block-based initial data; S2: Receive the initial data after it is divided into blocks, and perform deinterleaving and bit recovery operations on it. Rearrange the data order according to the 5G standard and restore its length. Output the data after the rate is restored. S3: Dynamically adjust the number of parallel paths according to the expansion factor required by the current decoding task, reassemble and interleave the data after the rate recovery, and output the reassembled and interleaved continuous data stream as the original variable node information; S4: Receive the continuous data stream after recombination and interleaving, perform iterative decoding through variable node updates, cyclic shifts, and check node updates, and output the parallel data after hard decision based on the updated variable node posterior probability information.

[0050] S5: Convert the decoded parallel data back into decoded data in a fixed parallel format; S6: Receive the decoded data in the fixed parallel format, sequentially concatenate the decoding results of each code block, perform cyclic redundancy check, and output the final decoded data and check status.

[0051] Specifically, during the core decoding process, multiple LDPC decoding data blocks from the high-speed input of the parallel conversion module 103 are written to the variable node memory (VN RAM) via the input interface. This VN RAM employs a pseudo-dual-port storage structure, supporting simultaneous reading and writing of code block data. The variable node information corresponding to each code block is stored according to a preset address mapping rule for subsequent layered reading and updating. The number of input data blocks can be dynamically configured according to system throughput requirements, and the memory depth is adapted to the maximum code length and number of layers defined in the 5G standard.

[0052] The decoding control unit monitors the status of each code block in the variable node memory (VN RAM) in real time to determine the number of code blocks currently in a valid decoding state. Based on the number of valid code blocks, it dynamically adjusts the interleaving granularity in subsequent decoding processes to achieve multi-code block pipelined interleaving processing. Specifically, when code block 1 completes processing at a certain layer and enters the next stage, code block 2 immediately begins processing at that layer, thereby achieving seamless connection between code blocks and improving hardware resource utilization and decoding throughput. This scheduling mechanism is implemented through a finite state machine to ensure that there are no conflicts or stalls during the processing of each code block.

[0053] Furthermore, variable node data is read layer by layer from the variable node memory (VN RAM). During each layer read, the cyclic shift value indicated by the non-zero element in the corresponding base matrix is ​​simultaneously obtained. This cyclic shift value is provided by a pre-stored shift table, consistent with the LDPC base matrix structure defined in the 5G standard. During the read process, the iteration layer counter and the global iteration count counter are updated simultaneously to track the decoding progress. Layered reading employs address generation logic, calculating the storage address in real time based on the current layer number and block number, supporting a mixed mode of continuous and random access.

[0054] When the variable node data output is valid, the cyclic shift module is initiated to perform a cyclic shift operation of the corresponding size on the data, aligning it with the data format required for the check node update. Simultaneously, the corresponding check node to variable node information (C2V information) is read from the information storage C2V RAM. To ensure data synchronization, the read control logic coordinates with the shift module, aligning their outputs within the same clock cycle before sending them to the subsequent check node update unit. The shift operation is implemented using a simplified QSN shift network, supporting all shift values ​​in the 5G standard.

[0055] The aligned variable node data and C2V information enter the check node update unit. A two-stage normalized minimum sum algorithm is used to update the check information, obtaining the updated C2V information, which is then written back to the C2V memory. Simultaneously, based on the updated C2V information and the corresponding variable node data, updated variable node information is calculated and output to the variable node update path. This check node update unit employs a parallel processing architecture, supporting simultaneous updates of up to 192 check nodes within the same base matrix layer to improve processing speed.

[0056] Furthermore, the updated variable node information is written back to the variable node memory, and the completed cyclic shift state of the data is recorded so that the reverse shift operation can be performed when reading from the next layer. The variable node memory uses a non-conflicting address mapping strategy based on the current write address and the next layer read address to ensure that read and write operations do not conflict and to achieve continuous iteration. The decoding control unit monitors the number of iterations. If the preset maximum number of iterations has not been reached and the early stopping condition is not met, the next round of iteration is triggered, and the process returns to step S4 to read the variable node data from the variable node memory layer by layer again.

[0057] In addition, the output variable node data is simultaneously fed into the early stopping unit, which performs hard decision and parity check calculations on the current decoding result. If the check passes, an early stopping flag is generated and fed back to the decoding control unit. Once the early stopping flag is valid, the decoding process terminates early, and the current decoding hard decision result is inversely shifted and formatted before being sent out through the output interface. If early stopping does not occur, the iteration continues until the maximum number of iterations is reached, and the final decoding result is output.

[0058] Furthermore, the multi-frame interleaving decoding technology described in this invention aims to maximize hardware resource utilization and achieve conflict-free pipelined processing, thereby significantly improving system throughput. This mechanism is specifically implemented collaboratively by a state monitoring unit, a scheduling decision subunit, and an interleaving execution unit.

[0059] In addition, the decoding control unit also includes a status monitoring subunit, a scheduling decision subunit, and an interleaving execution subunit. The status monitoring subunit tracks the decoding status of all code blocks in the variable node memory in real time. Each code block is associated with a status register, whose status indicators include: Idle, Loading, Iterating, DONE, and Early Stop. The status monitoring subunit continuously polls the status of each code block through a circular status buffer and counts the number of valid code blocks in the ITERATING state (denoted as ). Meanwhile, this unit also monitors the current iteration layer number and global iteration count of each ongoing code block, providing a basis for fine-grained scheduling.

[0060] The scheduling decision subunit receives the output of the status monitoring subunit. (and detailed status of each code block), and determines the resource allocation and execution order of subsequent decoding according to a preset scheduling strategy. Its core decision-making logic is as follows: a) Dynamic adjustment of interleaving granularity: Preset a maximum number of code blocks that can be interleaved. (Determined by hardware storage depth). Comparison of scheduling decision subunits. and :like This allows newly arriving code blocks to prepare for entry into the pipeline, with an interleaving granularity of [value missing]. ;like If a new code block is not found, it must wait until the state of any current code block changes to DONE or EARLY_STOPPED. This mechanism ensures that the hardware is always under high load.

[0061] b) Pipeline Stage Synchronization: To achieve the aforementioned "code block interleaving," the scheduling decision subunit divides the single code block decoding process into multiple atomic processing stages (e.g., data reading and shifting, check node updating, variable node updating and write-back, early stop judgment, etc.). The scheduling decision subunit maintains a stage pointer for each valid code block and ensures, through a unified timing controller, that when a code block... pointer from stage Entering the stage At that time, code block The pointer is just at the beginning stage This design allows different decoding stages of different code blocks to be completely interleaved and aligned in time, forming a deep pipeline.

[0062] Furthermore, the interleaving execution subunit is the hardware execution mechanism for scheduling decisions, responsible for generating access control signals for specific memory and functional units. The decoding control unit also includes a memory access arbitration subunit, which contains a multi-port arbitrator responsible for coordinating concurrent access requests from multiple code blocks to the variable node memory and C2V memory. The arbitrator employs a priority- and timing-constrained scheduling algorithm to ensure that each code block obtains access rights within its required clock cycles, avoiding read-write conflicts. This method uses a non-conflicting address mapping strategy. An address management module is integrated within the interleaving execution subunit. When code block data is initially written to the variable node memory, this module pre-calculates and allocates the physical addresses for read and write operations in all subsequent iteration layers based on its code block ID and the 5G standard base matrix structure. These addresses guarantee that the memory access addresses of any two different code blocks simultaneously in the pipeline, as well as adjacent read and write operations on the same code block, do not overlap. This mapping relationship is implemented through a lookup table.

[0063] The entire scheduling and control logic is implemented by multiple parallel sub-state machines under a unified master finite state machine. Each code block is tracked by a sub-state machine for its independent decoding progress, while the master state machine coordinates the progress of all sub-state machines and issues synchronization instructions based on the global resource status (such as the idle state of processing units and memory bandwidth occupancy). The state transition conditions of the state machines depend precisely on the completion signals of each processing unit, the early stop flag, and the value of the iteration layer / number counter, thereby achieving deterministic and efficient pipeline control.

[0064] Another embodiment of the present invention provides a channel decoding processing device for implementing the control method of the low-complexity high-speed LDPC decoder for 5G standards.

[0065] To verify the technical effects of this invention, this embodiment provides a hardware implementation based on a Field Programmable Gate Array (FPGA). Specifically, it is synthesized and implemented using the Xilinx XC7VX485TFFG1761-2 platform. The hardware architecture of this decoder is configured according to Embodiment 1, supporting typical code lengths and code rates in the 5G NR standard.

[0066] Under the clock frequency constraint of 250 MHz, the hardware resource usage of the decoder is comprehensively evaluated as shown in Table 1: Table 1 Decoder Hardware Resource Usage Table

[0067] Based on the above implementation, the decoder exhibits excellent overall performance: High throughput: At a working clock speed of 250 MHz, using an optimized partial spread factor Zc parallel decoding architecture and a multi-frame interleaved decoding structure, a data throughput of no less than 1.17 Gbps can be achieved for a 5G LDPC code with a code length of 7808 bits and a code rate of 7 / 8 in a typical scenario with an average number of 10 iterations.

[0068] Low resource consumption and high energy efficiency: As shown in Table 1, the decoder's proportion of key logic resources (LUT, FF) on the target FPGA platform is controlled at around 20%, and its memory resource (BRAM) consumption is approximately 15%. This indicates that through architecture and algorithm optimization, the present invention achieves high-speed decoding while maintaining low hardware complexity, reserving sufficient resources for integrating other communication baseband functions within a single chip, which is beneficial for improving the overall system's energy efficiency and integration.

[0069] Reliable error correction performance: By combining the two-stage normalized minimum sum algorithm with the intelligent early termination mechanism, simulation verification was performed under additive white Gaussian noise (AWGN) channel. The decoder of this invention achieves a target block error rate (BLER) of [missing value]. At that time, compared with the floating-point normalized min-sum algorithm, its decoding performance loss is less than 0.2dB, achieving an excellent balance between complexity and performance.

[0070] The above verifies the feasibility and superiority of the low-complexity, high-speed LDPC decoder described in this invention on mainstream FPGA platforms. The decoder achieves high-speed, high-performance data decoding with reasonable hardware resource overhead, perfectly meeting the high requirements of 5G communication systems for baseband processing units, and possesses extremely high practical value and industrialization prospects.

[0071] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0072] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0073] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A low-complexity, high-speed LDPC decoder for 5G standards, characterized in that, It includes an input quantization and preprocessing module (101), a rate recovery module (102), a parallel conversion module (103), a core decoding processing module (104), a parallel recovery module (105), and a code block concatenation and CRC check module (106), among which, The input quantization and preprocessing module (101) is used to receive soft information from the channel, perform dynamic range quantization, compression and code block segmentation on it, and output fixed-point and block-based initial data. The rate recovery module (102) is used to receive the initial data after it is divided into blocks, and to perform deinterleaving and bit recovery operations on it, rearrange the data order according to the 5G standard and restore its length, and output the data after rate recovery. The parallel conversion module (103) is used to dynamically adjust the number of parallel paths according to the expansion factor required by the current decoding task, reassemble and interleave the data after the rate recovery, and output the reassembled and interleaved continuous data stream as the original variable node information. The core decoding processing module (104) is used to receive the continuous data stream after recombination and interleaving, perform iterative decoding through variable node update, cyclic shift and check node update, and output the parallel data after hard decision of the updated variable node posterior probability information. The parallel recovery module (105) is used to convert the parallel data back into decoded data in a fixed parallel format; The code block splicing and CRC check module (106) is used to receive the decoding completion data in the fixed parallel format, sequentially splice the decoding results of each code block, perform cyclic redundancy check, and output the final decoding data and check status.

2. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 1, characterized in that, The input quantization and preprocessing module (101) includes a fixed-point quantization unit, a dynamic range adjustment unit, and a code block segmentation unit, wherein, The fixed-point unit is used to receive soft bit information from the channel demodulator and quantize the soft bit information into a signed integer of a preset number of bits to obtain quantized soft bit information, wherein the soft bit information is multi-bit LLR data; The dynamic range adjustment unit is used to scale the quantized soft bit information as a whole according to the external channel state information in order to optimize the dynamic range of the decoder input under different channel conditions. The code block segmentation unit is used to segment the dynamically adjusted soft bit information into independent LLR data code blocks according to the code block parameters of the 5G LDPC standard.

3. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 2, characterized in that, The rate recovery module (102) includes a deinterleaving unit and a bit recovery unit, wherein, The deinterleaving unit is used to determine the corresponding deinterleaving address mapping rule according to the 5G LDPC code parameters configured for the current decoding task, and generate read and write address control signals in real time according to the deinterleaving address mapping rule, and schedule the input LLR data code blocks to be output to the bit recovery unit according to the required parallelism and data arrangement order. The bit recovery unit is used to determine the corresponding bit recovery data length and address according to the 5G LDPC code parameters configured in the current decoding task, generate read / write control signals in real time according to the bit recovery data length, store the data input to the bit recovery unit into the corresponding address according to the read / write control signals, cyclically superimpose subsequent data exceeding the bit recovery data length onto the stored original data from the beginning, generate read control signals according to the deinterleaving address mapping rules, insert all zero values ​​or positive maximum values ​​into specific positions of the data input to the bit recovery unit, and then output to the parallel conversion module (103).

4. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 1, characterized in that, The deinterleaving unit includes buffer registers REG1, REG2, REG3, RAM1, RAM2, RAM3, and a multiplexer MUX1. The inputs of buffer registers REG1, REG2, and REG3 are all connected to the output of the input quantization and preprocessing module (101). The output of buffer register REG1 is connected to the input of RAM1, the output of buffer register REG2 is connected to the input of RAM2, and the output of buffer register REG3 is connected to the input of RAM3. The outputs of buffer registers REG1, REG2, and REG3 are all connected to the multiplexer MUX1.

5. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 3, characterized in that, The parallel conversion module (103) includes shift register 1, shift register 2, FIFO1, FIFO2, and multiplexer MUX2, wherein, The input terminals of shift register 1 and shift register 2 are respectively connected to the output terminal of the bit recovery unit. The output terminal of shift register 1 is connected to the input terminal of FIFO1. The output terminal of shift register 2 is connected to the input terminal of FIFO2. The output terminals of FIFO1 and FIFO2 are respectively connected to the input terminal of multiplexer MUX2. The output terminal of multiplexer MUX2 serves as the output terminal of the parallel conversion module (103).

6. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 1, characterized in that, The core decoding processing module (104) includes a decoding control unit, a variable node processing unit, a circular shift unit, a check node update unit, and an iterative early stopping unit, wherein, The variable node processing unit includes a multiplexer MUX3 and a variable node memory VN RAM. One input of the multiplexer MUX3 is connected to the output of the parallel conversion module (103), and the output of the multiplexer MUX3 is connected to the variable node memory VN RAM. The variable node processing unit is used to store the original variable node information from the parallel conversion module (103) or the updated variable node information from the verification node update unit into the variable node memory VN RAM using the multiplexer MUX3. Then, according to the read / write control signal issued by the decoding control unit, it reads and outputs data from the corresponding address in the variable node memory VN RAM. The cyclic shift unit is used to cyclically shift the data from the variable node memory (VN RAM) according to the shift parameter control signal of the decoding control unit, and output the cyclic shift result; The verification node update unit is used to utilize the cyclic shift result, employ a dynamic normalized minimum sum algorithm, and modulate the normalization parameter through the number of iterations to update the updated variable node information; The early stopping module is used to check whether the hard decision information of the posterior probability information of the updated variable node satisfies the verification equation. If it does, the iteration is terminated early, and the hard decision information is transmitted to the parallel recovery module (105) as the output of the core decoding processing module (104). If it does not satisfy the equation, the updated variable node information is transmitted to the multiplexer MUX3 to continue the iteration.

7. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 6, characterized in that, The verification node update unit includes a verification node memory (V2C RAM), an information memory (C2V RAM), and a verification node update processing subunit, wherein... When the information memory C2V RAM is reset, all values ​​are set to zero. The corresponding C2V information is read out through the read / write address control signal sent by the decoding control unit. The V2C information is obtained by subtracting the cyclic shift result from the cyclic shift unit. After the verification node update processing subunit completes the update, the updated C2V information is stored in the corresponding address of the information memory C2V RAM according to the control signal sent by the control decoding unit. The C2V information is the information passed from the verification node to the variable node, and the V2C information is the information passed from the variable node to the verification node. When the V2C information is obtained by subtraction, the V2C information is stored in the corresponding address of the V2C RAM by the write control signal sent by the control decoding unit. After the V2C update processing subunit completes the update, the V2C information at the corresponding address is read out according to the read control signal sent by the control decoding unit. The verification node update processing subunit is used to divide the 192 V2C information obtained by subtraction into 16 groups, with 12 V2C information in each group. The absolute value and sign bit are taken respectively, and the minimum and second smallest absolute values ​​are compared. The position corresponding to the minimum value is recorded. The extracted sign bit is stored in the internal register and the product of the sign bits is calculated. After the calculation is completed, the product of the minimum or second smallest absolute value and the sign bit is determined according to the position corresponding to the minimum absolute value. This product is used as the updated C2V information, and then added to the V2C information read from the verification node memory V2C RAM to obtain the updated variable node information, which is then transmitted to the multiplexer MUX3.

8. The low-complexity, high-speed LDPC decoder for 5G standards according to claim 6, characterized in that, The parallel recovery module (105) includes shift register 3 and FIFO 3, wherein, The parallel recovery module (105) is used when the spreading factor of the 5G-LDPC decoder... When the data input to the parallel recovery module (105) is greater than 12 bits, the high 12 bits of the valid data are stored in the FIFO3; when the data in the shift register 3 is greater than 12 bits, the high 12 bits of the valid data are stored in the FIFO3. At that time, two consecutive input data input to the parallel recovery module (105) are interleaved and stored in the shift register 3. When the valid data in the shift register 3 is greater than 12 bits, the high 12 bits of the valid data are stored in the FIFO3. After all the input data is stored in the FIFO3, the data is read out from the FIFO3 and transmitted to the code block splicing and CRC check module (106).

9. A control method for a low-complexity, high-speed LDPC decoder for 5G standards, characterized in that, The method, performed using any one of claims 1 to 8, is a low-complexity, high-speed LDPC decoder for 5G standards, comprising: S1: Receive soft information from the channel, perform dynamic range quantization, compression and code block segmentation on it, and output fixed-point and block-based initial data; S2: Receive the initial data after it is divided into blocks, and perform deinterleaving and bit recovery operations on it. Rearrange the data order according to the 5G standard and restore its length. Output the data after the rate is restored. S3: Dynamically adjust the number of parallel paths according to the expansion factor required by the current decoding task, reassemble and interleave the data after the rate recovery, and output the reassembled and interleaved continuous data stream as the original variable node information; S4: Receive the continuous data stream after recombination and interleaving, perform iterative decoding through variable node update, cyclic shift and check node update, and output the parallel data after hard decision of the updated variable node posterior probability information. S5: Convert the parallel data back into decoded data in a fixed parallel format; S6: Receive the decoded data in the fixed parallel format, sequentially concatenate the decoding results of each code block, perform cyclic redundancy check, and output the final decoded data and check status.

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