Wiring substrate

Abstract

A wiring substrate having high quality. The wiring substrate is composed of a multilayer core substrate and a buildup layer. The multilayer core substrate is formed of a central insulating layer, a first surface side insulating layer, and a second surface side insulating layer, and has a via, an inner layer conductor layer, and a surface layer conductor layer. The first surface side insulating layer is formed of at least two layers of insulating layers on the first surface side of the central insulating layer, the second surface side insulating layer is formed of at least two layers of insulating layers on the second surface side of the central insulating layer, the inner layer conductor layer is composed of a first inner layer conductor layer and a second inner layer conductor layer, the first inner layer conductor layer is formed on the first surface of the central insulating layer, and the second inner layer conductor layer is formed on the second surface of the central insulating layer, the surface layer conductor layer is composed of a first surface layer conductor layer and a second surface layer conductor layer, the first and second surface layer conductor layers are formed on the outermost layers of the first and second surface side insulating layers, respectively, the via is formed between the first surface layer conductor layer and the second surface layer conductor layer, and the via is also connected to the first and second inner layer conductor layers, and a component is disposed in the first surface side insulating layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to wiring substrates. Background Technology

[0002] Patent Document 1 discloses a multilayer core substrate with through-holes and a wiring board with multilayer wiring layers formed on both sides of the multilayer core substrate. The multilayer core substrate is composed of a resin substrate and an adhesive resin layer, forming a multilayer insulating layer structure (a total of 7 layers) consisting of a first resin substrate, a second resin substrate stacked on the first resin substrate via an adhesive resin layer, and a third resin substrate stacked on the second resin substrate via an adhesive resin layer. Conductor circuits composed of conductor layers are formed on both sides of each resin substrate. The through-holes are connected to the conductor circuits formed on both sides of each resin substrate, and are composed of a total of 6 conductor layers.

[0003] Patent Document 1: International Publication No. 2001 / 19148

[0004] [The issue of patent document 1]

[0005] With the increasing demands for high-speed and high-capacity signals, the issue of signal transmission delay within vias has arisen. In the wiring board described in Patent Document 1, it is argued that signal delay arises from the number of layers of conductor circuits connected to vias in a multilayer substrate. Therefore, due to signal delay, the parasitic capacitance of the vias is considered to increase. Summary of the Invention

[0006] The wiring substrate of the present invention is composed of a multilayer core substrate and a multilayer laminate. The multilayer core substrate is formed of a central insulating layer, a first side-mounted insulating layer, and a second side-mounted insulating layer, and has through-holes, inner conductor layers, and surface conductor layers. The first side-mounted insulating layer is formed by at least two insulating layers on the first side of the central insulating layer. The second side-mounted insulating layer is formed by at least two insulating layers on the second side of the central insulating layer. The inner conductor layer is composed of a first inner conductor layer and a second inner conductor layer, the first inner conductor layer being formed on the first side of the central insulating layer, and the second inner conductor layer being formed on the second side of the central insulating layer. The surface conductor layer is composed of a first surface conductor layer and a second surface conductor layer, the first surface conductor layer being formed on the outermost layer of the first side-mounted insulating layer, and the second surface conductor layer being formed on the outermost layer of the second side-mounted insulating layer. The through-holes are formed between the first surface conductor layer and the second surface conductor layer, and the through-holes are also connected to the first inner conductor layer and the second inner conductor layer. Components are disposed within the first side-mounted insulating layer. Attached Figure Description

[0007] Figure 1This is a schematic cross-sectional view of the wiring substrate of an embodiment.

[0008] Figure 2 yes Figure 1 Enlarged view of Part II.

[0009] Figure 3A This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0010] Figure 3B This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0011] Figure 3C This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0012] Figure 3D This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0013] Figure 3E This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0014] Figure 3F This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 3G This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 3H This is a cross-sectional view schematically illustrating a method for manufacturing a wiring substrate according to an embodiment.

[0017] Label Explanation

[0018] 1: Wiring substrate; 10: Central insulating layer; 10F: First side; 10S: Second side; 12: First inner conductor layer; 14: Second inner conductor layer; 20: First side insulating layer; 30: Second side insulating layer; 42: First surface conductor layer; 46: Connecting conductor; 52: Second surface conductor layer; 60: Component; 80: Through-hole; 100: Multilayer core substrate; 110: First stacked layer; 120: Second stacked layer. Detailed Implementation

[0019] [Wiring substrate 1 in the embodiment]

[0020] Figure 1 This is a cross-sectional view showing the wiring substrate 1 according to an embodiment. Figure 1As shown, the wiring substrate 1 has a multilayer core substrate 100, a first stacked layer 110, and a second stacked layer 120. The first stacked layer 110 is formed on a first surface 100F of the multilayer core substrate 100. The second stacked layer 120 is formed on a second surface 100S of the multilayer core substrate 100.

[0021] The multilayer core substrate 100 is formed of a central insulating layer 10, a first side-mounted insulating layer 20, and a second side-mounted insulating layer 30, and has through-holes 80, inner conductor layers, surface conductor layers, and connecting conductors 46. A component 60 is disposed within the multilayer core substrate 100. The first side-mounted insulating layer 20 is formed on the first surface 10F of the central insulating layer 10. The second side-mounted insulating layer 30 is formed on the second surface 10S of the central insulating layer 10. The central insulating layer 10 is sandwiched between the first side-mounted insulating layer 20 and the second side-mounted insulating layer 30. Furthermore, the inner conductor layers are a first inner conductor layer 12 and a second inner conductor layer 14, and the surface conductor layers are a first surface conductor layer 42 and a second surface conductor layer 52.

[0022] The first side insulating layer 20 is formed by a first resin substrate 40, a first insulating layer 22, and a third insulating layer 24. The first insulating layer 22 is formed on the first surface 10F of the central insulating layer 10. The first resin substrate 40 is formed on the surface of the first insulating layer 22 opposite to the central insulating layer 10. The third insulating layer 24 is formed on the surface of the first resin substrate 40 opposite to the first insulating layer 22. The second side insulating layer 30 is formed by a second resin substrate 50, a second insulating layer 32, and a fourth insulating layer 34. The second insulating layer 32 is formed on the second surface 10S of the central insulating layer 10. The second resin substrate 50 is formed on the surface of the second insulating layer 32 opposite to the central insulating layer 10. The fourth insulating layer 34 is formed on the surface of the second resin substrate 50 opposite to the second insulating layer 32. Furthermore, the first side insulating layer 20 and the second side insulating layer 30 are formed by at least two insulating layers. The first side insulating layer 20 and the second side insulating layer 30 may be formed by three or four insulating layers.

[0023] In the description of the wiring substrate 1 in this embodiment, the side of the wiring substrate 1 that is away from the central insulating layer 10 in the thickness direction is also referred to as "upper side" or "above" or simply "upper," and the side that is close to the central insulating layer 10 is also referred to as "lower side" or "below" or simply "below." Furthermore, in each conductor layer and each insulating layer, the surface facing the side opposite to the central insulating layer 10 is also referred to as the "upper surface," and the surface facing the central insulating layer 10 is also referred to as the "lower surface." Therefore, for example, in the description of the first stacked layer 110 and the second stacked layer 120, the side away from the multilayer core substrate 100 is also referred to as "upper side," "above," or simply "upper," and the side close to the multilayer core substrate 100 is also referred to as "lower side," "below," or simply "below." Additionally, in the description of the wiring substrate 1 in this embodiment, each conductor layer and each insulating layer is sometimes also referred to as "first surface" or "second surface." Here, for convenience, the first surface is described as the upper surface, but it can be either the upper surface or the lower surface.

[0024] A first inner conductor layer 12 is formed on the first surface 10F of the central insulating layer 10. The first inner conductor layer 12 is covered by the first insulating layer 22. The first inner conductor layer 12 can be any one of a single conductor layer or a multilayer conductor layer with two or more layers. The first inner conductor layer 12 has a portion connected to the through-hole 80 and a portion not directly connected to the through-hole 80. Furthermore, the portion of the first inner conductor layer 12 connected to the through-hole 80 is designated as a first inner through-hole connection portion 13a. The portion of the first inner conductor layer 12 not directly connected to the through-hole 80 is designated as a first inner through-hole non-connection portion 13b.

[0025] The second inner conductor layer 14 is formed on the second surface 10S of the central insulating layer 10. The second inner conductor layer 14 is covered by the second insulating layer 32. The second inner conductor layer 14 can be any one of a single conductor layer or a multilayer conductor layer with two or more layers. The second inner conductor layer 14 has a portion connected to the through hole 80 and a portion not directly connected to the through hole 80. Furthermore, the portion of the second inner conductor layer 14 connected to the through hole 80 is designated as the second inner through hole connection portion 15a. The portion of the second inner conductor layer 14 not directly connected to the through hole 80 is designated as the second inner through hole non-connection portion 15b.

[0026] The first surface conductor layer 42 is formed on the outermost layer of the first surface-side insulating layer 20. Specifically, the first surface conductor layer 42 is formed on the third insulating layer 24, which is the outermost layer of the first surface-side insulating layer 20. The first surface conductor layer 42 is formed of at least two or more conductor layers. The first surface conductor layer 42 may also be formed of three or four conductor layers. The first surface conductor layer 42 has a portion connected to the through hole 80 and a portion not directly connected to the through hole 80. Furthermore, the portion of the first surface conductor layer 42 connected to the through hole 80 is designated as a first surface through hole connection portion, and a first cover conductor 43 is formed in the first surface through hole connection portion. The portion of the first surface conductor layer 42 not directly connected to the through hole 80 is designated as a first surface through hole non-connection portion 44.

[0027] The second surface conductor layer 52 is formed on the outermost layer of the second surface insulating layer 30. Specifically, the second surface conductor layer 52 is formed on the fourth insulating layer 34, which is the outermost layer of the second surface insulating layer 30. The second surface conductor layer 52 is formed of at least two or more conductor layers. The first surface conductor layer 42 may also be formed of three or four conductor layers. The second surface conductor layer 52 has a portion connected to the through hole 80 and a portion not directly connected to the through hole 80. Furthermore, the portion of the second surface conductor layer 52 connected to the through hole 80 is designated as a second surface through hole connection portion, and a second cover conductor 53 is formed in the second surface through hole connection portion. The portion of the second surface conductor layer 52 not directly connected to the through hole 80 is designated as a second surface through hole non-connection portion 54.

[0028] A via 80 is formed between the first surface conductor layer 42 and the second surface conductor layer 52. The via 80 is connected to the first surface conductor layer 42 and the second surface conductor layer 52, and also to the first inner conductor layer 12 and the second inner conductor layer 14. That is, the via 80 is connected to four conductor layers.

[0029] The through-hole 80 is composed of an inner wall conductor layer 81 and a filling material 82. The inner wall conductor layer 81 is a conductor layer formed on the inner wall of the through-hole 80a. The inner wall conductor layer 81 can be a single-layer conductor layer or two or more conductor layers. The surface of the inner wall conductor layer 81 can also be roughened or otherwise surface-treated. The filling material 82 is formed inside the through-hole 80a. The through-hole 80a of the through-hole 80 penetrates the central insulating layer 10, the first side insulating layer 20, and the second side insulating layer 30.

[0030] A first surface through-hole connection portion, i.e., a first cover conductor 43, is formed on the outermost layer of the insulating layer 20 on the first side of the through-hole 80, consisting of an inner wall conductor layer 81 and a first surface conductor layer 43. The first cover conductor 43 covers the end face of the filler material 82. The first cover conductor 43 is a part of the first surface conductor layer 43. Alternatively, the first surface through-hole connection portion may be exposed without covering the end face of the filler material 82. A second surface through-hole connection portion, i.e., a second cover conductor 53, is formed on the outermost layer of the insulating layer 30 on the second side of the through-hole 80, consisting of an inner wall conductor layer 81 and a second surface conductor layer 53. The second cover conductor 53 covers the end face of the filler material 82. Furthermore, the second cover conductor 53 is a part of the second surface conductor layer 53. Alternatively, the second surface through-hole connection portion may be exposed without covering the end face of the filler material 82.

[0031] The through-hole 80 is connected to the first inner conductor layer 12 and the second inner conductor layer 14. An opening for forming the through-hole 80 is provided in the first inner conductor layer 12, where the through-hole 80 is connected. An opening for forming the through-hole 80 is provided in the second inner conductor layer 14, where the through-hole 80 is connected.

[0032] The thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer are not particularly limited, but preferably the thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer satisfy the relationship in Equation 1.

[0033] T1 < T2… Equation 1.

[0034] If the thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer follow the relationship of Equation 1, then the formation of the via 80 is stable. During the formation of the multilayer core substrate 100, substrate warpage is reduced, and the formation of the stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is also stable.

[0035] The number of inner conductor layers S1 and the number of outer conductor layers S2 are not particularly limited, but it is preferred that the number of inner conductor layers S1 and the number of outer conductor layers S2 satisfy the relationship in Equation 2.

[0036] S1 < S2 ... Equation 2.

[0037] If the number of inner conductor layers S1 and the number of outer conductor layers S2 are related by Equation 2, then the formation of via 80 is stable. When forming the multilayer core substrate 100, substrate warpage is reduced, and the formation of stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is also stable.

[0038] Furthermore, it is preferable that the thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer satisfy the relationship of Equation 1, and that the number of inner conductor layers S1 and the number of outer conductor layers S2 satisfy the relationship of Equation 2. By satisfying these two relationships, the formation of the via 80 is stable. When forming the multilayer core substrate 100, substrate warpage is reduced, and the formation of the stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is stable. It is believed that even if reliability tests are conducted, it is difficult for defects such as insulation to occur in the early stages.

[0039] Component 60 is disposed within the first side insulating layer 20. An opening 45 penetrating the first resin substrate 40 is formed therein. Component 60 is housed within the opening 45. Component 60 is an electronic component. Specifically, the electronic component is a capacitor, inductor, IVR, semiconductor, etc. Component 60 has an electrode surface 61 and a non-electrode surface 62 opposite to the electrode surface 61. The non-electrode surface 62 of component 60 faces the first insulating layer 22. The electrode surface 61 of component 60 faces the third insulating layer 24. A connecting conductor 46 penetrating the insulating layer is formed in the third insulating layer 24. The connecting conductor 46 is connected to a portion of the first surface conductor layer 42 that is not directly connected, namely the non-connected portion 44 of the first surface through-hole. The electrode surface 61 is connected to the connecting conductor 46. Thus, the electrode surface 61 of component 60 is connected to the non-connected portion 44 of the first surface through-hole via the connecting conductor 46. Therefore, component 60 is connected to the first surface conductor layer 42. The gap between the inner surface of the opening 45 and the component 60 is filled with embedded resin 63. Embedded resin 63 is, for example, a thermosetting resin. Embedded resin 63 can also be a photocurable resin. Embedded resin 63 is disposed separately from the first insulating layer 22, the first resin substrate 40, and the third insulating layer 24. Furthermore, multiple components 60 can be housed within the opening 45, and identical or different components can be configured.

[0040] A first stacked layer 110 and a second stacked layer 120 are formed on a multilayer core substrate 100. The first stacked layer 110 is formed on a first surface 100F of the multilayer core substrate 100, and consists of at least one layer, including an insulating layer 111, a conductor layer 112, and a via conductor 113. The second stacked layer 120 is formed on a second surface 100S of the multilayer core substrate 100, and consists of at least one layer, including an insulating layer 121, a conductor layer 122, and a via conductor 123.

[0041] exist Figure 1In this example, the first stacked layer 110 consists of two insulating layers 111 and two conductive layers 112, and the second stacked layer 120 consists of two insulating layers 121 and two conductive layers 122. Each insulating layer 111 includes a via conductor 113 connecting the conductive layer on the insulating layer 111 to the conductive layer below it. Each insulating layer 121 includes a via conductor 123 connecting the conductive layer on the insulating layer 121 to the conductive layer below it. Alternatively, the stacked layers can be formed on only one side of the multilayer core substrate. In this case, only the first stacked layer 110 or the second stacked layer 120 is formed on the multilayer core substrate.

[0042] In the illustrated example, both the first stacked layer 110 and the second stacked layer 120 contain two conductor layers and two insulating layers, but they may also contain more than three conductor layers and more than three insulating layers, or each conductor layer and insulating layer may be only one layer.

[0043] Connecting pads 112a are formed on the surface layer 112 of the first stacked layer 110, which is the outermost layer of the wiring substrate 1, and connecting pads 122a are formed on the surface layer 122 of the second stacked layer 120, which is the outermost layer of the wiring substrate 1. External electronic components, motherboards (not shown), etc., are mounted on the connecting pads 112a. When electronic components are mounted, bumps (not shown) made of any metal such as solder, copper, or tin are formed on the connecting pads 112a and 122a.

[0044] In the wiring substrate 1, the first inner conductor layer 12, the second inner conductor layer 14, the first surface conductor layer 42, the second surface conductor layer 52, the conductor layer 112 within the first stacked layer 110, and the conductor layer 122 within the second stacked layer 120 form arbitrary conductor patterns. For ease of observation, these conductor layers are simplified to have a single-layer structure; more specifically, see reference... Figure 2 As will be described later, it can also have a multi-layered structure with two or more layers.

[0045] The insulating layer and resin substrate constituting the multilayer core substrate 100 of the present invention are not particularly limited, but materials formed by impregnating an insulating resin into a core material serving as a reinforcing material and then curing it are preferred. As the insulating resin, epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, etc., can be used. Reinforcing materials include glass fiber, aramid fiber, glass nonwoven fabric, aramid nonwoven fabric, etc. By including a core material in the insulating layer and resin substrate, a wiring substrate 1 with high rigidity and suppressed warpage can be provided. On the other hand, the insulating layers 111 and 121 used for layering are preferably formed of an insulating resin that does not contain a core material. This is because an insulating resin that does not contain a core material is suitable for forming through-holes. Furthermore, each insulating layer may also contain inorganic fillers such as silica.

[0046] Reference Figure 2 This section details the structure of the conductors included in the wiring substrate 1. Figure 2 The middle shows Figure 1 Enlarged view of Part II.

[0047] like Figure 2 As shown, the first inner conductor layer 12 is formed of a metal foil layer 12a formed on the first surface 10F of the central insulating layer 10. The second inner conductor layer 14 is formed of a metal foil layer 14a formed on the second surface 10S of the central insulating layer 10. The metal foil layer 12a of the first inner conductor layer 12 and the metal foil layer 14a of the second inner conductor layer 14 have a single-layer structure, but they can also have a multi-layer structure with two or more layers. The type of metal foil used for the metal foil layers 12a and 14a is not particularly limited, but considering conductivity, it is preferable to use a metal foil with copper as the main component.

[0048] The conductor layer of this invention is composed of any combination of a metal foil layer, a seed layer, and an electroplated layer. The metal foil layer is a conductor layer in which a pattern is formed starting from a metal foil formed on an insulating layer. It should be noted that the type of metal in the metal foil is not particularly limited, but considering conductivity, a metal with copper as its main component is preferred. The seed layer is a conductor layer in which a seed film, such as a chemically plated film or a sputtered film, is formed on the entire surface of the substrate and a pattern is formed. It should be noted that the type of metal in the seed film is not particularly limited, but a metal with copper, nickel, or titanium as its main components is preferred. The electroplated layer is a conductor layer in which a pattern is formed using a resist based on the seed film formed on the substrate, and a pattern is formed using an electroplated film deposited on the non-formation areas of the resist. It should be noted that the type of metal in the electroplated film is not particularly limited, but considering conductivity, a metal with copper as its main component is preferred.

[0049] The first surface conductor layer 42 is composed of a metal foil layer, a seed layer, and an electroplated layer. Specifically, the first surface conductor layer 42 is formed by a metal foil layer 42a, a seed layer 42b on the metal foil layer 42a, an electroplated layer 42c on the seed layer 42b, a seed layer 42d on the electroplated layer 42c, and an electroplated layer 42e on the seed layer 42d, all formed on the upper surface of the third insulating layer 24. The first surface conductor layer 42 has a five-layer structure consisting of the metal foil 42a, the seed layer 42b, the electroplated layer 42c, the seed layer 42d, and the electroplated layer 42e. Furthermore, the first cover conductor 43 is formed by the seed layer 42d and the electroplated layer 42e. That is, the first surface conductor layer 42 has a five-layer structure.

[0050] A connecting conductor 46 penetrates the third insulating layer 24 and is formed within a hole 24a that exposes the electrode surface 61 of the component 60. The connecting conductor 46 is formed from a seed layer 42b formed on the inner wall surface of the hole 24a and the electrode surface 61, and an electroplated layer 42c formed on the seed layer 42b and filling the hole 24a. The seed layer 42b and electroplated layer 42c forming the connecting conductor 46 are shared with the seed layer 42b and electroplated layer 42c forming the first surface conductor layer 42. The first surface conductor layer 42 and the connecting conductor 46 are formed simultaneously. The connecting conductor 46 connects the electrode surface 61 of the component 60 to the non-connecting portion 44 of the first surface through-hole.

[0051] The second surface conductor layer 52 is composed of a metal foil layer, a seed layer, and an electroplated layer. Specifically, the second surface conductor layer 52 is formed by a metal foil layer 52a, a seed layer 52b on the metal foil layer 52a, an electroplated layer 52c on the seed layer 52b, a seed layer 52d on the electroplated layer 52c, and an electroplated layer 52e on the seed layer 52d, all formed on the upper surface of the fourth insulating layer 34. The second surface conductor layer 52 has a five-layer structure consisting of the metal foil layer 52a, the seed layer 52b, the electroplated layer 52c, the seed layer 52d, and the electroplated layer 52e. Furthermore, the second cover conductor 53 is formed by the seed layer 52d and the electroplated layer 52e. That is, the second surface conductor layer 52 has a five-layer structure.

[0052] In the wiring substrate 1 of the embodiment, it is preferable that the thickness T1 of the inner conductor layer (first inner conductor layer 12, second inner conductor layer 14) and the thickness T2 of the surface conductor layer (first surface conductor layer 42, second surface conductor layer 52) satisfy the following Equation 1 relationship.

[0053] T1 < T2… Equation 1.

[0054] If the thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer follow the relationship of Equation 1, then the formation of the via 80 is stable. During the formation of the multilayer core substrate 100, substrate warpage is reduced, and the formation of the stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is also stable. Specifically, the thickness T1 of the inner conductor layer refers to the thickness of the first inner through-hole connection portion 13a and the thickness of the second inner through-hole connection portion 15a, and the thickness T2 of the outer conductor layer refers to the thickness of the first outer through-hole connection portion and the thickness of the second outer through-hole connection portion.

[0055] Furthermore, the number of inner conductor layers (first inner conductor layer 12, second inner conductor layer 14) S1 and the number of surface conductor layers (first surface conductor layer 42, second surface conductor layer 52) S2 preferably satisfy the following relationship: Equation 2.

[0056] S1 < S2 ... Equation 2.

[0057] If the number of inner conductor layers S1 and the number of outer conductor layers S2 follow the relationship in Equation 2, then the formation of via 80 is stable. When forming the multilayer core substrate 100, substrate warpage is reduced, and the formation of stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is also stable. Specifically, the number of inner conductor layers S1 refers to the number of layers in the first inner through-hole connection portion 13a and the second inner through-hole connection portion 15a, and the number of outer conductor layers S2 refers to the number of layers in the first outer through-hole connection portion and the second outer through-hole connection portion.

[0058] Furthermore, it is preferable that the thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer satisfy the relationship of Equation 1, and that the number of inner conductor layers S1 and the number of outer conductor layers S2 satisfy the relationship of Equation 2. By satisfying these two relationships, the formation of the via 80 is stable. When forming the multilayer core substrate 100, substrate warpage is reduced, and the formation of the stacked layers 110 and 120 is also stable. Therefore, it is believed that warpage is suppressed during the fabrication of the wiring substrate, and the connection of the conductor layers is stable. It is believed that even if reliability tests are conducted, it is difficult for defects such as insulation to occur in the early stages.

[0059] The through-hole 80 is composed of an inner wall conductive layer 81 and a filling material 82. The inner wall conductive layer 81 of the through-hole 80 is formed by a seed layer 81b formed on the inner wall surface of the through-hole 80a and an electroplated layer 81c on the seed layer 81b. The seed layer 81b is shared with seed layers 42b and 52b and is formed simultaneously with the seed layers 42b and 52b. The electroplated layer 81c is shared with electroplated layers 42c and 52c and is formed simultaneously with the electroplated layers 42c and 52c. A filling material 82 is formed inside the through-hole 80. The filling material 82 is formed, for example, by an insulating material containing resins such as epoxy resin, acrylic resin, or phenol. Alternatively, the filling material 82 may also be a cured product of a conductive paste or conductive ink containing metal particles such as silver or copper. Through the filling material 82 formed inside the through-hole 80, a via conductor can be formed directly above the through-hole 80. A first cover conductor 43 and a second cover conductor 53 are formed on the end face of the filler material 82 to cover the end face of the filler material 82. Alternatively, the filler material 82 may be made of a conductive material.

[0060] The conductor layer 112 of the first stacked layer 110 is formed by a seed layer 112b and an electroplated layer 112c, and consists of two conductor layers. The conductor layer 122 of the second stacked layer 120 is formed by a seed layer 122b and an electroplated layer 122c, and consists of two conductor layers.

[0061] The via conductor 113 in the first stacked layer 110 is formed by a seed layer 112b and an electroplated layer 112c, and consists of two conductor layers. The seed layer 112b and electroplated layer 112c of the via conductor 113 are shared with the seed layer 112b and electroplated layer 112c of the conductor layer 112. The via conductor 123 in the second stacked layer 120 is formed by a seed layer 122b and an electroplated layer 122c, and consists of two conductor layers. The seed layer 122b and electroplated layer 122c of the via conductor 123 are shared with the seed layer 122b and electroplated layer 122c of the conductor layer 122.

[0062] [Method for manufacturing wiring substrate 1 according to the embodiment]

[0063] Figures 3A to 3H A method for manufacturing the wiring substrate 1 according to an embodiment is shown. Figures 3A to 3H It is a sectional view. For example... Figure 3A As shown, a central insulating layer 10 is prepared to have a first inner conductor layer 12 formed on the first surface 10F and a second inner conductor layer 14 formed on the second surface 10S. The central insulating layer 10 is formed using a double-sided copper-clad laminate with metal foils formed on both sides of a resin substrate containing a core material as the starting material. The first inner conductor layer 12 and the second inner conductor layer 14 with desired conductor patterns are formed by a subtractive method, such as etching the metal foils using a mask with traced wiring. Thus, a central insulating layer 10 with conductor layers formed on both sides is obtained. Alternatively, the central insulating layer 10 can also be formed with desired conductor patterns based on metals formed on both sides of an insulating material by sputtering, plating, or the like.

[0064] like Figure 3B As shown, a first resin substrate 40 without metal foil on both sides is prepared. The first resin substrate 40 is prepared as a starting material for a double-sided copper-clad laminate with metal foil formed on both sides of a resin substrate containing a core material. As an example, the first resin substrate 40 is formed by removing the metal foil on both sides of the double-sided copper-clad laminate through a full-surface etching process. Similarly, a second resin substrate 50 without metal foil on both sides is also prepared. Alternatively, a resin substrate without metal foil can be used beforehand.

[0065] like Figure 3C As shown in (a), an opening 45 is formed in the first resin substrate 40. The opening 45 extends between the upper and lower surfaces of the first resin substrate 40. The opening 45 is formed by laser, grooving, or the like.

[0066] like Figure 3C As shown in (b), a first resin substrate 40 with an opening 45 is placed on a support plate 66. The lower surface of the first resin substrate 40 faces the support plate 66. The lower surface of the first resin substrate 40 with the opening 45 is closed by the support plate 66. The lower surface of the first resin substrate 40 and the support plate 66 can also be bonded together by a release agent.

[0067] like Figure 3C As shown in (c), a component 60 is disposed within the opening 45. The non-electrode surface 62 of the component 60 is disposed on a support plate 66 exposed from the opening 45. At this time, the component 60 is fixed to the support plate 66 by providing an adhesive layer between the non-electrode surface 62 of the component 60 and the support plate 66. The electrode surface 61 of the component 60 is on the same plane as the upper surface of the first resin substrate 40. Alternatively, the electrode surface 61 of the component 60 may be lower than the upper surface of the first resin substrate 40. An embedded resin 63 is filled into the gap between the opening 45 of the first resin substrate 40 and the component 60. The filling of the embedded resin 63 is performed, for example, by potting. The embedded resin 63 is preferably a thermosetting resin or a photocurable resin. The embedded resin 63 is cured. The component 60 is fixed within the opening 45.

[0068] like Figure 3C As shown in (d), the support plate 66 is removed after the embedded resin 63 has cured. A first resin substrate 40 housing the component 60 is formed.

[0069] like Figure 3D As shown, the following are prepared: metal foil 42a, prepreg 24p cured to become the third insulating layer 24, first resin substrate 40 for housing component 60, prepreg 22p cured to become the first insulating layer 22, central insulating layer 10, prepreg 32p cured to become the second insulating layer 32, second resin substrate 50, prepreg 34p cured to become the fourth insulating layer 34, and metal foil 52a. Prepreg 22p is disposed on the first surface 10F side of the central insulating layer 10, the first resin substrate 40 is disposed on the prepreg 22p, prepreg 24p is disposed on the first resin substrate 40, and metal foil 42a is disposed on the prepreg 24p. Prepreg 32p is disposed on the second surface 10S side of the central insulating layer 10, the second resin substrate 50 is disposed on the prepreg 32p, prepreg 34p is disposed on the second resin substrate 50, and metal foil 52a is disposed on the prepreg 34p.

[0070] like Figure 3E As shown, Figure 3DThe metal foil 42a, prepreg 24p, first resin substrate 40, prepreg 22p, central insulating layer 10, prepreg 32p, second resin substrate 50, prepreg 34p, and metal foil 52a are overlapped and then pressed together. Thermosetting can be performed simultaneously with pressing or after pressing. Through pressing, prepregs 22p, 32p, 24p, and 34p are cured to form the first insulating layer 22, the second insulating layer 32, the third insulating layer 24, and the fourth insulating layer 34. A first-side insulating layer 20, composed of the first insulating layer 22, the first resin substrate 40, and the third insulating layer 24, is formed on the first surface 10F of the central insulating layer 10. A second-side insulating layer 30, composed of the second insulating layer 32, the second resin substrate 50, and the fourth insulating layer 34, is formed on the second surface 10S of the central insulating layer 10. Metal foil 42a is formed on the third insulating layer 24, and metal foil 52a is formed on the fourth insulating layer 34. The pressed first inner conductor layer 12 is embedded in the first insulating layer 22. The pressed second inner conductor layer 14 is embedded in the second insulating layer 32. A mid-substrate 2 is formed, consisting of a first side insulating layer 20, a central insulating layer 10, and a second side insulating layer 30.

[0071] For ease of explanation, the thickness of the first side insulating layer 20 and the second side insulating layer 30 are the same, but the thicknesses of the first side insulating layer 20 and the second side insulating layer 30 can also be different. Specifically, the thickness of the first side insulating layer 20 is less than the thickness of the second side insulating layer 30. This allows for adjustment of the overall thickness of the multilayer core substrate. Furthermore, when components are disposed within a resin substrate, the thickness can also be adjusted according to the thickness of the components.

[0072] like Figure 3F As shown, a through-hole is formed in the intermediate substrate 2. A through-hole 80a is formed, penetrating the metal foil 42a, the third insulating layer 24, the first resin substrate 40, the first insulating layer 22, the first inner conductor layer 12, the central insulating layer 10, the second inner conductor layer 14, the second insulating layer 32, the second resin substrate 50, the fourth insulating layer 34, and the metal foil 52a in the intermediate substrate 2. The through-hole 80a is formed, for example, by piercing with a cutting device such as a drill bit. The through-hole 80a can also be formed by laser irradiation. Furthermore, a hole 24a is formed, penetrating the metal foil 42a and the third insulating layer 24 and exposing the electrode surface 61 of the component 60. The hole 24a is formed, for example, by laser irradiation.

[0073] like Figure 3GAs shown, a conductor is formed in the through-hole 80a of the intermediate substrate 2. Seed films are formed on the metal foil of the intermediate substrate 2 and the inner wall of the through-hole. Specifically, seed film 42b is formed on the metal foil 42a of the intermediate substrate 2, and seed film 81b is formed on the inner wall of the through-hole 80a. Seed film 52b is formed on the metal foil 52a. Seed films 42b, 81b, and 52b are formed simultaneously, for example, by chemical plating or sputtering to form a metal film. An electroplated film is formed, which serves as the power supply layer for the metal layer used as the seed film. Electroplated films 42c, 81c, and 52c are formed on the seed films. An inner wall conductor 81, composed of seed film 81b and electroplated film 81c, is formed on the inner wall of the through-hole. Electroplated film 42c fills the hole 24a. A connecting conductor 46 is formed by the seed layer 42b formed on the inner wall of the hole 24a and the electroplated layer 42c filling the hole 24a.

[0074] The cavity of the through hole 80a is filled with a filler material 82. For example, resins such as epoxy resin, acrylic resin, or phenol are injected from one or both ends of the through hole 80a. The filler material 82 can also be filled with a conductive paste containing conductive particles such as silver particles instead of an insulating resin such as epoxy resin. The insulating resin such as epoxy resin or the conductive paste used for the filler material 82 is cured by heating or the like as needed to form the filler material 82. The through hole 80 is formed in the through hole 80a by an inner wall conductive layer 81 and the filler material 82. The end faces of the cured filler material 82 can be ground as needed by any method such as chemical grinding or mechanical grinding. Preferably, by this grinding, the two end faces of the filler material 82 are approximately flush with the surfaces of the electroplated films 42c and 52c, respectively.

[0075] Furthermore, a seed film 42d and an electroplated film 42e are sequentially formed on the electroplated film 42c and the filler material 82 on the first surface of the intermediate substrate 2. Simultaneously, a seed film 52d and an electroplated film 52e are sequentially formed on the electroplated film 52c and the filler material 82 on the second surface of the intermediate substrate 2. The seed films 42d, 52d and the electroplated films 42e, 52e are formed, for example, by the same method as the seed layers 42b, 52b and the electroplated layers 42c, 52c. A five-layer structure of metal foil film 42a, seed film 42b, electroplated film 42c, seed film 42d, and electroplated film 42e is formed on the third insulating layer 24. A five-layer structure of metal foil 52a, seed film 52b, electroplated film 52c, seed film 52d, and electroplated film 52e is formed on the fourth insulating layer 34. Then, as... Figure 3HAs shown, a first surface conductor layer 42 and a second surface conductor layer 52 with desired conductor patterns are formed by a subtractive method, such as etching using a mask depicting wiring. Simultaneously, a first cover conductor 43, consisting of a seed layer 42d and an electroplated layer 42e, is formed at the end of the filler material 82 on the first side of the insulating layer 20 (third insulating layer 24 side). The first cover conductor 43 has a five-layer structure consisting of a metal foil layer 42a, a seed layer 42b, an electroplated layer 42c, a seed layer 42d, and an electroplated layer 42e. A second cover conductor 53, consisting of a seed layer 52d and an electroplated layer 52e, is formed at the end of the filler material 82 on the second side of the insulating layer 30 (fourth insulating layer 34 side). The second cover conductor 53 also has a five-layer structure consisting of a metal foil layer 52a, a seed layer 52b, an electroplated layer 52c, a seed layer 52d, and an electroplated layer 52e. A multilayer core substrate 100 is formed, comprising a central insulating layer 10, a first side-mounted insulating layer 20, a second side-mounted insulating layer 30, a through-hole 80, a first inner conductor layer 12, a second inner conductor layer 14, a first surface conductor layer 42, and a second surface conductor layer 52. As an example of the multilayer core substrate 100, the thickness T1 of the first inner conductor layer 12 and the second inner conductor layer 14 is 10 μm, and the total number S1 of the first inner conductor layer 12 and the second inner conductor layer 14 is 1 layer. The thickness T2 of the first surface conductor layer 42 and the second surface conductor layer 54 is 25 μm, and the total number S2 of the first surface conductor layer 42 and the second surface conductor layer 54 is 5 layers.

[0076] Layers are formed on both sides of the multilayer core substrate 100. A first layer 110 is formed on the first surface 100F of the multilayer core substrate 100. A second layer 120 is formed on the second surface 100S of the multilayer core substrate 100. For example, a film-like insulating resin (e.g., epoxy resin) without reinforcing material is hot-pressed onto the first surface 100F and the second surface 100S to form an insulating layer 111 on the first surface 100F side and an insulating layer 121 on the second surface 100S side of the two insulating layers 111. Through-holes are formed at the formation sites of the via conductors 113 or 123 of the insulating layers 111 and 121, for example, using a carbon dioxide laser. Seed films made of conductors such as copper are formed on the inner walls of the through-holes and on the surfaces of the insulating layers 111 and 121 by chemical plating or sputtering. A seed film is used as the power supply layer, and a resist with openings for forming conductor layers is formed. Electroplating is then performed through these openings to form an electroplated film. Conductor layers 112 and 122, consisting of the seed layer and the electroplated layer, as well as via conductors 113 and 123, are formed through resist stripping and etching. Specifically, conductor layer 112 on the first side 100F and conductor layer 122 on the second side 100S of the two conductor layers 112 are formed using a semi-additive process (SAP) without metal foil. A via conductor 113 penetrating the insulating layer 111 on the first side 100F and a via conductor 123 penetrating the insulating layer 121 on the second side 100S are formed together with these conductor layers 112 and 122.

[0077] Furthermore, the insulating layers 111 and 121 on the surface side are formed using the same method as the insulating layers 111 on the first surface 100F side and 121 on the second surface 100S side. Additionally, the conductor layers 112 and 122 on the surface side are formed using the same method as the conductor layers 112 on the first surface 100F side and 122 on the second surface 100S side. Furthermore, the via conductors 113 and 123 penetrating the insulating layers 111 and 121 on the surface side are formed using the same method as the via conductor 113 penetrating the insulating layer 111 on the first surface 100F side and the via conductor 123 penetrating the insulating layer 121 on the second surface 100S side. Thus, the first stacked layer 110 and the second stacked layer 120 are formed. As a result, the wiring substrate 1 of the embodiment is obtained. Figure 1 ).

[0078] In the wiring substrate 1 of this embodiment, the via 80 is connected to the first surface conductor layer 42, the second surface conductor layer 52, the first inner conductor layer 12, and the second inner conductor layer 14. The via 80 is connected to four conductor layers. Therefore, since the number of conductor layers connected to the via is reduced, delay is suppressed through the transmission of signal lines within the via 80. Furthermore, since signal delay is suppressed, the parasitic capacitance of the via 80 is reduced. Specifically, compared to the number of conductor layers in the via of the multilayer core substrate in Patent Document 1, the number of conductor layers connected to the via is reduced in the wiring substrate 1 of this embodiment.

[0079] In the wiring substrate of this embodiment, the via is connected to a first surface conductor layer, a second surface conductor layer, a first inner conductor layer, and a second inner conductor layer. The via is connected to four conductor layers. Therefore, since the number of conductor layers connected to the via is reduced, delay is suppressed through the transmission of signal lines within the via. Furthermore, since signal delay is suppressed, the parasitic capacitance of the via is reduced.

Claims

1. A wiring substrate comprising a multilayer core substrate and laminated layers, wherein, The multilayer core substrate is formed by a central insulating layer, a first side insulating layer, and a second side insulating layer, and the multilayer core substrate has through holes, an inner conductor layer, and a surface conductor layer. The first side insulating layer is formed by at least two insulating layers on the first side of the central insulating layer. The second-side insulating layer is formed by at least two insulating layers on the second-side of the central insulating layer. The inner conductor layer is composed of a first inner conductor layer and a second inner conductor layer. A first inner conductor layer is formed on the first surface of the central insulating layer, and a second inner conductor layer is formed on the second surface of the central insulating layer. The surface conductor layer is composed of a first surface conductor layer and a second surface conductor layer. The first surface conductor layer is formed on the outermost layer of the first surface-side insulating layer. The second surface conductor layer is formed on the outermost layer of the second side insulating layer. The via is formed between the first surface conductor layer and the second surface conductor layer, and the via is also connected to the first inner conductor layer and the second inner conductor layer. A component is disposed within the insulating layer on the first side.

2. The wiring substrate according to claim 1, wherein, The thickness T1 of the inner conductor layer and the thickness T2 of the outer conductor layer satisfy the relationship of Equation 1. T1 < T2… Equation 1.

3. The wiring substrate according to claim 1, wherein, The number of inner conductor layers S1 and the number of outer conductor layers S2 satisfy the relationship in Equation 2. S1 < S2 ... Equation 2.

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