Semiconductor device and method of manufacturing the same, memory system

Abstract

The embodiments of the present disclosure disclose a semiconductor device, a manufacturing method thereof and a memory system, the semiconductor device comprising: a first semiconductor structure, the first semiconductor structure comprising: a semiconductor layer; a first transistor, a first active region of the first transistor being located in the semiconductor layer; and a first connection structure, the first connection structure at least penetrating the semiconductor layer covering the first active region in a first direction; wherein the first connection structure is connected with the first active region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and its fabrication method, as well as a memory system. Background Technology

[0002] Some semiconductor devices, such as memory devices, can be used to store information. Some semiconductor memories, including both non-volatile and volatile memories, have gradually become widely used products in the storage market due to their high storage density, controllable production costs, suitable read / write speeds, and retention characteristics. However, as people's requirements for storage devices continue to increase, there is still much room for improvement in storage devices and their manufacturing methods. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a semiconductor device is provided, including a first semiconductor structure, the first semiconductor structure including: a semiconductor layer; a first transistor, a first active region of the first transistor being located in the semiconductor layer; a first connection structure extending through and covering the semiconductor layer along a first direction at least covering the first active region; wherein the first connection structure is connected to the first active region.

[0004] In some embodiments, the first semiconductor structure further includes: a pad located on the side of the first connection structure away from the first active region; the pad is connected to the first connection structure.

[0005] In some embodiments, the dimension of the end of the first connection structure near the first active region in the second direction is less than or equal to the dimension of the end of the first connection structure away from the first active region in the second direction; the second direction intersects the first direction.

[0006] In some embodiments, the first semiconductor structure further includes: a first conductive layer located on the side of the first active region away from the first connection structure, the first conductive layer being in contact with the first active region; and the first connection structure penetrating the first active region and in contact with the first conductive layer.

[0007] In some embodiments, the constituent materials of the first conductive layer include at least one of metal oxides or metal silicides.

[0008] In some embodiments, the first semiconductor structure further includes: a second conductive layer located between the first connection structure and the first active region; the second conductive layer is connected to the first connection structure on one side of the first direction and to the first active region on the other side.

[0009] In some embodiments, the resistance of the constituent material of the second conductive layer is less than or equal to the resistance of the constituent material of the first connection structure.

[0010] In some embodiments, the constituent materials of the second conductive layer include at least one of ruthenium or ruthenium alloys.

[0011] In some embodiments, the second conductive layer extends into the first active region along the first direction.

[0012] In some embodiments, the semiconductor layer has a first side and a second side disposed opposite to each other in the first direction, and the pad is located on the second side of the semiconductor layer; the first active region of the first transistor is close to the first side of the semiconductor layer relative to the pad; the first semiconductor structure further includes: a peripheral circuit, the peripheral circuit including the first transistor, and at least a portion of the peripheral circuit is located on the first side of the semiconductor layer.

[0013] In some embodiments, the semiconductor device further includes: a second semiconductor structure located on the side of the peripheral circuit away from the semiconductor layer; the second semiconductor structure is bonded to the first semiconductor structure.

[0014] In some embodiments, the second semiconductor structure includes: a second transistor including a first doped region, a second doped region, and a gate layer; a bit line connected to the first doped region; and a capacitor structure connected to the second doped region; wherein the bit line is located between the second transistor and the peripheral circuit, and the second transistor is located between the bit line and the capacitor structure.

[0015] In some embodiments, the second transistor includes: a semiconductor body extending along the first direction; a first doped region and a second doped region located at opposite ends of the semiconductor body in the first direction; wherein the gate layer extends along a direction intersecting the first direction, and the gate layer covers a portion of the sidewall of the semiconductor body extending along the first direction.

[0016] According to some aspects of the present public embodiments, a method for fabricating a semiconductor device is provided, comprising: providing a first semiconductor structure; bonding the first semiconductor structure to a second semiconductor structure; the first semiconductor structure including a semiconductor layer, wherein the semiconductor layer has a first active region having a first transistor; forming a first connection structure extending along a first direction; wherein the first connection structure at least penetrates the semiconductor layer covering the first active region, and the first connection structure is connected to the first active region.

[0017] In some embodiments, the method of forming the first connection structure includes: etching at least the semiconductor layer on the first active region to form a first opening; and forming the first connection structure in the first opening.

[0018] In some embodiments, the first active region is located on the first conductive layer; the fabrication method further includes: etching the first active region to make the first opening penetrate the first active region; wherein the bottom of the first opening exposes the first conductive layer.

[0019] In some embodiments, the bottom of the first opening exposes the first active region, and the manufacturing method further includes: forming a second conductive layer at the bottom of the first opening, the second conductive layer being connected to the first active region; and forming the first connection structure on the second conductive layer, the first connection structure being connected to the second conductive layer.

[0020] In some embodiments, the semiconductor layer has a first side and a second side disposed opposite to each other in the first direction, and the method of forming the first active region includes: doping the first side of the semiconductor layer to form the first active region; the method of fabricating the first semiconductor structure includes: forming a peripheral circuit on the first side of the semiconductor layer; the peripheral circuit includes the first transistor, and the first active region of the first transistor is close to the first side of the semiconductor layer.

[0021] In some embodiments, the fabrication method further includes: bonding the side of the peripheral circuit away from the semiconductor layer to the second semiconductor structure; and forming the first connection structure along the side of the first semiconductor structure away from the second semiconductor structure.

[0022] In some embodiments, the fabrication method further includes: forming a pad on the side of the first connection structure away from the first active region, the pad being connected to the first connection structure; the pad being located on a second side of the semiconductor layer.

[0023] In some embodiments, the method of fabricating the second semiconductor structure includes: forming a second transistor, the second transistor including a first doped region, a second doped region, and a gate layer; forming a bit line connected to the first doped region; and forming a capacitor structure connected to the second doped region; wherein the bit line is located between the second transistor and the peripheral circuit, and the second transistor is located between the bit line and the capacitor structure.

[0024] In some embodiments, a method of forming the second transistor includes: forming a semiconductor body extending along a first direction, wherein a first doped region and a second doped region are located at two opposite ends of the semiconductor body disposed in the first direction; forming the gate layer on a side of the semiconductor body; wherein the gate layer extends along a direction intersecting the first direction, and the gate layer covers a portion of the sidewall of the semiconductor body extending along the first direction.

[0025] According to some aspects of embodiments of this disclosure, a memory system is provided, including: the semiconductor device; and a memory controller connected to and controlling the semiconductor device.

[0026] This disclosure provides a semiconductor device including a first semiconductor structure. The first semiconductor structure may include a semiconductor layer, a first transistor, and a first connection structure. The first active region of the first transistor may be located in the semiconductor layer. The first connection structure extends through the semiconductor layer covering the first active region in a first direction (e.g., the thickness direction). The first connection structure is connected to the first active region to supply power to the first transistor or to supply power to a circuit composed of the first transistor. This reduces the area occupied by the first semiconductor structure on the device and helps to improve the integration density of the semiconductor device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a storage array according to an exemplary embodiment;

[0028] Figures 2 to 4 This is a schematic diagram of a semiconductor device according to an example embodiment;

[0029] Figures 5 to 8 This is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0030] Figure 9 This is a schematic diagram of a semiconductor device fabrication process according to an embodiment of the present disclosure;

[0031] Figures 10 to 20 This is a schematic diagram of semiconductor device fabrication according to embodiments of the present disclosure;

[0032] Figure 21 and Figure 22 This is a schematic diagram of an exemplary system according to an embodiment of the present disclosure. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0039] The semiconductor devices mentioned in the embodiments of this disclosure may include memory structures, and may serve as memory devices, or as at least a part of memory devices, such as Dynamic Random Access Memory (DRAM), or at least as at least a part of DRAM. The semiconductor devices provided in the embodiments of this disclosure may be memory devices or at least a part of memory devices. The semiconductor devices may be DRAM, or at least a portion of DRAM, or the memory devices may include DRAM. DRAM may include the semiconductor devices of this disclosure, and is applicable to Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR4 memory specifications, Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR5 memory specifications, and Low Power Double Data Rate DRAM using LPDDR5 memory specifications. The examples of semiconductor devices, semiconductor structures, memory devices, and memory devices described in the embodiments of this disclosure are merely illustrative, merely illustrating a hierarchical logical division of inclusion relationships for ease of explanation. In actual implementation, there may be other division methods, which this disclosure does not limit. In some other embodiments, multiple structures, chips, units, or components may be combined, integrated into another system, or some features may be ignored or not included.

[0040] In some embodiments, in DRAM, the memory array can be arranged in rows and columns, allowing memory cells to be addressed by specifying the rows and columns of the array. The memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting a memory cell at the intersection of a selected word line and a selected bit line selects it for read, write, or refresh operations. Figure 1 As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is connected to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is connected to the bit line. The other electrode of the capacitor may be grounded or have an additional voltage (such as Vcc / 2) applied to it. Figure 1As shown, the memory cell array is arranged in an x-column, y-row configuration. The rows and columns can be perpendicular or not. The z-direction is either vertical or the thickness direction of the device, and can be the first direction in this embodiment. The xoy plane intersects with or is perpendicular to the z-direction, and the x-direction can be the second direction in this embodiment. The y-direction can be a third direction in this embodiment. The extension direction of word lines or rows can be parallel to the y-direction or at an angle to it. The extension direction of bit lines or columns can be parallel to the x-direction or at an angle to it. The orthographic projection of the word line onto the xoy plane is perpendicular to the orthographic projection of the bit line onto the xoy plane, or they may not be perpendicular but have an angle between them.

[0041] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0042] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0043] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1 Peripheral circuitry connected to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to, sense amplifier circuitry, row decoding circuitry, column decoding circuitry, and voltage generation circuitry. The sense amplifier circuitry is connected to the bit lines and is configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sense amplifier circuitry may include latches to latch the reconstructed capacitor voltage value, allowing information stored in the memory cell to be transferred from the capacitor to the amplifier circuitry. The sense amplifier circuitry may include differential sense amplifier circuitry connected to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuitry is configured to address the memory array and apply operating voltages to the word lines. The column decoding circuitry is configured to address the memory array by column, applying or receiving bit line voltages. The voltage generation circuitry generates the required high and low voltages for each device.

[0044] In some embodiments, the peripheral circuit may include a CMOS structure or CMOS circuit, including digital or analog circuits composed of transistors, for controlling the memory array or powering the memory array. Increasing the device integration of the peripheral circuit is beneficial to increasing the overall integration of the memory device, and improving the stability of the peripheral circuit devices is beneficial to improving the operational stability of the memory device.

[0045] In some embodiments, Figure 2 A semiconductor device 10 is provided, including a first semiconductor structure 11 and a second semiconductor structure 12 stacked along the z-direction. The first semiconductor structure 11 and the second semiconductor structure 12 can be interconnected by hybrid bonding to achieve electrical signal interconnection, which may include power supply, data transmission, control signal interaction, etc. The first semiconductor structure 11 and the second semiconductor structure 12 can be connected by a bonding layer having bonding contacts 131. The bonding layer may include a dielectric layer, and the bonding contacts 131 may penetrate the dielectric layer. The first semiconductor structure 11 and the second semiconductor structure 12 achieve electrical signal interconnection through the bonding contacts 131. In some embodiments, the first semiconductor structure 11 and the second semiconductor structure 12 may not be connected by bonding. The first semiconductor structure 11 may be stacked on the second semiconductor structure 12, and the bonding contacts 131 may not be provided. Alternatively, conductive contacts or other connection structures may be provided between the two semiconductor structures to achieve electrical signal interconnection.

[0046] Reference Figure 2As shown, the first semiconductor structure 11 may include, but is not limited to, peripheral circuits 110, and the second semiconductor structure 12 may include memory cells, memory structures, or memory arrays composed of memory cells. The memory cells may include transistors and capacitor structures 122 connected to the transistors (e.g., the second transistor 121), or the memory cells may include NAND, SRAM, or other memory cells. The second semiconductor structure 12 can control the operation of the first semiconductor structure 11 and provide different voltages to different devices in the first semiconductor structure 11, providing different voltages according to different timing sequences. Before the first semiconductor structure 11 and the second semiconductor structure 12 are bonded, the surfaces to be bonded of the first semiconductor structure 11 and the second semiconductor structure 12 respectively have a first bonding layer with multiple first bonding contacts and a second bonding layer with multiple second bonding contacts. The first bonding contacts and the second bonding contacts respectively lead the electrical signals of the semiconductor structure to the surfaces to be bonded. The bonding contacts may include pads 132, conductive plugs, or other structures. The surfaces to be bonded or the layers to be bonded of the first semiconductor structure 11 and the second semiconductor structure 12 are bonded, and the two surfaces to be bonded form a bonding interface. The first bonding layer and the second bonding layer are bonded at the bonding interface to achieve bonding and fixation of the first semiconductor structure 11 and the second semiconductor structure 12. A larger bonding area provides a larger bonding force. After bonding, the first and second bonding layers may not have a physical boundary and can be considered as bonding layers. Similarly, after bonding, the first bonding contact 131 and the second bonding contact 131 may not have a physical boundary and can be considered as bonding contact 131. The bonding contact 131 penetrates the bonding interface, which is formed after the two dielectric layers or the two layers to be bonded contact and bond. The portion of the bonding contact 131 located in the first semiconductor structure 11 is the first bonding contact 131 before bonding, and the portion of the bonding contact 131 located in the second semiconductor structure 12 is the second bonding contact 131 before bonding. The bonding contact 131 leads the electrical signals of the first semiconductor structure 11 and the second semiconductor structure 12 to the bonding interface for electrical signal interconnection. The bonding contact 131 can be connected to various parts of the semiconductor structure through conductive structures such as wiring layers, connection structures, and contact structures.

[0047] In some embodiments, refer to Figure 2As shown, the second semiconductor structure 12 may include connection structures extending along the z-direction, such as a first connection structure 141. The first connection structure 141 may be connected to an interconnect layer 151. The side of the interconnect layer 151 closest to the first semiconductor structure 11 is connected to a bonding contact 131, and the side of the interconnect layer 151 furthest from the first semiconductor structure 11 is connected to various components of the second semiconductor structure 12, such as a memory array in the second semiconductor structure 12. The first connection structure 141 can be used to connect to an external integrated circuit and interact with it via electrical signals. The external integrated circuit can provide power, data transmission, and control signal interaction to the first semiconductor structure 11 and the second semiconductor structure 12 through the first connection structure 141. The interconnect layer 151 may include multiple stacked wiring layers, with adjacent wiring layers connected by conductive plugs, conductive channels, and conductive strips. The first connection structure 141 may include multiple sub-connection structures stacked and connected in the z-direction.

[0048] In some embodiments, refer to Figure 2 and Figure 3 As shown, the first semiconductor structure 11 may include peripheral circuits 110, which may include, but are not limited to, digital or analog circuits such as sensing amplification circuits, row decoding circuits, column decoding circuits, and voltage generation circuits. The peripheral circuits 110 may include, but are not limited to, transistors and other devices. The first semiconductor structure 11 may include a semiconductor layer 100 and a first transistor 111. The semiconductor layer 100 may be doped to form an active region, and the first active region 1111 of the first transistor 111 may be located in the semiconductor layer 100, for example, the first active region 1111 may be located in at least a portion of the active region of the semiconductor layer 100. The first active region 1111 of the first transistor 111 can be the source and drain of the transistor; the first transistor 111 also includes a gate 1114; the source, drain, channel region 1113 and gate 1114 of the first transistor 111 can be respectively provided with connection structures and connected to the wiring layer; at least one of the source, drain, channel region 1113 and gate 1114 of the first transistor 111 can be connected to the bonding contact 131, or connected to the bonding contact 131 through the wiring layer.

[0049] In some embodiments, refer to Figure 2 As shown, the second semiconductor structure 12 may include a memory array, which may include, but is not limited to, DRAM, phase-change memory structure, resistive switching memory structure, or magnetic switching memory structure. Figure 3 The second semiconductor structure 12 may include a DRAM memory array, and may include at least transistors and a capacitor structure 122 connected to the transistors, for example, a second transistor 121 connected to the capacitor structure 122. In some other embodiments, Figure 3The capacitor structure 122 can be replaced with a phase-change memory structure, a resistive switching memory structure, or a magnetic switching memory structure to form other memory devices. The specific structures of the second transistor 121 and the capacitor structure 122 are not limited. For example, the second transistor 121 may include a planar transistor, a vertical transistor extending along the z-direction, or other transistor shapes. The capacitor structure 122 may include a first electrode, a dielectric layer, and a second electrode. The dielectric layer electrically isolates the first electrode and the second electrode. One electrode in the capacitor structure 122 may extend along the z-direction and may be columnar in shape. The semiconductor device 10 also includes a first connection structure 141 located in the second semiconductor structure 12, and a pad 132 located on the side of the first connection structure 141 away from the first semiconductor structure 11. The pad 132 is connected to the first connection structure 141 and serves as an I / O interface for power supply and communication with the semiconductor device 10.

[0050] In some embodiments, refer to Figure 3 As shown, the second semiconductor structure 12 may include: a second transistor 121, including a first doped region, a second doped region, and a gate layer 1213; a bit line 123 connected to the first doped region; and a capacitor structure 122 connected to the second doped region. The bit line 123 is located between the second transistor 121 and the peripheral circuit 110, and the second transistor 121 is located between the bit line 123 and the capacitor structure 122. The first doped region and the second doped region may be either the source or the drain of the second transistor 121, and the positions of the source and drain can be interchanged.

[0051] In some embodiments, refer to Figure 3 As shown, the second transistor 121 may include: a semiconductor body 1211 extending along the z-direction; a first doped region and a second doped region located at opposite ends of the semiconductor body 1211 along the z-direction; wherein, a gate layer 1213 extends along a direction intersecting the z-direction, and the gate layer 1213 covers a portion of the sidewall of the semiconductor body 1211 extending along the z-direction. A bit line 123 may extend along the x-direction, and the gate layer 1213 may extend along the y-direction, serving as a word line for the memory array; the x and y directions intersect and are perpendicular; the z-direction may be perpendicular to the xoy plane. Figure 3 As exemplified, the semiconductor device 10 may include a pad 132 disposed in the z-direction, a capacitor structure 122, a second transistor 121, a bit line 123, a bonding contact 131, peripheral circuitry 110, and a semiconductor layer 100.

[0052] The second transistor 121 may include a semiconductor body 1211 extending along the z-direction, and the semiconductor body 1211 may include semiconductor pillars extending along the z-direction. The semiconductor body 1211 has a first end and a second end disposed opposite to each other in the z-direction. A first doped region connected to the bit line 123 may be located at the end of the semiconductor body 1211 relatively close to the first semiconductor structure 11, and a second doped region connected to the capacitor structure 122 may be located at the end of the semiconductor body 1211 relatively far from the first semiconductor structure 11. The region between the first doped region and the second doped region is a channel region. A gate layer 1213 extends along the y-direction and covers the sidewalls of the semiconductor body 1211 extending along the z-direction, such as covering the sidewalls between the first end and the second end of the semiconductor body 1211. The gate layer 1213 serves as the control gate of the second transistor 121 to control the conduction and cutoff of the second transistor 121. A gate dielectric layer 1212 is located between the semiconductor body 1211 and the gate layer 1213. The cross-sectional shape of the semiconductor body 1211 in the xoy plane may include, but is not limited to: rectangle, quadrilateral, other polygons; circle, ellipse or other irregular shape, etc., and this disclosure does not impose any restrictions on it.

[0053] For example, a semiconductor body 1211, a gate layer 1213, and a gate dielectric layer 1212 can constitute a second transistor 121. Dielectric material can be filled between adjacent second transistors 121. The dielectric material may include or form an air gap 126 to reduce inductive capacitance. A conductive structure 125 can be provided between adjacent semiconductor bodies 1211 to reduce crosstalk between adjacent second transistors 121. The conductive structure 125 and the gate layer 1213 can be disposed on opposite sides of a semiconductor body 1211 in the x-direction. When the gate layer 1213 applies a turn-on voltage to the second transistor 121, the conductive structure 125 can be grounded or connected to a fixed voltage (e.g., a negative voltage) to reduce crosstalk between the second transistors 121. The fixed voltage may be a fixed voltage value calibrated during the factory testing phase of the memory device, or a calibrated voltage range.

[0054] For example, taking two adjacent conductive structures 125 in the x direction as an example, two semiconductor bodies 1211 can be disposed between the two adjacent conductive structures 125, two gate layers 1213 disposed face-to-face are disposed between the two semiconductor bodies 1211, and an air gap 126 is disposed between the two gate layers 1213 disposed face-to-face. Figure 3One semiconductor body 1211 can correspond to one gate layer 1213, and two semiconductor bodies 1211 can share one conductive structure 125. In other embodiments, to increase the gate structure control performance of the semiconductor body 1211, one semiconductor body 1211 can be provided with two gate layers 1213, or a fully surrounding gate layer 1213 can be provided around the sidewalls of the semiconductor body 1211. To adapt to the increased integration of the semiconductor device 10 and the reduction of parasitic capacitance and parasitic resistance, the conductive structure 125 can also have other arrangements, such as one semiconductor body 1211 corresponding to one conductive structure 125.

[0055] The semiconductor body 1211 may have the same type of doping at its first and second ends in the z-direction to serve as the first and second doped regions, respectively, acting as the drain and source of the second transistor 121. The drain and source can be interchanged. The intermediate region between the first and second ends may have a doping type opposite to that at the first end to serve as the channel of the second transistor 121. The first end of the semiconductor body 1211 near the bit line 123 may be heavily doped or a metal silicide may be formed to reduce the contact resistance between the semiconductor body 1211 and the bit line 123. The bit line 123 may include a metallic conductive material or a metal-semiconductor compound. For example, the semiconductor body 1211 may include silicon, and the bit line 123 may include a metal silicide, such as tungsten silicide or titanium silicide; or it may include a metal silicide layer and a metal layer deposited on the side of the metal silicide layer away from the semiconductor body 1211 to form the bit line 123. The metal layer may include, but is not limited to, tungsten, copper, aluminum, etc.

[0056] Gate layer 1213 can serve as word lines, and one gate layer 1213 can correspond to multiple semiconductor bodies 1211 arranged in the y-direction; bit line 123 extends along the x-direction, and one bit line 123 can correspond to multiple semiconductor bodies 1211 arranged in the x-direction. Selecting gate layer 1213 and bit line 123 allows selection of the semiconductor body 1211 corresponding to both gate layer 1213 and bit line 123, enabling the semiconductor body 1211 to conduct and select capacitor structure 122. Charging and discharging capacitor structure 122 or sensing the amount of charge can then be used to perform write, refresh, or read operations.

[0057] Reference Figure 4The illustrated second transistor 121 and capacitor structure 122 are partially enlarged schematic diagrams. The capacitor structure 122 may include a first electrode 1221 extending along the z-direction, a dielectric layer 1223 surrounding the first electrode 1221, and a second electrode 1222 surrounding the dielectric layer 1223. The dielectric layer 1223 is located between the first electrode 1221 and the second electrode 1222. The second electrode 1222 is connected to a second end of the semiconductor body 1211 away from the bit line 123, i.e., the second electrode 1222 is connected to a second doped region of the semiconductor body 1211. The dimension in the x-direction of the end of the capacitor structure 122 away from the semiconductor body 1211 in the z-direction may be greater than or equal to the dimension in the z-direction of the end of the capacitor structure 122 close to the semiconductor body 1211. The first electrodes 1221 of multiple capacitor structures 122 may be connected to an interconnect layer (e.g., ...). Figure 3 The first interconnect layer 124 is used to ground or connect to other operating voltages. Alternatively, multiple capacitor structures 122 share a first electrode 1221, which has a film structure extending along the x and / or y directions at the end away from the semiconductor body 1211. The first electrode 1221 is grounded or connected to other operating voltages, and the multiple capacitor structures 122 share the first electrode 1221 and are connected to a common voltage.

[0058] In some embodiments, a contact portion may be provided between the capacitor structure 122 and the semiconductor body 1211. The semiconductor body 1211 is connected to the capacitor structure 122 through the contact portion. The contact portion may include a metal silicide to reduce the contact resistance between the semiconductor body 1211 and the capacitor structure 122 and improve the adhesion, such as titanium silicide. The contact portion may include a multilayer structure. The portion near the semiconductor body 1211 and the portion in contact with the semiconductor body 1211 may include a metal silicide to reduce contact resistance and improve adhesion; the portion in contact with the capacitor structure 122 may include metal to improve electrical connection performance.

[0059] For example, the semiconductor body 1211 may include, but is not limited to, elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. It may also include materials such as indium gallium zinc oxide (IGZO), which may be composed of oxides of elements such as indium, gallium, and zinc, exhibiting superior semiconductor properties. The addition of indium and gallium can improve the electron mobility of the semiconductor material, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps improve the stability of the semiconductor material. The IGZO material allows the semiconductor body 1211 to directly contact and connect with the metal material of the bit line 123, capacitor structure 122, or other contact structures, reducing contact resistance.

[0060] The gate layer 1213, the first electrode 1221, the second electrode 1222, and the first connection structure 141 may include, but are not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, chromium, cobalt, or nickel. In addition to the aforementioned conductive materials, the bit line 123 may also include doped semiconductor materials, such as doped silicon, or may also include metal silicides.

[0061] The gate dielectric layer 1212 may include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The gate dielectric layer 1212 may be the same as or similar to the dielectric material filling the space between adjacent semiconductor bodies 1211, and may not have a clear physical boundary.

[0062] In some embodiments, refer to Figure 3 As shown, the semiconductor device 10 also includes a pad 132 located on the side of the second semiconductor structure 12 away from the first semiconductor structure 11. The pad 132 is connected to the first connection structure 141. The pad 132 can serve as the I / O interface of the semiconductor device 10, providing power and communication to the semiconductor device 10. The bit line 123, gate layer 1213, capacitor structure 122, and pad 132 can lead electrical signals to the bonding interface through the interconnect layer and connection structure, and connect to the bonding contact 131, which in turn connects to the peripheral circuit 110 in the first semiconductor structure 11. The interconnect layer can include a wiring layer, a circuit layer, or multiple stacked wiring layers connected by conductive vias or conductive plugs. The connection structure can include conductive plugs, conductive vias, or multiple stacked and connected conductive plugs.

[0063] For example, pad 132 can be connected to bonding contact 131 via first connection structure 141; bit line 123 can be connected to bonding contact 131 via second connection structure 142; multiple capacitor structures 122 can be connected via first interconnect layer 124, and first interconnect layer 124 can be connected to bonding contact 131 via third connection structure 143; as Figure 3 The first electrode 1221 of the capacitor structure 122 is connected to the first interconnect layer 124; the first transistor 111 or other device structure in the peripheral circuit 110 can be connected to the bonding contact 131 by a connection structure; the gate layer 1213 can be connected to the bonding contact 131 by other connection structures, such as a fourth connection structure on at least one end of the gate layer 1213 in the y direction, to lead the electrical signal of the gate layer 1213 to the bonding contact 131. The fourth connection structure is not shown because the cross-sectional direction is blocked.

[0064] In some embodiments, it may be Figure 3The first connection structure 141 is disposed in the first semiconductor structure 11, which can reduce the size of the first connection structure 141 in the z direction. The first connection structure 141 can be connected to the first transistor 111 in the first semiconductor structure 11, which can help reduce the area occupied by the peripheral circuit 110.

[0065] According to some aspects of embodiments of this disclosure, Figure 5 A semiconductor device 10 is provided, including a first semiconductor structure 11, the first semiconductor structure 11 including: a semiconductor layer 100; a first transistor 111, the first active region 1111 of the first transistor 111 being located in the semiconductor layer 100; a first connection structure 141 extending through at least the semiconductor layer 100 covering the first active region 1111 along a first direction (z direction); wherein the first connection structure 141 is connected to the first active region 1111.

[0066] The first semiconductor structure 11 may include peripheral circuitry 110, which may include a first transistor 111. The first transistor 111 may include active regions with different doping types, such as a source, a drain, and a channel region 1113. The first active region 1111 may serve as either the source or drain of the first transistor 111, and the positions of the source and drain can be interchanged. The first transistor 111 also includes a gate 1114 and a first dielectric layer 1115 located between the gate 1114 and the channel region 1113. The first dielectric layer 1115 may cover the channel region 1113 and other areas of the semiconductor layer 100. Multiple transistors may share the first dielectric layer 1115 as a gate dielectric. The semiconductor layer 100 may be doped to form the first active region 1111 and the channel region 1113. The doping type of the first active region 1111 is opposite to that of the channel region 1113. The first active region 1111 is located within the semiconductor layer 100. For example, a first active region 1111 is formed by doping the first side of the semiconductor layer 100. A gate 1114, a first dielectric layer 1115 and other device structures can be provided on the first side of the semiconductor layer 100 to form a peripheral circuit 110. The side of the peripheral circuit 110 away from the semiconductor layer 100 is used to bond with the second semiconductor structure 12.

[0067] For example, semiconductor layer 100 may include a first side and a second side disposed opposite to each other in the z-direction. The first side of semiconductor layer 100 is the side of semiconductor layer 100 relatively closer to the second semiconductor structure 12, and the second side of semiconductor layer 100 is the side of semiconductor layer 100 relatively farther away from the second semiconductor structure 12. Before bonding, the first side of semiconductor layer 100 may be the front side of semiconductor layer 100, and the second side of semiconductor layer 100 may be the back side of semiconductor layer 100. Semiconductor layer 100 may be a semiconductor substrate, a semiconductor wafer, or a semiconductor layer 100 epitaxially grown on a substrate or wafer. The substrate may be removed, or the back side of semiconductor layer 100 may be thinned. After the first semiconductor structure 11 and the second semiconductor structure 12 are bonded, the first side of semiconductor layer 100 and the portion of peripheral circuit 110 located on the first side of semiconductor layer 100 are covered and not exposed. Figure 5 The second side of the semiconductor layer 100 may be exposed or a dielectric layer may be formed on the second side of the semiconductor layer 100 to protect the semiconductor layer 100.

[0068] In some embodiments, a first doping is performed on a first side of the semiconductor layer 100 to form a channel region 1113 of a first transistor 111. The thickness of the channel region 1113 in the z-direction is less than or equal to the thickness of the semiconductor layer 100, and one side surface of the channel region 1113 in the z-direction is exposed relative to the semiconductor layer 100 in the z-direction. A second doping is performed on the channel region 1113 to form a first active region 1111 and a second active region 1112 spaced apart. One side surface of the first active region 1111 and the second active region 1112 in the z-direction is exposed relative to the channel region 1113 in the z-direction, and the thickness of the first active region 1111 and the second active region 1112 in the z-direction is less than that of the channel region 1113. The first active region 1111 and the second active region 1112 serve as the source and drain of the first transistor 111, respectively. The channel region 1113, the first active region 1111, the second active region 1112, and the semiconductor layer 100 body (or, an intrinsic semiconductor portion, or a lightly doped portion) have different doping concentrations and may not have physical boundaries. The gate 1114 may cover the channel region 1113 between the first active region 1111 and the second active region 1112, and a first dielectric layer 1115 is disposed between the gate 1114 and this portion of the channel region 1113. Connection structures extending along the z-direction may be respectively provided to connect to the gate 1114, the second active region 1112, and the first active region 1111, connecting each part of the first transistor 111 to the interconnect layer.

[0069] In some embodiments, the first semiconductor structure 11 may include a plurality of first transistors 111 or other transistors to form a peripheral circuit 110. The transistors may be isolated from each other by an isolation structure 112 to reduce mutual leakage. The isolation structure 112 may include, but is not limited to, shallow trench isolation. For example, an isolation structure 112 located at the edge of the channel region 1113 of the first transistor 111, the isolation structure 112 penetrating a portion of the thickness of the semiconductor layer 100 in the z direction, and the channel region 1113 located between two isolation structures 112.

[0070] In some embodiments, the first connection structure 141 penetrates the channel region 1113 and the semiconductor layer 100 above the first active region 1111 along the z-direction, or penetrates the semiconductor layer 100 having the channel region 1113. When the semiconductor layer 100 and the channel region 1113 do not have a clear physical boundary, the first connection structure 141 can be regarded as penetrating and covering the semiconductor layer 100 on the first active region 1111, or the doped semiconductor layer 100, and the first connection structure 141 is connected to the first active region 1111. The first connection structure 141 may stop at the surface of the first active region 1111 in the z-direction without extending into the first active region 1111; or the first connection structure 141 may extend into the first active region 1111, or the first connection structure 141 may penetrate the first active region 1111, so that a part of the first connection structure 141 is surrounded by the first active region 1111, increasing the contact area between the first connection structure 141 and the first active region 1111.

[0071] In some embodiments, refer to Figure 6 As shown, the first semiconductor structure 11 further includes a pad 132 located on the side of the first connection structure 141 away from the first active region 1111; the pad 132 is connected to the first connection structure 141. The pad 132 may be located on the side of the first semiconductor structure 11 away from the second semiconductor structure 12, that is, on the dielectric material on the second side of the semiconductor layer 100. The pad 132 can serve as the I / O interface of the semiconductor device 10, providing power and communication to the semiconductor device 10. When the first connection structure 141 supplies power to the semiconductor device 10, the side of the first active region 1111 away from the first connection structure 141 may not have a connection structure.

[0072] In some embodiments, refer to Figure 5 and Figure 6As shown, the dimension of the first connection structure 141 in the x-direction near the first active region 1111 is less than or equal to the dimension of the first connection structure 141 in the x-direction away from the first active region 1111; the x-direction intersects the z-direction. The first connection structure 141 can be formed along the second side of the semiconductor layer 100. After the first semiconductor structure 11 and the second semiconductor structure 12 are bonded, the semiconductor layer 100 can be etched to form an opening that penetrates the semiconductor layer 100 and the channel region 1113. The opening can extend into or penetrate the first active region 1111, and the first connection structure 141 is formed in the opening. Before forming the opening, the semiconductor layer 100 can be thinned on the back side to reduce the amount of etching. Due to the loading effect of etching, the dimension of the opening end of the aperture in the x-direction, or the inner diameter of the opening end of the aperture, can be greater than or equal to the dimension of the bottom of the aperture. This results in the dimension of the first connecting structure 141 in the x-direction at the end away from the first active region 1111 being greater than or equal to the dimension of the contact end between the first connecting structure 141 and the first active region 1111. The cross-sectional shape of the first connecting structure 141 in the xoz plane is not limited in this embodiment. It may include circles, ellipses, or other irregular shapes, including but not limited to rectangles, quadrilaterals, or other regular or irregular polygons.

[0073] In some embodiments, Figure 7 A partially enlarged schematic diagram of the first semiconductor structure 11 is shown, while a portion of the second semiconductor structure 12 is omitted. A second dielectric layer 114 is formed between the first connection structure 141 and the semiconductor layer 100, and between the first connection structure 141 and the channel region 1113. The second dielectric layer 114 laterally surrounds the first connection structure 141 along a direction perpendicular to the z-axis. When the first connection structure 141 extends into or penetrates the first active region 1111, the second dielectric layer 114 may not be provided in the overlapping area between the first connection structure 141 and the first active region 1111.

[0074] In some embodiments, such as Figure 7As shown, the first semiconductor structure 11 further includes: a first conductive layer 113 located on the side of the first active region 1111 away from the first connection structure 141, the first conductive layer 113 being in contact with the first active region 1111; the first connection structure 141 penetrating the first active region 1111 and contacting the first conductive layer 113. After penetrating the first active region 1111 along the z-direction, the first connection structure 141 may stop at the surface of the first conductive layer 113 and contact the first conductive layer 113, or it may extend into the first conductive layer 113 along the z-direction, or it may penetrate the first conductive layer 113 along the z-direction; a portion of the first connection structure 141 is surrounded and contacted by the first active region 1111; a portion of the first connection structure 141 may be surrounded and contacted by the first conductive layer 113. The first conductive layer 113 can serve as a stop layer or a size adjustment layer for the first connection structure 141, reducing over-etching during the etching process of fabricating the first connection structure 141. This reduces the risk of the first connection structure 141 extending excessively through the conductive layer and forming a short circuit with other conductive structures 125, or causing leakage due to insufficient distance from other conductive structures 125. The first conductive layer 113 allows the first connection structure 141 to connect to the first active region 1111 whether it penetrates through or not, thus improving the fabrication process window. The dimension of the first conductive layer 113 in the x-direction can be larger than that of the first active region 1111 in the x-direction, providing a larger landing area in the x-direction and reducing the alignment difficulty of the first connection structure 141.

[0075] In some embodiments, the first connection structure 141 may penetrate the first active region 1111 and contact the first conductive layer 113. A second dielectric layer 114 is provided between the first connection structure 141 and the semiconductor layer 100. The second dielectric layer 114 may extend into the channel layer and the first active region 1111. The second dielectric layer 114 surrounds the sidewall of the first connection structure 141 in a transverse direction perpendicular to the z-direction, thereby reducing leakage current between the first connection structure 141 and the semiconductor layer 100 and the channel region 1113, and reducing the diffusion of the constituent materials of the first connection structure 141.

[0076] In some embodiments, a first conductive layer 113 is provided on the side of an active region other than the first active region 1111 that is away from the first connecting structure 141, serving as a stop layer for the current-leading structure on that active region. For example, a first conductive layer 113 is provided on the side of the second active region 1112 that is away from the first connecting structure 141, covering and contacting the second active region 1112; a fifth connecting structure 145 is located on the side of the second active region 1112 that is away from the first connecting structure 141, extending towards the second active region 1112 along the z-direction, and may stop on the first conductive layer 113, extend into the first conductive layer 113, or penetrate the first conductive layer 113 to connect with the second active region 1112. The fifth connecting structure 145 may penetrate the first conductive layer 113 and stop on the surface of the second active region 1112, with the first conductive layer 113 surrounding the contact end of the fifth connecting structure 145 in a transverse direction perpendicular to the z-direction.

[0077] In some embodiments, the constituent material of the first conductive layer 113 includes at least one of metal oxides or metal silicides. Metal oxides may include, but are not limited to, zinc oxide, indium oxide, tin oxide, indium tin oxide, copper oxide, tungsten oxide, etc.; metal silicides may include, but are not limited to, titanium silicide, tungsten silicide, etc.; the first conductive layer 113 can serve as a stable landing surface for the first connection structure 141, improving the adhesion between the first connection structure 141 and the first active region 1111, reducing the contact resistance between the first connection structure 141 and the first active region 1111, and improving the stability of the device.

[0078] In some embodiments, Figure 8 A partially enlarged schematic diagram of the first semiconductor structure 11 is shown, while a portion of the second semiconductor structure 12 is omitted; as shown Figure 8 As shown, the first semiconductor structure 11 further includes a second conductive layer 115, located between the first connection structure 141 and the first active region 1111. The second conductive layer 115 is connected to the first connection structure 141 on one side in the z-direction and to the first active region 1111 on the other side. The second conductive layer 115 may be located in the channel region 1113, and the thickness of the second conductive layer 115 in the z-direction is smaller than the thickness of the channel region 1113. The second conductive layer 115 is used to connect the first connection structure 141 and the first active region 1111, reducing the contact resistance between the first connection structure 141 and the first active region 1111. The second conductive layer 115 may include metal silicides, such as titanium silicide, tungsten silicide, etc., to reduce the contact resistance between the metal and the semiconductor material and increase adhesion.

[0079] In some embodiments, the resistance of the constituent material of the second conductive layer 115 is less than or equal to the resistance of the constituent material of the first connection structure 141. The constituent material of the first connection structure 141 may include, but is not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, chromium, cobalt, or nickel. In some embodiments, the constituent material of the second conductive layer 115 includes at least one of ruthenium or ruthenium alloys. For example only, the first connection structure 141 may include tungsten or aluminum; and the second conductive layer 115 may include ruthenium.

[0080] In some embodiments, the second conductive layer 115 extends into the first active region 1111 along the z-direction. During the fabrication of the second conductive layer 115 and the first connection structure 141, the semiconductor layer 100 is etched to form an opening along the z-direction that penetrates the semiconductor layer 100 covering the first active region 1111 and the channel region 1113, exposing the first active region 1111. The second conductive layer 115 and the first connection structure 141 are formed within the opening. The first active region 1111 can be over-etched, allowing the opening to extend into but not penetrate the first active region 1111, thus enabling the second conductive layer 115 to extend into the first active region 1111. This increases the fabrication process window for the second conductive layer 115 while simultaneously increasing the contact area between the second conductive layer 115 and the first active region 1111, thereby reducing contact resistance.

[0081] In some embodiments, a second dielectric layer 114 may be provided on the sidewall of the first connection structure 141, and the second dielectric layer 114 surrounds the first connection structure 141 in a transverse direction perpendicular to the z-direction to reduce leakage current; a third dielectric layer may be provided between the second conductive layer 115 and the channel region 1113 to reduce leakage current to the channel region 1113; the second dielectric layer 114 and the third dielectric layer may be continuous films formed by the same deposition process.

[0082] In some embodiments, refer to Figure 6As shown, the semiconductor layer 100 has a first side and a second side disposed opposite to each other in the z direction, and the pad 132 is located on the second side of the semiconductor layer 100; the first active region 1111 of the first transistor 111 is close to the first side of the semiconductor layer 100 relative to the pad 132; the first semiconductor structure 11 further includes: a peripheral circuit 110, the peripheral circuit 110 including the first transistor 111, and at least a portion of the peripheral circuit 110 is located on the first side of the semiconductor layer 100. The peripheral circuit 110 may include digital or analog circuits composed of multiple transistors, capacitors, interconnect layers, connection structures, and contact structures. Some components of the peripheral circuit 110 are located in the semiconductor layer 100, such as the first active region 1111 of the first transistor 111 being located in the semiconductor layer 100, and the first connection structure 141 penetrating the semiconductor layer 100. Some components of the peripheral circuit 110 may be located on the first side of the semiconductor layer 100, which is the side near the bonding layer of the first semiconductor structure 11 and the side near the bonding second semiconductor structure 12; for example, the gate 1114 of the first transistor 111 is located on the first side of the semiconductor layer 100. Some components of the semiconductor structure are located on the second side of the semiconductor layer 100, such as the pad 132, which serves as an I / O interface to power the semiconductor device 10 and provide communication interaction. A redistribution layer may also be provided between the second side of the semiconductor layer 100 and the pad 132 for power supply and communication. The pad 132 may be a conductive contact, solder pad, or bump, which can be connected to external integrated circuits by soldering, wire bonding, or plugging to achieve electrical signal interconnection.

[0083] In some embodiments, refer to Figure 5 and Figure 6 As shown, the semiconductor device 10 further includes: a second semiconductor structure 12 located on the side of the peripheral circuit 110 away from the semiconductor layer 100; the second semiconductor structure 12 is bonded to the first semiconductor structure 11. Figure 5 as well as Figure 6 The second semiconductor structure 12 shown can be as follows Figure 3 Similarly, the second semiconductor structure 12 may include Figure 3 The memory array shown may include a second transistor 121 and a connected capacitor structure 122, a bit line 123 connected to a first doped region of the second transistor 121, and a gate layer 1213 extending along the y direction; the peripheral circuit 110 of the first semiconductor structure 11 may be connected to at least the bit line 123 and the gate layer 1213 through bonding contacts 131.

[0084] In some embodiments, refer to Figures 3 to 6As shown, the second semiconductor structure 12 includes: a second transistor 121, including a first doped region, a second doped region, and a gate layer 1213; a bit line 123 connected to the first doped region; and a capacitor structure 122 connected to the second doped region. The bit line 123 is located between the second transistor 121 and the peripheral circuit 110, and the second transistor 121 is located between the bit line 123 and the capacitor structure 122. In some embodiments, the second transistor 121 includes: a semiconductor body 1211 extending along the z-direction; the first doped region and the second doped region are located at opposite ends of the semiconductor body 1211 in the z-direction; wherein the gate layer 1213 extends along a direction intersecting the z-direction, and the gate layer 1213 covers a portion of the sidewall of the semiconductor body 1211 extending along the z-direction. Figure 6 As exemplified, the semiconductor device 10 may include a pad 132 disposed in the z-direction, a semiconductor layer 100, peripheral circuitry 110, bonding contacts 131, bit lines 123, a second transistor 121, and a capacitor structure 122.

[0085] The second transistor 121 may include a semiconductor body 1211 extending along the z-direction, and the semiconductor body 1211 may include semiconductor pillars extending along the z-direction; the semiconductor body 1211 has a first end and a second end disposed opposite to each other in the z-direction, a first doped region connected to the bit line 123 may be located at the end of the semiconductor body 1211 relatively close to the first semiconductor structure 11, and a second doped region connected to the capacitor structure 122 may be located at the end of the semiconductor body 1211 relatively far from the first semiconductor structure 11; the region between the first doped region and the second doped region is a channel; a gate layer 1213 extends along the y-direction and covers the sidewall of the semiconductor body 1211 extending along the z-direction, such as the gate layer 1213 covering the sidewall between the first end and the second end of the semiconductor body 1211, and the gate layer 1213 serves as the control gate of the second transistor 121 to control the conduction and cutoff of the second transistor 121; a gate dielectric layer 1212 is located between the semiconductor body 1211 and the gate layer 1213. The cross-sectional shape of the semiconductor body 1211 in the xoy plane may include, but is not limited to, rectangles, quadrilaterals, other polygons, circles, ellipses, or other irregular shapes, etc., and this disclosure does not impose any limitations on this. The gate layer 1213 can serve as a word line, and one gate layer 1213 can correspond to multiple semiconductor bodies 1211 arranged in the y direction; the bit line 123 extends along the x direction, and one bit line 123 can correspond to multiple semiconductor bodies 1211 arranged in the x direction. By selecting the gate layer 1213 and the bit line 123, the semiconductor body 1211 corresponding to the gate layer 1213 and the bit line 123 can be selected, causing the semiconductor body 1211 to conduct to select the capacitor structure 122, and performing write, refresh, or read operations by charging and discharging the capacitor structure 122 or sensing the amount of charge.

[0086] Figure 6 and Figure 7 Further explanations of the second transistor 121, capacitor structure 122, bit line 123, and gate layer 1213 in the second semiconductor structure 12 shown can be found in the preceding text. Figure 3 This part will not be elaborated upon here.

[0087] According to some aspects of this public embodiment, Figure 9 A method for fabricating a semiconductor device 10 is provided, comprising: providing a semiconductor layer, wherein the semiconductor layer has a first active region having a first transistor; forming a first connection structure extending along a first direction; wherein the first connection structure at least penetrates the semiconductor layer covering the first active region, and the first connection structure is connected to the first active region.

[0088] In some embodiments, a first semiconductor structure may be bonded to a second semiconductor structure first to form a first connection structure in the first semiconductor structure; the fabrication method may include: providing a first semiconductor structure, bonding the first semiconductor structure to a second semiconductor structure; the first semiconductor structure includes a semiconductor layer, the semiconductor layer having a first active region of a first transistor; forming a first connection structure extending along a first direction; wherein the first connection structure at least penetrates the semiconductor layer covering the first active region, and the first connection structure is connected to the first active region.

[0089] In some embodiments, the semiconductor layer 100 has a first side and a second side disposed opposite to each other in the z-direction. A method for forming a first active region 1111 includes: doping the first side of the semiconductor layer 100 to form the first active region 1111; a method for fabricating a first semiconductor structure 11 includes: forming a peripheral circuit 110 on the first side of the semiconductor layer 100; the peripheral circuit 110 includes a first transistor 111, the first active region 1111 of the first transistor 111 being close to the first side of the semiconductor layer 100; wherein the side of the peripheral circuit 110 away from the semiconductor layer 100 is used for bonding with a second semiconductor structure 12. (Refer to...) Figure 10As shown, the first semiconductor structure 11 may include peripheral circuitry 110, which may include a first transistor 111. The first transistor 111 may include active regions with different doping types, such as a source, a drain, and a channel region 1113. For example, the first active region 1111 may serve as either the source or the drain of the first transistor 111, and the positions of the source and drain can be interchanged. The first transistor 111 also includes a gate 1114 and a first dielectric layer 1115 located between the gate 1114 and the channel region 1113. The semiconductor layer 100 can be doped to form a first active region 1111 and a channel region 1113. The doping type of the first active region 1111 is opposite to that of the channel region 1113. The first active region 1111 is located in the semiconductor layer 100. For example, the first side of the semiconductor layer 100 can be doped to form the first active region 1111. A gate 1114, a first dielectric layer 1115, and other device structures can be disposed on the first side of the semiconductor layer 100 to form a peripheral circuit 110. The side of the peripheral circuit 110 away from the semiconductor layer 100 is used for bonding with the second semiconductor structure 12. The second semiconductor structure 12 may include a memory array, a second transistor 121, and a capacitor structure 122 connected to the second transistor 121.

[0090] Reference Figure 10As shown, before bonding the first semiconductor structure 11 and the second semiconductor structure 12, the first side of the semiconductor layer 100 can be the front side of the semiconductor layer 100, and the second side of the semiconductor layer 100 can be the back side of the semiconductor layer 100. The semiconductor layer 100 can be a semiconductor substrate, a semiconductor wafer, or a semiconductor layer 100 epitaxially grown on a substrate or wafer. The substrate can be removed, or the semiconductor layer 100 can be thinned on the back side. A first doping is performed on the first side of the semiconductor layer 100 to form a channel region 1113 of the first transistor 111. The thickness of the channel region 1113 in the z-direction is less than or equal to the thickness of the semiconductor layer 100, and one side surface of the channel region 1113 in the z-direction is exposed relative to the semiconductor layer 100 in the z-direction. A second doping is performed on the channel region 1113 to form a first active region 1111 and a second active region 1112 spaced apart. One side surface of the first active region 1111 and the second active region 1112 in the z-direction is exposed relative to the channel region 1113 in the z-direction, and the thickness of the first active region 1111 and the second active region 1112 in the z-direction is less than that of the channel region 1113. The first active region 1111 and the second active region 1112 serve as the source and drain of the first transistor 111, respectively. A first dielectric layer 1115 and a gate 1114 can be formed on the first side of the semiconductor layer 100. The gate 1114 can cover the channel region 1113 between the first active region 1111 and the second active region 1112. The first dielectric layer 1115 is disposed between the gate 1114 and this part of the channel layer. A plurality of connection structures extending along the z-direction are formed on the first side of the semiconductor layer 100, which are respectively connected to the gate 1114, the second active region 1112, and the first active region 1111. An interconnect layer can be formed on the connection structure to connect various parts of the first transistor 111 to the interconnect layer.

[0091] In some embodiments, isolation structures 112 are formed between transistors to isolate them and reduce mutual leakage current. The isolation structure 112 may include, but is not limited to, shallow trench isolation. For example, an isolation structure 112 is formed at the edge of the channel region 1113 of the first transistor 111. The isolation structure 112 penetrates a portion of the thickness of the semiconductor layer 100 in the z direction, and the channel region 1113 is located between two isolation structures 112.

[0092] In some embodiments, the fabrication method further includes: bonding the side of the peripheral circuit 110 away from the semiconductor layer 100 to the second semiconductor structure 12; and forming a first connection structure 141 along the side of the first semiconductor structure 11 away from the second semiconductor structure 12.

[0093] In some embodiments, refer to Figure 11As shown, the first semiconductor structure 11 and the second semiconductor structure 12 are bonded together. For example, the side of the peripheral circuit 110 of the first semiconductor structure 11 away from the semiconductor layer 100 can be bonded to the second semiconductor structure 12. A carrier wafer can be provided on the side of the second semiconductor structure 12 away from the first semiconductor structure 11 for support. The carrier wafer exposes the second side or the back side of the semiconductor layer 100 of the first semiconductor structure 11, allowing the carrier wafer to be removed later. (Refer to...) Figure 12 As shown, a first connection structure 141 extending along the z-direction is formed. The first connection structure 141 at least penetrates the semiconductor layer 100 on the first active region 1111 and penetrates the channel region 1113 on the first active region 1111; or penetrates the semiconductor layer 100 including the channel region 1113. The first connection structure 141 is connected to the first active region 1111. The first connection structure 141 may stop at the surface of the first active region 1111, or the first connection structure 141 may extend into the first active region 1111 along the z-direction, or the first connection structure 141 may penetrate the first active region 1111 along the z-direction.

[0094] In some embodiments, the manufacturing method further includes: referring to Figure 6 As shown, a pad 132 is formed on the side of the first connection structure 141 away from the first active region 1111, and the pad 132 is connected to the first connection structure 141; the pad 132 is located on the second side of the semiconductor layer 100. The pad 132 can serve as an I / O interface to power the semiconductor device 10 and provide communication interaction. A redistribution layer can also be formed between the second side of the semiconductor layer 100 and the pad 132 for power supply and communication.

[0095] In some embodiments, the method for fabricating the second semiconductor structure 12 includes: referring to Figure 11 As shown, a second transistor 121 is formed, comprising a first doped region, a second doped region, and a gate layer 1213; a bit line 123 is formed connected to the first doped region; and a capacitor structure 122 is formed connected to the second doped region; wherein the bit line 123 is located between the second transistor 121 and the peripheral circuit 110, and the second transistor 121 is located between the bit line 123 and the capacitor structure 122. In some embodiments, reference is made to... Figure 11 As shown, the method of forming the second transistor 121 includes: forming a semiconductor body 1211 extending along the z-direction, wherein a first doped region and a second doped region are located at two opposite ends of the semiconductor body 1211 in the z-direction; forming a gate layer 1213 on the side of the semiconductor body 1211; wherein the gate layer 1213 extends along a direction intersecting the z-direction, and the gate layer 1213 covers a portion of the sidewall of the semiconductor body 1211 extending along the z-direction.

[0096] The second transistor 121 may include a semiconductor body 1211 extending along the z-direction, and the semiconductor body 1211 may include semiconductor pillars extending along the z-direction; the semiconductor body 1211 has a first end and a second end disposed opposite to each other in the z-direction, a first doped region connected to the bit line 123 may be located at the end of the semiconductor body 1211 relatively close to the first semiconductor structure 11, and a second doped region connected to the capacitor structure 122 may be located at the end of the semiconductor body 1211 relatively far from the first semiconductor structure 11; the region between the first doped region and the second doped region is a channel; a gate layer 1213 extends along the y-direction and covers the sidewall of the semiconductor body 1211 extending along the z-direction, such as the gate layer 1213 covering the sidewall between the first end and the second end of the semiconductor body 1211, and the gate layer 1213 serves as the control gate of the second transistor 121 to control the conduction and cutoff of the second transistor 121; a gate dielectric layer 1212 is located between the semiconductor body 1211 and the gate layer 1213. The cross-sectional shape of the semiconductor body 1211 in the xoy plane may include, but is not limited to, rectangles, quadrilaterals, other polygons, circles, ellipses, or other irregular shapes, etc., and this disclosure does not impose any limitations on this. The gate layer 1213 can serve as a word line, and one gate layer 1213 can correspond to multiple semiconductor bodies 1211 arranged in the y direction; the bit line 123 extends along the x direction, and one bit line 123 can correspond to multiple semiconductor bodies 1211 arranged in the x direction. By selecting the gate layer 1213 and the bit line 123, the semiconductor body 1211 corresponding to the gate layer 1213 and the bit line 123 can be selected, causing the semiconductor body 1211 to conduct to select the capacitor structure 122, and performing write, refresh, or read operations by charging and discharging the capacitor structure 122 or sensing the amount of charge. Figure 11 Further explanations of the second transistor 121, capacitor structure 122, bit line 123, and gate layer 1213 in the second semiconductor structure 12 shown can be found in the preceding text. Figure 3 This part will not be elaborated upon here.

[0097] In some embodiments, Figures 13 to 20 A partial schematic diagram of the first semiconductor structure 11 is shown, while the specific device structure of the second semiconductor structure 12 is omitted. The method for forming the first connection structure 141 includes: etching at least the semiconductor layer 100 on the first active region 1111 to form a first opening 14; and forming the first connection structure 141 in the first opening 14. (Refer to...) Figure 13The diagram shows a first opening 14 that penetrates the semiconductor layer 100 and the channel region 1113, with the bottom of the first opening 14 exposing the first active region 1111. The first opening 14 may stop at the surface of the first active region 1111 or extend into the first active region 1111 but not penetrate it. A conductive material is filled in the first opening 14 to form a first connection structure 141. Alternatively, a second dielectric layer 114 is formed on the sidewall of the first opening 14, and then the first opening 14 is filled with conductive material to form the first connection structure 141. The first dielectric layer 1115 can reduce the diffusion of conductive material in the semiconductor layer 100 and the channel region 1113, and reduce leakage current in the first connection structure 141. Exemplarily, the etching process may include, but is not limited to, dry etching, wet etching, or any combination thereof.

[0098] In some embodiments, before etching the semiconductor layer 100 to form the first aperture 14, the semiconductor layer 100 may be thinned on the back side to reduce the aperture depth and reduce the etching load effect. The thinning process may include, but is not limited to, etching, chemical mechanical planarization, or a combination thereof.

[0099] For example, the process for forming the second dielectric layer 114 and the first connection structure 141 may include, but is not limited to, deposition processes, including but not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For example, the second dielectric layer 114 may be formed on the sidewall of the first opening 14 using an atomic layer deposition process, and the first connection structure 141 may be deposited in the first opening 14 using a combination of atomic layer deposition and chemical vapor deposition, with the second dielectric layer 114 surrounding the first connection structure 141.

[0100] In some embodiments, the first active region 1111 is located on the first conductive layer 113; the fabrication method further includes: referring to Figure 14 As shown, the first active region 1111 is etched so that the first opening 14 penetrates the first active region 1111; wherein, the bottom of the first opening 14 exposes the first conductive layer 113; see reference. Figure 15As shown, a first connection structure 141 is formed in the first opening 14. The first opening 14 can stop at the surface of the first conductive layer 113 after penetrating the first active region 1111, or extend into the first conductive layer 113. Alternatively, the first opening 14 may not penetrate the first conductive layer 113. The first conductive layer 113 can serve as an etching stop layer for the first opening 14, which helps to expand the etching process window of the first opening 14. The dimension of the first conductive layer 113 in the x-direction can be larger than the dimension of the first active region 1111 in the x-direction, providing a larger landing area in the x-direction and reducing the alignment difficulty of the first connection structure 141.

[0101] In some embodiments, refer to Figure 16 As shown, a pad 132 is formed on the second side of the semiconductor layer 100, and the pad 132 is connected to the side of the first connection junction away from the second semiconductor structure 12. The method of forming the pad 132 may include forming a dielectric material on the second side of the semiconductor layer 100, etching the dielectric material to form a groove exposing the first connection structure 141, and forming the pad 132 in the groove.

[0102] In some embodiments, refer to Figure 17 As shown, the bottom of the first opening 14 exposes the first active region 1111, and the manufacturing method further includes: referring to Figure 18 As shown, a second conductive layer 115 is formed at the bottom of the first opening 14, and the second conductive layer 115 is connected to the first active region 1111; Refer to Figure 19 As shown, a first connection structure 141 is formed on the second conductive layer 115, and the first connection structure 141 is connected to the second conductive layer 115. In some embodiments, it is possible to... Figure 17 A second dielectric layer 114 is formed on the sidewall of the first opening 14, and the second dielectric layer 114 surrounds the second conductive layer 115 and the first connection structure 141; or it may be possible to Figure 18 A second dielectric layer 114 is formed on the sidewall of the first opening 14 above the second conductive layer 115. The second dielectric layer 114 is located above the second conductive layer 115 and surrounds the sidewall of the first connection structure 141.

[0103] In some embodiments, the first opening 14 extends into the first active region 1111; the second conductive layer 115 extends into the first active region 1111.

[0104] Figure 17The first opening 14 shown may stop at the surface of the first active region 1111, and the formed first connection structure 141 may contact the upper surface of the first active region 1111; or, the first active region 1111 may be over-etched so that the first opening 14 extends into the first active region 1111, and the first opening 14 does not penetrate the first active region 1111; the formed first connection structure 141 extends into the first active region 1111, and the first connection structure 141 does not penetrate the first active region 1111.

[0105] In some embodiments, refer to Figure 20 As shown, a pad 132 is formed on the second side of the semiconductor layer 100, and the pad 132 is connected to the side of the first connection junction away from the second semiconductor structure 12.

[0106] According to some aspects of embodiments of the present disclosure, a memory system 202 is provided, comprising: at least as described above. Figures 3 to 8 The example semiconductor device 10; and the memory controller 206, which is connected to and controls the semiconductor device 10. Figure 21 A memory system 202 is provided, comprising a memory device 204 and a memory controller 206 coupled thereto, the memory controller 206 controlling the memory device 204, the memory device 204 including at least... Figures 3 to 8 The semiconductor device 10 exemplified is a memory device 204 or at least a portion thereof.

[0107] Reference Figure 21 As shown, this disclosure provides a system 200 including a host 208. The system 200 may be a mobile phone, graphics processing device, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 21 As shown, system 200 may include host 208 and memory system 202, the memory system 202 having one or more memory devices 204 and memory controller 206. Host 208 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)). Host 208 may be configured to send data to or receive data from memory device 204, memory device 204 may include at least... Figures 3 to 8 The example semiconductor device 10.

[0108] According to some embodiments, a memory controller 206 is coupled to the memory device 204 and the host 208, and is configured to control the memory device 204 to perform read, write, or refresh operations. The memory controller 206 can manage data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes DRAM, or a package structure formed by stacking multiple DRAMs, which can be applied to HBM or HMC package structures.

[0109] In some specific examples, the HBM packaging structure may include multiple DRAM chips vertically stacked on a logic chip, with electrical interconnections between the logic chip and the multiple DRAM chips via through-silicon vias (TSVs). The multiple DRAM chips and the logic chip can form a memory system. The logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches. The logic chip may be configured as a memory controller 206. Figures 3 to 8 The example semiconductor device 10 can be configured as a memory device 204 or a DRAM chip; the HBM package structure may also include processor chips such as GPUs, CPUs, or SOC chips, with a memory controller integrated in the processor to control data transfer of the DRAM chips. For example, a processor such as a GPU is coupled to a logic chip, and data interaction occurs between the logic chip and the DRAM. In other specific examples, the HMC (Hybrid Memory Cube) package structure may include multiple DRAM chips vertically stacked on a logic chip, with the logic chip and the multiple DRAM chips interconnected via TSVs. The multiple DRAM chips and the logic chip can form a memory system, and the logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches, and may integrate a memory controller.

[0110] In some specific examples, the memory system 202 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Many high-end SSD products choose to embed DRAM to enhance performance and improve random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, making the SSD storage more efficient and faster. Flash memory includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory. In some specific examples, the memory system 202 can be used as a cache device in a graphics processing device (GPU), which may include, but is not limited to, a graphics graphics card.

[0111] In other embodiments, reference is made to Figure 22As shown, system 200 may consist only of host 208 and a memory device 204 coupled thereto. The controller for the memory device 204 may be located inside host 208, such as a memory controller integrated within a central processing unit (CPU), or a southbridge or northbridge chip integrated into the motherboard of system 200. Memory device 204 may include, but is not limited to: DDR4 memory, DDR5 memory (Double Data Rate Synchronous Dynamic Random Access Memory), and LPDDR5 memory (Low Power Double Data Rate Synchronous Dynamic Random Access Memory). Memory device 204 may include at least the following: Figures 3 to 8 The example semiconductor device 10.

[0112] In some embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the components shown or discussed may be directly or indirectly coupled to each other. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, Includes a first semiconductor structure, the first semiconductor structure comprising: Semiconductor layer; A first transistor, wherein a first active region of the first transistor is located in the semiconductor layer; A first connection structure extends at least through the semiconductor layer covering the first active region along a first direction; wherein the first connection structure is connected to the first active region.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: The pad is located on the side of the first connection structure away from the first active region; the pad is connected to the first connection structure.

3. The semiconductor device according to claim 1, characterized in that, The dimension of the end of the first connection structure closest to the first active region in the second direction is less than or equal to the dimension of the end of the first connection structure furthest from the first active region in the second direction; the second direction intersects the first direction.

4. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A first conductive layer is located on the side of the first active region away from the first connecting structure, and the first conductive layer is in contact with the first active region; the first connecting structure penetrates the first active region and is in contact with the first conductive layer.

5. The semiconductor device according to claim 4, characterized in that, The constituent materials of the first conductive layer include at least one of metal oxides or metal silicides.

6. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A second conductive layer is located between the first connection structure and the first active region; the second conductive layer is connected to the first connection structure on one side in the first direction and to the first active region on the other side.

7. The semiconductor device according to claim 6, characterized in that, The resistance of the constituent material of the second conductive layer is less than or equal to the resistance of the constituent material of the first connection structure.

8. The semiconductor device according to claim 7, characterized in that, The constituent materials of the second conductive layer include at least one of ruthenium or ruthenium alloys.

9. The semiconductor device according to claim 6, characterized in that, The second conductive layer extends into the first active region along the first direction.

10. The semiconductor device according to claim 2, characterized in that, The semiconductor layer has a first side and a second side disposed opposite to each other in the first direction, and the pad is located on the second side of the semiconductor layer; the first active region of the first transistor is close to the first side of the semiconductor layer relative to the pad. The first semiconductor structure further includes: The peripheral circuit includes the first transistor, and at least a portion of the peripheral circuit is located on a first side of the semiconductor layer.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: A second semiconductor structure is located on the side of the peripheral circuit away from the semiconductor layer; the second semiconductor structure is bonded to the first semiconductor structure.

12. The semiconductor device according to claim 11, characterized in that, The second semiconductor structure includes: The second transistor includes a first doped region, a second doped region, and a gate layer; Bit lines are connected to the first doped region; A capacitor structure is connected to the second doped region; The bit line is located between the second transistor and the peripheral circuit, and the second transistor is located between the bit line and the capacitor structure.

13. The semiconductor device according to claim 12, characterized in that, The second transistor includes: A semiconductor body extends along the first direction; the first doped region and the second doped region are located at opposite ends of the semiconductor body in the first direction. The gate layer extends along a direction intersecting the first direction, and the gate layer covers a portion of the sidewall of the semiconductor body extending along the first direction.

14. A method for fabricating a semiconductor device, characterized in that, Forming a first semiconductor structure includes: A semiconductor layer is provided, wherein a first active region of a first transistor is provided in the semiconductor layer; A first connection structure is formed extending along a first direction; wherein the first connection structure at least penetrates the semiconductor layer covering the first active region, and the first connection structure is connected to the first active region.

15. The manufacturing method according to claim 14, characterized in that, The method for forming the first connection structure includes: At least the semiconductor layer on the first active region is etched to form a first opening; the first connection structure is formed in the first opening.

16. The manufacturing method according to claim 15, characterized in that, The first active region is located on the first conductive layer; the fabrication method further includes: The first active region is etched so that the first opening penetrates the first active region; wherein the bottom of the first opening exposes the first conductive layer.

17. The manufacturing method according to claim 15, characterized in that, The bottom of the first opening exposes the first active region, and the manufacturing method further includes: A second conductive layer is formed at the bottom of the first opening, and the second conductive layer is connected to the first active region; The first connection structure is formed on the second conductive layer, and the first connection structure is connected to the second conductive layer.

18. The manufacturing method according to claim 14, characterized in that, The semiconductor layer has a first side and a second side disposed opposite to each other in the first direction, and the method for forming the first active region includes: The first side of the semiconductor layer is doped to form the first active region; the method for fabricating the first semiconductor structure includes: A peripheral circuit is formed on a first side of the semiconductor layer; the peripheral circuit includes the first transistor, and a first active region of the first transistor is located near the first side of the semiconductor layer.

19. The manufacturing method according to claim 18, characterized in that, The fabrication method further includes: bonding the side of the peripheral circuit away from the semiconductor layer to the second semiconductor structure; and forming the first connection structure along the side of the first semiconductor structure away from the second semiconductor structure.

20. The manufacturing method according to claim 19, characterized in that, The manufacturing method further includes: A pad is formed on the side of the first connection structure away from the first active region, and the pad is connected to the first connection structure; the pad is located on the second side of the semiconductor layer.

21. The manufacturing method according to claim 19, characterized in that, The method for fabricating the second semiconductor structure includes: A second transistor is formed, the second transistor including a first doped region, a second doped region, and a gate layer; A bit line is formed that connects to the first doped region; A capacitor structure connected to the second doped region is formed; The bit line is located between the second transistor and the peripheral circuit, and the second transistor is located between the bit line and the capacitor structure.

22. The manufacturing method according to claim 21, characterized in that, The method of forming the second transistor includes: A semiconductor body extending along the first direction is formed, wherein the first doped region and the second doped region are located at opposite ends of the semiconductor body in the first direction; The gate layer is formed on the side of the semiconductor body; wherein the gate layer extends in a direction intersecting the first direction and covers a portion of the sidewall of the semiconductor body extending in the first direction.

23. A memory system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 13; as well as A memory controller is connected to and controls the semiconductor device.

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