Semiconductor device and method of manufacturing the same
By forming amorphous and recrystalline word line electrodes during DRAM fabrication, the problem of high-quality word line structure has been solved, improving the electrical performance and reliability of DRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-12-04
- Publication Date
- 2026-06-05
AI Technical Summary
In existing DRAM fabrication methods, obtaining high-quality word line structures without affecting other device performance is an urgent problem to be solved.
By forming a first electrode layer in the word line trench, the surface grains are destroyed to form an amorphous layer, and the amorphous layer is recrystallized by a cold sintering process to form a dense recrystallized layer. This process is repeated multiple times to improve the density of the crystal structure.
It achieves better leakage protection and blocking performance, while ensuring high-quality word line electrodes at low temperatures, adjusting the selectivity of threshold voltage, and improving the overall electrical performance of the device.
Smart Images
Figure CN122161090A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology
[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more fabrication methods based on existing structures is a favorable means to overcome existing technological barriers.
[0003] In current DRAM fabrication methods, transistor performance is closely related to the quality of word line structure. Therefore, how to obtain high-quality word line structure without affecting other device performance is an urgent problem to be solved. Summary of the Invention
[0004] According to a first aspect of the present disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a substrate in which word line trenches are formed; forming a first electrode layer in the word line trenches; destroying at least a portion of the surface grains of the first electrode layer to form an amorphous layer; recrystallizing the amorphous layer; and patterning the first electrode layer to form a first word line electrode.
[0005] In some embodiments, the step of destroying at least a portion of the surface grains of the first electrode layer to form an amorphous layer is to destroy at least a portion of the surface grains of the first electrode layer by an ion implantation process.
[0006] In some embodiments, the ion implantation process uses nitrogen for ion implantation.
[0007] In some embodiments, the ion implantation process uses nitrogen and krypton alternately for ion implantation.
[0008] In some embodiments, the step of recrystallizing the amorphous layer is to recrystallize the amorphous layer by a cold sintering process.
[0009] In some embodiments, the cold sintering process includes: impregnating a first electrode layer; increasing the gas pressure to 50 MPa to 600 MPa at a rate of 20 MPa per second to 50 MPa per second; and increasing the temperature to 200°C to 400°C for 1 to 5 minutes in an inert gas environment at a rate of 5°C per second to 20°C per second.
[0010] In some embodiments, a second electrode layer is formed on the surface of the first electrode layer; while the first electrode layer is patterned, the second electrode layer is patterned to form a first word line electrode and a second word line electrode.
[0011] In some embodiments, the steps of destroying at least a portion of the surface grains of the first electrode layer to form an amorphous layer are performed repeatedly; and the step of recrystallizing the amorphous layer is performed.
[0012] In some embodiments, the material of the first electrode layer is titanium nitride.
[0013] In some embodiments, the material of the second electrode layer is tungsten.
[0014] According to a second aspect of the present disclosure, a semiconductor device is provided that is prepared according to any of the foregoing methods.
[0015] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate having an array of active regions arranged therein; a word line structure disposed in the substrate and passing through the active regions; the word line structure and the active regions it passes through constituting a transistor structure; wherein the word line structure includes a first word line electrode, the first word line electrode including a recrystallization layer, the recrystallization layer having a denser lattice structure than other portions of the first word line electrode.
[0016] In some embodiments, the word line structure further includes a second word line electrode; wherein the first word line electrode is made of titanium nitride and the second word line electrode is made of tungsten.
[0017] In some embodiments, the recrystallization layer is located on the surface of the first word line electrode away from the substrate.
[0018] In some embodiments, the grain size of the recrystallized layer is smaller than the grain size of other portions of the first word line electrode.
[0019] The first word line electrode prepared by the method of this disclosure has a recrystallized layer with a denser lattice structure, thus providing better leakage protection and blocking performance. Forming a recrystallized layer with smaller grain size provides more options for adjusting the threshold voltage. Recrystallization at low temperatures ensures the formation of a high-quality first word line electrode without affecting the performance of other parts of the device, thereby obtaining a high-quality device. Attached Figure Description
[0020] Figure 1 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment; Figures 2-11 This is a schematic cross-sectional view along the direction of the active region in a step of a method for fabricating a semiconductor device according to an exemplary embodiment. Detailed Implementation The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0021] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0022] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0023] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0024] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0025] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0026] According to a first aspect of the embodiments of this disclosure, such as Figures 1-10 As shown, a method for fabricating a semiconductor device is provided, comprising: providing a substrate 100; In some embodiments, the substrate is prepared from semiconductor materials such as single-crystal silicon, germanium silicon, silicon carbide, or silicon-on-insulator.
[0027] In some embodiments, the substrate includes the structure formed in the foregoing steps, the substrate includes an array region 20, the array region includes an array of active regions 200, and an isolation layer 300 disposed between the active regions.
[0028] In some embodiments, the substrate further includes a peripheral region 30.
[0029] In some embodiments, the active regions arranged in the array are formed by a patterning process. Specifically, the patterning process includes forming photoresist on a substrate, exposing and developing the photoresist to form a photoresist with a preset pattern, and etching the substrate with the patterned photoresist to form the active regions and isolation trenches.
[0030] In some embodiments, the patterning process further includes forming a hard mask on a substrate, forming photoresist on the hard mask, exposing and developing the photoresist to form a preset pattern, etching the hard mask with the patterned photoresist to transfer the preset pattern onto the hard mask, stripping the photoresist, and etching the substrate with the patterned hard mask to form an active region and isolation trenches.
[0031] In some embodiments, with the development of semiconductor fabrication processes, integration density increases and dimensions shrink. A single patterning process cannot form the predetermined width required for active regions and isolation trenches, necessitating multiple patterning processes. Examples include two-stage exposure and etching (LELE), self-aligned double patterning (SADP), or self-aligned quad patterning (SAQP). Optionally, a patterned substrate with strip-shaped spacing is first formed, and then portions of the strip-shaped patterned substrate are etched to form an array of active region patterns.
[0032] In some embodiments, the process of etching the substrate to form active regions and isolation trenches includes anisotropic etching or isotropic etching, such as dry etching or wet etching.
[0033] In some embodiments, the insulating material deposited in the isolation trench to form the isolation layer is selected from one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. Preferably, silicon nitride and silicon oxide are deposited alternately; more preferably, silicon nitride is deposited first, followed by silicon oxide.
[0034] In some embodiments, the deposition method for depositing insulating material in the isolation trench to form an isolation layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for depositing the insulating material is chemical vapor deposition (CVD). Preferably, the method for depositing the insulating material involves forming a material layer by chemical vapor deposition (CVD), and then planarizing the material layer using chemical mechanical polishing to remove a portion of the insulating material layer located on the surface of the active region, exposing the active region.
[0035] In some embodiments, after the array region forms an array of active regions and isolation layers, a peripheral circuit region and a peripheral isolation layer are formed in the peripheral region. Optionally, the fabrication process of the peripheral region can be the same as or different from that of the array region. When the peripheral region and the array region are fabricated using the same process, the fabrication of both regions can be completed simultaneously in a single process. Optionally, the critical dimension of the peripheral circuit is lower than that of the array region. Preferably, the peripheral region is fabricated using a different process. Optionally, the peripheral region can be fabricated using a similar patterning process after the array region is fabricated, or the peripheral region can be fabricated first using a patterning process and then the array region can be fabricated. Optionally, in subsequent steps, the fabrication of the peripheral circuit structure and the peripheral cover layer can be completed simultaneously with the array region, or they can be fabricated sequentially in separate steps.
[0036] Word line trenches of 400V are formed in the substrate; specifically, word line trenches are formed in the substrate through a patterning process, which is similar to that described above and will not be repeated here.
[0037] A first electrode layer M401 is formed in the word line trench; In some embodiments, the first electrode layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the first electrode layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.
[0038] In some embodiments, a first electrode layer is formed on the substrate surface and at the bottom and sidewalls of the word line trench.
[0039] In some embodiments, the first electrode layer material is titanium nitride (TiN) formed by atomic layer deposition (ALD), and the titanium nitride deposition thickness is between 1 nm and 50 nm.
[0040] In some embodiments, before forming the first electrode layer, a gate insulating layer 410 is further formed in the word line trench. The material of the gate insulating layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the gate masking layer is silicon oxide. Optionally, the method for forming the gate insulating layer includes: depositing a gate insulating layer material on the substrate surface and the word line trench surface. The deposition method of the gate insulating layer material is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. Preferably, the deposition method of the insulating material is rapid thermal oxidation. The gate insulating layer material on the substrate surface is removed, and the remaining gate insulating layer material in the word line trench constitutes the gate insulating layer. The method for removing the gate insulating layer material on the substrate surface is selected from etching and chemical mechanical polishing (CMP).
[0041] In some embodiments, such as Figure 3 As shown, according to relevant experiments, the titanium nitride lattice structure 401G deposited by atomic layer deposition is a columnar structure, such as... Figure 3 Magnified view of a section. The columnar structure has obvious grain boundaries and is not dense enough. Therefore, thin titanium nitride will result in insufficient blocking ability. Moreover, titanium nitride has a high work function, which can reduce leakage current, so a thicker titanium nitride layer is needed. However, if the deposition thickness is insufficient, the blocking effect is still not good enough, while excessively thick titanium nitride deposition will lead to an increase in threshold voltage and alter the electrical properties. How to maintain a stable threshold voltage while increasing the thickness of titanium nitride is an urgent problem to be solved.
[0042] At least a portion of the surface grains of the first electrode layer are destroyed to form an amorphous layer 401A; In some embodiments, such as Figure 4 As shown, the grains on the surface of the first electrode layer are destroyed by the ion implantation process PT1. Due to the influence of factors such as the direction and penetration of the ion implantation process, it is possible to control the destruction of only the bottom of the groove and the surface of the first electrode layer.
[0043] In some embodiments, nitrogen is used for ion implantation to disrupt the grains on the surface of the first electrode layer. When the first electrode layer is titanium nitride, nitrogen ion implantation does not introduce other elements. The ion implantation dose is 1E15 / cm². 2 ~50E15 / cm 2 The voltage ranges from 1 KeV to 30 KeV.
[0044] In some embodiments, krypton is used for ion implantation to disrupt the grains on the surface of the first electrode layer. Krypton has a larger atomic weight, resulting in a better grain-disrupting effect, and it does not react with the first electrode layer material.
[0045] In some embodiments, nitrogen and krypton are used alternately for ion implantation to disrupt the grains on the surface of the first electrode layer.
[0046] In some embodiments, such as Figure 5 As shown, an amorphous layer 401A is formed by destroying at least a portion of the surface grains of the first electrode layer through ion implantation process PT1. Figure 5 A magnified view of a portion of the sample. Prior to the ion implantation process, a substrate barrier layer RC1 is formed on the substrate surface to protect the active region from contamination. The substrate barrier layer material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof; or one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride; or photoresist, etc. The substrate barrier layer can be formed by methods such as physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, spin coating, or damascus coating.
[0047] Recrystallize the amorphous layer; In some embodiments, the amorphous layer is recrystallized by rapid thermal annealing.
[0048] In some embodiments, the amorphous layer is recrystallized by a cold sintering process.
[0049] In some embodiments, the cold sintering process includes wetting the first electrode layer to form a wetting layer WET1, such as Figure 6 As shown, specifically, the wetting process can be implemented in the cleaning process (scrubber), with the following process conditions: nitrogen flow rate of 20L / min~80L / min in an inert gas environment, temperature controlled at 20℃~30℃, deionized water flow rate of 50sccm~3000sccm (standard cubic centimeters per minute), drying conditions of 1500 rpm~4000 rpm, and duration of 10s~60s.
[0050] In some embodiments, the cold sintering process further includes applying a pressure of 50 MPa to 600 MPa at a rate of 20 MPa / min to 50 MPa / min to the substrate with the wetting layer formed, under an inert gas environment; heating the substrate to 200°C to 400°C at a rate of 5°C / s to 20°C / s for a duration of 1 min to 5 min. This results in the formation of a substrate with the wetting layer formed under the pressure of 50 MPa to 600 MPa at a rate of 20 MPa / min to 50 MPa / min. Figure 7 As shown, the amorphous layer on the surface of the first electrode layer at the bottom of the character line groove is recrystallized to form a recrystallized layer 401R, and the first electrode layer with the recrystallized layer is 401D.
[0051] In some embodiments, experiments have shown that the grain size of titanium nitride increases during high-temperature thermal annealing, and the increased grain size leads to a higher threshold voltage. Furthermore, high temperatures can affect the electrical performance of previous doping processes or other structures. When the first electrode layer is titanium nitride, the recrystallized layer 401R has a smaller grain size and is more dense due to the lower temperature of the cold sintering process, resulting in a better barrier effect. Moreover, while increasing the electrode thickness, the threshold voltage can be adjusted within an appropriate range, thus obtaining a device with better electrical performance.
[0052] In some embodiments, at least a portion of the surface grains of the first electrode layer are destroyed to form an amorphous layer, the amorphous layer is recrystallized to form a recrystallized layer, then at least a portion of the surface grains of the recrystallized layer are destroyed again to form a second amorphous layer, and the second amorphous layer is recrystallized again to form a second recrystallized layer. This process is repeated multiple times to obtain a multilayer or more compact recrystallized layer.
[0053] In some embodiments, an amorphous layer is formed by destroying the grains on the surface of the first electrode layer through ion implantation, and the amorphous layer is then recrystallized through cold sintering to form a recrystallized layer. The grains on the surface of the recrystallized layer are then destroyed again through ion implantation to form a second amorphous layer, and the second amorphous layer is then recrystallized through cold sintering to form a second recrystallized layer. Because the recrystallized layer has a denser crystal structure, repeating the ion implantation process will not completely destroy the entire recrystallized layer.
[0054] In some embodiments, the process parameters for re-performing the ion implantation process are changed so that only a portion of the grains on the surface of the recrystallized layer are destroyed.
[0055] The first electrode layer is patterned to form the first word line electrode 401.
[0056] In some embodiments, the method of patterning the first electrode layer includes an etching process or chemical mechanical polishing (CMP). Specifically, it includes removing the first electrode layer from the substrate surface and a portion of the first electrode layer in the word line trench, with the remaining portion of the first electrode layer on the gate insulating layer in the word line trench constituting the first word line electrode.
[0057] In some embodiments, patterning the first electrode layer includes removing a portion of the first electrode layer from the sidewalls of the word line trench, with the remaining portion of the first electrode layer on the gate insulating layer in the word line trench constituting the first word line electrode.
[0058] In some embodiments, while removing a portion of the first electrode layer, the gate insulating layer on the substrate surface is also removed to expose the active layer.
[0059] In some embodiments, prior to patterning the first electrode layer, the method further includes, as shown in the example... Figure 8 As shown, a second electrode layer M402 is formed on a substrate on which a first electrode layer is formed. The material of the second electrode layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the second electrode layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or damascus deposition, etc.
[0060] In some embodiments, the first electrode layer is titanium nitride, and the second electrode layer is tungsten formed by chemical vapor deposition. The titanium nitride with the recrystallized layer can prevent tungsten precursors from contaminating the active region.
[0061] In some embodiments, the substrate on which the second electrode layer is formed is patterned, such as... Figure 9 As shown, the first electrode layer and the second electrode layer are simultaneously patterned to form the first word line electrode 401 and the second word line electrode 402. The method for patterning the first electrode layer and the second electrode layer includes etching or chemical mechanical polishing (CMP). Specifically, this includes removing the first electrode layer and the second electrode layer from the substrate surface, and a portion of the first electrode layer and the second electrode layer in the word line trench. The remaining portion of the first electrode layer on the gate insulating layer in the word line trench constitutes the first word line electrode, and the second electrode layer constitutes the second word line electrode.
[0062] In some embodiments, after forming the first word line electrode and the second word line electrode, a gate masking layer 403 is further formed on the first word line electrode and the second word line electrode, such as... Figure 10 As shown, the gate masking layer fills the word line trench and is flush with the upper surface of the substrate. The first word line electrode, the second word line electrode, and the gate masking layer together constitute the word line structure 400. The word line structure and the active layer 200 it controls constitute the transistor structure Tr.
[0063] In some embodiments, the step of forming a gate masking layer includes forming a gate masking material layer on the substrate surface and in the word line trenches where the first word line electrode and the second word line electrode are formed. The gate masking material layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the gate masking material layer is silicon nitride. The method for forming the gate masking material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. The gate masking material layer on the substrate surface is removed, and the remaining gate masking material layer forms a gate masking layer. The gate masking layer fills the word line trenches, and its upper surface is flush with the substrate surface. The method for removing the gate masking material layer on the substrate surface is selected from etching or chemical mechanical polishing (CMP).
[0064] In some embodiments, after forming the first word line electrode and the second word line electrode, and before forming the gate masking layer, a third word line electrode is further formed. Specifically, a third electrode layer is formed on the substrate where the first word line electrode and the second word line electrode are formed. The third electrode layer is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The method for forming the third electrode layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or damascus deposition, etc. A third electrode layer fills the word line trenches, is formed on the first and second word line electrodes, and covers the substrate surface. The third electrode layer on the substrate surface and a portion of the third electrode layer in the word line trenches are removed. The remaining portion of the third electrode layer on the first and second word line electrodes in the word line trenches constitutes the third word line electrode. The method for removing the third electrode layer on the substrate surface and a portion of the third electrode layer in the word line trenches is selected from etching processes or chemical mechanical polishing (CMP).
[0065] In some embodiments, the third electrode layer is selected from a low work function material, preferably doped or undoped polycrystalline silicon.
[0066] In some embodiments, such as Figure 11As shown, a gate masking layer S403 is formed in the word line trench where the first word line electrode S401 is formed. The first word line electrode and the gate masking layer together constitute the word line structure S400. The first word line electrode is titanium nitride. The step of forming the gate masking layer includes forming a gate masking material layer on the substrate surface and in the word line trench where the first word line electrode is formed. The gate masking material layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the gate masking material layer is silicon nitride. The method for forming the gate masking material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. The gate masking material layer on the substrate surface is removed, and the remaining gate masking material layer forms the gate masking layer. The gate masking layer fills the word line trench, and its upper surface is flush with the substrate surface. The method for removing the gate masking material layer on the substrate surface is selected from etching or chemical mechanical polishing (CMP).
[0067] In some embodiments, after forming the first word line electrode, a third word line electrode is further formed before forming the gate cover layer. Specifically, a third electrode layer is formed on the substrate where the first word line electrode is formed. The third electrode layer is selected from a low work function material, preferably doped or undoped polysilicon. The method for forming the third electrode layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, or damascus deposition, etc. The third electrode layer fills the word line trench, is formed on the first word line electrode, and covers the substrate surface. The third electrode layer on the substrate surface and a portion of the third electrode layer in the word line trench are removed, and the remaining portion of the third electrode layer on the first word line electrode in the word line trench constitutes the third word line electrode. The method for removing the third electrode layer on the substrate surface and a portion of the third electrode layer in the word line trench is selected from etching or chemical mechanical polishing (CMP).
[0068] According to a second aspect of the present disclosure, a semiconductor device is provided that is prepared according to any of the foregoing methods.
[0069] According to a third aspect of the present disclosure, a semiconductor device 10 is provided, comprising: a substrate 100 having an array of active regions 200 arranged therein; a word line structure 400 disposed in the substrate and passing through the active regions; the word line structure and the active regions it passes through constituting a transistor structure; wherein the word line structure includes a first word line electrode 401, the first word line electrode including a recrystallization layer 401R, the recrystallization layer having a denser lattice structure than other portions of the first word line electrode.
[0070] In some embodiments, the word line structure further includes a second word line electrode; wherein the first word line electrode is made of titanium nitride and the second word line electrode is made of tungsten.
[0071] In some embodiments, the recrystallization layer is located on the surface of the first word line electrode away from the substrate.
[0072] In some embodiments, the grain size of the recrystallized layer is smaller than the grain size of other portions of the first word line electrode.
[0073] In some embodiments, the semiconductor device 10 is a dynamic random access memory (DRAM), comprising: a substrate 100 having an array region 20 and a peripheral region 30; an active region 200 having an array of active regions arranged in the array region; a word line structure 400 disposed in the substrate and passing through the active region; the word line structure and the active region it passes through constitute a transistor structure; a bit line structure 500 disposed in the array region and in contact with the active region; a memory node 900 disposed on the active region and in contact with the active region; and a peripheral region including a peripheral circuit structure 700 and a peripheral capping layer covering the peripheral circuit structure; wherein the word line structure includes a first word line electrode 401, the first word line electrode including a recrystallization layer 401R, the recrystallization layer having a denser lattice structure than other parts of the first word line electrode. The word line structure and the bit line structure are electrically connected to the peripheral circuit structure, respectively.
[0074] In some embodiments, the storage node is selected from one or more of the following: storage capacitor, phase-change memory, magnetoresistive memory, or ferroelectric memory. Taking a storage capacitor as an example, the storage capacitor includes a lower electrode, a dielectric layer, and a top electrode. The lower electrode of the storage capacitor is connected to the active layer of the transistor structure. The dielectric layer covers the lower electrode, and the top electrode covers the dielectric layer. Multiple storage capacitors share the top electrode.
[0075] In some embodiments, the material of the lower electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped single-crystal silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the lower electrode is titanium nitride (TiN). The method for forming the lower electrode material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is atomic layer deposition (ALD).
[0076] In some embodiments, the material of the capacitor dielectric layer is selected from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or includes at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The method for forming the capacitor dielectric layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.
[0077] In some embodiments, the material of the upper electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the upper electrode is titanium nitride (TiN). The method for forming the upper electrode material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for forming the lower electrode is atomic layer deposition (ALD).
[0078] In some embodiments, the upper electrode is covered with a filler layer. The filler layer material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped single-crystal silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the filler layer material is doped or undoped polycrystalline silicon. The filler layer is formed by a method selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.
[0079] Because the first word line electrode has a recrystallization layer, the resulting semiconductor device has better electrical performance.
[0080] The various semiconductor devices illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase-Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).
[0081] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which word line trenches are formed; A first electrode layer is formed in the word line trench; The first electrode layer is damaged to form an amorphous layer by destroying at least a portion of the surface grains. Recrystallize the amorphous layer; The first electrode layer is patterned to form the first word line electrode.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of destroying at least a portion of the surface grains of the first electrode layer to form the amorphous layer is as follows: The first electrode layer surface grains are destroyed by ion implantation.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The ion implantation process uses nitrogen for ion implantation.
4. The method for fabricating a semiconductor device according to claim 2, characterized in that, The ion implantation process uses nitrogen and krypton alternately for ion implantation.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of recrystallizing the amorphous layer is as follows: The amorphous layer is recrystallized using a cold sintering process.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The cold sintering process includes: Wet the first electrode layer; The air pressure is increased to 50 MPa to 600 MPa, with a pressurization rate of 20 MPa per second to 50 MPa per second; In an inert gas environment, the temperature is raised to 200°C to 400°C for 1 to 5 minutes, with a heating rate of 5°C to 20°C per second.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, A second electrode layer is formed on the surface of the first electrode layer; The first electrode layer is patterned while the second electrode layer is patterned to form the first word line electrode and the second word line electrode.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Execute in a loop multiple times. The step of destroying at least a portion of the surface grains of the first electrode layer to form the amorphous layer; The steps of re-crystallizing the amorphous layer.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the first electrode layer is titanium nitride.
10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The material of the second electrode layer is tungsten.
11. A semiconductor device, characterized in that, include: Semiconductor devices prepared by the method according to any one of claims 1-10.
12. A semiconductor device, characterized in that, include: A substrate having an array of active regions; A word line structure, wherein the word line structure is disposed in the substrate and passes through the active region; The word line structure and the active region it passes through constitute a transistor structure; The word line structure includes a first word line electrode, which includes a recrystallization layer, and the recrystallization layer has a denser lattice structure than other parts of the first word line electrode.
13. The semiconductor device according to claim 12, characterized in that, The word line structure further includes a second word line electrode; wherein the material of the first word line electrode is titanium nitride, and the material of the second word line electrode is tungsten.
14. The semiconductor device according to claim 12, characterized in that, The recrystallization layer is located on the surface of the first word line electrode away from the substrate.
15. The semiconductor device according to claim 12, characterized in that, The grain size of the recrystallized layer is smaller than the grain size of other parts of the first word electrode.