A semiconductor memory device, a manufacturing method thereof, and an electronic device
By using metallic materials and dielectric isolation units, combined with epitaxial growth and selective etching techniques, the problems of high bit line resistance and parasitic capacitance in semiconductor memory devices have been solved, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN SICARRIER IND MACHINES CO LTD
- Filing Date
- 2025-03-28
- Publication Date
- 2026-06-05
AI Technical Summary
The large resistance and parasitic capacitance of bit lines in existing semiconductor memory devices result in poor performance.
Metal bit lines are fabricated using metallic materials, and dielectric isolation units are set in the substrate structure to isolate the metal bit lines from the substrate. By combining epitaxial growth and selective etching techniques, the process flow is simplified and the resistance and parasitic capacitance are reduced.
It effectively reduces the resistance and parasitic capacitance of bit lines, thereby improving the performance of semiconductor memory devices.
Smart Images
Figure CN122161091A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and specifically discloses a semiconductor memory device and its fabrication method, as well as an electronic device. Background Technology
[0002] Semiconductor memory devices, characterized by fast read / write speeds, high integration density, and random access, have become core components of modern electronic systems. Currently, the bit lines (BLs) in semiconductor memory devices are fabricated using N+ ion implantation. However, the resistance and parasitic capacitance of BLs are relatively high, resulting in poor performance of semiconductor memory devices.
[0003] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0004] This application discloses semiconductor memory devices and their fabrication methods, as well as electronic devices, which are used to solve the problems of large bit line resistance and parasitic capacitance, and improve the performance of semiconductor memory devices.
[0005] In a first aspect, this application provides a semiconductor memory device, comprising:
[0006] Substrate structure; the substrate structure has opposing first and second surfaces;
[0007] Multiple metal bit lines are located on a first surface of the substrate structure, each metal bit line extends along a first direction, and the multiple metal bit lines are arranged along a second direction; the first direction and the second direction are perpendicular to each other;
[0008] Transistor, located on the surface of the metal bit line away from the substrate structure;
[0009] The capacitor is located on the side of the transistor away from the metal bit line.
[0010] The semiconductor memory device in this application includes a substrate structure, metal bit lines, transistors, and capacitors. The metal bit lines are made of metal, which can reduce the resistance and parasitic capacitance of the bit lines and improve the performance of the semiconductor memory device.
[0011] In one possible implementation, the substrate structure includes:
[0012] Substrate; the substrate has opposing first and second surfaces;
[0013] A first dielectric isolation section includes a first dielectric isolation unit and a plurality of second dielectric isolation units; the first dielectric isolation unit is located on a first surface of the substrate, and the plurality of second dielectric isolation units are arranged along a second direction, each second dielectric isolation unit extending from the surface of the first dielectric isolation unit away from the substrate to the transistor and corresponding to a word line;
[0014] A semiconductor transition layer is located on the surface of the first dielectric isolation unit away from the substrate;
[0015] A plurality of second dielectric isolation portions are arranged along a first direction, and each second dielectric isolation portion extends from the first dielectric isolation unit to the substrate.
[0016] In this embodiment, the first dielectric isolation unit in the substrate structure is located between the substrate and the metal bit line. The first dielectric isolation unit plays the role of isolation and blocking, which can prevent electrons from the metal bit line from moving to the substrate, thereby causing leakage problems and floating body effect.
[0017] In one possible implementation, the transistor includes a channel layer, source-drain structures located on two opposite surfaces of the channel layer, and word lines; the word lines are of equal width and located within the channel layer.
[0018] In this embodiment, the letter lines are of uniform width throughout, and can be directly filled during manufacturing. The sidewalls within the channel layer do not need to be etched, which simplifies the manufacturing process.
[0019] In one possible implementation, it also includes:
[0020] A metal transition layer located between the transistor and the capacitor.
[0021] In this embodiment, the contact resistance between the capacitor and the metal silicide layer can be reduced by setting a metal transition layer, thereby improving the performance of the semiconductor memory device.
[0022] Secondly, this application provides a method for fabricating a semiconductor memory device, comprising:
[0023] A memory device prefabricated structure is obtained; the memory device prefabricated structure includes a substrate structure and a transistor prefabricated structure stacked from bottom to top, and the memory device prefabricated structure has a plurality of first trenches extending from the transistor prefabricated structure to the substrate structure and arranged along a first direction; the substrate structure includes a first semiconductor layer;
[0024] The first semiconductor layer is selectively etched through the first trench and filled with metal material to form the metal bit line to be processed;
[0025] Remove the metal located on the sidewall of the first trench to form a plurality of metal bit lines; each of the metal bit lines extends along a first direction, and the plurality of metal bit lines are arranged along a second direction; the first direction and the second direction are perpendicular;
[0026] The memory device prefabrication structure is processed to form a transistor; the transistor is located on the surface of the metal bit line away from the substrate structure.
[0027] A capacitor is fabricated on the side of the transistor away from the metal bit line to obtain a semiconductor memory device.
[0028] The semiconductor memory device fabricated by the method in this embodiment includes a substrate structure, metal bit lines, transistors, and capacitors. The material of the metal bit lines is metal, which can reduce the resistance and parasitic capacitance of the bit lines and improve the performance of the semiconductor memory device.
[0029] In one possible implementation, obtaining the storage device prefabrication structure includes:
[0030] A second semiconductor layer, a semiconductor transition layer, and the first semiconductor layer are epitaxially grown sequentially on the first surface of a substrate to form a substrate prefabrication structure; the doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer.
[0031] A transistor prefabrication structure is fabricated on the surface of the first semiconductor layer away from the semiconductor transition layer to form the memory device prefabrication structure;
[0032] The memory device prefabricated structure is patterned in a first direction to form a plurality of first trenches, the first trenches extending from the transistor prefabricated structure into the substrate;
[0033] Multiple second dielectric isolation sections are formed by filling multiple first trenches with dielectric material;
[0034] In a second direction, the memory device prefabricated structure is patterned to form a plurality of second trenches, the second trenches extending from the transistor prefabricated structure to the interface between the substrate and the second semiconductor layer;
[0035] The second semiconductor layer is selectively etched through the second trench and filled with dielectric material to form a first dielectric isolation portion; the first dielectric isolation portion includes a first dielectric isolation unit located on a first surface of the substrate and a second dielectric isolation unit located in the second trench;
[0036] A portion of the second dielectric isolation portion in each of the first trenches is removed, and the remaining second dielectric isolation portion extends from the first dielectric isolation unit to the substrate.
[0037] In this embodiment, during the fabrication of the memory device prefabrication structure, a first dielectric isolation unit is fabricated in the substrate structure. The first dielectric isolation unit plays the role of isolation and blocking, which can prevent electrons from the metal bit lines from moving to the substrate, thereby avoiding leakage problems and floating body effects.
[0038] In one possible implementation, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0039] A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer.
[0040] The first doped silicon layer and the third doped silicon layer have the same doping elements, but are different from the doping elements in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0041] In this embodiment, the first, second, and third doped silicon layers are grown directly in situ using epitaxial growth, which eliminates the need for high-temperature processing, reduces interface damage between adjacent doped silicon layers, and eliminates the need for masks, thus reducing costs. Epitaxial growth is also easier to control, allowing for the definition of transistor dimensions.
[0042] In one possible implementation, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0043] A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer.
[0044] The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0045] In this embodiment, the first, second, and third doped silicon layers are grown directly in situ using epitaxial growth, which eliminates the need for high-temperature processing, reduces interface damage between adjacent doped silicon layers, and eliminates the need for masks, thus reducing costs. Epitaxial growth is also easier to control, allowing for the definition of transistor dimensions.
[0046] In one possible implementation, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0047] A first silicon layer, a second silicon layer, and a third silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer;
[0048] The first silicon layer, the second silicon layer, and the third silicon layer are doped to form a first doped silicon layer, a second doped silicon layer, and a third doped silicon layer, respectively.
[0049] The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0050] In this embodiment, undoped first, second, and third silicon layers are grown first, and then doped by implantation. This method is the same as the prior art, and no process modification is required.
[0051] In one possible implementation, processing the memory device prefabrication structure to form a transistor includes:
[0052] A third dielectric isolation section is formed by filling each of the first trenches with dielectric material.
[0053] A portion of the third dielectric isolation portion in each of the first trenches and a portion of the first dielectric isolation portion in each of the second trenches are removed, leaving the remaining first dielectric isolation portion and the third dielectric isolation portion flush with the interface between the first doped silicon layer and the second doped silicon layer;
[0054] A gate oxide layer is formed in the first trench and the second trench;
[0055] Metal is deposited in the first trench and the second trench, and the metal located at the bottom of the first trench is removed to form word lines; the word lines are of equal width at all points.
[0056] The first trench and the second trench are filled with dielectric material to form a first dielectric body;
[0057] The gate oxide layer and the word line are etched to obtain the transistor.
[0058] In this embodiment, the letter lines are formed by directly filling the first and second trenches with metal, so that the letter lines are of equal width everywhere, and there is no need to etch the sidewalls of the trench layer, thereby simplifying the manufacturing process.
[0059] In one possible implementation, after removing the metal located on the sidewall of the first trench to form a plurality of metal bit lines, the method further includes:
[0060] An annealing process is performed to form metal silicide between the metal bit line and the transistor.
[0061] The metal bit line is made of metal and contacts the source / drain structure in the transistor. The source / drain structure is a semiconductor. The contact resistance between the metal bit line and the source / drain structure is relatively large. In this embodiment, metal silicide is formed by annealing, which can reduce the contact resistance and improve the performance of the semiconductor memory device.
[0062] In one possible implementation, before forming a capacitor on the side of the transistor away from the metal bit line, the following is further included:
[0063] A metal transition layer is formed on the surface of the transistor away from the metal bit line.
[0064] In this embodiment, by fabricating a metal transition layer on the surface of the transistor, the contact resistance between the capacitor and the metal silicide layer can be reduced, thereby improving the performance of the semiconductor memory device.
[0065] Thirdly, this application provides an electronic device including any of the semiconductor memory devices described above. Attached Figure Description
[0066] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0067] Figure 1 A top view of a semiconductor memory device provided in an embodiment of this application;
[0068] Figure 2A A schematic cross-sectional view of a semiconductor memory device in the X direction provided in an embodiment of this application;
[0069] Figure 2B A schematic cross-sectional view of a semiconductor memory device in the Y direction provided in an embodiment of this application;
[0070] Figure 3A A cross-sectional schematic diagram in the X direction for another semiconductor memory device provided in an embodiment of this application;
[0071] Figure 3B A schematic cross-sectional view in the Y direction of another semiconductor memory device provided in an embodiment of this application;
[0072] Figure 4 A flowchart illustrating a method for fabricating a semiconductor memory device according to an embodiment of this application;
[0073] Figures 5A to 23BA process flow diagram illustrating the fabrication process of a semiconductor memory device provided in an embodiment of this application;
[0074] Figure 24A and Figure 24B This is a fabrication process diagram of another semiconductor memory device provided in an embodiment of this application.
[0075] Explanation of reference numerals in the attached figures:
[0076] 10-Substrate structure;
[0077] 101-Substrate; 102-First dielectric isolation layer; 103-Semiconductor transition layer; 104-Second dielectric isolation layer;
[0078] 30-capacitor;
[0079] 301 - First electrode; 302 - Second dielectric; 303 - Second electrode;
[0080] 40-transistor;
[0081] 401-Channel layer; 402-Source / drain structure; 403-Word line; 404-First dielectric; 405-Binder layer; 406-Gate oxide layer; 407-Third dielectric isolation section;
[0082] 20 - Metal bit line; 50 - Metal transition layer; 60 - Second semiconductor layer; 70 - First semiconductor layer; 80 - Hard mask; 90 - First trench; 100 - Second trench; 110 - Metal silicide layer. Detailed Implementation
[0083] There are various types of semiconductor memory devices, such as DRAM (Dynamic Random Access Memory). DRAM typically uses a two-dimensional matrix of capacitors and transistors as units, and its principle is to use the amount of charge stored in the capacitor to represent a binary bit. For example, the BL in 4F2 DRAM is formed using N+ ion implantation. BL has relatively high resistance and parasitic capacitance, resulting in poor performance of the semiconductor memory device. The technology in this application can be applied to 4F2 DRAM, and the following embodiments use 4F2 DRAM as an example for description.
[0084] Example 1
[0085] This embodiment provides a semiconductor memory device; please refer to [reference needed]. Figures 1 to 2B It can include:
[0086] Substrate structure 10; the substrate structure 10 has opposing first and second surfaces;
[0087] Multiple metal bit lines 20 are located on the first surface of the substrate structure 10, each metal bit line 20 extends along a first direction, and the multiple metal bit lines 20 are arranged along a second direction; the first direction and the second direction are perpendicular to each other;
[0088] Transistor 40 is located on the surface of the metal bit line 20 away from the substrate structure 10;
[0089] Capacitor 30 is located on the side of transistor 40 away from metal bit line 20.
[0090] The first direction is the Y direction, and the second direction is the X direction.
[0091] It should be noted that the semiconductor memory device also includes a metal silicide layer 110 located between the transistor 40 and the capacitor 30.
[0092] Transistor 40 includes a channel layer 401, a source-drain structure 402, and a word line 403, which are well known to those skilled in the art and will not be described in detail here.
[0093] In this embodiment, the number of metal bit lines 20 is not limited and depends on the situation. Figure 1 The number of metal bit lines 20 is shown as an example of six.
[0094] The material of the metal bit line 20 is entirely metal. The specific type of metal is not limited in this embodiment and can be selected at will. For example, the material of the metal bit line can be W, Ru, Mo, etc.
[0095] The capacitor 30 includes a first electrode 301, a second dielectric 302, and a second electrode 303. The first electrode 301 can be made of a metallic material, such as TiN, Ru, or Mo. The second dielectric 302 can be made of a high dielectric constant material, such as any one of HfO2, ZrO2, AlO2, TiO2, Nb2O5, and SrTiO3, or any combination of HfO2, ZrO2, AlO2, and TiO2. The second electrode 303 can be made of a metallic material, such as TiN, Ru, or Mo.
[0096] It should be noted that the substrate structure is not limited in this embodiment, as long as it can at least provide a substrate effect for semiconductor memory devices.
[0097] The semiconductor memory device in this embodiment includes a substrate structure 10, a metal bit line 20, a transistor 40, and a capacitor 30. The metal bit line 20 is made of metal, which can reduce the resistance and parasitic capacitance of the bit line and improve the performance of the semiconductor memory device.
[0098] Example 2
[0099] Based on the above embodiments, in this embodiment, the substrate structure 10 includes:
[0100] Substrate 101; the substrate 101 has opposing first and second surfaces;
[0101] The first dielectric isolation section 102 includes a first dielectric isolation unit and a plurality of second dielectric isolation units; the first dielectric isolation unit is located on a first surface of the substrate 101, and the plurality of second dielectric isolation units are arranged along a second direction, each second dielectric isolation unit extending from the surface of the first dielectric isolation unit away from the substrate 101 to the transistor 40 and corresponding to the word line 403;
[0102] Semiconductor transition layer 103 is located on the surface of the first dielectric isolation unit away from the substrate 101;
[0103] A plurality of second dielectric isolation portions 104 are arranged along a first direction, and each second dielectric isolation portion 104 extends from the first dielectric isolation unit to the substrate 101.
[0104] Substrate 101 can be a silicon substrate.
[0105] The material of the first dielectric isolation section 102 includes, but is not limited to, insulating dielectric materials such as SiO, SiN, and Al2O3, but is not specifically limited in this embodiment.
[0106] The first and second media isolation units are manufactured as a single unit.
[0107] The end of the second dielectric isolation unit furthest from the first dielectric isolation unit is flush with the interface between the channel layer 401 and the source / drain structure 402 in the transistor 40, such as... Figure 2A As shown.
[0108] The semiconductor transition layer 103 can be a silicon layer or a doped silicon layer, and the doping element can be B, P or Ge.
[0109] The material of the second dielectric isolation section 104 can be SiO, SiN, Al2O3, etc., and no specific limitation is made in this embodiment.
[0110] like Figure 2B As shown, one end of the second dielectric isolation portion 104 is flush with the interface between the first dielectric isolation unit and the metal bit line 20, and the other end is located inside the substrate 101.
[0111] In this embodiment, a first dielectric isolation section 102 including a first dielectric isolation unit and a plurality of second dielectric isolation units is provided in the substrate structure 10. The first dielectric isolation unit is located between the substrate 101 and the metal bit line 20. The first dielectric isolation unit plays the role of isolation and blocking, which can prevent electrons from the metal bit line 20 from moving to the substrate 101, thereby causing leakage current and floating body effect.
[0112] Example 3
[0113] Based on any of the above embodiments, in this embodiment, the transistor 40 includes a channel layer 401, source-drain structures 402 located on two opposite surfaces of the channel layer 401, and word lines 403; the word lines 403 are of equal width at all locations and are located in the channel layer 401.
[0114] Word line 403 is also known as gate. The material of word line 403 is metal, such as W, Mo, Ru, etc., but no specific limitation is made in this embodiment.
[0115] It should be noted that the transistor 40 also includes a first dielectric 404 filled inside the word line 403 and an adhesive layer 405 located on the outer surface of the word line 403. The material of the first dielectric 404 can be a material with a low dielectric constant, such as SiOC, SiCN, SiN, etc.; the material of the adhesive layer can be TiN.
[0116] As one possible implementation, transistor 40 may further include a gate oxide layer 406 located between word line 403 and channel layer 401, which isolates the direct contact between word line 403 and channel layer 401 and can prevent current in word line 403 from flowing directly into channel layer 401.
[0117] In this embodiment, the letter lines 403 are of equal width at all points, and can be directly filled during manufacturing. The sidewalls inside the channel layer 401 do not need to be etched, which simplifies the manufacturing process.
[0118] Example 4
[0119] Based on any of the above embodiments, in this embodiment, please refer to Figure 3A and Figure 3B Semiconductor storage devices may also include:
[0120] A metal transition layer 50 is located between the transistor 40 and the capacitor 30.
[0121] The material of the metal transition layer 50 can be W, etc.
[0122] It should be noted that an adhesive layer is also provided between the metal transition layer 50 and the metal silicide 110, and the material of the adhesive layer can be TiN.
[0123] The contact resistance between the metal silicide layer 110 and the capacitor 30 is relatively large. By providing the metal transition layer 50, the contact resistance between the capacitor 30 and the metal silicide layer 110 can be reduced, thereby improving the performance of the semiconductor memory device.
[0124] Example 5
[0125] This embodiment provides a method for fabricating a semiconductor memory device. Please refer to [link / reference]. Figure 4 It can include:
[0126] Step S101: Obtain a memory device prefabricated structure; the memory device prefabricated structure includes a substrate structure and a transistor prefabricated structure stacked from bottom to top, the memory device prefabricated structure having a plurality of first trenches extending from the transistor prefabricated structure to the substrate structure and arranged along a first direction; the substrate structure includes a first semiconductor layer.
[0127] As one possible implementation, obtaining a prefabricated structure for the storage device includes:
[0128] Step S1011: A second semiconductor layer, a semiconductor transition layer and the first semiconductor layer are epitaxially grown sequentially on the first surface of the substrate to form a substrate prefabrication structure; the doping concentration of the second semiconductor layer is greater than the doping concentration of the first semiconductor layer.
[0129] like Figure 5A and Figure 5B As shown, the second semiconductor layer 60, the semiconductor transition layer 103, and the first semiconductor layer 70 are stacked sequentially on the first surface of the substrate 101 from bottom to top.
[0130] The substrate is a clean substrate.
[0131] The second semiconductor layer 60 and the first semiconductor layer 70 can be doped silicon layers, and the doping element can be Ge, etc.
[0132] The reason why the doping concentration of the second semiconductor layer 60 is greater than that of the first semiconductor layer 70 is to enable selective etching in the subsequent process. The higher the doping concentration, the faster the selective etching rate. In the subsequent fabrication, the second semiconductor layer needs to be etched away first in order to fill the dielectric material to achieve isolation. Therefore, the doping concentration of the second semiconductor layer needs to be higher.
[0133] The doping concentration in the second semiconductor layer 60 can range from 5% to 80%, and the doping concentration in the first semiconductor layer can also range from 5% to 80%. The lower the doping concentration of the second semiconductor layer 60 and the first semiconductor layer 70, the closer their properties are to silicon, and the easier it is to epitaxially grow them on a silicon substrate. Since the doping concentrations of the second semiconductor layer 60 and the first semiconductor layer 70 need to be different, setting the doping concentration of the second semiconductor layer 60 within this range facilitates setting the doping concentration of the first semiconductor layer 70, thereby creating a larger difference between the doping concentrations of the second semiconductor layer 60 and the first semiconductor layer 70.
[0134] The semiconductor transition layer 103 can be a silicon layer or a doped silicon layer, and the doping element can be B or P.
[0135] As one possible implementation, the difference in doping concentration between the second semiconductor layer 60 and the first semiconductor layer 70 can be in the range of 5% to 75%, so that there is a relatively large difference in selectivity between the second semiconductor layer and the first semiconductor layer 70, thereby enabling better selective etching.
[0136] The thickness of the second semiconductor layer 60 can be between 2nm and 100nm, the range of the semiconductor transition layer 103 can be between 0.5nm and 50nm, and the range of the thickness of the first semiconductor layer 70 can be between 2nm and 100nm. The specific thickness can be set by the user and is not specifically limited in this application.
[0137] Step S1012: Fabricate a transistor prefabricated structure on the surface of the first semiconductor layer away from the semiconductor transition layer to form the memory device prefabricated structure.
[0138] like Figure 5A and Figure 5B As shown, the transistor prefabrication structure includes a first doped silicon layer, a second doped silicon layer, and a third doped silicon layer stacked sequentially from bottom to top on the first semiconductor layer 70. The second doped silicon layer serves as the channel layer 401, and the first and third doped silicon layers serve as the source / drain structure 402.
[0139] The method of fabricating the transistor prefabrication structure is not limited in this embodiment, but will be described in the following embodiments.
[0140] Step S1013: The memory device prefabricated structure is patterned in a first direction to form a plurality of the first trenches, the first trenches extending from the transistor prefabricated structure into the substrate.
[0141] like Figure 6A and Figure 6BAs shown, a hard mask 80 is formed on the transistor prefabrication structure, and then patterning is performed to form first trenches 90 arranged in a first direction. Multiple first trenches 90 are arranged along the first direction. The first trenches 90 are trenches of equal width, and the critical dimensions of the first trenches 90 can range from 10nm to 100nm.
[0142] Step S1014: Fill the plurality of first trenches with dielectric material to form a plurality of second dielectric isolation sections.
[0143] like Figure 7A and Figure 7B As shown, the dielectric material fills the first trench 90 to form the second dielectric isolation section 104. The dielectric material can be SiO, SiN, Al2O3, etc.
[0144] The functions of the second medium isolation section 104 include: first, supporting the column structure between two adjacent second medium isolation sections 104 to prevent collapse; second, reserving space for subsequent fabrication of the character line 403; and third, serving as a partition structure between two adjacent metal character lines 20.
[0145] Step S1015: The memory device prefabricated structure is patterned in a second direction to form a plurality of second trenches, the second trenches extending from the transistor prefabricated structure to the interface between the substrate and the second semiconductor layer.
[0146] like Figure 8A and Figure 8B As shown, the second trench 100 is formed by patterning. The critical dimension of the second trench 100 can be in the range of 10nm to 100nm. The critical dimension of the second trench 100 is smaller than that of the first trench 90.
[0147] Step S1016: Selectively etch the second semiconductor layer through the second trench and fill it with dielectric material to form a first dielectric isolation portion; the first dielectric isolation portion includes a first dielectric isolation unit located on the first surface of the substrate and a second dielectric isolation unit located in the second trench.
[0148] like Figure 9A and Figure 9B As shown, the second semiconductor layer is selectively etched away.
[0149] like Figure 10A and Figure 10B As shown, the dielectric material fills the region where the second semiconductor layer is located and the second trench 100 to obtain the first dielectric isolation portion 102. The filling dielectric material can be SiO, SiN, Al2O3, etc.
[0150] The first dielectric isolation unit is made of insulating dielectric material. It is located between the metal bit line 20 and the substrate, and serves to separate the metal bit line 20 and the substrate to avoid the floating body effect and leakage problems.
[0151] Step S1017: Remove a portion of the second dielectric isolation portion in each of the first trenches, with the remaining second dielectric isolation portion extending from the first dielectric isolation unit to the substrate.
[0152] like Figure 11A and Figure 11B As shown, the second dielectric isolation portion 104 is etched back to remove a portion of the second dielectric isolation portion 104.
[0153] In the process of fabricating the memory device prefabrication structure, a first dielectric isolation unit is fabricated in the substrate structure. The first dielectric isolation unit plays the role of isolation and blocking, which can prevent electrons from the metal bit lines from moving to the substrate, thus preventing leakage problems and floating body effect.
[0154] Step S102: Selectively etch the first semiconductor layer through the first trench and fill it with metal material to form the metal bit line to be processed.
[0155] like Figure 12A and Figure 12B As shown, the first semiconductor layer 70 is selectively removed.
[0156] like Figure 13A and Figure 13B As shown, the metal material fills the area where the first semiconductor layer 70 is located, and the sidewalls of the first trench 90 are also distributed with metal as the metal bit line 20 to be processed.
[0157] Step S103: Remove the metal located on the sidewall of the first trench to form a plurality of metal bit lines; each of the metal bit lines extends along a first direction, and the plurality of metal bit lines are arranged along a second direction; the first direction and the second direction are perpendicular.
[0158] like Figure 14A and Figure 14B As shown, the metal bit line 20 to be processed is etched back to form the metal bit line 20.
[0159] As one possible implementation, after removing the metal located on the sidewall of the first trench to form multiple metal bit lines, the process may further include:
[0160] An annealing process is performed to form metal silicide between the metal bit line and the transistor.
[0161] The metal bit line is made of metal and contacts the source / drain structure in the transistor. The source / drain structure is a semiconductor. The contact resistance between the metal bit line and the source / drain structure is relatively large. By annealing to form metal silicide, the contact resistance can be reduced and the performance of the semiconductor memory device can be improved.
[0162] Step S104: Process the memory device prefabrication structure to form a transistor; the transistor is located on the surface of the metal bit line away from the substrate structure.
[0163] As one possible implementation, processing the memory device prefabrication structure to form a transistor may include:
[0164] Step S1041: Fill each of the first trenches with a dielectric material to form a third dielectric isolation section.
[0165] like Figure 15A and Figure 15B As shown, the dielectric material is located above the metal bit line 20 and fills the first trench 90 to form the third dielectric isolation portion 407. The dielectric material can be SiO, SiN, Al2O3, etc.
[0166] Step S1042: Remove a portion of the third dielectric isolation portion in each of the first trenches and a portion of the first dielectric isolation portion in each of the second trenches, leaving the remaining first dielectric isolation portion and the third dielectric isolation portion flush with the interface between the first doped silicon layer and the second doped silicon layer.
[0167] like Figure 16A and Figure 16B As shown, the third dielectric isolation section 407 and the first dielectric isolation section 102 are subjected to a back-etching process.
[0168] Step S1043: Form a gate oxide layer in the first trench and the second trench.
[0169] like Figure 17A and Figure 17B As shown, the gate oxide layer 406 is located on the sidewall of the first trench 90 and the surface of the third dielectric isolation portion 407, and on the sidewall of the second trench 100 and the surface of the first dielectric isolation portion 102.
[0170] The fabrication methods for the gate oxide layer 406 include, but are not limited to, ALD (Atomic Layer Deposition), ISSG (In Situ Steam Generation), and RPO (Removed Plasma Oxidation).
[0171] In this embodiment, the gate oxide layer 406 can isolate the direct contact between the word line 403 and the channel layer 401, and can prevent the current in the word line 403 from flowing directly into the channel layer 401.
[0172] Step S1044: Deposit metal in the first trench and the second trench, and remove the metal located at the bottom of the first trench to form word lines; the word lines are of equal width at all locations.
[0173] like Figure 18A and Figure 18B As shown, before depositing the metal, a TiN binder layer 405 is deposited first, followed by metal deposition. Then, the metal and binder layer 405 at the bottom of the first trench 90 are etched in the Y direction to form the word line 403. The word line 403 can also be called the gate. The metal material can be W, Mo, Ru, etc.
[0174] It should be noted that when the metal material of the word line 403 is other metals such as Mo or Ru, the adhesive layer 405 may not be required.
[0175] In this embodiment, the word lines 403 are formed by directly filling the first trench 90 and the second trench 100 with metal, so that the word lines 403 have the same width everywhere, without the need to etch the sidewalls of the channel layer 401, thereby simplifying the manufacturing process.
[0176] Step S1045: Fill the first trench and the second trench with dielectric material to form a first dielectric.
[0177] like Figure 19A and Figure 19B As shown, a first dielectric 404 is formed in the first trench 90 and the second trench 100. The material of the first dielectric 404 can be a material with a low dielectric constant, such as SiOC, SiCN, SiN, etc.
[0178] Step S1046: Etch the gate oxide layer and the word line to obtain a transistor.
[0179] like Figure 20A and Figure 20B As shown, the gate oxide layer 406 and word line 403 are etched back to the interface between the source / drain structure 402 and the channel layer 401, or slightly below the interface between the source / drain structure 402 and the channel layer 401.
[0180] In this embodiment, etching is used to etch the gate oxide layer 406 and the word line 403, which can precisely control the size of the gate oxide layer 406 and the word line 403.
[0181] It should be noted that after the etch back, the first and second trenches need to be filled with a low dielectric constant material, such as SiOC, SiCN, or SiN, before grinding and polishing. Figure 21A and Figure 21B As shown.
[0182] It should be noted that other methods can also be used to fabricate transistors, and this embodiment does not impose any specific limitations.
[0183] Step S105: A capacitor is fabricated on the side of the transistor away from the metal bit line to obtain a semiconductor memory device.
[0184] The process of manufacturing a capacitor may include:
[0185] Step S1051: Deposit a metal layer on the surface of the transistor and perform annealing to form a metal silicide layer;
[0186] like Figure 22A and Figure 22B As shown, the metal silicide layer 110 is located on the surface of the source / drain structure 402. After annealing, further cleaning or etching is required to remove excess metal material from the surface. The deposited metal material can be Mo, Ti, Co, etc.
[0187] Step S1052: Form the first electrode of the capacitor on the surface of the metal silicide layer.
[0188] like Figure 23A and Figure 23B As shown, the capacitor architecture is first formed through patterning and etching. Each capacitor corresponds to a pillar between adjacent first trench 90 and adjacent second trench 100. Then, a metal material, such as TiN, Ru, Mo, etc., is filled in to form the first electrode 301.
[0189] Step S1053: Fill with dielectric material to form a second dielectric, and fill with metal to form a second electrode.
[0190] like Figure 2A and Figure 2B As shown, a material with a high dielectric constant is filled to form a second dielectric 302. The material with a high dielectric constant can be any one of HfO2, ZrO2, AlO2, TiO2, Nb2O5, and SrTiO3, or any combination of HfO2, ZrO2, AlO2, and TiO2. Then, a metal is filled to form a second electrode 303. The metal material of the second electrode 303 can be TiN, Mo, Ru, etc.
[0191] As one possible implementation, before fabricating a capacitor on the side of the transistor away from the metal bit line, the following may be included:
[0192] A metal transition layer is formed on the surface of the transistor away from the metal bit line.
[0193] like Figure 24A and Figure 24B As shown, a binder layer is first deposited on the surface of the metal silicide layer 110, and then a metal transition layer 50 is deposited. The binder layer can be made of TiN, and the metal transition layer 50 can be made of W, etc. Correspondingly, the first electrode 301 of the capacitor is fabricated on the surface of the metal transition layer 50, as shown. Figure 3A and Figure 3B As shown.
[0194] Since the contact resistance between the metal silicide layer 110 and the capacitor is relatively large, the contact resistance between the capacitor and the metal silicide can be reduced by setting the metal transition layer 50, thereby improving the performance of the semiconductor memory device.
[0195] The semiconductor memory device fabricated by the method in this embodiment includes a substrate structure, metal bit lines, transistors, and capacitors. The material of the metal bit lines is metal, which can reduce the resistance and parasitic capacitance of the bit lines and improve the performance of the semiconductor memory device.
[0196] Example 6
[0197] Based on the above embodiments, in this embodiment, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0198] A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer.
[0199] The first doped silicon layer and the third doped silicon layer have the same doping elements, but are different from the doping elements in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0200] The doping elements in the first, second, and third doped silicon layers can be any of B, P, As, Sb, etc., and no specific limitation is made in this embodiment. For example, the first and third doped silicon layers can be doped with P, and the second doped silicon layer can be doped with B.
[0201] By doping with different elements, the source / drain structure and channel layer are defined, forming the contact between the source / drain structure and the metal bit lines and capacitors.
[0202] In this embodiment, the first, second, and third doped silicon layers are grown directly in situ using epitaxial growth, which eliminates the need for high-temperature processing, reduces interface damage between adjacent doped silicon layers, and eliminates the need for masks, thus reducing costs. Epitaxial growth also makes it easier to control the growth process and allows for the definition of transistor dimensions.
[0203] Example 7
[0204] Based on the above embodiments, in this embodiment, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0205] A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer.
[0206] The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0207] In this embodiment, the first, second, and third doped silicon layers contain the same doping element, which can be any one of B, P, As, Sb, etc. The doping concentration range in the first, second, and third doped silicon layers can be 1E14~1E22 / cm³. 3 .
[0208] By doping with the same element and controlling different doping concentrations, the source / drain structure and channel layer are defined, forming the contact between the source / drain structure and the metal bit lines and capacitors.
[0209] In this embodiment, the first, second, and third doped silicon layers are grown directly in situ using epitaxial growth, which eliminates the need for high-temperature processing, reduces interface damage between adjacent doped silicon layers, and eliminates the need for masks, thus reducing costs. Epitaxial growth also makes it easier to control the growth process and allows for the definition of transistor dimensions.
[0210] Example 8
[0211] Based on the above embodiments, in this embodiment, fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes:
[0212] A first silicon layer, a second silicon layer, and a third silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer;
[0213] The first silicon layer, the second silicon layer, and the third silicon layer are doped to form a first doped silicon layer, a second doped silicon layer, and a third doped silicon layer, respectively.
[0214] The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
[0215] By doping with the same element and controlling different doping concentrations, the source / drain structure and channel layer are defined, forming the contact between the source / drain structure and the metal bit lines and capacitors.
[0216] In this embodiment, undoped first, second, and third silicon layers are grown first, and then doped by implantation. This method is the same as the prior art, and no process modification is required.
[0217] Example 9
[0218] This embodiment provides an electronic device, including the semiconductor memory device described in any of the above embodiments.
[0219] Electronic devices include, but are not limited to, computers, servers, and mobile storage devices.
[0220] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A semiconductor memory device, characterized in that, include: Substrate structure; The substrate structure has opposing first and second surfaces; Multiple metal bit lines are located on a first surface of the substrate structure, each metal bit line extends along a first direction, and the multiple metal bit lines are arranged along a second direction; the first direction and the second direction are perpendicular to each other; A transistor is located on the surface of the metal bit line away from the substrate structure; The capacitor is located on the side of the transistor away from the metal bit line.
2. The semiconductor memory device as claimed in claim 1, characterized in that, The substrate structure includes: Substrate; the substrate has opposing first and second surfaces; A first dielectric isolation section includes a first dielectric isolation unit and a plurality of second dielectric isolation units; the first dielectric isolation unit is located on a first surface of the substrate, and the plurality of second dielectric isolation units are arranged along a second direction, each second dielectric isolation unit extending from the surface of the first dielectric isolation unit away from the substrate to the transistor and corresponding to a word line; A semiconductor transition layer is located on the surface of the first dielectric isolation unit away from the substrate; A plurality of second dielectric isolation portions are arranged along a first direction, and each second dielectric isolation portion extends from the first dielectric isolation unit to the substrate.
3. The semiconductor memory device as claimed in claim 1, characterized in that, The transistor includes a channel layer, source and drain structures located on two opposite surfaces of the channel layer, and word lines; the word lines are of equal width and are located in the channel layer.
4. The semiconductor memory device according to any one of claims 1 to 3, characterized in that, Also includes: A metal transition layer located between the transistor and the capacitor.
5. A method for fabricating a semiconductor memory device, characterized in that, include: Obtain the prefabricated structure of the storage device; The memory device prefabricated structure includes a substrate structure and a transistor prefabricated structure stacked from bottom to top. The memory device prefabricated structure is distributed with a plurality of first trenches extending from the transistor prefabricated structure to the substrate structure and arranged along a first direction. The substrate structure includes a first semiconductor layer; The first semiconductor layer is selectively etched through the first trench and filled with metal material to form the metal bit line to be processed; Remove the metal located on the sidewall of the first trench to form multiple metal bit lines; Each of the metal bit lines extends along a first direction, and the plurality of metal bit lines are arranged along a second direction; the first direction and the second direction are perpendicular to each other. The memory device prefabrication structure is processed to form a transistor; the transistor is located on the surface of the metal bit line away from the substrate structure. A capacitor is fabricated on the side of the transistor away from the metal bit line to obtain a semiconductor memory device.
6. The method for fabricating a semiconductor memory device as described in claim 5, characterized in that, Obtaining the prefabricated structure of the storage device includes: A second semiconductor layer, a semiconductor transition layer, and the first semiconductor layer are epitaxially grown sequentially on the first surface of a substrate to form a substrate prefabrication structure; the doping concentration of the second semiconductor layer is greater than that of the first semiconductor layer. A transistor prefabrication structure is fabricated on the surface of the first semiconductor layer away from the semiconductor transition layer to form the memory device prefabrication structure; The memory device prefabricated structure is patterned in a first direction to form a plurality of first trenches, the first trenches extending from the transistor prefabricated structure into the substrate; Multiple second dielectric isolation sections are formed by filling multiple first trenches with dielectric material; In a second direction, the memory device prefabricated structure is patterned to form a plurality of second trenches, the second trenches extending from the transistor prefabricated structure to the interface between the substrate and the second semiconductor layer; The second semiconductor layer is selectively etched through the second trench and filled with dielectric material to form a first dielectric isolation portion; the first dielectric isolation portion includes a first dielectric isolation unit located on a first surface of the substrate and a second dielectric isolation unit located in the second trench; A portion of the second dielectric isolation portion in each of the first trenches is removed, and the remaining second dielectric isolation portion extends from the first dielectric isolation unit to the substrate.
7. The method for fabricating a semiconductor memory device as described in claim 6, characterized in that, Fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes: A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer. The first doped silicon layer and the third doped silicon layer have the same doping elements, but are different from the doping elements in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
8. The method for fabricating a semiconductor memory device as described in claim 6, characterized in that, Fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes: A first doped silicon layer, a second doped silicon layer, and a third doped silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer. The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
9. The method for fabricating a semiconductor memory device as described in claim 6, characterized in that, Fabricating a transistor prefabrication structure on the surface of the first semiconductor layer away from the semiconductor transition layer includes: A first silicon layer, a second silicon layer, and a third silicon layer are epitaxially grown sequentially on the surface of the first semiconductor layer away from the semiconductor transition layer; The first silicon layer, the second silicon layer, and the third silicon layer are doped to form a first doped silicon layer, a second doped silicon layer, and a third doped silicon layer, respectively. The first doped silicon layer and the third doped silicon layer have the same doping concentration, but different from the doping concentration in the second doped silicon layer; the first doped silicon layer and the third doped silicon layer serve as source / drain structures, and the second doped silicon layer serves as a channel layer.
10. The method for fabricating a semiconductor memory device according to any one of claims 7 to 9, characterized in that, Processing the memory device prefabrication structure to form a transistor includes: A third dielectric isolation section is formed by filling each of the first trenches with dielectric material. A portion of the third dielectric isolation portion in each of the first trenches and a portion of the first dielectric isolation portion in each of the second trenches are removed, leaving the remaining first dielectric isolation portion and the third dielectric isolation portion flush with the interface between the first doped silicon layer and the second doped silicon layer; A gate oxide layer is formed in the first trench and the second trench; Metal is deposited in the first trench and the second trench, and the metal located at the bottom of the first trench is removed to form word lines; the word lines are of equal width at all points. The first trench and the second trench are filled with dielectric material to form a first dielectric body; The gate oxide layer and the word line are etched to obtain the transistor.
11. The method for fabricating a semiconductor memory device as described in claim 5, characterized in that, After removing the metal located on the sidewall of the first trench to form multiple metal bit lines, the process further includes: An annealing process is performed to form metal silicide between the metal bit line and the transistor.
12. The method for fabricating a semiconductor memory device according to any one of claims 5 to 11, characterized in that, Before fabricating a capacitor on the side of the transistor away from the metal bit line, the following is also included: A metal transition layer is formed on the surface of the transistor away from the metal bit line.
13. An electronic device, characterized in that, Includes the semiconductor memory device as described in any one of claims 1 to 4.