Semiconductor structure and method of forming the same, memory
By forming a second trench in the substrate and embedding word line structures, and forming and sealing air gaps between adjacent word line structures, the problems of increased parasitic capacitance and power consumption in semiconductor devices are solved, achieving higher integration and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-08-24
- Publication Date
- 2026-07-07
AI Technical Summary
As semiconductor devices shrink in size, the spacing between word lines decreases, leading to increased parasitic capacitance, power consumption, and impact on product stability.
A second trench is formed in the substrate and word line structures are embedded therein. An air gap is formed between adjacent word line structures and the air gap is sealed by a sealing layer to reduce parasitic capacitance.
It effectively reduces parasitic capacitance between word line structures, reduces power consumption, and improves device integration and product yield.
Smart Images
Figure CN117693185B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology
[0002] With the continuous development of mobile devices, battery-powered mobile devices such as mobile phones, tablets, and wearable devices are increasingly used in our lives. As an indispensable component in mobile devices, memory has generated huge demands for smaller size and integration.
[0003] Currently, Dynamic Random Access Memory (DRAM) is widely used in mobile devices due to its fast data transfer speed. However, as semiconductor devices continue to shrink in size, the number of word lines per unit area increases, leading to smaller spacing between word lines, increased parasitic capacitance between word lines, and consequently, increased power consumption of the semiconductor structure.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce parasitic capacitance, lower power consumption, and improve product stability.
[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:
[0007] A substrate is provided, the substrate comprising a substrate and an insulating dielectric layer, the substrate comprising a plurality of first trenches spaced apart along a first direction, the insulating dielectric layer filling each of the first trenches;
[0008] The substrate is patterned by etching to form a plurality of second trenches spaced apart along a second direction, the second direction intersecting the first direction;
[0009] A character line structure is formed in each of the second grooves;
[0010] An air gap is formed between two adjacent word line structures;
[0011] The air gap is then sealed.
[0012] In one exemplary embodiment of this disclosure, the forming method further includes:
[0013] An insulating layer is formed between adjacent word line structures, and the air gap is located within the insulating layer.
[0014] In one exemplary embodiment of this disclosure, forming the insulating layer includes:
[0015] A protective layer is formed that conforms to the sidewall of the second groove;
[0016] A first insulating material layer is formed on the surface of the structure formed by the substrate and the protective layer;
[0017] A first insulating layer is formed in the second trench having the first insulating material layer, wherein the top of the first insulating layer is lower than the top of the first insulating layer;
[0018] A second insulating material layer is formed on top of the first insulating layer;
[0019] The surface of the second insulating material layer is planarized so that the top of the second insulating material layer is flush with the surface of the substrate, and the remaining second insulating material layer together with the first insulating material layer constitutes the second insulating layer.
[0020] The protective layer and the insulating dielectric layer are etched back to form insulating gaps;
[0021] The insulating gaps are filled with insulating material, and the insulating material together with the second insulating layer constitutes a passivation layer.
[0022] In a direction perpendicular to the substrate, the protective layer of a predetermined thickness is removed to form a word line filling trench, the word line filling trench not exposing the bottom of the second trench.
[0023] In one exemplary embodiment of this disclosure, forming the word line structure includes:
[0024] An inter-gate dielectric layer is formed at the bottom of the word line filling groove and on the sidewall of the word line filling groove away from the insulating layer;
[0025] A first conductive material is filled into the word line filling trench having the inter-gate dielectric layer to form a word line structure.
[0026] In one exemplary embodiment of this disclosure, forming the air gap includes:
[0027] After the word line structure is formed, the passivation layer is etched back until the first insulating layer is exposed;
[0028] Remove the first insulating layer to form the air gap.
[0029] In one exemplary embodiment of this disclosure, sealing the air gap includes:
[0030] A sealing layer is formed on the surface of the passivation layer having the air gap, the sealing layer at least covering the opening of the air gap.
[0031] In one exemplary embodiment of this disclosure, the forming method further includes:
[0032] Before the word line structure is formed, a bit line structure is formed at the bottom of the second trench, the bit line structure traversing multiple second trenches, and the bit line structure is insulated from the word line structure.
[0033] In one exemplary embodiment of this disclosure, forming the bitline structure includes:
[0034] A portion of the substrate material located below the second trench is removed to form a third trench below the second trench, the third trench penetrating each of the second trenches;
[0035] The third trench is filled with a second conductive material to form the bit line structure.
[0036] In one exemplary embodiment of this disclosure, the protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated from each other by the protective layer.
[0037] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:
[0038] The substrate includes a substrate and an insulating dielectric layer. The substrate includes a plurality of first trenches spaced apart along a first direction and a plurality of second trenches spaced apart along a second direction. The insulating dielectric layer fills each of the first trenches, and the second trenches penetrate each of the first trenches and the insulating dielectric layer therein. The second direction intersects the first direction.
[0039] Multiple character line structures are formed in each of the second grooves, and an air gap is formed between two adjacent character line structures;
[0040] A sealing layer that at least covers the opening of the air gap.
[0041] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:
[0042] An insulating layer is formed between adjacent word line structures, and the air gap is located within the insulating layer.
[0043] In one exemplary embodiment of this disclosure, the insulating layer includes:
[0044] A protective layer is located on the sidewall of the second trench, and in a direction perpendicular to the substrate, the top of the protective layer is lower than the top surface of the second trench;
[0045] A passivation layer fills the second trench having the protective layer, and in a direction perpendicular to the substrate, a word line filling trench is formed at one end of the passivation layer away from the protective layer. The air gap is located in the passivation layer between adjacent word line filling trenches, and the air gap is insulated from the word line filling trench through the passivation layer.
[0046] In one exemplary embodiment of this disclosure, the word line structure includes:
[0047] An inter-gate dielectric layer is formed at the bottom of the word line filling trench and on the sidewall of the word line filling trench away from the insulating layer;
[0048] A first conductive layer is filled in the word line filling trench having the inter-gate dielectric layer.
[0049] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:
[0050] A bit line structure is formed at the bottom of the second trench, the bit line structure traverses multiple second trenches, and the bit line structure is insulated from the word line structure.
[0051] In one exemplary embodiment of this disclosure, the protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated from each other by the protective layer.
[0052] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.
[0053] The semiconductor structure and its formation method disclosed herein, as well as the memory, on the one hand, help save structural space and improve device integration by forming a second trench in the substrate and burying the word line structure in the second trench; on the other hand, an air gap can be formed between two adjacent word line structures. Since the dielectric constant of the air gap is small, the parasitic capacitance between the word line structures can be effectively reduced, thereby reducing device power consumption; furthermore, by sealing the air gap, the air gap can be sealed between adjacent word line structures, which can prevent the final semiconductor structure from breaking at the opening of the air gap and improve product yield.
[0054] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0056] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
[0057] Figure 2 This is a schematic diagram of the substrate in the embodiments of this disclosure;
[0058] Figure 3 This is a schematic diagram showing the substrate cut along a second direction in an embodiment of this disclosure;
[0059] Figure 4 This is a schematic diagram of the character line structure in the present disclosure cut along the second direction;
[0060] Figure 5 This is a schematic diagram of the protective layer in the embodiments of this disclosure;
[0061] Figure 6 This is a schematic diagram of the first insulating material layer in an embodiment of this disclosure;
[0062] Figure 7 This is a schematic diagram of the first insulating layer in an embodiment of the present disclosure;
[0063] Figure 8 This is a schematic diagram of the second insulating layer in an embodiment of the present disclosure;
[0064] Figure 9 This is a schematic diagram showing the section cut along the second direction after step S460 is completed in this embodiment of the present disclosure;
[0065] Figure 10 After completing step S460 in this embodiment of the present disclosure Figure 9 A schematic diagram showing the section cut by the dashed line.
[0066] Figure 11 This is a schematic diagram showing the section cut along the second direction after step S470 is completed in this embodiment of the present disclosure;
[0067] Figure 12 After completing step S470 in this embodiment of the present disclosure Figure 11 A schematic diagram showing the section cut by the dashed line.
[0068] Figure 13 This is a schematic diagram showing the section cut along the second direction after step S480 is completed in this embodiment of the present disclosure;
[0069] Figure 14 This is a schematic diagram showing the section cut along the second direction after step S510 is completed in this embodiment of the present disclosure;
[0070] Figure 15 After completing step S510 in this embodiment of the present disclosure, along Figure 14 A schematic diagram showing the section cut by the dashed line.
[0071] Figure 16 After completing step S520 in this embodiment of the present disclosure Figure 4 A schematic diagram showing the section cut by the dashed line.
[0072] Figure 17 This is a schematic diagram showing the section cut along the second direction after step S140 is completed in this embodiment of the present disclosure;
[0073] Figure 18 This is a schematic diagram showing the material cut along the first direction after backfilling with insulating material in an embodiment of this disclosure.
[0074] Figure 19 This is a schematic diagram showing the section cut along the second direction after step S610 is completed in this embodiment of the present disclosure;
[0075] Figure 20 This is a schematic diagram showing the section cut along the second direction after step S150 is completed in this embodiment of the present disclosure.
[0076] Explanation of reference numerals in the attached figures:
[0077] 1. Substrate; 11. Substrate; 12. Insulating dielectric layer; 101. Second trench; 110. Support pillar; 2. Word line structure; 21. Inter-gate dielectric layer; 22. First conductive material; 201. Word line filling trench; 3. Insulating layer; 31. Protective layer; 32. First insulating layer; 33. Passivation layer; 331. Second insulating layer; 3311. First insulating material layer; 301. Air gap; 302. Insulating void; 4. Sealing layer; 5. Bit line structure; 6. Mask layer; A. First direction; B. Second direction. Detailed Implementation
[0078] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0079] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0080] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0081] This disclosure provides a method for forming a semiconductor structure. Figure 1 A flowchart illustrating the method for forming the semiconductor structure of this disclosure is shown; see [link to flowchart]. Figure 1 As shown, the forming method may include steps S110-S150, wherein:
[0082] Step S110, providing a substrate, the substrate including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart along a first direction, the insulating dielectric layer filling each of the first trenches;
[0083] Step S120: Pattern etching is performed on the substrate to form a plurality of second trenches spaced apart along a second direction, the second direction intersecting the first direction;
[0084] Step S130: Form word line structures in each of the second grooves;
[0085] Step S140: An air gap is formed between two adjacent word line structures;
[0086] Step S150: Seal the air gap.
[0087] The method for forming a semiconductor structure disclosed herein, on the one hand, helps to save structural space and improve device integration by forming a second trench in the substrate and burying the word line structure in the second trench; on the other hand, an air gap can be formed between two adjacent word line structures. Since the dielectric constant of the air gap is small, the parasitic capacitance between the word line structures can be effectively reduced, thereby reducing device power consumption; furthermore, by sealing the air gap, the air gap can be sealed between adjacent word line structures, which can prevent the final semiconductor structure from breaking at the opening of the air gap and improve product yield.
[0088] The specific details of the method for forming a semiconductor structure according to the embodiments of this disclosure are described in detail below:
[0089] like Figure 1 As shown, in step S110, a substrate is provided, the substrate including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart along a first direction, and the insulating dielectric layer filling each of the first trenches.
[0090] In one exemplary embodiment of this disclosure, such as Figure 2 As shown, the substrate 1 may include a substrate 11 and an insulating dielectric layer 12. The substrate 11 may have a plurality of first trenches (not shown) spaced apart along a first direction A, and each first trench may extend along a second direction B. The first trench may be a groove-shaped structure formed by indentation inward from the surface of the substrate 11, and may be connected to both ends of the substrate 11.
[0091] The first direction A may intersect with the second direction B; for example, the first direction A and the second direction B may be perpendicular to each other. It should be noted that perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during manufacturing. In this disclosure, angular deviations may occur due to manufacturing limitations, resulting in a certain deviation in the angle between the first direction A and the second direction B. As long as the angular deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered perpendicular. For example, the preset range can be 10°, meaning that the first direction A and the second direction B can be considered perpendicular when the angle between them is greater than or equal to 80° and less than or equal to 100°.
[0092] Insulating material can be filled into each of the first trenches to form an insulating dielectric layer 12. The insulating dielectric layer 12 can fill each of the first trenches, and the upper surface of the insulating dielectric layer 12 can be flush with the upper surface of the substrate 11.
[0093] In one exemplary embodiment of this disclosure, a substrate 1 is provided, the substrate 1 including a substrate 11 and an insulating dielectric layer 12. The substrate 11 includes a plurality of first trenches spaced apart along a first direction A. The insulating dielectric layer 12 filling each of the first trenches (i.e., step S110) may include steps S210-S230, wherein:
[0094] Step S210, provide substrate 11.
[0095] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be silicon or other semiconductor materials. No special restrictions are placed on the shape and material of the substrate 11.
[0096] Step S220: The substrate 11 is etched to form a plurality of spaced first trenches, the first trenches extending along the second direction B, and the plurality of first trenches spaced along the first direction A.
[0097] Multiple first trenches can be formed within the substrate 11 using photolithography. Each first trench can extend along a second direction B, and the multiple first trenches can be spaced apart along a first direction A. For example, a photoresist layer can be formed on the surface of the substrate 11 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the substrate 11 can be the same as the shape of the surface of the substrate 11. The photoresist layer can be exposed using a mask, and the pattern of the mask can match the pattern required for each first trench. Subsequently, the exposed photoresist layer can be developed to form a developed area, which exposes the substrate 11. The pattern of the developed area can be the same as the pattern required for the first trench, and the size of the developed area can be the same as the size of the required first trench. Anisotropic etching can be performed on the substrate 11 in the developed area to form each first trench. It should be noted that, in the direction perpendicular to the substrate 11, the first trench does not penetrate the substrate 11, that is, the bottom of the first trench still retains substrate 11 material.
[0098] Step S230: Fill each of the first trenches with insulating material to form an insulating dielectric layer 12.
[0099] The insulating material can be filled into the first trench using methods such as vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the insulating material can fill all of the first trench. In one embodiment, the insulating material can be an oxide, for example, silicon oxide.
[0100] like Figure 1 As shown, in step S120, the substrate is patterned by etching to form a plurality of second trenches spaced apart along a second direction B, the second direction B intersecting the first direction A.
[0101] The substrate 1 can be etched to form a plurality of spaced-apart second trenches 101 within the substrate 1. For example... Figure 3 As shown, each second trench 101 can extend along the first direction A, and multiple second trenches 101 can be distributed at intervals along the second direction B. In some embodiments of this disclosure, in the direction perpendicular to the substrate 11, the second trench 101 does not penetrate the substrate 11, that is, the bottom of the second trench 101 still retains material of the substrate 11. For example, in the direction perpendicular to the substrate 11, the depth of the second trench 101 can be less than the depth of the first trench, or it can be equal to the depth of the first trench, without any special limitation.
[0102] In one exemplary embodiment of this disclosure, see also Figure 2 and Figure 3 As shown, each second trench 101 and each first trench can separate multiple groups of support pillars 110 spaced apart along a first direction A within the substrate 11. For example, the support pillars 110 in each group can be equally spaced along the first direction A; multiple groups of support pillars 110 can be spaced apart along a second direction B. For example, each group of support pillars 110 can be equally spaced along the second direction B.
[0103] In one exemplary embodiment of this disclosure, etching the substrate 1 to form a plurality of second trenches 101 spaced apart along the second direction B (i.e., step S120) may include steps S310-S350, wherein:
[0104] Step S310: A mask layer 6 is formed on the surface of the substrate 1.
[0105] In this embodiment of the present disclosure, a mask layer 6 can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other methods. The mask layer 6 can be a multilayer film structure or a single-layer film structure. Its material can be at least one of polymer, SiO2, SiN, polycrystalline silicon and SiCN. Of course, it can also be other materials, which will not be listed here.
[0106] In some embodiments, the mask layer 6 may be multilayered, including a polymer layer, an oxide layer, and a hard mask layer 6. The polymer layer may be formed on the surface of the substrate 1, and the oxide layer may be located between the hard mask layer 6 and the polymer layer. The polymer layer can be formed on the surface of the substrate 1 by chemical vapor deposition, the oxide layer on the surface of the polymer layer by vacuum evaporation, and the hard mask layer 6 on the surface of the oxide layer by atomic layer deposition.
[0107] Step S320: A photoresist layer is formed on the surface of the mask layer 6.
[0108] A photoresist layer can be formed on the surface of the mask layer 6 away from the substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive photoresist or negative photoresist, and no special limitation is made here.
[0109] Step S330: Expose and develop the photoresist layer to form multiple spaced development areas.
[0110] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the required pattern of the second trench 101. Subsequently, the exposed photoresist layer can be developed to form multiple spaced development areas, each of which exposes the surface of the photomask layer 6. The pattern of the development area can be the same as the required pattern of the second trench 101, and the size of the development area can be the same as the required size of the second trench 101.
[0111] In step S340, the mask layer 6 is etched in the developing area to form a plurality of mask patterns spaced apart along the second direction B, the orthogonal projection of the mask patterns on the substrate 11 traversing the plurality of the first trenches.
[0112] The mask layer 6 can be etched in each developing area using an anisotropic etching process, exposing the substrate 1 in the etched areas. This forms multiple mask patterns on the mask layer 6. The mask patterns can be strip-shaped and intersect the extension direction of the first trenches. The orthogonal projection of each mask pattern onto the substrate 1 can traverse multiple first trenches. For example, the mask pattern can be a strip-shaped pattern extending along a first direction A, and the multiple mask patterns can be spaced apart along a second direction B.
[0113] It should be noted that when the mask layer 6 is a single-layer structure, a mask pattern can be formed by a single etching process. When the mask layer 6 is a multi-layer structure, each layer can be etched in layers. That is, a single etching process can etch one layer, and multiple etching processes can be used to etch through the mask layer 6 to form a mask pattern. In one embodiment, the shape and size of the mask pattern can be the same as the pattern and size required for each second trench 101.
[0114] It should be noted that after the above etching process is completed, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing, so that the etched mask layer 6 is no longer covered by the photoresist layer.
[0115] In step S350, the substrate 1 is anisotropically etched using the mask layer 6 having the mask pattern as a mask to form a plurality of second trenches 101 extending along the first direction A and spaced apart along the second direction B.
[0116] A mask layer 6 with a mask pattern can be used as a mask to perform anisotropic etching on the substrate 1 to form multiple second trenches 101 extending along a first direction A and spaced apart along a second direction B. In some embodiments of this disclosure, the second trenches 101 are perpendicular to the first trenches. The first and second trenches 101 can divide the substrate 11 into multiple arrayed support pillars 110, which can be arranged in rows and columns. After forming each second trench 101, it is not necessary to remove the mask layer 6 for use in the subsequent etching process to form the third trench. This avoids the need to separately form a mask layer 6 for accommodating the trenches of the bit line structure 5, simplifying the process and reducing manufacturing costs.
[0117] like Figure 1 As shown, in step S130, word line structures are formed in each of the second trenches.
[0118] like Figure 4 As shown, conductive material can be filled into each of the second trenches 101, thereby forming word line structures 2 in each of the second trenches 101. In some embodiments of this disclosure, word line structures 2 can be formed in a one-to-one correspondence between each of the second trenches 101. That is, there can be multiple word line structures 2, and the number of word line structures 2 is equal to the number of second trenches 101. Each word line structure 2 can extend along a first direction A, and multiple word line structures 2 can be distributed at intervals along a second direction B.
[0119] In one exemplary embodiment of this disclosure, an insulating layer 3 that subsequently isolates each word line structure 2 may be formed before forming the word line structure 2. For example, forming the insulating layer 3 may include steps S410-S480, wherein:
[0120] Step S410: A protective layer 31 is formed that conformally adheres to the sidewall of the second groove 101.
[0121] like Figure 5 As shown, a protective layer 31 can be formed on the sidewall of the second trench 101 by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc., and is conformally attached to the sidewall of the second trench 101. The protective layer 31 can protect the surface of the sidewall of the second trench 101 and prevent the surface of the sidewall of the second trench 101 exposed to the outside world from being damaged in subsequent processes. The material of the protective layer 31 can be an insulating material, and its material can be the same as the material of the insulating dielectric layer 12. For example, its material can be silicon nitride or silicon oxide, etc. No special limitation is made on the material of the protective layer 31 here.
[0122] In one exemplary embodiment of this disclosure, the method of forming this disclosure may further include:
[0123] In step S160, before forming the word line structure 2, a bit line structure 5 is formed at the bottom of the second groove 101. The bit line structure 5 traverses multiple second grooves 101 and is insulated from the word line structure 2.
[0124] In some embodiments of this disclosure, see further reference. Figure 5 As shown, after the protective layer 31 is formed, a third trench (not shown in the figure) can be formed through the second trench 101. During this process, the specific formation position of the third trench can be defined by each second trench 101, thereby improving the alignment accuracy of the third trench. The third trench can be located at the bottom of the second trench 101 and communicate with the bottom of the second trench 101. In some embodiments of this disclosure, the third trench can penetrate the bottom of multiple second trenches 101. There can be multiple third trenches, each of which can extend along the second direction B, and the multiple third trenches can be distributed at intervals along the first direction A.
[0125] In one exemplary embodiment of this disclosure, forming a bit line structure 5 at the bottom of the second trench 101 may include steps S1601 and S1602, wherein:
[0126] Step S1601: Remove a portion of the material of the substrate 11 located below the second trench 101 to form a third trench below the second trench 101, the third trench penetrating each of the second trenches 101.
[0127] The substrate 11 at the bottom of the second trench 101 can be etched to form a third trench. The third trench can extend along the second direction B, and the bottom of each of the second trenches 101 can be connected along the second direction B. That is, the third trench can hollow out the bottom of each of the support pillars 110 spaced apart along the second direction B, thereby connecting the bottom of each of the second trenches 101 spaced apart along the second direction B. At this time, the insulating dielectric layer 12 between each support pillar 110 can support each support pillar 110 to prevent the support pillars 110 from collapsing, thereby improving the product yield. In this process, the specific formation position of the third trench can be defined by each second trench 101, thereby improving the alignment accuracy of the third trench.
[0128] It should be noted that during the formation of the third trench, the mask layer 6 used to form the second trench 101 can be used as a mask to etch the bottom of the second trench 101, thereby forming the third trench that runs through each of the second trenches 101. This avoids the need to form a separate mask layer 6 for accommodating the trench of the bit line structure 5, which simplifies the process and reduces manufacturing costs.
[0129] Step S1602: Fill the third trench with a second conductive material to form the bit line structure 5.
[0130] The second conductive material can be filled into each third trench by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation. Of course, other methods can also be used to fill the third trench with the second conductive material, thereby forming a bit line structure 5 in the third trench.
[0131] In some embodiments of this disclosure, during the filling of the second conductive material, for the convenience of the process, the second conductive material can be deposited simultaneously on the surface of the mask layer 6. The deposition is stopped when the second conductive material fills the third trench. The second conductive material located outside the third trench can be removed by an etching process, leaving only the second conductive material located in the third trench, so that the bit line structure 5 can be formed only in the third trench.
[0132] In one exemplary embodiment of this disclosure, the second conductive material can be a highly metallic material, which can reduce the contact resistance of the final bit line structure 5. For example, the material can be titanium nitride or silicon cobaltide.
[0133] In some embodiments of this disclosure, bit line structures 5 can be formed in a one-to-one correspondence with each of the third trenches. That is, there can be multiple bit line structures 5, and the number of bit line structures 5 is equal to the number of third trenches. Each bit line structure 5 can extend along the second direction B, and the multiple bit line structures 5 can be distributed at intervals along the first direction A.
[0134] Step S420: A first insulating material layer 3311 is formed on the surface of the structure formed by the substrate 1 and the protective layer 31.
[0135] See Figure 6 As shown, a first insulating material layer 3311 can be formed on the surface of the structure jointly formed by the substrate 11 and the protective layer 31 using processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that when a bit line structure 5 is formed at the bottom of the substrate 11, the first insulating material layer 3311 can be simultaneously formed on the surface of the bit line structure 5. The first insulating material layer 3311 can provide insulation and isolation between the bit line structure 5 and the word line structure 2 subsequently formed in the second trench 101, thereby preventing coupling or short circuits between the bit line structure 5 and the subsequently formed word line structure 2, and improving product yield.
[0136] In some embodiments of this disclosure, the thickness of the first insulating material layer 3311 can be 2nm to 5nm. For example, the thickness of the first insulating material layer 3311 can be 2nm, 3nm, 4nm or 5nm. Of course, the thickness of the first insulating material layer 3311 can also be other values, which will not be listed here.
[0137] In some embodiments of this disclosure, the material of the first insulating material layer 3311 may be different from the material of the protective layer 31. For example, its material may be silicon nitride. Of course, the material of the first insulating material layer 3311 may also be other materials, which are not specifically limited here.
[0138] In step S430, a first insulating layer 32 is formed in the second trench 101 having the first insulating material layer 3311, wherein the top of the first insulating layer 32 is lower than the top of the first insulating material layer 3311.
[0139] See Figure 7 As shown, insulating material can be filled into the second trench 101, which has a protective layer 31 and a first insulating material layer 3311, thereby forming the first insulating layer 32 within the second trench 101. For example, the first insulating layer 32 can be formed within the second trench 101 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, for ease of fabrication, insulating material can be deposited simultaneously within the second trench 101 and on the surface of the first insulating material layer 3311 at the top of the second trench 101 while forming the first insulating layer 32. Subsequently, the deposited insulating material can be etched back so that the top of the first insulating layer 32 is lower than the top of the first insulating material layer 3311. During this process, the insulating material on the surface of the first insulating material layer 3311 at the top of the second trench 101 can be removed simultaneously, leaving only the insulating material within the second trench 101, thereby forming the first insulating layer 32 within the second trench 101.
[0140] In some embodiments of this disclosure, the depth of back etching of the insulating material can be 15nm to 25nm, that is, the height difference between the top of the first insulating layer 32 and the top of the first insulating material layer 3311 can be 15nm to 25nm. For example, the height difference between the top of the first insulating layer 32 and the top of the first insulating material layer 3311 can be 15nm, 18nm, 21nm, 24nm or 25nm. Of course, other height differences are also possible, which will not be listed here.
[0141] In some embodiments of this disclosure, the material of the first insulating layer 32 is different from the material of the first insulating material layer 3311. For example, the material of the first insulating layer 32 may be silicon oxide, and the material of the first insulating material layer 3311 may be silicon nitride.
[0142] Step S440: A second insulating material layer is formed on top of the first insulating layer 32.
[0143] After the first insulating layer 32 is formed, a second insulating material layer (not shown in the figure) can be formed on top of the first insulating layer 32. The material of the second insulating material layer can be the same as the material of the first insulating material layer 3311. The second insulating material layer can be in contact with the first insulating material layer 3311. The first insulating layer 32 can be covered by the second insulating material layer and the first insulating material layer 3311.
[0144] The second insulating material layer can be formed on top of the first insulating layer 32 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In this process, for the convenience of the process, the second insulating material layer can be deposited on the surface of the first insulating material layer 3311 at the same time.
[0145] Step S450: The surface of the second insulating material layer is planarized so that the top of the second insulating material layer is flush with the surface of the substrate 11, and the remaining second insulating material layer and the first insulating material layer 3311 together constitute the second insulating layer 331.
[0146] The surface of the second insulating material layer can be ground or polished using a chemical mechanical polishing process until the first insulating material layer 3311 and the second insulating material layer located on top of the substrate 11 are completely removed. During this process, the tops of both the second insulating material layer and the first insulating material layer 3311 can be flush with the surface of the substrate 11. In some embodiments of this disclosure, such as... Figure 8 As shown, the remaining second insulating material layer can be combined with the first insulating material layer 3311 to form the second insulating layer 331, that is, the second insulating layer 331 can cover the first insulating layer 32 around the perimeter.
[0147] Step S460: Etch back the protective layer 31 and the insulating dielectric layer 12 to form an insulating void 302.
[0148] like Figure 9 and Figure 10 As shown, the protective layer 31 and the insulating dielectric layer 12 can be etched back to form an insulating gap 302 between the second insulating layer 331 and the sidewall of the second trench 101. In some embodiments, during the etch-back process, a portion of the protective layer 31 can be removed, without completely removing it. Specifically, the protective layer 31 at the end farther from the bit line structure 5 can be removed, while the protective layer 31 at the end closer to the bit line structure 5 is retained. Simultaneously, the thickness of the insulating dielectric layer 12 can be reduced so that the top of the insulating dielectric layer 12 is lower than the top of each support pillar 110. In some embodiments, the thickness of the insulating dielectric layer 12 removed can be equal to the thickness of the protective layer 31 removed in a direction perpendicular to the substrate 11.
[0149] It should be noted that the width of the insulating gap 302 formed between the second insulating layer 331 and the sidewall of the second trench 101 after removing the protective layer 31 can be much smaller than the spacing between adjacent support columns 110 after removing the insulating dielectric layer 12.
[0150] In step S470, insulating material is filled into the insulating gap 302, and the insulating material together with the second insulating layer 331 constitutes the passivation layer 33.
[0151] Insulating material can be filled into the insulating voids 302 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. To ensure precise positioning of the word line structure 2, the insulating material can completely fill the insulating voids 302. For ease of processing, insulating material can be deposited simultaneously on the surface of the remaining insulating dielectric layer 12 during the deposition process. During this process, because the width of the insulating voids 302 is much smaller than the spacing between adjacent support pillars 110 after removing the insulating dielectric layer 12, filling the insulating voids 302 will only form a thin layer of insulating material on the exposed sidewalls of each support pillar 110, without filling the gaps between adjacent support pillars 110. This exposes the surface of the insulating dielectric layer 12. The cross-sectional view taken along the second direction B after completing step S470 is shown below. Figure 11 As shown, the cross-sectional view taken along the first direction A after completing step S470 is as follows. Figure 12 As shown.
[0152] The insulating material can be the same as the material of the second insulating layer 331, and the insulating material located in the insulating gap 302 can form a passivation layer 33 together with the second insulating layer 331.
[0153] In step S480, the protective layer 31 of a predetermined thickness is removed in a direction perpendicular to the substrate 11 to form a word line filling trench 201, wherein the word line filling trench 201 does not expose the bottom of the second trench 101.
[0154] like Figure 13 As shown, a wet etching process can be used to remove part of the protective layer 31 located on the sidewall of the second trench 101, thereby forming a word line filling trench 201 for accommodating the word line structure 2. In this process, the protective layer 31 can be etched through the exposed surface of the insulating dielectric layer 12. For example, a hydrofluoric acid dilution solution (DHF) can be used to etch the exposed surface of the insulating dielectric layer 12, thereby hollowing out a space downward in the insulating dielectric layer 12. This space can extend laterally and expose the protective layer 31. Since the material of the protective layer 31 is the same as the material of the insulating dielectric layer 12, the exposed protective layer 31 can be further etched using a hydrofluoric acid dilution solution (DHF) to remove part of the protective layer 31 located on the sidewall of the second trench 101, so as to expose the sidewall of each support post 110.
[0155] For example, a mixed solution of 49% HF and deionized water can be used to clean the insulating dielectric layer 12 and the protective layer 31. The ratio of HF to deionized water can be 1:500 to 1:2000, for example, 1:500, 1:1000, 1:1500, or 1:2000. Other ratios are also possible and will not be listed here. During wet etching, the protective layer 31 at the bottom of the second trench 101 can be retained. For example, the protective layer 31 covering the surface of the bit line structure 5 can be retained. The remaining protective layer 31 can insulate and isolate the bit line structure 5 and the subsequent word line structure 2 formed in the word line filling trench 201, preventing short circuits or coupling between the word line structure 2 and the bit line structure 5. That is, the protective layer 31 is located between the bit line structure 5 and the word line structure 2, and the bit line structure 5 and the word line structure 2 are insulated by the protective layer 31. The passivation layer 33 and the remaining protective layer 31 together constitute the insulating layer 3 of this disclosure.
[0156] After the insulating layer 3 is formed, a word line structure 2 can be formed within the word line filling groove 201. In an exemplary embodiment of this disclosure, forming the word line structure 2 may include steps S510 and S520, wherein:
[0157] Step S510: An inter-gate dielectric layer 21 is formed at the bottom of the word line filling groove 201 and on the sidewall of the word line filling groove 201 away from the insulating layer 3.
[0158] The material of the inter-gate dielectric layer 21 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination of the aforementioned materials. Its thickness may be 1 nm to 9 nm. For example, it may be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm or 9 nm. Of course, it may also be other thicknesses, which will not be listed here.
[0159] For example, such as Figure 14 and Figure 15 As shown, a conformally attached inter-gate dielectric layer 21 can be formed at the bottom of each word line filling trench 201 and on the sidewalls of each word line filling trench 201 away from the insulating layer 3 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, or thermal oxidation. Of course, the inter-gate dielectric layer 21 can also be formed by other means, which are not specifically limited here. It should be noted that the inter-gate dielectric layer 21 can be conformally attached to the sidewalls of each exposed support post 110 to facilitate the subsequent formation of a ring grid structure.
[0160] In some embodiments of this disclosure, the surface of the inter-gate dielectric layer 21 can be treated by thermal oxidation to improve the density of the inter-gate dielectric layer 21, thereby reducing leakage current, improving gate control capability, and enhancing the barrier effect of the inter-gate dielectric layer 21 on impurities in the substrate 11, preventing impurities in the substrate 11 from diffusing into the word line filling trench 201, thus improving structural stability.
[0161] In step S520, a first conductive material 22 is filled into the word line filling trench 201 having the inter-gate dielectric layer 21 to form a word line structure 2.
[0162] like Figure 4 and Figure 16 As shown, the first conductive material 22 can fill the word line filling trench 201 and completely fill each word line filling trench 201, and the first conductive material 22 can contact the inter-gate dielectric layer 21 on the surface of each support post 110. The first conductive material 22 can be tungsten or titanium nitride, etc., and of course, it can also be other materials with strong conductivity, which will not be listed here.
[0163] For example, a first conductive material 22 can be deposited on the surface of the structure formed by the support pillars 110 and the second trench 101 having the inter-gate dielectric layer 21 through processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation, thereby forming the word line structure 2. Of course, the word line structure 2 can also be formed in other ways, and no special limitation is made here on the formation method of the word line structure 2.
[0164] In one exemplary embodiment of this disclosure, after the word line structure 2 is formed, an insulating layer 3 can be formed between adjacent word line structures 2. The insulating layer 3 can be used to insulate and isolate adjacent word line structures 2, thereby preventing coupling or short circuit between word line structures 2.
[0165] like Figure 1 As shown, in step S140, an air gap is formed between two adjacent word line structures.
[0166] like Figure 17 As shown, the air gap 301 can be formed between adjacent word line structures 2. For example, the air gap 301 can be located in the insulating layer 3 between adjacent word line structures 2. Since the dielectric constant of the air gap 301 is small, it can effectively reduce the parasitic capacitance between word line structures 2 and reduce device power consumption.
[0167] In one exemplary embodiment of this disclosure, forming the air gap 301 may include steps S610 and S620, wherein:
[0168] In step S610, after forming the word line structure 2, the passivation layer 33 is etched back until the first insulating layer 32 is exposed.
[0169] In some embodiments of this disclosure, such as Figure 18 As shown, after forming the word line structure 2, an insulating material can be deposited on the exposed surface of the word line structure 2 to provide insulation protection and prevent coupling or short circuits between the word line structure 2 and other subsequently formed structures, thus helping to improve product yield. This insulating material can be the same as the material of the passivation layer 33; for example, the insulating material can be silicon nitride.
[0170] For example, insulating material can be deposited on the surface of the exposed word line structure 2 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or thermal evaporation. The insulating material can at least fill the gaps between each support pillar 110. During this process, for ease of fabrication, insulating material can be deposited simultaneously on the top of each support pillar 110. Subsequently, the insulating material can be planarized using polishing or grinding processes, thereby removing the insulating material on top of the support pillars 110 and exposing the tops of each support pillar 110. Then, the passivation layer 33 can be etched back (e.g., ...). Figure 19 (as shown), until the top of the first insulating layer 32 is exposed, so that the first insulating layer 32 can be removed subsequently.
[0171] Step S620: Remove the first insulating layer 32 to form the air gap 301.
[0172] See also Figure 17 As shown, the first insulating layer 32 can be removed by etching, thereby forming an air gap 301 in the insulating layer 3. The width of the air gap 301 can be equal to the width of the first insulating layer 32. For example, the width of the air gap 301 can be 1nm to 15nm, such as 1nm, 3nm, 6nm, 9nm, 12nm or 15nm. Of course, it can also be other widths, which are not specifically limited here.
[0173] In one exemplary embodiment of this disclosure, an acidic solution can be used to selectively etch the first insulating layer 32, thereby removing the first insulating layer 32. During this process, the first insulating layer 32 is made of a different material than the passivation layer 33 and has a high selective etching ratio. For example, the selective etching ratio of the first insulating layer 32 to the passivation layer 33 can be 10:1. In some embodiments of this disclosure, the acidic solution can be hydrofluoric acid.
[0174] like Figure 1 As shown, in step S150, the air gap is sealed.
[0175] The air gap 301 can be sealed to prevent the final semiconductor structure from breaking at the opening of the air gap 301, thereby improving product yield.
[0176] In one exemplary embodiment of this disclosure, such as Figure 20 As shown, sealing the air gap 301 may include forming a sealing layer 4 on the surface of the passivation layer 33 having the air gap 301, the sealing layer 4 at least covering the opening of the air gap 301.
[0177] The sealing layer 4 can be located on the surface of the remaining passivation layer 33 and can at least fill the opening of the air gap 301 to seal the opening of the air gap 301. For example, the sealing layer 4 can be formed on the surface of the passivation layer 33 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, or magnetron sputtering. The material of the sealing layer 4 can be an insulating material, for example, silicon nitride. The thickness of the sealing layer 4 can be set according to actual needs, and no special limitation is made here.
[0178] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0179] This disclosure also provides a semiconductor structure. Figure 20 A schematic diagram of the semiconductor structure of this disclosure is shown; see [link / reference]. Figure 20 As shown, the semiconductor structure may include a substrate 1, multiple word line structures 2, and a sealing layer 4, wherein:
[0180] The substrate 1 includes a substrate 11 and an insulating dielectric layer 12. The substrate 11 includes a plurality of first trenches spaced apart along a first direction A and a plurality of second trenches 101 spaced apart along a second direction B. The insulating dielectric layer 12 fills each of the first trenches, and the second trenches 101 penetrate each of the first trenches and the insulating dielectric layer 12 inside them. The second direction B intersects with the first direction A.
[0181] Multiple character line structures 2 are formed in each second groove 101, and an air gap 301 is formed between two adjacent character line structures 2;
[0182] The sealing layer 4 shall at least cover the opening of the air gap 301.
[0183] The semiconductor structure disclosed herein, on the one hand, helps to save structural space and improve device integration by burying the word line structure 2 in the second trench 101; on the other hand, an air gap 301 can be formed between two adjacent word line structures 2. Since the dielectric constant of the air gap 301 is small, the parasitic capacitance between the word line structures 2 can be effectively reduced, thereby reducing device power consumption; furthermore, by sealing the air gap 301 with the sealing layer 4, the air gap 301 can be sealed between adjacent word line structures 2, which can prevent the final semiconductor structure from breaking at the opening of the air gap 301 and improve product yield.
[0184] The semiconductor structure disclosed herein can be formed by the semiconductor structure formation method in any of the above embodiments. For specific details and beneficial effects, please refer to the embodiments of the semiconductor structure formation method described above, which will not be repeated here.
[0185] This disclosure also provides a memory, which may include the semiconductor structure of any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and the method of forming the semiconductor structure, and will not be repeated here.
[0186] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.
[0187] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a substrate and an insulating dielectric layer, the substrate comprising a plurality of first trenches spaced apart along a first direction, the insulating dielectric layer filling each of the first trenches; The substrate is patterned by etching to form a plurality of second trenches spaced apart along a second direction, the second direction intersecting the first direction; A character line structure is formed in each of the second grooves; An air gap is formed between two adjacent word line structures; Seal the air gap; The forming method further includes: An insulating layer is formed between adjacent word line structures, and the air gap is located within the insulating layer; Forming the insulating layer includes: A protective layer is formed that conforms to the sidewall of the second groove; A first insulating material layer is formed on the surface of the structure formed by the substrate and the protective layer; A first insulating layer is formed in the second trench having the first insulating material layer, wherein the top of the first insulating layer is lower than the top of the first insulating layer; A second insulating material layer is formed on top of the first insulating layer; The surface of the second insulating material layer is planarized so that the top of the second insulating material layer is flush with the surface of the substrate, and the remaining second insulating material layer together with the first insulating material layer constitutes the second insulating layer. The protective layer and the insulating dielectric layer are etched back to form insulating gaps; The insulating gaps are filled with insulating material, and the insulating material together with the second insulating layer constitutes a passivation layer. In a direction perpendicular to the substrate, the protective layer of a predetermined thickness is removed to form a word line filling trench, the word line filling trench not exposing the bottom of the second trench.
2. The forming method according to claim 1, characterized in that, Forming the word line structure includes: An inter-gate dielectric layer is formed at the bottom of the word line filling groove and on the sidewall of the word line filling groove away from the insulating layer; A first conductive material is filled into the word line filling trench having the inter-gate dielectric layer to form a word line structure.
3. The forming method according to claim 1, characterized in that, Forming the air gap includes: After the word line structure is formed, the passivation layer is etched back until the first insulating layer is exposed; Remove the first insulating layer to form the air gap.
4. The forming method according to claim 3, characterized in that, Sealing the air gap includes: A sealing layer is formed on the surface of the passivation layer having the air gap, the sealing layer at least covering the opening of the air gap.
5. The forming method according to claim 1, characterized in that, The forming method further includes: Before the word line structure is formed, a bit line structure is formed at the bottom of the second trench, the bit line structure traversing multiple second trenches, and the bit line structure is insulated from the word line structure.
6. The forming method according to claim 5, characterized in that, Forming the bitline structure includes: A portion of the substrate material located below the second trench is removed to form a third trench below the second trench, the third trench penetrating each of the second trenches; The third trench is filled with a second conductive material to form the bit line structure.
7. The forming method according to claim 5, characterized in that, The protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated from each other by the protective layer.
8. A semiconductor structure, said semiconductor structure being prepared by the formation method according to any one of claims 1-7, characterized in that, include: The substrate includes a substrate and an insulating dielectric layer. The substrate includes a plurality of first trenches spaced apart along a first direction and a plurality of second trenches spaced apart along a second direction. The insulating dielectric layer fills each of the first trenches, and the second trenches penetrate each of the first trenches and the insulating dielectric layer therein. The second direction intersects the first direction. Multiple character line structures are formed in each of the second grooves, and an air gap is formed between two adjacent character line structures; A sealing layer that at least covers the opening of the air gap.
9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: An insulating layer is formed between adjacent word line structures, and the air gap is located within the insulating layer.
10. The semiconductor structure according to claim 9, characterized in that, The insulating layer includes: A protective layer is located on the sidewall of the second trench, and in a direction perpendicular to the substrate, the top of the protective layer is lower than the top surface of the second trench; A passivation layer fills the second trench having the protective layer, and in a direction perpendicular to the substrate, a word line filling trench is formed at one end of the passivation layer away from the protective layer. The air gap is located in the passivation layer between adjacent word line filling trenches, and the air gap is insulated from the word line filling trench through the passivation layer.
11. The semiconductor structure according to claim 10, characterized in that, The word line structure includes: An inter-gate dielectric layer is formed at the bottom of the word line filling trench and on the sidewall of the word line filling trench away from the insulating layer; A first conductive layer is filled in the word line filling trench having the inter-gate dielectric layer.
12. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A bit line structure is formed at the bottom of the second trench, the bit line structure traverses multiple second trenches, and the bit line structure is insulated from the word line structure.
13. The semiconductor structure according to claim 12, characterized in that, The protective layer is located between the bit line structure and the word line structure, and the bit line structure and the word line structure are insulated from each other by the protective layer.
14. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 8-13.