Method for manufacturing a semiconductor structure and semiconductor structure
By nitriding the spacer layer of the bit line isolation structure, increasing the nitrogen content of the nitride layer and reducing the thickness of the oxide layer, the problems of high resistance, unstable contact and capacitance caused by improper thickness of the bit line isolation structure are solved, thus improving the performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-08-05
- Publication Date
- 2026-06-26
AI Technical Summary
If the thickness of the bit line isolation structure is too high, the resistance will be too high and the write recovery time will not meet the requirements. If the thickness is too low, it will easily cause problems such as short bit line contact or missing bit lines.
By nitriding the spacer layer of the bit line isolation structure, the nitrogen content of the nitride layer is increased and the thickness of the oxide layer is reduced, thereby improving the etch resistance of the spacer layer and improving the parasitic capacitance and contact stability of the bit line.
It improves the sensitivity and write recovery time of semiconductor devices, reduces the possibility of short or missing bit line contacts, and improves the problem of bit line parasitic capacitance.
Smart Images
Figure CN117594524B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] Currently, bit line isolation structures in semiconductor technology are used to protect the sidewall metal of bit lines due to their low parasitic capacitance. Commonly used bit line isolation structures include nitride-oxide-nitride forms.
[0003] However, if the thickness of the bit line isolation structure is too high, its resistance will be too high, and the write recovery time of the semiconductor device will not meet the requirements; if the thickness of the bit line isolation structure is too low, it will cause problems such as short bit line contact and missing bit line isolation structure. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0005] To overcome the problems existing in related technologies, this disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure.
[0006] This disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate, the substrate including a substrate and signal lines located on the substrate; forming at least one initial spacer layer on the sidewalls of the signal lines; and performing a nitriding treatment on the at least one initial spacer layer to obtain at least one spacer layer.
[0007] According to some embodiments of this disclosure, forming at least one initial spacer layer on the sidewall of the signal line and performing nitriding treatment on at least one initial spacer layer includes: sequentially forming multiple initial spacer layers on the sidewall of the signal line, and performing nitriding treatment on each initial spacer layer after it is formed to obtain the spacer layer.
[0008] According to some embodiments of this disclosure, the at least one spacer layer includes at least one nitride layer and at least one oxide layer.
[0009] According to some embodiments of this disclosure, forming at least one initial spacer layer on the sidewall of the signal line and performing a nitriding treatment on the at least one initial spacer layer includes: forming a first initial nitride layer, the first initial nitride layer at least covering the sidewall of the signal line; performing a first nitriding treatment on the first initial nitride layer to obtain a first nitride layer; forming an initial oxide layer, the initial oxide layer covering the first nitride layer; performing a second nitriding treatment on the initial oxide layer to obtain an oxide layer; forming a second initial nitride layer, the second nitride layer covering the oxide layer; and performing a third nitriding treatment on the second initial nitride layer to obtain a second nitride layer.
[0010] According to some embodiments of this disclosure, before the second nitriding treatment is performed, there is a first distance between the initial oxide layer and the sidewall of the signal line, and after the second nitriding treatment is performed, there is a second distance between the oxide layer and the sidewall of the signal line, wherein the first distance is greater than the second distance.
[0011] According to some embodiments of this disclosure, the thickness of the first initial nitride layer is 2-5 nm; the thickness of the initial oxide layer is 6-10 nm; and the thickness of the second initial nitride layer is 6-10 nm.
[0012] According to some embodiments of this disclosure, at least one of the initial spacer layers is nitrided using a remote plasma nitriding process.
[0013] According to some embodiments of this disclosure, the power of the remote plasma nitriding is 800-1200W.
[0014] According to some embodiments of this disclosure, the signal line includes a bit line, and a cover layer is disposed on the bit line; the spacer layer located on the inner side covers the sidewall of the bit line and the sidewall and top wall of the cover layer.
[0015] A second aspect of this disclosure provides a semiconductor structure comprising: a substrate, the substrate including a base and a signal line located on the base; and a spacer structure covering the sidewalls of the signal line, the spacer structure including at least one spacer layer, wherein the nitrogen content of at least one spacer layer on the side closer to the signal line is less than the nitrogen content on the side farther from the signal line.
[0016] According to some embodiments of this disclosure, the spacing structure includes multiple spacing layers, wherein the nitrogen content on the side of each spacing layer closer to the signal line is less than the nitrogen content on the side farther from the signal line.
[0017] According to some embodiments of this disclosure, the at least one spacer layer includes at least one nitride layer and at least one oxide layer.
[0018] According to some embodiments of this disclosure, the at least one spacer layer includes a first nitride layer, an oxide layer, and a second nitride layer disposed sequentially from the side closest to the signal line to the side furthest from the signal line.
[0019] According to some embodiments of this disclosure, the first nitride layer includes a first nitride sublayer and a second nitride sublayer located outside the first nitride sublayer, wherein the nitrogen content of the second nitride sublayer is greater than the nitrogen content of the first nitride sublayer; the oxide layer includes an oxide sublayer and a nitride-oxide sublayer located outside the oxide sublayer; the second nitride layer includes a third nitride sublayer and a fourth nitride sublayer located outside the third nitride sublayer, wherein the nitrogen content of the fourth nitride sublayer is greater than the nitrogen content of the third nitride sublayer.
[0020] According to some embodiments of this disclosure, the signal line includes a bit line, a cover layer is disposed on the bit line, and the spacer layer located on the inner side covers the sidewall of the bit line as well as the sidewall and top wall of the cover layer.
[0021] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: by nitriding the spacer layer, which serves as a bit line isolation structure, the nitrogen content of the nitride layer in the spacer layer is increased, thereby improving the etch resistance of the spacer layer, enhancing the sensitivity of the semiconductor device, and ensuring that the semiconductor device has a write recovery time that meets the requirements; at the same time, the increased nitrogen content on the nitride layer in the spacer layer reduces the possibility of short bit line contact or missing bit line isolation structure when the spacer layer is thin; in addition, nitriding the oxide layer in the spacer layer can improve the etch resistance of the spacer layer, increasing the thickness of the oxide layer while reducing the thickness of the nitride layer, thereby improving the problem of bit line parasitic capacitance.
[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. Attached Figure Description
[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0024] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.
[0025] Figure 2 This is a schematic diagram illustrating the position of the initial layer of the interval according to an exemplary embodiment.
[0026] Figure 3 This is a schematic diagram illustrating a spacer layer structure according to an exemplary embodiment.
[0027] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.
[0028] Figure 5 This is a schematic diagram illustrating the structure of a first nitride layer according to an exemplary embodiment.
[0029] Figure 6 This is a schematic diagram illustrating an oxide layer structure according to an exemplary embodiment.
[0030] Figure 7 This is a schematic diagram illustrating the structure of a second nitride layer according to an exemplary embodiment.
[0031] Figure 8 This is a schematic diagram illustrating a semiconductor structure according to another exemplary embodiment.
[0032] Figure Labels
[0033] 1. Substrate; 11. Substrate; 12. Signal line; 13. Capping layer; 2. Spacer layer; 3. First nitride layer; 31. First nitride sublayer; 32. Second nitride sublayer; 4. Oxide layer; 41. Oxide sublayer; 42. Oxide nitride sublayer; 5. Second nitride layer; 51. Third nitride sublayer; 52. Fourth nitride sublayer. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0035] As mentioned in the background section, bit line isolation structures are used to protect the sidewall metal of signal lines. When the thickness of the bit line isolation structure is too high, it is easy to cause its resistance to be too high, and the write recovery time of the semiconductor device cannot meet the requirements. When the thickness of the bit line isolation structure is too low, it is easy to cause problems such as short bit line contact and missing bit line isolation structure.
[0036] Based on this, this disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure. By nitriding the spacer layer, which serves as a bit line isolation structure, the nitrogen content in the spacer layer is increased, thereby improving the etch resistance of the spacer layer. At the same time, the thickness of the oxide layer on the nitride layer in the spacer layer is reduced, thereby reducing the parasitic capacitance of the bit line and improving the sensitivity of the semiconductor device, ensuring that the semiconductor device has a write recovery time that meets the requirements. Furthermore, nitriding the oxide layer in the spacer layer can improve the etch resistance of the spacer layer and increase the thickness of the oxide layer, reducing the possibility of short bit line contact or loss of bit line isolation structure when the spacer layer is thin.
[0037] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment. Figures 2-3 This is a schematic diagram illustrating a spacer layer structure according to an exemplary embodiment. Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment. Figures 5-7 This is a schematic diagram illustrating the structure of a first nitride layer according to an exemplary embodiment. Figure 8 This is a schematic diagram illustrating a semiconductor structure according to another exemplary embodiment. The following is in conjunction with... Figures 1-7 The methods for fabricating semiconductor structures are explained.
[0038] The specific embodiments described below are intended to help those skilled in the art understand this embodiment, but this embodiment is not limited to the specific embodiments described below.
[0039] Reference Figure 1 This disclosure provides an exemplary embodiment of a method for fabricating a semiconductor structure, the method comprising: S100, providing a substrate, the substrate including a substrate and signal lines located on the substrate.
[0040] For example, refer to Figure 2 and Figure 3 The substrate 1 includes a substrate 11 and signal lines 12 fixed on the substrate 11. The substrate 11 serves as a support component for the memory, supporting other components disposed thereon; the signal lines 12 can be bit lines or word lines.
[0041] In this embodiment, the substrate 11 material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds.
[0042] S200. At least one initial spacer layer is formed on the sidewall of the signal line, and the at least one initial spacer layer is nitrided to obtain at least one spacer layer.
[0043] For example, refer to Figure 2 and Figure 3 The initial spacer layer 2 includes a first nitride sublayer 31, which covers the signal line 12 and a portion of the top surface of the substrate 11 located on both sides of the signal line 12. The first nitride sublayer 31 is formed on the substrate 11 by deposition and etching. For example, nitride material is deposited on the top surface of the substrate 11 by ALD (Atomic layer deposition) process, so that the deposited nitride material covers the top surface of the substrate 11, and then etched downward from the top surface of the substrate 11 by SADP (Self-Aligned Double Patterning) process to remove excess nitride material. The remaining portion of the nitride material forms the first nitride sublayer 31.
[0044] Nitriding treatment is performed on the sidewalls and top surface of the first nitride sublayer 31 to increase the nitrogen content of the first nitride sublayer 31, and a nitrogen atom layer is formed on the sidewalls and top surface of the first nitride sublayer 31. The nitrogen atom layer covers the first nitride sublayer 31 and serves as the second nitride sublayer 32.
[0045] After the first nitride sublayer 31 is nitrided, a second nitride sublayer 32 is formed. The etch resistance of the spacer layer 2 formed by the first nitride sublayer 31 and the second nitride sublayer 32 is improved, which improves the sensitivity of the semiconductor device and ensures that the semiconductor device has a write recovery time that meets the requirements. At the same time, it reduces the possibility of short bit line contact or missing bit line isolation structure when the spacer layer 2 is thin.
[0046] In this embodiment, other methods can also be used, such as CVD (Chemical Vapor Deposition) processes. For example, high-density plasma chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to deposit nitride materials, and the nitride materials can be etched using SAQP (Self-Aligned Quadruple Patterning) or SALELE (Self-Aligned Lithe-Etch-Lithe-Etch).
[0047] It should be understood that the above-described method of forming nitride material on the sidewalls and topwalls of signal line 12 to form the first nitride sublayer 31 is only one specific embodiment. In other specific embodiments, an oxide material may be deposited on substrate 11 to form a layer structure corresponding to the oxide material, and the layer structure may be nitrided to increase the nitrogen content of the layer structure while forming a corresponding nitrogen film on the sidewalls and topwalls of the layer structure. In this embodiment, the deposition of oxide material on substrate 11 may also be replaced by etching and oxidizing polysilicon to form a layer structure different from the material of the first nitride sublayer 31.
[0048] Reference Figure 2 and Figure 3 In an exemplary embodiment of this disclosure, step S200, forming at least one initial spacer layer on the sidewall of the signal line and performing nitriding treatment on the at least one initial spacer layer, specifically includes: sequentially forming multiple initial spacer layers on the sidewall of the signal line, and performing nitriding treatment on each initial spacer layer after its formation to obtain a spacer layer.
[0049] This embodiment is not limited to the number of layers covering the signal line; that is, the initial spacer layer 2 can be two layers or other numbers of layers. Similarly, the material of the initial spacer layer 2 does not have to be the same. For example, nitride and oxide can be deposited sequentially on the outside of the signal line 12, and each layer can be nitrided after deposition or formation to form a spacer layer 2 with a multi-layer structure; or oxide and nitride can be deposited sequentially, and each layer can be nitrided after deposition or formation to form a spacer layer 2 with a multi-layer structure.
[0050] Whether a nitride-based or oxide-based layer structure is first formed on the outer side of the signal line 12, the significance lies in increasing the nitrogen content in the spacer layer 2, thereby improving its etch resistance. Furthermore, since the spacer layer 2 can include both nitride-based and oxide-based layer structures, nitriding the outer layer of the spacer layer 2 will solidify the inner layer structure, reducing its thickness. In applications where the signal line 12 is a bit line, nitriding the first nitride sublayer 31 as the inner spacer layer 2 improves its etch resistance, reduces the possibility of short bit line contact or missing bit line isolation structures when the spacer layer 2 is thin, and simultaneously improves the sensitivity of the semiconductor device, ensuring that the semiconductor device has the required write recovery time. Nitriding the oxide layer structure outside the second nitride sublayer 32 can improve its etch resistance, increase the thickness of the oxide layer 4 while reducing the thickness of the first nitride sublayer 31 and the second nitride sublayer 32, thus improving the problem of bit line parasitic capacitance.
[0051] In an exemplary embodiment of this disclosure, reference is made to Figure 2 and Figure 3 At least one spacer layer 2 includes at least one nitride layer and at least one oxide layer 4.
[0052] Continue to refer to Figure 2 and Figure 3 For example, the nitride layer includes a first nitride sublayer 31 and a second nitride sublayer 32 covering the outside of the signal line 12, and the oxide layer 4 includes an oxide sublayer 41 and a oxynitride sublayer 42 covering the outside of the second nitride sublayer 32.
[0053] Oxide material is deposited on the sidewalls and top surface of the second nitride sublayer 32 using the ALD (Atomic Layer Deposition) process, so that the deposited oxide material covers the top surface and sidewalls of the second nitride sublayer 32. Then, the excess oxide material is removed by etching downward from the second nitride sublayer 32 using the SADP (Self Aligned Double Patterning) process. The remaining part of the oxide material forms the oxide sublayer 41, which covers the outside of the second nitride sublayer 32 and covers the top surface of the substrate 11 located on both sides of the second nitride sublayer 32.
[0054] By nitriding the sidewalls and top surface of the formed oxide sublayer 41, the nitrogen content of the oxide sublayer 41 is increased, and a double oxide sublayer 41 is formed on the outside of the oxide sublayer 41, forming a double-layer oxide layer 4.
[0055] When the oxide sublayer 41 is nitrided, the first nitride sublayer 31 and the second nitride sublayer 32 are compacted, that is, the thickness of the inner layer structure in the spacer layer 2 is reduced. When applied to the field where the signal line 12 is a bit line, the reduction in the thickness of the first nitride sublayer 31 and the second nitride sublayer 32, combined with the increase in the thickness of the oxide sublayer 41, can improve the effect of improving the parasitic capacitance problem of the bit line.
[0056] In an exemplary embodiment of this disclosure, reference is made to Figure 4 Step S200, forming at least one initial spacer layer on the sidewall of the signal line, and subjecting the at least one initial spacer layer to nitriding treatment specifically includes:
[0057] S210, Form a first initial nitride layer, the first initial nitride layer at least covering the sidewalls of the signal line.
[0058] Reference Figure 5In this step, nitride material is deposited on the top surface of substrate 11 using ALD (Atomic layer deposition) process, so that the deposited nitride material covers the top surface of substrate 11. Then, the excess nitride material is removed by etching from the top surface of substrate 11 downwards using SADP (Self-Aligned Double Patterning) process. The remaining part of the nitride material forms the first initial nitride layer. In this step, the first initial nitride layer is the first nitride sublayer 31. The first nitride sublayer 31 covers the sidewalls and top of signal line 12, and covers the part of the top surface of substrate 11 located on both sides of signal line 12.
[0059] In this step, other methods can also be used, such as CVD (Chemical Vapor Deposition) processes. For example, high-density plasma chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to deposit nitride materials, and the nitride materials can be etched using SAQP (Self-Aligned Quadruple Patterning) or SALELE (Self-Aligned Lithe-Etch-Lithe-Etch).
[0060] S220. Perform a first nitriding treatment on the first initial nitride layer to obtain the first nitride layer.
[0061] Continue to refer to Figure 5 In this step, the sidewalls and top surface of the first nitride sublayer 31 are nitrided to increase the nitrogen content of the first nitride sublayer 31, and a nitrogen atom layer is formed on the sidewalls and top surface of the first nitride sublayer 31. The nitrogen atom layer covers the first nitride sublayer 31 and serves as the second nitride sublayer 32. The first nitride sublayer 31 and the second nitride sublayer 32 together form the first nitride layer 3.
[0062] The etch resistance of the first nitride layer 3 formed after nitriding is improved, reducing the possibility of short bit line contact or missing bit line isolation structure when the spacer layer 2 is thin. At the same time, it improves the sensitivity of the semiconductor device and ensures that the semiconductor device has a write recovery time that meets the requirements.
[0063] S230, an initial oxide layer is formed, which covers the first nitride layer.
[0064] Reference Figure 6In this step, an oxide material is deposited on the top surface and sidewalls of the first nitride layer 3 using a CVD (Chemical Vapor Deposition) process, such as a high-density plasma chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process. The deposited oxide material covers the top surface and sidewalls of the first nitride layer 3. Then, the excess oxide material is removed by etching downwards from the top of the first nitride layer 3 using a SAQP (Self-Aligned Quadruple Patterning) process. The remaining part of the oxide material forms an oxide sublayer 41. The oxide sublayer 41 in this step is the initial oxide layer 4. The oxide sublayer 41 covers the sidewalls and top of the first nitride layer 3 and covers the top surface of the substrate 11 located on both sides of the first nitride layer 3.
[0065] It should be understood that the above-described deposition of oxide materials using CVD is only one specific embodiment. In other specific embodiments, ALD (Atomic Layer Deposition) technology can also be used to deposit oxide materials. Similarly, in other specific embodiments, SALELE (Self-Aligned Lithe-Etch-Lithe-Etch) can be used to etch the oxide material to form an oxide sublayer 41.
[0066] S240. Perform a second nitriding treatment on the initial oxide layer to obtain the oxide layer.
[0067] Continue to refer to Figure 6 In this step, the sidewalls and top surface of the formed oxide sublayer 41 are nitrided to increase the nitrogen content of the oxide sublayer 41, and a single-atom layer is formed on the sidewalls and top surface of the oxide sublayer 41. The nitrogen atom layer covers the oxide sublayer 41 and serves as the oxynitride sublayer 42. The oxide sublayer 41 and the oxynitride sublayer 42 together form the oxide layer 4.
[0068] The etch resistance of the nitrided oxide layer 4 is improved, and the increased thickness of the oxide layer 4 also helps to improve the problem of bit line parasitic capacitance.
[0069] S250, a second initial nitride layer is formed, and the second nitride layer covers the oxide layer.
[0070] Reference Figure 7In this step, nitride material is deposited on the top surface and sidewalls of oxide layer 4 using ALD (Atomic layer deposition) process, so that the deposited nitride material covers the top surface and sidewalls of oxide layer 4. Then, the excess nitride material is removed by etching from above oxide layer 4 downwards using SADP (Self-Aligned Double Patterning) process. The remaining part of the nitride material forms a second initial nitride layer. In this step, the second initial nitride layer is a third nitride sublayer 51. The third nitride sublayer 51 covers the sidewalls and top of oxide layer 4, and covers the part of the top surface on both sides of oxide layer 4 on substrate 11.
[0071] In this step, other methods can also be used, such as CVD (Chemical Vapor Deposition) processes. For example, high-density plasma chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to deposit nitride materials, and the nitride materials can be etched using SAQP (Self-Aligned Quadruple Patterning) or SALELE (Self-Aligned Lithe-Etch-Lithe-Etch).
[0072] S260. Perform a third nitriding treatment on the second initial nitride layer to obtain the second nitride layer.
[0073] Continue to refer to Figure 7 In this step, the sidewalls and top surface of the formed third nitride sublayer 51 are nitrided to increase the nitrogen content of the third nitride sublayer 51, and a nitrogen atom layer is formed on the sidewalls and top surface of the third nitride sublayer 51. The nitrogen atom layer covers the third nitride sublayer 51 and serves as the fourth nitride sublayer 52. The second nitride sublayer 32 and the fourth nitride sublayer 52 together form the second nitride layer 5.
[0074] The etch resistance of the second nitride layer 5 formed after nitriding is improved, reducing the possibility of short bit line contact or missing bit line isolation structure when the spacer layer 2 is thin. At the same time, it improves the sensitivity of the semiconductor device and ensures that the semiconductor device has a write recovery time that meets the requirements.
[0075] In an exemplary embodiment of this disclosure, a remote plasma nitriding process is used to nitrid at least one initial spacer layer.
[0076] For example, the power of remote plasma nitriding is 800-1200W.
[0077] Compared to conventional gas nitriding, RPN (remote plasma nitriding) is faster, produces a less brittle nitrided layer, is easier to achieve localized nitriding, and allows for better control of the nitrided layer thickness.
[0078] In an exemplary embodiment of this disclosure, referring to 6, before the second nitriding treatment, there is a first distance between the initial oxide layer 4 and the sidewall of the signal line 12, and after the second nitriding treatment, there is a second distance between the oxide layer 4 and the sidewall of the signal line 12, wherein the first distance is greater than the second distance.
[0079] For example, the first distance is d, and the second distance is D. Before the second nitriding treatment, that is, before the formation of the oxide nitride sublayer 42, d is the sum of the thicknesses of the first nitride sublayer 31 and the second nitride sublayer 32. During the second nitriding treatment, RPN (remote plasma nitridation) causes the oxide sublayer 41 to compress the first nitride layer 3, thereby compacting the first nitride layer 3 and reducing the thickness of the first nitride layer 3, so that the first distance d is greater than the second distance D.
[0080] Because the second nitriding treatment increases the thickness of the oxide layer 4 and reduces the thickness of the first nitride layer 3, the problem of bit line parasitic capacitance is improved.
[0081] In this embodiment, additional reference is made. Figure 5 The thickness of the first initial nitride layer is 2-5 nm; the thickness of the initial oxide layer 4 is 6-10 nm; and the thickness of the second initial nitride layer is 6-10 nm. In other specific embodiments, the thicknesses of the first initial nitride layer (first nitride sublayer 31), the initial oxide layer 4 (oxide sublayer 41), and the second initial nitride layer (third nitride sublayer 51) can be varied according to different operating conditions and requirements.
[0082] In an exemplary embodiment of this disclosure, reference is made to Figure 7 The signal line 12 includes a bit line, and a cover layer 13 is disposed on the bit line; the inner spacer layer 2 covers the side wall of the bit line and the side wall and top wall of the cover layer 13.
[0083] For example, the capping layer 13 is fixed and covers the top surface of the bit line, and the first nitride sublayer 31 covers the top surface and sidewalls of the capping layer 13.
[0084] Reference Figure 8In a second aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: a substrate 1, the substrate 1 including a substrate 11 and a signal line 12 located on the substrate 11; a spacer structure covering the sidewalls of the signal line 12, the spacer structure including at least one spacer layer 2, wherein the nitrogen content of at least one spacer layer 2 on the side closer to the signal line 12 is less than the nitrogen content on the side farther from the signal line 12.
[0085] For example, the substrate 1 includes a substrate 11 and signal lines 12 fixed on the substrate 11. The substrate 11 serves as a support component for the memory, supporting other components disposed thereon; the signal lines 12 can be bit lines or word lines. The spacer structure includes a spacer layer 2 covering the outer side and top of the signal lines 12. In this embodiment, the spacer layer 2 includes a first nitride layer 3 covering the signal lines 12. The first nitride layer 3 has a multilayer structure extending outward along the signal lines 12. For the first nitride layer 3 forming the spacer layer 2, the nitrogen content of the inner layer structure of the first nitride layer 3 near the signal lines 12 is less than the nitrogen content of the outer layer structure of the first nitride layer 3 away from the signal lines 12.
[0086] In this embodiment, the materials of the multilayer structure of the first nitride layer 3 can be the same or different. The multilayer structure of the first nitride layer 3 can be sequentially deposited on the signal line 12, and each layer is nitrided after formation to ensure that the nitrogen content in the spacer layer 2 near the signal line 12 is less than the nitrogen content away from the signal line 12. For example, the nitriding treatment of each layer in the first nitride layer 3 can employ RPN (remote plasma nitridation) processes with different powers.
[0087] It should be understood that the first nitride layer 3 described above is only one specific embodiment. In other specific embodiments, an oxide of a different material than the first nitride layer 3 may be used to form a spacer layer 2 on the signal line 12. Similarly, the spacer layer 2 may be one layer, or two or more layers.
[0088] In this embodiment, the substrate 11 material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds.
[0089] In an exemplary embodiment of this disclosure, reference is made to Figure 8 The spacer structure includes multiple spacer layers 2, and the nitrogen content on the side of each spacer layer 2 closer to the signal line 12 is less than the nitrogen content on the side farther from the signal line 12.
[0090] For example, at least one spacer layer 2 includes at least one nitride layer and at least one oxide layer 4. The nitride layer includes a first nitride layer 3 covering the sidewalls and top of the signal line 12, and the oxide layer 4 covers the sidewalls and top of the first nitride layer 3. Since the spacer layer 2 is a multilayer structure, the first nitride layer 3 can be considered as a single layer in the spacer layer 2, and the same applies to the oxide layer 4. That is, the nitrogen content on the side of the first nitride layer 3 closer to the signal line 12 is less than the nitrogen content on the side of the first nitride layer 3 farther from the signal line 12, and the same applies to the oxide layer 4.
[0091] In an exemplary embodiment of this disclosure, reference is made to Figure 8 At least one spacer layer 2 includes a first nitride layer 3, an oxide layer 4, and a second nitride layer 5 sequentially disposed from the side closer to the signal line 12 to the side farther away from the signal line 12.
[0092] For example, the second nitride layer 5 covers the sidewalls and topwalls of the oxide layer 4, and the nitrogen content on the side of the second nitride layer 5 closer to the signal line 12 is less than the nitrogen content on the side of the first nitride layer 3 farther from the signal line 12.
[0093] In an exemplary embodiment of this disclosure, reference is made to Figure 8 The first nitride layer 3 includes a first nitride sublayer 31 and a second nitride sublayer 32 located outside the first nitride sublayer 31, wherein the nitrogen content of the second nitride sublayer 32 is greater than the nitrogen content of the first nitride sublayer 31; the oxide layer 4 includes an oxide sublayer 41 and a nitride oxide sublayer 42 located outside the oxide sublayer 41; the second nitride layer 5 includes a third nitride sublayer 51 and a fourth nitride sublayer 52 located outside the third nitride sublayer 51, wherein the nitrogen content of the fourth nitride sublayer is greater than the nitrogen content of the third nitride sublayer 51.
[0094] For example, the first nitride layer 3 specifically includes a first nitride sublayer 31 and a second nitride sublayer 32. The first nitride sublayer 31 covers the sidewalls of the signal line 12, the top of the signal line 12, and a portion of the top surface on the substrate 11 located on both sides of the signal line 12. The second nitride sublayer 32 covers the sidewalls of the first nitride sublayer 31, the top surface of the first nitride sublayer 31, and a portion of the top surface on the substrate 11 located on both sides of the first nitride sublayer 31. For the first nitride layer 3 forming a spacer layer 2, the nitrogen content of the first nitride sublayer 31 is less than the nitrogen content of the second nitride sublayer 32.
[0095] After the first nitride sublayer 31 is nitrided, a second nitride sublayer 32 is formed. The etch resistance of the spacer layer 2 formed by the first nitride sublayer 31 and the second nitride sublayer 32 is improved, which improves the sensitivity of the semiconductor device and ensures that the semiconductor device has a write recovery time that meets the requirements. At the same time, it reduces the possibility of short bit line contact or missing bit line isolation structure when the spacer layer 2 is thin.
[0096] The oxide layer 4 includes an oxide sublayer 41 and an oxide nitride sublayer 42. The oxide sublayer 41 covers the sidewalls and top wall of the second nitride sublayer 32, as well as a portion of the top surface on the substrate 11 located on both sides of the second nitride sublayer 32; the oxide nitride sublayer 42 covers the sidewalls and top wall of the oxide sublayer 41, as well as a portion of the top surface on the substrate 11 located on both sides of the oxide sublayer 41. For the oxide layer 4 forming a spacer layer 2, the nitrogen content of the oxide sublayer 41 is less than the nitrogen content of the oxide nitride sublayer 42.
[0097] The etch resistance of the nitrided oxide layer 4 is improved, and the increased thickness of the oxide layer 4 also helps to improve the parasitic capacitance problem of bit lines. Since the first nitride sublayer 31 and the second nitride sublayer 32 are compacted during the nitriding process of the oxide sublayer 41, the thickness of the inner layer structure in the spacer layer 2 is reduced. When applied to areas where the signal line 12 is a bit line, the reduction in the thickness of the first nitride sublayer 31 and the second nitride sublayer 32, combined with the increase in the thickness of the oxide sublayer 41, can improve the effect of improving the parasitic capacitance problem of bit lines.
[0098] The second nitride layer 5 includes a third nitride sublayer 51 and a fourth nitride sublayer 52. The third nitride sublayer 51 covers the sidewalls of the oxynitride sublayer 42, the top wall of the oxynitride sublayer 42, and a portion of the top surface on the substrate 11 located on both sides of the oxynitride sublayer 42; the fourth nitride sublayer 52 covers the sidewalls of the third nitride sublayer 51, the top wall of the third nitride sublayer 51, and a portion of the top surface on the substrate 11 located on both sides of the third nitride sublayer 51. For the second nitride layer 5 forming a spacer layer 2, the nitrogen content of the third nitride sublayer 51 is less than the nitrogen content of the fourth nitride sublayer 52.
[0099] Similarly, the third nitride sublayer 51 is nitrided to form the fourth nitride sublayer 52. The etch resistance of the spacer layer 2 formed by the third nitride sublayer 51 and the fourth nitride sublayer 52 is improved, which improves the sensitivity of the semiconductor device, ensures that the semiconductor device has a write recovery time that meets the requirements, and reduces the possibility of short bit line contact or missing bit line isolation structure when the spacer layer 2 is thin.
[0100] The first nitride sublayer 31 can be formed on the substrate 11 by deposition and etching. For example, nitride material is deposited on the top surface of the substrate 11 by ALD (Atomic layer deposition) process, so that the deposited nitride material covers the top surface of the substrate 11, and then the excess nitride material is removed by SADP (Self Aligned Double Patterning) process from the top surface of the substrate 11. The remaining part of the nitride material forms the first nitride sublayer 31.
[0101] Nitriding treatment is performed on the sidewalls and top surface of the first nitride sublayer 31 to increase the nitrogen content of the first nitride sublayer 31, and a nitrogen atom layer is formed on the sidewalls and top surface of the first nitride sublayer 31. The nitrogen atom layer covers the first nitride sublayer 31 and serves as the second nitride sublayer 32.
[0102] In this embodiment, other methods can also be used, such as CVD (Chemical Vapor Deposition) processes. For example, high-density plasma chemical vapor deposition or plasma-enhanced chemical vapor deposition can be used to deposit nitride materials, and then the nitride materials can be etched using SAQP (Self-Aligned Quadruple Patterning) or SALELE (Self-Aligned Lithe-Etch-Lithe-Etch). Similarly, the oxide layer 4 and the second nitride layer 5 can also be implemented using the above process steps.
[0103] In an exemplary embodiment of this disclosure, reference is made to Figure 8 The signal line 12 includes a bit line, and a cover layer 13 is disposed on the bit line. The spacer layer 2 located on the inner side covers the side wall of the bit line and the side wall and top wall of the cover layer 13.
[0104] For example, the capping layer 13 is fixed and covers the top wall of the signal line 12, and the first nitride sublayer 31 covers the side wall of the signal line 12, the side wall of the capping layer 13, the top wall of the capping layer 13, and the portion of the top surface on the substrate 11 located on both sides of the signal line 12.
[0105] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0106] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.
[0107] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, the substrate including a substrate and signal lines located on the substrate; At least one initial spacer layer is formed on the sidewall of the signal line, and the at least one initial spacer layer is nitrided to obtain at least one spacer layer; The process of forming at least one initial spacer layer on the sidewall of the signal line and nitriding the at least one initial spacer layer includes: Multiple initial spacer layers are sequentially formed on the sidewall of the signal line, and after each initial spacer layer is formed, the initial spacer layer is nitrided to obtain the spacer layer.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The at least one spacer layer includes at least one nitride layer and at least one oxide layer.
3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The process of forming at least one initial spacer layer on the sidewall of the signal line and nitriding the at least one initial spacer layer includes: A first initial nitride layer is formed, the first initial nitride layer at least covering the sidewalls of the signal line; The first initial nitride layer is subjected to a first nitriding treatment to obtain a first nitride layer; An initial oxide layer is formed, which covers the first nitride layer; The initial oxide layer is subjected to a second nitriding treatment to obtain an oxide layer; A second initial nitride layer is formed, which covers the oxide layer; The second initial nitride layer is subjected to a third nitriding treatment to obtain a second nitride layer.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Before the second nitriding treatment, there is a first distance between the initial oxide layer and the sidewall of the signal line. After the second nitriding treatment, there is a second distance between the oxide layer and the sidewall of the signal line. The first distance is greater than the second distance.
5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The thickness of the first initial nitride layer is 2-5 nm; The thickness of the initial oxide layer is 6-10 nm; The thickness of the second initial nitride layer is 6-10 nm.
6. The method for fabricating a semiconductor structure according to any one of claims 1 to 5, characterized in that, At least one of the initial spacer layers is nitrided using a remote plasma nitriding process.
7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The power of the remote plasma nitriding is 800-1200W.
8. The method for fabricating a semiconductor structure according to any one of claims 1 to 5, characterized in that, The signal line includes a bit line, and a cover layer is disposed on the bit line; The spacer layer located on the inside covers the sidewalls of the bit line as well as the sidewalls and top wall of the cover layer.
9. A semiconductor structure, said semiconductor structure being fabricated using the fabrication method according to any one of claims 1-8, characterized in that, The semiconductor structure includes: A substrate, the substrate including a substrate and signal lines located on the substrate; A spacer structure covering the sidewall of the signal line, the spacer structure comprising at least one spacer layer, wherein the nitrogen content of at least one spacer layer on the side closer to the signal line is less than the nitrogen content on the side farther from the signal line.
10. The semiconductor structure according to claim 9, characterized in that, The spacing structure includes multiple spacing layers, and the nitrogen content on the side of each spacing layer closer to the signal line is less than the nitrogen content on the side farther from the signal line.
11. The semiconductor structure according to claim 9, characterized in that, The at least one spacer layer includes at least one nitride layer and at least one oxide layer.
12. The semiconductor structure according to claim 11, characterized in that, The at least one spacer layer includes a first nitride layer, an oxide layer, and a second nitride layer disposed sequentially from the side closest to the signal line to the side furthest from the signal line.
13. The semiconductor structure according to claim 12, characterized in that, The first nitride layer includes a first nitride sublayer and a second nitride sublayer located outside the first nitride sublayer, wherein the nitrogen content of the second nitride sublayer is greater than the nitrogen content of the first nitride sublayer; The oxide layer includes an oxide sublayer and a nitrogen oxide sublayer located outside the oxide sublayer; The second nitride layer includes a third nitride sublayer and a fourth nitride sublayer located outside the third nitride sublayer, wherein the nitrogen content of the fourth nitride sublayer is greater than the nitrogen content of the third nitride sublayer.
14. The semiconductor structure according to any one of claims 9 to 13, characterized in that, The signal line includes a bit line, and a cover layer is disposed on the bit line. The spacer layer located on the inner side covers the sidewall of the bit line as well as the sidewall and top wall of the cover layer.