Method for manufacturing a semiconductor structure and semiconductor structure
By employing an in-situ water vapor generation process to form a dense gate dielectric layer and a smooth floating gate and erase gate structure in the semiconductor structure, the problem of easy erosion of the isolation dielectric layer between the select gate and the erase gate is solved, thereby improving the cycle life and performance of the eflash memory cell.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GTA SEMICON CO LTD
- Filing Date
- 2026-03-23
- Publication Date
- 2026-06-05
AI Technical Summary
In the traditional floating-gate eflash memory cell structure, the isolation dielectric layer between the select gate and the erase gate is easily eroded in subsequent processes, resulting in reduced write and erase efficiency and affecting the cycle life of the device.
A dense grid dielectric layer is formed by in-situ water vapor generation process, covering the sidewalls and bottom surface of the receiving trench between the selective grid structures, and forming a smooth floating grid and erase grid structure in the receiving trench, which enhances the isolation effect and reduces leakage current.
It significantly improves the device's cycle performance and reliability, enhances programming efficiency, reduces operating voltage, and extends device lifespan.
Smart Images
Figure CN122161099A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] In the field of semiconductor manufacturing technology, embedded flash memory (eflash) has become increasingly important in the field of non-volatile memory due to its performance advantages such as low cost, low power consumption and fast access speed.
[0003] In embedded systems, cyclic management of embedded flash memory cells is one of the core technologies for ensuring long-term reliable operation. Cycling management of embedded flash memory cells has a significant impact on the reliability, lifespan, and cost of semiconductor products, and is also key to overcoming the limitations of traditional flash memory. Summary of the Invention
[0004] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.
[0005] According to some embodiments, this application provides a method for fabricating a semiconductor structure, the method comprising:
[0006] A substrate is provided, on which a first selection gate structure and a second selection gate structure are formed, and an isolation layer is formed. The isolation layer is located on the top surface of the first selection gate structure and the second selection gate structure, and an accommodating trench is formed between the first selection gate structure and the second selection gate structure.
[0007] A gate dielectric layer is formed using a preset process. The gate dielectric layer covers the sidewalls and bottom surface of the receiving trench, and the top surface of the gate dielectric layer is flush with the top surface of the isolation layer.
[0008] A first floating grid structure and a second floating grid structure are formed within a receiving trench, and a target trench is formed between the first floating grid structure and the second floating grid structure.
[0009] A control grid structure is formed within the target trench;
[0010] A first erase gate structure and a second erase gate structure are formed. The first erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the first floating gate structure. The second erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the second floating gate structure. Both the first erase gate structure and the second erase gate structure have smooth bottom surfaces.
[0011] In the semiconductor structure fabrication method of the above embodiments, a first select gate structure and a second select gate structure are formed on a substrate, and an accommodating trench is formed between the first select gate structure and the second select gate structure. A gate dielectric layer covering the sidewalls and bottom surface of the accommodating trench is formed using a preset process. A first floating gate structure and a second floating gate structure are formed in the accommodating trench, and a first erase gate structure and a second erase gate structure are formed. Both the first erase gate structure and the second erase gate structure have smooth bottom surfaces, which can effectively enhance the isolation effect between the first erase gate structure and the second erase gate structure and the first select gate structure and the second select gate structure, reduce the leakage current between the erase gate structure and the select gate structure, and thus effectively improve the cycle performance of the device.
[0012] In some embodiments, a gate dielectric layer is formed using a preset process, including:
[0013] The gate dielectric layer is formed using an in-situ water vapor generation process.
[0014] In some embodiments, the gate dielectric layer located at the junction of the accommodating trench sidewall and the bottom surface has a smooth surface.
[0015] In some embodiments, the thickness of the gate dielectric layer is 80 Å to 120 Å.
[0016] In some embodiments, after forming the first floating gate structure and the second floating gate structure in the receiving trench and before forming the control gate structure in the target trench, the method further includes:
[0017] A sacrificial layer is formed within the target trench;
[0018] The target doped region is formed within the substrate;
[0019] Remove the sacrificial layer.
[0020] In some embodiments, the doping type of the target doped region is N-type;
[0021] In some embodiments, forming a target doped region within a substrate includes:
[0022] The target doped region is formed in the substrate using a preset ion implantation process.
[0023] In some embodiments, after forming the first floating gate structure and the second floating gate structure within the receiving trench, the method further includes:
[0024] An insulating layer is formed within the receiving trench, the insulating layer being located between the control gate structure and the first floating gate structure, and between the control gate structure and the second floating gate structure;
[0025] A tunneling layer is formed, which is located at least between the erase grid structure and the first floating grid structure, and between the erase grid structure and the second floating grid structure.
[0026] In some embodiments, the thickness of the insulating layer is 300 Å to 350 Å.
[0027] In some embodiments, the gate dielectric layer is made of silicon oxide;
[0028] In some embodiments, the sacrificial layer is made of silicon nitride;
[0029] In some embodiments, the insulating layer is made of silicon oxide.
[0030] According to some embodiments, this application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method in any of the above embodiments. Attached Figure Description
[0031] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.
[0032] Figure 2 This is a schematic cross-sectional view of the structure obtained in steps S10 and S30 of a semiconductor structure fabrication method provided in an embodiment of this application;
[0033] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S50 of a semiconductor structure fabrication method according to an embodiment of this application;
[0034] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S61 of a semiconductor structure fabrication method according to an embodiment of this application;
[0035] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S63 of a semiconductor structure fabrication method according to an embodiment of this application;
[0036] Figure 6 This is a schematic cross-sectional view of the structure obtained in steps S70 and S90 of a semiconductor structure fabrication method provided in an embodiment of this application;
[0037] Figure 7 This is a schematic diagram of the electrical performance curves of a semiconductor structure obtained by a method for fabricating a semiconductor structure according to an embodiment of this application.
[0038] Explanation of reference numerals in the attached figures: 10, substrate; 21, first select gate structure; 22, second select gate structure; J1, accommodating trench; 30, isolation layer; 40, gate dielectric layer; 50, first floating gate structure; 52, second floating gate structure; J2, target trench; 60, control gate structure; 71, first erase gate structure; 72, second erase gate structure; 80, sacrificial layer. Detailed Implementation
[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0041] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0042] Furthermore, to clearly illustrate the multiple layers and regions in the accompanying drawings, the thickness of each layer and each region has been enlarged to clearly demonstrate the relative positions of the layers and the distribution of the regions. When a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, this description includes not only the case where it is "directly" above the other portion, but also the case where other layers are present in between. Moreover, it is understood that when a portion of a layer, film, region, plate, etc., is described as being "on one side" of another portion, it generally refers to the side directly above the other portion.
[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0045] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.
[0046] In the field of embedded non-volatile memory, embedded flash memory (eflash) has become one of the key technologies widely used in system-on-a-chip (SoC) due to its advantages such as low power consumption, low cost, and fast access. As embedded systems increasingly demand higher data storage reliability, eflash's cycling management capability has become a core factor affecting product lifespan, system stability, and overall cost.
[0047] For example, in a traditional floating-gate EFlash memory cell structure, the select gate (SG) controls channel conduction to isolate the effects of write and erase operations on adjacent cells. The floating gate (FG) injects electrons through hot carrier injection (HCI) to raise the threshold voltage, thus enabling the write operation. The erase operation relies on the erase gate (EP) applying a high voltage, causing the floating gate's stored electrons to tunnel through the FN gate, thereby lowering the threshold voltage. To meet the industry requirement of 100k write / erase cycles for EFlash, the dielectric layer (TEOS) between the select gate and the floating gate must possess extremely high process reliability.
[0048] However, in the traditional floating-gate eflash memory cell structure, the select gate spacer uses an ONO structure as the isolation layer. Phosphoric acid (HPO) used in the subsequent SiN removal process erodes the SiN on top of the SG sidewall, causing divot during subsequent EP deposition. This weakens the electrical isolation between the erase gate and the select gate, affecting erase / write efficiency and ultimately reducing the device's cycling life. Therefore, optimizing the isolation structure between the erase gate and the select gate to improve its reliability after multiple erase / write cycles has become a key technical challenge for improving eflash performance.
[0049] Based on this, embodiments of this application provide a method for preparing a semiconductor structure and a semiconductor structure.
[0050] Please see Figure 1 This application provides a method for fabricating a semiconductor structure, which includes the following steps.
[0051] Step S10: Provide a substrate, form a first selection gate structure and a second selection gate structure on the substrate, and form an isolation layer. The isolation layer is located on the top surface of the first selection gate structure and the second selection gate structure, and an accommodating trench is formed between the first selection gate structure and the second selection gate structure.
[0052] Step S30: A gate dielectric layer is formed using a preset process. The gate dielectric layer covers the sidewalls and bottom surface of the receiving trench, and the top surface of the gate dielectric layer is flush with the top surface of the isolation layer.
[0053] Step S50: A first floating grid structure and a second floating grid structure are formed in the receiving trench, and a target trench is formed between the first floating grid structure and the second floating grid structure.
[0054] Step S70: Form a control grid structure within the target trench;
[0055] Step S90: Form a first erase gate structure and a second erase gate structure. The first erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the first floating gate structure. The second erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the second floating gate structure. Both the first erase gate structure and the second erase gate structure have smooth bottom surfaces.
[0056] In the semiconductor structure fabrication method of the above embodiments, a first select gate structure and a second select gate structure are formed on a substrate, and an accommodating trench is formed between the first select gate structure and the second select gate structure. A gate dielectric layer covering the sidewalls and bottom surface of the accommodating trench is formed using a preset process. A first floating gate structure and a second floating gate structure are formed in the accommodating trench, and a first erase gate structure and a second erase gate structure are formed. Both the first erase gate structure and the second erase gate structure have smooth bottom surfaces, which can effectively enhance the isolation effect between the first erase gate structure and the second erase gate structure and the first select gate structure and the second select gate structure, reduce the leakage current between the erase gate structure and the select gate structure, and thus effectively improve the cycle performance of the device.
[0057] In some embodiments, step S30, forming a gate dielectric layer using a preset process, includes:
[0058] Step S31: Form the gate dielectric layer using an in-situ water vapor generation process.
[0059] In some embodiments, the gate dielectric layer located at the junction of the accommodating trench sidewall and the bottom surface has a smooth surface.
[0060] In some embodiments, the thickness of the gate dielectric layer is 80 Å to 120 Å.
[0061] In some embodiments, after step S50, forming the first floating gate structure and the second floating gate structure in the receiving trench, and before step S70, forming the control gate structure in the target trench, the method further includes:
[0062] Step S61: Form a sacrificial layer within the target trench;
[0063] Step S62: Form the target doped region in the substrate;
[0064] Step S63: Remove the sacrificial layer.
[0065] In some embodiments, the doping type of the target doped region is N-type;
[0066] In some embodiments, step S62, forming a target doped region in the substrate, includes:
[0067] Step S621: Form the target doped region in the substrate using a preset ion implantation process.
[0068] In some embodiments, after step S50, forming the first floating gate structure and the second floating gate structure within the receiving trench, the method further includes:
[0069] Step S501: An insulating layer is formed in the receiving trench, the insulating layer being located between the control gate structure and the first floating gate structure, and between the control gate structure and the second floating gate structure;
[0070] Step S502: Form a tunneling layer, which is located at least between the erase grid structure and the first floating grid structure, and between the erase grid structure and the second floating grid structure.
[0071] In the embodiments disclosed above, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.
[0072] To more clearly illustrate the semiconductor structure fabrication method provided in the above embodiments, the following is combined with... Figures 2 to 7 The method is described in detail.
[0073] Step S10: Provide a substrate 10, form a first selection gate structure 21 and a second selection gate structure 22 on the substrate 10, and form an isolation layer 30. The isolation layer 30 is located on the top surface of the first selection gate structure 21 and the second selection gate structure 22, and an accommodating trench J1 is formed between the first selection gate structure 21 and the second selection gate structure 22.
[0074] like Figure 2As shown, in step S10, the substrate 10 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon-germanium (SiGe) substrate 10, a silicon-germanium-carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0075] For example, the materials of the first selection gate structure 21 and the second selection gate structure 22 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).
[0076] For example, the insulating layer 30 can be made of silicon oxide produced by tetraethyl orthosilicate, and the insulating layer 30 can play a good electrical isolation role.
[0077] In some embodiments, the thickness of the insulating layer 30 ranges from 300 Å to 350 Å. For example, the thickness of the insulating layer 30 can be 300 Å, 310 Å, 320 Å, 330 Å, 340 Å, or 250 Å, etc. By providing an insulating layer 30 with sufficient thickness, the isolation effect can be guaranteed, which helps to avoid leakage.
[0078] like Figure 2 As shown, in step S30, a gate dielectric layer 40 is formed using a preset process. The gate dielectric layer 40 covers the sidewalls and bottom surface of the accommodating trench J1, and the top surface of the gate dielectric layer 40 is flush with the top surface of the isolation layer 30.
[0079] In some embodiments, step S30, forming the gate dielectric layer 40 using a preset process, includes:
[0080] Step S31: Form the gate dielectric layer 40 using an in-situ water vapor generation process.
[0081] In some embodiments, the gate dielectric layer 40 located at the junction of the sidewall and bottom surface of the accommodating trench J1 has a smooth surface.
[0082] In some embodiments, the gate dielectric layer 40 is a single film layer.
[0083] In some embodiments, the thickness of the gate dielectric layer 40 ranges from 80 Å to 120 Å. For example, the thickness of the gate dielectric layer 40 can be 80 Å, 90 Å, 100 Å, 110 Å, or 120 Å, etc.
[0084] For example, the consumption ratio of the first selected gate structure 21 and / or the second selected gate structure 22 to the gate dielectric layer 40 is 1:1. For instance, in an embodiment where the first selected gate structure 21 and / or the second selected gate structure 22 is made of polysilicon, the gate dielectric layer 40 may be made of silicon oxide.
[0085] In some embodiments, the preset process may include an in-situ steam generation process. In conventional processes, a silicon nitride film layer typically remains on the sidewalls of the selected gate structure, and this silicon nitride film layer is partially eroded during subsequent phosphoric acid removal, resulting in an undesirable morphology of the gate dielectric layer 40. It is understood that when the gate dielectric layer 40 is formed using the preset process, a dense gate dielectric layer 40 can be generated, thereby ensuring the integrity of the morphology of the gate dielectric layer 40.
[0086] It is understandable that the ISSG process utilizes the in-situ reaction of hydrogen and oxygen on the wafer surface to generate water vapor. Its high growth temperature and extremely pure oxidation environment enable the formation of denser films with lower defect densities. This significantly reduces the interface state trap density at the interface between the film and the substrate 10. Due to the substantial reduction in interface state traps, electrons are less likely to be trapped by interface defects during channel hot carrier injection, allowing more electrons to be successfully injected into the floating gate. This improves the efficiency of programming operations, thereby increasing programming speed and reducing operating voltage. Furthermore, the improved programming efficiency also means that, under the same number of erase / write cycles, the device's threshold voltage window is more stable and its tolerance is stronger.
[0087] Meanwhile, the ISSG process offers excellent topology control, effectively reducing the sharpness of active region corners and mitigating local electric field concentration effects, thereby suppressing tip leakage and further reducing device leakage current. By reducing interface defects, electrons are less likely to be trapped by interface traps during floating gate injection, thus improving programming efficiency.
[0088] Step S50: A first floating grid structure 50 and a second floating grid structure 52 are formed in the receiving trench J1, and a target trench J2 is formed between the first floating grid structure 50 and the second floating grid structure 52.
[0089] For example, in step S50, a first floating gate structure 50 and a second floating gate structure 52 may be formed in the receiving trench J1 using a chemical vapor deposition process. The chemical vapor deposition process may include one or more of atmospheric-pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).
[0090] For example, the materials of the first floating gate structure 50 and the second floating gate structure 52 include, but are not limited to, one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).
[0091] like Figures 3 to 5 As shown, in some embodiments, after step S50, forming the first floating gate structure 50 and the second floating gate structure 52 in the receiving trench J1, and before step S70, forming the control gate structure 60 in the target trench J2, the method further includes the following steps S61 to S63.
[0092] Step S61, as follows Figure 4 As shown, a sacrificial layer 80 is formed within the target trench J2;
[0093] In some embodiments, the sacrificial layer 80 is made of silicon nitride;
[0094] Step S62: Form the target doped region (not shown) within the substrate 10;
[0095] In some embodiments, the doping type of the target doped region is N-type;
[0096] For example, a pre-defined ion implantation process can be used to form a target doped region within the substrate 10;
[0097] In some embodiments, the doping element in the preset ion implantation process is arsenic.
[0098] In some embodiments, step S62, forming a target doped region within the substrate 10, includes:
[0099] Step S621: Form the target doped region in the substrate 10 using a preset ion implantation process.
[0100] Step S63, as follows Figure 5 As shown, the sacrificial layer 80 is removed.
[0101] For example, in step S63, the sacrificial layer 80 can be removed by an etching-back process or a chemical mechanical polishing process. For instance, this step can be performed using anisotropic etching, which selectively etches the material in a preset crystal orientation or crystal plane direction, leaving little or no etching traces in other directions. Using anisotropic etching for etching-back in this step can make the morphology of the resulting structure more precise and controllable.
[0102] In some embodiments, after step S50, forming the first floating gate structure 50 and the second floating gate structure 52 in the receiving trench J1, the method further includes:
[0103] Step S501: An insulating layer (not shown) is formed in the receiving trench J1. The insulating layer is located between the control gate structure 60 and the first floating gate structure 50, and between the control gate structure 60 and the first floating gate structure 50.
[0104] Step S502: Form a tunneling layer (not shown), which is located at least between the erase grid structure and the first floating grid structure 50, and between the erase grid structure and the second floating grid structure 52.
[0105] like Figure 6 As shown, in step S70, a control gate structure 60 is formed in the target trench J2;
[0106] like Figure 6 As shown, in step S90, a first erase gate structure 71 and a second erase gate structure 72 are formed. The first erase gate structure 71 is located on the top surface of the isolation layer 30, the top surface of the gate dielectric layer 40, and the top surface of the first floating gate structure 50. The second erase gate structure 72 is located on the top surface of the isolation layer 30, the top surface of the gate dielectric layer 40, and the top surface of the second floating gate structure 52. Both the first erase gate structure 71 and the second erase gate structure 72 have smooth bottom surfaces.
[0107] For example, in steps S70 and S90, a chemical vapor deposition process can be used to form the control gate structure 60, the first erase gate structure 71, and the second erase gate structure 72. The chemical vapor deposition process can include one or more of atmospheric-pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).
[0108] For example, the materials of the control gate structure 60, the first erase gate structure 71 and the second erase gate structure 72 are, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).
[0109] In the semiconductor structure fabrication method of the above embodiment, a first select gate structure 21 and a second select gate structure 22 are formed on a substrate 10, and a receiving trench J1 is formed between the first select gate structure 21 and the second select gate structure 22. A gate dielectric layer 40 covering the sidewalls and bottom surface of the receiving trench J1 is formed using a preset process. A first floating gate structure 50 and a second floating gate structure 52 are formed in the receiving trench J1, and a first erase gate structure 71 and a second erase gate structure 72 are formed. The first erase gate structure 71 and the second erase gate structure 72 both have smooth bottom surfaces, which can effectively enhance the isolation effect between the first erase gate structure 71 and the second erase gate structure 72 and the first select gate structure 21 and the second select gate structure 22, reduce the leakage current between the erase gate structure and the select gate structure, and thus effectively improve the cycle performance of the device.
[0110] In the semiconductor structure fabrication method of the above embodiment, a first select gate structure 21 and a second select gate structure 22 are formed on a substrate 10, and a receiving trench J1 is formed between the first select gate structure 21 and the second select gate structure 22. A gate dielectric layer 40 covering the sidewalls and bottom surface of the receiving trench J1 is formed using a preset process. A first floating gate structure 50 and a second floating gate structure 52 are formed in the receiving trench J1, and a first erase gate structure 71 and a second erase gate structure 72 are formed. The first erase gate structure 71 and the second erase gate structure 72 both have smooth bottom surfaces, which can effectively enhance the isolation effect between the first erase gate structure 71 and the second erase gate structure 72 and the first select gate structure 21 and the second select gate structure 22, reduce the leakage current between the erase gate structure and the select gate structure, and thus effectively improve the cycle performance of the device.
[0111] Please combine Figure 7 Understood. The applicant's experiments demonstrate that, after using the ISSG process to generate the gate dielectric layer 40, the document data shows that the device's electrical parameter Ioff_SG can be improved by three orders of magnitude, resulting in a significant improvement in device performance. Simultaneously, cycle data shows that the new process route significantly reduces leakage current at 1K / 10K / 100K currents, greatly improving device reliability and lifetime.
[0112] According to some embodiments, this application also provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the above embodiments. Since a superior preparation method is used to prepare the semiconductor structure, the beneficial effects of the above-described semiconductor structure preparation methods are also present in the semiconductor structure of this application, and will not be elaborated further here.
[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0114] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a first selection gate structure and a second selection gate structure are formed, and an isolation layer is formed, the isolation layer being located on the top surface of the first selection gate structure and the second selection gate structure, and an accommodating trench is formed between the first selection gate structure and the second selection gate structure. A gate dielectric layer is formed using a preset process. The gate dielectric layer covers the sidewalls and bottom surface of the receiving trench, and the top surface of the gate dielectric layer is flush with the top surface of the isolation layer. A first floating grid structure and a second floating grid structure are formed within the accommodating trench, and a target trench is formed between the first floating grid structure and the second floating grid structure. A control grid structure is formed within the target trench; A first erase gate structure and a second erase gate structure are formed. The first erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the first floating gate structure. The second erase gate structure is located on the top surface of the isolation layer, the top surface of the gate dielectric layer, and the top surface of the second floating gate structure. Both the first erase gate structure and the second erase gate structure have smooth bottom surfaces.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The gate dielectric layer is formed using a preset process, including: The gate dielectric layer is formed using an in-situ water vapor generation process.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The gate dielectric layer located at the junction of the sidewall and bottom surface of the receiving trench has a smooth surface.
4. The method for preparing a semiconductor structure according to any one of claims 3, characterized in that, The thickness of the gate dielectric layer is 80 Å to 120 Å.
5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, After forming the first floating gate structure and the second floating gate structure in the receiving trench, and before forming the control gate structure in the target trench, the method further includes: A sacrificial layer is formed within the target trench; A target doped region is formed within the substrate; Remove the sacrificial layer.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The target doped region is of the N-type doping type; Forming a target doped region within the substrate includes: The target doped region is formed in the substrate using a preset ion implantation process.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the first floating gate structure and the second floating gate structure within the accommodating trench, the method further includes: An insulating layer is formed within the receiving trench, the insulating layer being located between the control gate structure and the first floating gate structure, and between the control gate structure and the second floating gate structure; A tunneling layer is formed, which is located at least between the erase gate structure and the first floating gate structure, and between the erase gate structure and the second floating gate structure.
8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the isolation layer is 300 Å to 350 Å.
9. The method for preparing a semiconductor structure according to claim 5, characterized in that, It meets at least one of the following characteristics: The gate dielectric layer is made of silicon oxide; The sacrificial layer is made of silicon nitride. The insulating layer is made of silicon oxide.
10. A semiconductor structure, characterized in that, It is prepared by the method for preparing the semiconductor structure as described in any one of claims 1-9.