Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The present disclosure relates to methods, devices, systems, and techniques for managing isolation structures in a semiconductor device. An example semiconductor device includes a stack of conductive layers and isolation layers alternating with each other along a first direction and a channel structure extending through the stack. The example semiconductor device also includes a conductive structure extending through a dielectric layer, wherein the conductive structure is connected to a corresponding channel structure, and wherein, along a second direction perpendicular to the first direction, a length of a first end portion of a first conductive structure of the conductive structure is greater than a length of the channel structure, and an isolation structure extending through the dielectric layer and at least one conductive layer of the stack along the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing contact structures in semiconductor devices.

[0004] One aspect of this disclosure features a semiconductor device. The semiconductor device includes: a stack of conductive layers and insulating layers alternating with each other along a first direction; a channel structure extending through the stack, wherein the channel structure includes a first end and a second end disposed opposite each other along the first direction; a dielectric layer located on one side of the stack along the first direction and including a first dielectric material; a first conductive structure extending through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, wherein the first conductive structure includes a first end and a second end disposed opposite each other along the first direction, and wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and an insulating structure extending along the first direction through at least one conductive layer of the dielectric layer and the stack.

[0005] In some embodiments, the isolation structure is located between two adjacent channel structures along the second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

[0006] In some embodiments, the semiconductor device further includes an insulating layer stacked between the stack and the dielectric layer, wherein the isolation structure extends through the insulating layer along a first direction.

[0007] In some embodiments, along the second direction, the length of the first end of the first conductive structure is greater than the length of the second end of the first conductive structure, the second end of the first conductive structure is located on the opposite side of the first end of the first conductive structure along the first direction, and wherein the second end of the first conductive structure contacts the first end of the channel structure along the first direction.

[0008] In some embodiments, the channel structure further includes a channel plug that contacts a second end of the first conductive structure along a first direction, and wherein, along the second direction, the length of the first end of the channel structure is greater than the length of the second end of the first conductive structure.

[0009] In some embodiments, the semiconductor device includes a second conductive structure having a first end and a second end disposed opposite to each other along a first direction, wherein the second conductive structure is connected to a corresponding channel structure, and wherein, along a second direction, the length of the first end of the first conductive structure is greater than the length of the first end of the second conductive structure, and the first end of the second conductive structure is further away from the stack than the second end of the second conductive structure.

[0010] In some embodiments, the isolation structure includes an outer layer located in a dielectric layer, wherein the outer layer includes a second dielectric material, and wherein the first dielectric material of the dielectric layer is different from the second dielectric material of the outer layer of the isolation structure.

[0011] In some embodiments, the semiconductor device includes a third conductive structure partially surrounded by an isolation structure, the third conductive structure being connected to a corresponding channel structure, and wherein the third conductive structure is in contact with the outer layer of the isolation structure located in the dielectric layer along a second direction.

[0012] In some embodiments, the first and second conductive structures in the dielectric layer are connected to the interconnect structure via a coupling lead-out structure.

[0013] In some embodiments, along the second direction, the length of the first end of the second conductive structure is at least twice the length of the coupling lead-out structure.

[0014] Another aspect of this disclosure features a method for forming a semiconductor device. The method includes: forming a stack of conductive and insulating layers alternating with each other along a first direction, wherein the stack includes a channel structure extending through the stack along the first direction, and wherein the channel structure includes a first end and a second end disposed opposite to each other along the first direction; forming a dielectric layer located on one side of the stack along the first direction and including a first dielectric material; forming a first conductive structure extending through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, wherein the first conductive structure includes a first end and a second end disposed opposite to each other, and wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and forming an insulating structure extending through at least one conductive layer of the dielectric layer and the stack along the first direction.

[0015] In some embodiments, forming the isolation structure includes: etching through a dielectric layer to form a first space, wherein the first space contacts a corresponding conductive structure; deepening the first space by etching through at least one conductive layer of the stack along a first direction from an end of the first space and etching a portion of the corresponding conductive structure to form a second conductive structure, the end of the first space being connected to the stack; and filling the first space with a dielectric material to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along a second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

[0016] In some embodiments, the method further includes forming an insulating layer by depositing a dielectric material on the ends of the stack body prior to forming the dielectric layer, wherein the insulating layer is stacked between the stack body and the insulating layer, and wherein the conductive structure extends through the insulating layer and connects to a corresponding channel structure.

[0017] In some embodiments, forming the isolation structure further includes: etching through a dielectric layer to form a second space, wherein the second space is in contact with a corresponding conductive structure; etching through an insulating layer at an end of the second space along a first direction, the end of the second space being connected to the insulating layer; deepening the second space by etching through at least one conductive layer of the stack along the first direction from the end of the second space and etching a portion of the corresponding conductive structure to form a second conductive structure; and filling the second space with a dielectric material to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along a second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

[0018] In some embodiments, the second conductive structure includes a first end and a second end disposed opposite to each other along a first direction, wherein, along the second direction, the length of the first end of the first conductive structure is greater than the length of the first end of the second conductive structure, and the first end of the second conductive structure is further away from the stack than the second end.

[0019] In some embodiments, the isolation structure further includes an outer layer located in the dielectric layer, and wherein forming the isolation structure includes: etching through the dielectric layer to form a third space, wherein the third space is in contact with a corresponding conductive structure; depositing an insulating layer on the inner wall of the third space; deepening the third space by etching through at least one conductive layer of the insulating layer and the stack body from an end of the third space along a first direction, the end of the third space being connected to the stack body; and filling the third space with a dielectric material to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along a second direction, and the isolation structure is spaced apart from the channel structures along the second direction.

[0020] In some embodiments, the semiconductor device further includes a third conductive structure partially surrounded by an isolation structure, wherein the third conductive structure contacts the outer layer of the isolation structure located in the dielectric layer along a second direction.

[0021] In some embodiments, the method further includes forming a coupling lead-out structure, wherein a first conductive structure and a second conductive structure in the dielectric layer are connected to an interconnect structure via the coupling lead-out structure.

[0022] In some embodiments, along the second direction, the length of the first end of the second conductive structure is at least twice the length of the coupling lead-out structure.

[0023] Another aspect of this disclosure is a memory system. The memory system includes a memory device and a memory controller coupled to and configured to control the memory device. The memory device includes: a stack of conductive layers and insulating layers alternating with each other along a first direction; a channel structure extending through the stack, wherein the channel structure includes a first end and a second end disposed opposite each other along the first direction; a dielectric layer located on one side of the stack along the first direction and including a first dielectric material; a first conductive structure extending through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, wherein the first conductive structure includes a first end and a second end disposed opposite each other along the first direction, and wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and an insulating structure extending along the first direction through at least one conductive layer of the dielectric layer and the stack.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1 A top view of an exemplary semiconductor device is shown.

[0026] Figure 2A A top view of an exemplary semiconductor device is shown.

[0027] Figure 2B It shows Figure 2A A cross-sectional view of an exemplary semiconductor device.

[0028] Figure 2C It shows Figure 2AA top view of an exemplary semiconductor device.

[0029] Figure 2D A top view of an exemplary semiconductor device is shown.

[0030] Figure 2E It shows Figure 2D A cross-sectional view of an exemplary semiconductor device.

[0031] Figure 2F It shows Figure 2D A top view of an exemplary semiconductor device.

[0032] Figures 3A to 3F It shows Figure 2A Cross-sectional views of the structure of a 3D semiconductor device at various stages of the manufacturing process.

[0033] Figures 4A to 4G It shows Figure 3D Cross-sectional views of the structure of a 3D semiconductor device at various stages of the manufacturing process.

[0034] Figure 5 A flowchart illustrating an exemplary process for manufacturing a semiconductor device is shown.

[0035] Figure 6 A block diagram of an exemplary system is shown.

[0036] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0037] Due to the demand for cheaper memory devices with higher density, memory devices (e.g., 3D NAND flash memory) can be formed with a large number of layers and high aspect ratios. This large number of layers and high aspect ratio can pose challenges to the manufacturing process. For example, a large number of layers requires a larger area for the connection regions of each conductive layer of the memory device, which necessitates additional dummy channel arrays during the manufacturing process. In other words, the large area of ​​the connection regions and the additional dummy channel arrays can challenge increasing the density of the memory device. Another method of forming the connection regions requires an additional isolation layer stack on top of the conductive structure, which increases manufacturing costs and steps, thereby increasing the complexity of the manufacturing process. Therefore, a manufacturing method capable of addressing the aforementioned problems is needed.

[0038] In one or more embodiments of this disclosure, an exemplary semiconductor device is provided. The semiconductor device includes a stack of conductive and insulating layers alternating with each other along a first direction, and a channel structure extending through the stack, wherein each channel structure includes a first end and a second end disposed opposite to each other along the first direction. The semiconductor device also includes a dielectric layer located on one side of the stack along the first direction and including a first dielectric material, and a conductive structure extending through the dielectric layer, wherein the conductive structure is connected to a corresponding channel structure. Each conductive structure includes a first end and a second end disposed opposite to each other along the first direction, wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure. The semiconductor device may further include an insulating structure extending through the dielectric layer and at least one conductive layer of the stack along the first direction.

[0039] The embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. First, the isolation structures of this disclosure can be formed without the need for dummy channel structures. In other words, the isolation structures help reduce the area of ​​the interconnect regions, which increases device density. Second, the isolation structures discussed in this disclosure can be formed on the same stack as the conductive structures, which simplifies the manufacturing process. In other words, the conductive structures serve as masks for the isolation structures, thereby reducing the need for high-resolution lithography tools during the manufacturing process. Third, the conductive layers in the stack of the semiconductor device serve as etch stop layers to control the depth of the isolation structures, thereby providing simple process control for the semiconductor device.

[0040] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), etc. It can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-layer memory) devices, MLC (multi-layer memory) devices (e.g., 2-layer memory devices), TLC (triple-layer memory) devices, QLC (quadruple-layer memory) devices, or PLC (five-layer memory) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0041] Notice, Figure 1 The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of the various components in the semiconductor device. The substrate of the semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed; and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether one component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, such as the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0042] Figure 1 A top view of an exemplary semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections for the one or more array regions. In some embodiments, such as Figure 1 As shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). It should be understood that... Figure 1The examples in the examples are for illustrative purposes only and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of various regions in the semiconductor device 100 can be applied. In some cases, the semiconductor device 100 may have two connection regions 104 and an array region 102 arranged along the X direction between the two connection regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connection region 104 arranged along the X direction between the two array regions 102.

[0043] Semiconductor device 100 includes alternating conductive layers and insulating layers (e.g., such as...). Figure 2B or Figure 2E The stack 106 shown comprises conductive layer 204a and insulating layer 204b. In some embodiments, a portion of the stack 106 may be located in the array region 102, and another portion of the stack 106 may be located in the connection region 104. In some embodiments, such as Figure 1 As shown, the stack 106 may further include a dielectric layer (e.g., stacked along the Z-direction on top of alternating conductive and insulating layers) on top of the stacked conductive and insulating layers. Figure 2B or Figure 2E The semiconductor device 100 also includes a stack 108 of alternating dielectric and isolation layers. In some embodiments, the stack 108 may be located in a connection region 104. The stack 106 is connected to the stack 108.

[0044] Semiconductor device 100 may include an array of channel structures extending through a stack 106 in array region 102. Figure 1 (Not shown in the diagram). Each channel structure can be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction) perpendicular to the first horizontal direction (e.g., the X direction). In some embodiments, such as Figure 1 As shown, the semiconductor device 100 may further include a conductive structure 110 extending through a dielectric layer. The conductive structure 110 is connected to a corresponding channel structure of a stack 106 in an array region 102 of the semiconductor device 100. In some embodiments, the semiconductor device 100 may include dummy channel structures 112 (also referred to as dummy memory strings) for process variable control during manufacturing and / or for additional mechanical support. The dummy channel structures 112 may extend through the stack 106 and / or stack 108. In some embodiments, the dummy channel structures 112 are located in a connection region 104. For example, some dummy channel structures 112 may be located in the stack 108. In some embodiments, the dummy channel structures 112 are located in the array region 102 (e.g., a region adjacent to the connection region 104). In some embodiments, the dummy channel structures 112 have a structure that is the same as or substantially similar to the channel structure.

[0045] like Figure 1 As shown, the semiconductor device 100 may include a contact structure 116 in the connection region 104. The contact structure 116 may be configured to connect a corresponding conductive layer in the conductive layer of the stack 106 to a control circuit. The semiconductor device 100 may include one or more gate line structures 118. Each gate line structure 118 may extend in the X direction. The gate line structure 118 may extend into both the array region 102 and the connection region 104. In some embodiments, the gate line structure 118 may divide the array region 102 into a plurality of memory blocks 124. In some embodiments, the gate line structure 118 may serve as a common source contact for the channel structure in the array region 102. In some embodiments ( Figure 1 (Not shown in the diagram), the gate line structure 118 may further include one or more segments extending along a second horizontal direction (e.g., the Y direction). In some embodiments, the gate line structure 118 may include multiple segments connected in an H-shape or a T-shape.

[0046] The semiconductor device 100 may include an isolation structure 120. The isolation structure 120 extends along the Z-direction through at least one conductive layer of the dielectric layer and the stack 106. In some embodiments, such as Figure 1 As shown, the isolation structure 120 extends along the X direction in the array region 102. In some embodiments, the isolation structure 120 is connected to the conductive structure 110 in the array region 102 along a second horizontal direction perpendicular to the X and Z directions (e.g., the Y direction). In some embodiments, the isolation structure 120 extends along the X direction in the array region 102. In some embodiments, the isolation structure 120 divides the memory blocks 124 of the array region 102 into one or more memory block finger regions 126.

[0047] Figure 2A It shows the Figure 1 A top view of an exemplary semiconductor device 200a, magnified in region A. (See attached image.) Figure 2A As shown, the semiconductor device 200a includes alternating conductive layers and insulating layers (e.g., as shown in the figure). Figure 2B The stack 202 shows conductive layer 204a and insulating layer 204b. Semiconductor device 200a may include a channel structure (e.g., [missing information]) extending through the stack 202 in a vertical direction (e.g., Z direction). Figure 2B An array of channel structures 208 in the stack. In some embodiments, the stack 202 may further include a dielectric layer (e.g., stacked along the Z direction on top of alternating conductive and insulating layers). Figure 2B (Dielectric layer 206 in the middle). In some embodiments, such as Figure 2AAs shown, semiconductor device 200a may include a conductive structure 210 extending through a dielectric layer. The conductive structure 210 is connected along the Z-direction to a corresponding channel structure 208 of the stack 202. In some embodiments, the conductive structure 210 contacts the corresponding channel structure 208 of the stack 202 along the Z-direction. In some embodiments, the conductive structure 210 may be connected to… Figure 1 The conductive structure 110 of the semiconductor device 100 is similar or identical.

[0048] like Figure 2A As shown, semiconductor device 200a may include an isolation structure 212 extending in a horizontal direction (e.g., the X direction) perpendicular to the Z direction. The isolation structure 212 extends through a portion of a corresponding conductive structure 210 in a second horizontal direction (e.g., the Y direction) perpendicular to both the Z and X directions. In some embodiments, the isolation structure 212 extends in the Z direction through a conductive layer 204a of the dielectric layer 206 and the stack 202. In some embodiments, the isolation structure 212 may be coupled with… Figure 1 The isolation structure 120 of the semiconductor device 100 is similar to or the same as that of the semiconductor device 200a. The semiconductor device 200a may include one or more gate line structures 214. Each gate line structure 214 may extend in the X direction and divide the stack 202 into one or more blocks 203. In some embodiments, the gate line structure 214 may be similar to... Figure 1 The gate line structure 118 of the semiconductor device 100 is similar or identical. In some embodiments, the isolation structure 212 extends along the X direction in the stack 202. In some embodiments, the isolation structure 212 divides the memory block 203 of the stack 202 into one or more memory block finger regions 205.

[0049] In some embodiments, the semiconductor device 200a may further include a coupling lead structure 216 connected along the Z-direction to the corresponding conductive structure 210. The coupling lead structure 216 extends in the Y-direction. In some embodiments, the conductive structure 210 in the dielectric layer 206 is coupled to the interconnect structure 218 via the coupling lead structure 216. In some embodiments, the interconnect structure 218 may be a bit line structure.

[0050] Figure 2B The edge of semiconductor device 200b is shown. Figure 2A A cross-sectional view of the semiconductor device 200a along cut line AA'. The semiconductor device 200b may be in... Figure 2A Semiconductor device 200a or Figure 1 The structure of the intermediate manufacturing process of the semiconductor device 100.

[0051] like Figure 2B As shown, semiconductor device 200b includes a semiconductor layer ( Figure 2B (Not shown in the diagram) A stack 202 of alternating conductive layers 204a and insulating layers 204b. The stack 202 is disposed on a substrate. The semiconductor layer can be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or single-crystal semiconductor. For example, the substrate can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the semiconductor layer can be removed from the semiconductor device 200b in subsequent processes of manufacturing the semiconductor device 200b.

[0052] The conductive layer 204a and the insulating layer 204b can alternate in a vertical direction (e.g., the Z direction) perpendicular to the second horizontal direction. The conductive layers 204a can be the same or different in thickness, for example, in the range of 10 nm to 500 nm, such as about 35 nm. The insulating layers 204b can also be the same or different in thickness, for example, in the range of 10 nm to 500 nm, such as about 25 nm. It should be noted that... Figure 2B The number of conductive layers 204a and insulating layers 204b shown is for illustrative purposes only, and the stack 202 may include any suitable number of conductive layers 204a and insulating layers 204b. Conductive layer 204a may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. In some embodiments, insulating layer 204b may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 204b may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0053] Semiconductor device 200b may include a channel structure 208 extending through a stack 202. In some embodiments, each channel structure 208 may include a first end 208-1 and a second end 208-2 along the Z direction. Each channel structure 208 may extend through the stack 202 along the Z direction. In some examples, the channel structure 208 may be cylindrical or pillar-shaped and may include a dielectric outer layer 209a, a barrier layer surrounded by the outer layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer 209c surrounded by the tunneling layer, a core filler layer 209d surrounded by the channel layer 209c, and a channel plug 209e formed above the core filler layer 209d and in contact with the channel layer 209c. In some embodiments, the channel layer 209c may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer (collectively referred to as memory film 209b) may include an ONO dielectric (silicon oxide-silicon oxynitride-silicon oxide).

[0054] like Figure 2B As shown, semiconductor device 200b may include a dielectric layer 206 stacked on top of stack 202 along the Z direction. In some embodiments, semiconductor device 200b may further include a conductive structure 210 extending through the dielectric layer 206 along the Z direction. The conductive structure 210 is connected to a corresponding channel structure 208 along the Z direction. In some embodiments, conductive structure 210 may include a first conductive structure 210a, wherein the first conductive structure 210a may include a first end 210a-1 and a second end 210a-2. In some embodiments, along the Y direction, the length of the first end 210a-1 of the first conductive structure 210a is greater than the length of the first end 208-1 of the channel structure 208. The first end 210a-1 of the first conductive structure 210a is farther from the stack 202 than the second end 210a-2 of the first conductive structure 210a. In some embodiments, the first end 208-1 of the channel structure 208 is closer to the dielectric layer 206 than the second end 208-2. In some embodiments, the first end 208-1 of the channel structure is a contact area located along the Y direction between the channel structure 208 and the corresponding conductive structure 210.

[0055] Semiconductor device 200b may include an isolation structure 212. The isolation structure 212 extends along the Z-direction through at least one conductive layer of dielectric layer 206 and stack 202. In some embodiments, dielectric layer 206 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, isolation structure 212 is located between two adjacent channel structures 208 along the Y-direction, and is spaced apart from channel structures 208 along the Y-direction. In some embodiments, isolation structure 212 may include a dielectric material similar to or the same as the dielectric material of dielectric layer 206. In some embodiments, isolation structure 212 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the dielectric material of isolation structure 212 may be similar to or the same as the dielectric material of isolation layer 204b. In some embodiments, conductive structure 210 may be used as a protective structure to protect channel structure 208 during subsequent processes in the fabrication of semiconductor device 200b. For example, the greater length of the first end 210a-1 of the conductive structure 210 compared to the end 208-1 of the channel structure 208 protects the channel structure 208 during the formation of the isolation structure 212.

[0056] In some embodiments, the semiconductor device 200b may include an insulating layer 220 stacked between the stack 202 and the dielectric layer 206. An isolation structure 212 extends through the insulating layer 220 in the Z direction. In some embodiments, in the Y direction, the length of a first end portion 210a-1 of the first conductive structure 210a is greater than the length of a second end portion 210a-2 of the first conductive structure 210a. The second end portion 210a-2 of the first conductive structure 210a is located on the opposite side of the first end portion 210a-1 in the Z direction, and the second end portion 210a-2 contacts the first end portion 208-1 of the corresponding channel structure 208 in the Z direction. In some embodiments, the insulating layer 220 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the insulating layer 220 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. In some embodiments, the dielectric material in the isolation structure 212 is different from the dielectric material of the insulating layer 220. For example, the isolation structure 212 may include silicon oxide, and the insulating layer 220 may include silicon nitride.

[0057] In some embodiments, the channel plug 209e of the channel structure 208 is connected to the corresponding conductive structure 210 along the Z direction, wherein the length of end 208-1 of the channel structure 208 is greater than the length of the second end 210a-2 of the first conductive structure 210a. In some embodiments, along the Y direction, the length of the first end 208-1 of the channel structure is the length of the contact area between the conductive structure 210 and the channel structure 208. In some embodiments, along the Y direction, the length of the channel plug 209e is greater than the length of the first end 208-1 of the channel structure 208. In some embodiments, the conductive structure 210 in the dielectric layer 206 is connected to the interconnect structure 218 via a coupling lead-out structure 216.

[0058] In some implementations, such as Figure 2B As shown, the conductive structure 210 may include a second conductive structure 210b in contact with the corresponding isolation structure 212. In some embodiments, the second conductive structure 210b may include a first end 210b-1 and a second end 210b-2, wherein, along the Z direction, the first end 210b-1 of the second conductive structure 210b is further away from the stack 202 than the second end 210b-2. The length of the first end 210a-1 of the first conductive structure 210a is greater than the length of the first end 210b-1 of the second conductive structure 210b. In some embodiments, the second conductive structure 210b may serve as a protective structure to protect the channel structure 208 during the formation of the isolation structure 212, wherein a portion of the conductive material on the first end 210b-1 of the second conductive structure 210b is etched during the fabrication of the isolation structure 212. In some embodiments, the isolation structure 212 contacts the second conductive structure 210b along the Y direction, wherein the isolation structure 212 is spaced apart from the first conductive structure 210a along the Y direction. In some embodiments, the coupling lead-out structure contacts the first ends 210a-1 and 210b-1 of the corresponding conductive structures 210a and 210b. Along the Y direction, the lengths of the first ends 210a-1 and 210b-1 of the corresponding conductive structures 210a and 210b are at least twice the length of the end 216-1 of the coupling lead-out structure 216, which is connected along the first direction to the corresponding conductive structure 210. For example, as... Figure 2AAs shown, adjacent conductive structures 210a and 210b are connected to two interconnect structures 218 via corresponding coupling leads 216, wherein the two interconnect structures 218 are spaced apart from each other along the X direction. The corresponding coupling leads 216 contact the corresponding conductive structures 210a and 210b and are spaced apart from each other along the X direction, requiring that the length of each conductive structure 210a or 210b is at least twice the length of the coupling lead 216, such that two adjacent coupling leads 216 can be separated from each other along the X direction. In some embodiments, an isolation structure 212 contacts at least one second conductive structure 210b, wherein the isolation structure 212 is spaced apart from the first conductive structure along the Y direction.

[0059] Figure 2C It shows the Figure 2A An enlarged top view of an exemplary semiconductor device 200c, showing region B of the semiconductor device 200a. The semiconductor device 200c may be in... Figure 2A Semiconductor device 200a or Figure 1 The structure of the intermediate manufacturing process of the semiconductor device 100.

[0060] like Figure 2C As shown, the isolation structure 212 is connected to the second conductive structure 210b along the Y direction, and the second conductive structure 210b partially surrounds the isolation structure 212. The coupling lead-out structure 216 is connected to the second conductive structure 210b along the Z direction. In some embodiments, along the X direction, the length of the first end 210b-1 of the second conductive structure 210b is at least twice the length of the end 216-1 of the coupling lead-out structure 216. In some embodiments, the second conductive structure 210b may serve as a protective structure during the formation of the isolation structure 212 to protect the channel structure 208. Figure 2C As shown, a portion of the conductive material on the first end 210b-1 of the second conductive structure 210b is etched during the fabrication of the isolation structure 212, wherein the second conductive structure 210b is connected to the isolation structure 212 along the Y direction.

[0061] Figure 2D It shows the Figure 1 A top view of an exemplary semiconductor device 200d, magnified in region A. In some embodiments, the semiconductor device 200d may be similar to... Figure 2A The semiconductor device 200a in the middle is different in that, such as Figure 2E As shown, with Figure 2A Compared to the isolation structure 212 of the semiconductor device 200a, the isolation structure 212 includes an outer layer 211 located in the dielectric layer 206. For example... Figure 2DAs shown, the isolation structure 212 extends along the X direction in the semiconductor device 200d and is connected along the Y direction to the corresponding conductive structure 210. The corresponding conductive structure 210 extends along the Y direction into a portion of the isolation structure 212 of the semiconductor device 200d. In some embodiments, the isolation structure 212 extends along the X direction in the stack 202. In some embodiments, the isolation structure 212 divides the memory blocks 203 of the stack 202 into one or more memory block finger regions 205.

[0062] Figure 2E It shows along Figure 2D A cross-sectional view of semiconductor device 200e with cut line CC' of semiconductor device 200d. Semiconductor device 200e may be in Figure 2D Semiconductor device 200d or Figure 1 The structure of the intermediate manufacturing process of the semiconductor device 100.

[0063] like Figure 2E As shown, the isolation structure 212 includes an outer layer 211 located within the dielectric layer 206. In some embodiments, the outer layer 211 includes a dielectric material different from the dielectric material of the dielectric layer 206. For example, the outer layer 211 may include SiN, and the dielectric layer 206 may include silicon oxide. In some embodiments, such as Figure 2E As shown, the conductive structure 210 includes a third conductive structure 210c partially surrounded along the Y direction by a corresponding isolation structure 212. The third conductive structure 210c is connected along the Y direction to an outer layer 211 of the isolation structure 212 located in the dielectric layer 206. In some embodiments, the outer layer 211 may serve as a protective layer during the formation of the isolation structure 212 to protect the channel structure 208 and the third conductive structure 210c.

[0064] Figure 2F It shows the Figure 2D An enlarged top view of an exemplary semiconductor device 200f, showing region D of the semiconductor device 200d. The semiconductor device 200f may be in... Figure 2D Semiconductor device 200d or Figure 1 The structure of the intermediate manufacturing process of the semiconductor device 100.

[0065] like Figure 2FAs shown, the third conductive structure 210c is partially surrounded by the isolation structure 212 along the horizontal direction (e.g., the X and Y directions). In some embodiments, the third conductive structure 210c contacts the outer layer 211 of the isolation structure 212 of the semiconductor device 200d along the Y direction. In some embodiments, the third conductive structure 210c may include a first end 210c-1 and a second end 210c-2, wherein, along the Z direction, the first end 210c-1 of the conductive structure 210c is further away from the stack 202 than the second end 210c-2 of the conductive structure 210c. In some embodiments, the outer layer 211 may serve as a protective layer during the formation of the isolation structure 212 to protect the channel structure 208 and the third conductive structure 210c. A coupling lead-out structure 216 is connected to the third conductive structure 210c along the Z direction. In some embodiments, along the X direction, the length of the first end 210c-1 of the third conductive structure 210c is at least twice the length of the end 216-1 of the coupling lead-out structure 216, and the end 216-1 of the coupling lead-out structure 216 is connected to the corresponding conductive structure 210 along the first direction. For example, as Figure 2C As shown, adjacent conductive structures 210a and 210c are connected to two interconnect structures 218 via corresponding coupling leads 216, wherein the two interconnect structures 218 are spaced apart from each other along the X direction. The corresponding coupling leads 216 are in contact with the corresponding conductive structures 210a and 210c and are spaced apart from each other along the X direction. This requires that the length of each conductive structure 210a or 210c is at least twice the length of the coupling lead 216, so that two adjacent coupling leads 216 can be separated from each other along the X direction.

[0066] Figures 3A-3F This illustrates the manufacture of semiconductor devices (e.g.) Figure 2A An exemplary process of the semiconductor device 200a shown. Figures 3A-3F Cross-sectional views of an exemplary semiconductor structure at various stages of the manufacturing process are shown.

[0067] like Figure 3A As shown, a semiconductor structure 300a is formed. The semiconductor structure 300a includes a stack 304 of conductive layers 306a and insulating layers 306b that alternate with each other in a vertical direction (e.g., the Z direction). The semiconductor structure 300a also includes a channel structure 308 extending through the stack 304 in the Z direction.

[0068] Figure 3BA semiconductor structure 300b is shown, which can be formed by depositing a dielectric material on top of a stack 304 to form a dielectric layer 310. The semiconductor structure 300b may include a conductive structure 312. The conductive structure 312 is formed by etching through a portion of the dielectric layer 310 in a vertical direction (e.g., the Z-direction) and filling that portion of the etched dielectric layer 310 with a conductive material. The conductive structure 312 is connected in the Z-direction to a corresponding channel structure 308 of the stack 304. In some embodiments, the conductive structure 312 contacts the corresponding channel structure 308 of the stack 304 in the Z-direction. In some embodiments, the semiconductor structure 300b may further include an insulating layer 314 stacked between the dielectric layer 310 and the stack 304, which can be formed by depositing an insulating material on the stack 304 in the Z-direction. In some embodiments, the insulating layer 314 may be used as an etch stop layer during the manufacturing process. For example, forming the conductive structure 312 includes: etching a portion of the dielectric layer along the Z direction (where the etching process is stopped by the insulating layer 314), deepening the etched portion by etching through the insulating layer 314, and filling the etched portion of the dielectric layer 310 with a conductive material.

[0069] Figure 3C A semiconductor structure 300c is shown. The semiconductor structure 300c can be formed by depositing a sacrificial material on top of a semiconductor structure 300b to form a sacrificial layer 316. The semiconductor structure 300c also includes one or more spaces 318. The one or more spaces 318 are formed by etching along the Z-direction through a portion of the sacrificial layer 316 and the dielectric layer 310. In some embodiments, the conductive structure 312 includes a first conductive structure 312a and a second conductive structure 312b. The one or more spaces 318 are connected to a corresponding second conductive structure 312b of the semiconductor structure 300c.

[0070] Figure 3DA semiconductor structure 300d is shown, which can be formed by etching along the Z-direction from the ends of one or more spaces 318 through a portion of at least one conductive layer 306a and a portion of a second conductive structure 312b in a dielectric layer of a stack 304. The conductive structure 312b serves as a protective structure during the etching of the stack 304, wherein a portion of the conductive material of the conductive structure 312b is etched during the manufacturing process to protect the channel structure 308. In some embodiments, the semiconductor structure 300d includes an insulating layer 314, and the semiconductor structure 300d is formed by etching along the Z-direction from the ends of one or more spaces 318 through the insulating layer 314, at least one conductive layer 306a of the stack 304, and a portion of the second conductive structure 312b in the dielectric layer. The ends of the one or more spaces 318 are closer to the stack 304 than the surface of the dielectric layer 310.

[0071] Figure 3E A semiconductor structure 300e is shown, which can be formed by removing the sacrificial layer 316 and depositing a dielectric material into one or more spaces 318 to form an isolation structure 320. In some embodiments, the dielectric material of the isolation structure 320 is similar to or the same as the dielectric material of the dielectric layer 310 and the dielectric material of the isolation layer 306b of the stack 304.

[0072] Figure 3F A semiconductor structure 300f is shown. The semiconductor structure 300f can be formed by depositing a conductive material on top of a conductive structure 312 to form a coupling lead structure 322, wherein the conductive structure 312 in the dielectric layer 310 is connected to the interconnect structure 324 through the coupling lead structure 322.

[0073] Figures 4A-4G This illustrates the manufacture of semiconductor devices (e.g.) Figure 2D An exemplary process of the semiconductor device 200d shown. Figures 4A-4G Cross-sectional views of an exemplary semiconductor structure at various stages of the manufacturing process are shown.

[0074] like Figure 4A As shown, a semiconductor structure 400a is formed. The semiconductor structure 400a includes a stack 404 of conductive layers 406a and insulating layers 406b alternating with each other in a vertical direction (e.g., the Z direction). The semiconductor structure 400a also includes a channel structure 408 extending through the stack 404 in the Z direction.

[0075] Figure 4BA semiconductor structure 400b is shown, which can be formed by depositing a dielectric material on top of a stack 404 to form a dielectric layer 410. The semiconductor structure 400b may include a conductive structure 412. The conductive structure 412 is formed by etching through a portion of the dielectric layer 410 in a vertical direction (e.g., the Z-direction) and filling the etched portion of the dielectric layer 410 with a conductive material. The conductive structure 412 is connected in the Z-direction to a corresponding channel structure 408 of the stack 404. In some embodiments, the conductive structure 412 contacts the corresponding channel structure 408 of the stack 404 in the Z-direction. In some embodiments, the semiconductor structure 400b may also include an insulating layer 414 stacked between the dielectric layer 410 and the stack 404, which can be formed by depositing an insulating material on the stack 404 in the Z-direction. In some embodiments, the insulating layer 414 may be used as an etch stop layer during the manufacturing process. For example, forming the conductive structure 412 includes: etching a portion of the dielectric layer along the Z direction (where the etching process is stopped by the insulating layer 414), deepening the etched portion by etching through the insulating layer 414, and filling the etched portion of the dielectric layer 310 with a conductive material.

[0076] Figure 4C A semiconductor structure 400c is shown, which can be formed by depositing a sacrificial material on top of a semiconductor structure 400b to form a sacrificial layer 416. The semiconductor structure 400c also includes one or more spaces 418. The one or more spaces 418 are formed by etching along the Z-direction through a portion of the sacrificial layer 416 and the dielectric layer 410. In some embodiments, the conductive structure 412 includes a first conductive structure 412a and a third conductive structure 412c. The one or more spaces 418 are connected to a corresponding second conductive structure 412b of the semiconductor structure 400c.

[0077] Figure 4D A semiconductor structure 400d is shown, which can be formed by removing the sacrificial layer 416 on the surface of the semiconductor structure 400c. The semiconductor structure 400d may include an outer layer 420. The outer layer 420 can be formed by depositing a dielectric material on the inner walls of one or more spaces 418 and on top of the dielectric layer 410. In some embodiments, the dielectric material of the outer layer 420 may be similar to or the same as the dielectric material of the insulating layer 414.

[0078] Figure 4EA semiconductor structure 400e is illustrated. The semiconductor structure 400e can be formed by etching along the Z-direction from the ends of one or more spaces 418 through an outer layer 420 of a stack 404, at least one conductive layer 406a, and removing a portion of the outer layer 420 located on the surface of a dielectric layer 410. The outer layer 420 serves as a protective layer during the etching of the stack 404 to protect the channel structure 408. The ends of one or more spaces 418 are connected to the stack 404. In some embodiments, the semiconductor structure 400e includes an insulating layer 414, and the semiconductor structure 400e can be formed by etching along the Z-direction from the ends of one or more spaces 418 through the insulating layer 414, the outer layer 420, and at least one conductive layer 406a of the stack 404. In some embodiments, a third conductive structure 412c is connected to the outer layer 420 of one or more spaces 418.

[0079] Figure 4F A semiconductor structure 400f is shown, which can be formed by depositing a dielectric material into one or more spaces 418 to form an isolation structure 422. In some embodiments, the dielectric material of the isolation structure 422 is similar to or the same as the dielectric material of the dielectric layer 410 of the stack 404 and the dielectric material of the isolation layer 406b.

[0080] Figure 4G A semiconductor structure 400g is shown. The semiconductor structure 400g can be formed by depositing a conductive material on top of a conductive structure 412 to form a coupling lead structure 424, wherein the conductive structure 412 in the dielectric layer 410 is connected to the interconnect structure 426 through the coupling lead structure 424.

[0081] Figure 5 A flowchart of an exemplary process 500 is shown. Process 500 can be performed to form a semiconductor device (e.g., Figure 2A The semiconductor device 200a shown or Figure 2D The semiconductor device shown is 200d. Process 500 can be referenced. Figures 3A-3F and Figures 4A-4G The process 500 may include forming... Figures 3A-3F and Figures 4A-4G The process of manufacturing a semiconductor structure in process 500 includes one or more steps. It should be understood that the operations shown in process 500 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 5 The different execution sequences are shown.

[0082] At operation 502, conductive layers (e.g., the Z direction) are formed that alternate with each other along a first direction (e.g., the Z direction). Figure 3A The conductive layer 306a or Figure 4A The conductive layer 406a) and the insulating layer (e.g., Figure 3A In the isolation layer 306b or Figure 4A The stack of isolation layer 406b in the middle (e.g., Figure 3A Stack body 304 or Figure 4A The stack body 404 in the stack body includes a channel structure extending through the stack body in a first direction (e.g., Figure 3A Channel structure 308 or Figure 4A The channel structure 408 in the channel structure includes a first end and a second end disposed opposite to each other along a first direction.

[0083] At operation 504, a dielectric layer is formed on one side of the stack along the first direction and includes a first dielectric material (e.g., Figure 3B Dielectric layer 310 or Figure 4B (Dielectric layer 410 in the middle).

[0084] At operation 506, a conductive structure extending through the semiconductor layer is formed (e.g., ...). Figure 3B Conductive structure 312 or Figure 4B The conductive structure 412 is connected to a corresponding channel structure. Each conductive structure includes a first end and a second end disposed opposite each other along a first direction, and wherein, along a second direction perpendicular to the first direction (e.g., the Y direction), the first conductive structure (e.g., ...) is connected to a corresponding channel structure. Figure 3C The first conductive structure 312a or Figure 4C The first end of the first conductive structure 412a in the first part (e.g., Figure 2B or Figure 2D The length of 210a-1) is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther away from the stack than the second end, and the first end of the channel structure is closer to the dielectric layer than the second end.

[0085] At operation 508, an isolation structure is formed extending along a first direction through at least one conductive layer of the dielectric layer and the stack (e.g., Figure 3E The isolation structure 320 or Figure 4F (Isolation structure 422 in the middle).

[0086] In some implementations, forming the isolation structure includes etching through the dielectric layer to form a first space (e.g., Figure 3COne or more spaces 318 in the stack), wherein the first space is in contact with a corresponding conductive structure; the first space is deepened by etching at least one conductive layer through the stack along a first direction from the end of the first space and etching a portion of the corresponding conductive structure to form a second conductive structure (e.g., Figure 3D The second conductive structure 312b), the end of the first space is connected to the stack; and a dielectric material is filled into the first space to form an isolation structure, wherein the isolation structure is located between two adjacent channel structures along a second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

[0087] In some implementations, an insulating layer is formed by depositing a dielectric material on the ends of the stack before forming the dielectric layer (e.g., Figure 3B Insulating layer 314 or Figure 4B The insulating layer 414 is stacked between the stack body and the insulating layer, and the conductive structure extends through the insulating layer and connects to the corresponding channel structure.

[0088] In some implementations, forming the isolation structure includes etching through the dielectric layer to form a second space (e.g., Figure 3C One or more spaces 318), wherein the second space is associated with a corresponding conductive structure (e.g., Figure 3D The second conductive structure 312b) is in contact; the end of the second space is etched through the insulating layer along the first direction, the end of the second space being connected to the insulating layer; the second space is deepened by etching through at least one conductive layer of the stack along the first direction from the end of the second space and etching a portion of the corresponding conductive structure to form the second conductive structure; and a dielectric material is filled into the second space to form an isolation structure, wherein the isolation structure is located between two adjacent channel structures along the second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

[0089] In some embodiments, the second conductive structure includes a first end and a second end along a first direction, wherein, along the second direction, the length of the first end of the first conductive structure is greater than the length of the first end of the second conductive structure (e.g., Figure 2B The length of the end 210b-1 in the middle, the first end of the second conductive structure is farther away from the stack than the second end.

[0090] In some embodiments, the isolation structure further includes an outer layer located within the dielectric layer (e.g., Figure 4D The outer layer 420), and wherein forming the isolation structure includes: etching through the dielectric layer to form a third space (e.g., Figure 4DOne or more spaces 418 in the third space, wherein the third space is in contact with a corresponding conductive structure; an insulating layer is deposited on the inner wall of the third space; the third space is deepened by etching at least one conductive layer through the insulating layer and the stack body from the end of the third space along a first direction, the end of the third space being connected to the stack body; and a dielectric material is filled into the third space to form an isolation structure, wherein the isolation structure is located between two adjacent channel structures along a second direction and is spaced apart from the channel structures along the second direction.

[0091] In some embodiments, the conductive structure further includes a third conductive structure partially surrounded by the insulating structure (e.g., Figure 4B The third conductive structure 412c is in contact with the outer layer of the isolation structure located in the dielectric layer along the second direction. In some embodiments, the operation further includes forming a coupling lead-out structure (e.g., Figure 3F The coupling lead-out structure 322 and Figure 4G The coupling lead-out structure 424 in the dielectric layer is connected to the interconnect structure (e.g., ...) via the coupling lead-out structure. Figure 3F Interconnection structure 324 and Figure 4G Interconnection structure 426 in the middle.

[0092] In some embodiments, the coupling lead-out structure contacts a first end of the conductive structure, and wherein, along a second direction, the length of the first end of the second conductive structure is at least twice the length of the coupling lead-out structure.

[0093] Figure 6 A block diagram of an exemplary system 600 is shown. According to one or more embodiments of this disclosure, system 600 may have one or more semiconductor devices (e.g., memory devices). System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage devices. Figure 6 As shown, system 600 may include a host device 608 and a memory system 602 having one or more memory devices 604 and a memory controller 606. The host device 608 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 608 may be configured to send data to or receive data from one or more memory devices 604.

[0094] Memory device 604 can be any memory device disclosed in this disclosure, such as Figure 1and Figures 2A-2F The memory device shown is an example of a NAND flash memory. A memory controller 606 (also referred to as controller circuitry) is coupled to the memory device 604 and the host device 608. According to embodiments of this disclosure, the memory device 604 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 606 may be coupled to the memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the memory device 604 and communicate with the host device 608.

[0095] In some embodiments, the memory controller 606 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 606 is designed / configured to operate in high duty cycle environments in SSDs or in embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 606 may be configured to control the operation of the memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 may also be configured to manage various functions regarding data stored or to be stored in the memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 604. The memory controller 606 may also perform any other appropriate function, such as formatting the memory device 604.

[0096] The memory controller 606 can communicate with external devices (e.g., host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0097] The memory controller 606 and one or more memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 6 In one example shown, the memory controller 606 and a single memory device 604 can be integrated into the memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMC), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0098] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0099] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0100] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0101] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0102] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0103] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0104] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0105] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0106] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0107] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0108] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0109] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0110] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0111] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0112] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0113] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A stack of conductive and insulating layers alternating with each other along a first direction; A channel structure extending through the stack, wherein the channel structure includes a first end and a second end disposed opposite to each other along the first direction; A dielectric layer, located on one side of the stack along the first direction, and comprising a first dielectric material; A first conductive structure extends through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, wherein the first conductive structure includes a first end and a second end disposed opposite to each other along the first direction, and Wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther away from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and An isolation structure extending along the first direction through at least one conductive layer of the dielectric layer and the stack.

2. The semiconductor device according to claim 1, wherein, The isolation structure is located between two adjacent channel structures along the second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

3. The semiconductor device according to claim 1 or 2, wherein, The semiconductor device further includes an insulating layer located between the stack and the dielectric layer, wherein the isolation structure extends through the insulating layer along the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein, Along the second direction, the length of the first end of the first conductive structure is greater than the length of the second end of the first conductive structure, and wherein the second end of the first conductive structure contacts the first end of the channel structure along the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The channel structure further includes a channel plug that contacts a second end of the first conductive structure along the first direction, and wherein, along the second direction, the length of the first end of the channel structure is greater than the length of the second end of the first conductive structure.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The semiconductor device includes a second conductive structure having a first end and a second end disposed opposite to each other along the first direction, wherein the second conductive structure is connected to a corresponding channel structure, and wherein, along the second direction, the length of the first end of the first conductive structure is greater than the length of the first end of the second conductive structure, and the first end of the second conductive structure is farther away from the stack than the second end of the second conductive structure.

7. The semiconductor device according to any one of claims 1 to 5, wherein, The isolation structure includes an outer layer located within the dielectric layer, wherein the outer layer includes a second dielectric material, and wherein the first dielectric material of the dielectric layer is different from the second dielectric material of the outer layer of the isolation structure.

8. The semiconductor device according to any one of claims 1 to 5 or claim 7, wherein, The semiconductor device includes a third conductive structure partially surrounded by the isolation structure, the third conductive structure being connected to a corresponding channel structure, and The third conductive structure is in contact with the outer layer of the isolation structure located in the dielectric layer along the second direction.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The first conductive structure and the second conductive structure in the dielectric layer are connected to the interconnect structure through a coupling lead-out structure.

10. The semiconductor device according to any one of claims 1 to 9, wherein, Along the second direction, the length of the first end of the second conductive structure is at least twice the length of the coupling lead-out structure.

11. A method for forming a semiconductor device, wherein, The method includes: A stack of conductive and insulating layers alternating with each other along a first direction is formed, wherein the stack includes a channel structure extending through the stack along the first direction, and wherein the channel structure includes a first end and a second end disposed opposite to each other along the first direction; A dielectric layer is formed, the dielectric layer being located on one side of the stack along the first direction and comprising a first dielectric material; A first conductive structure is formed extending through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, and wherein the first conductive structure includes a first end and a second end disposed opposite to each other along the first direction. Wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther away from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and An isolation structure is formed, which extends along the first direction through at least one conductive layer of the dielectric layer and the stack.

12. The method according to claim 11, wherein, Forming the isolation structure includes: Etching through the dielectric layer to form a first space, wherein the first space is in contact with a corresponding conductive structure; The first space is deepened by etching at least one conductive layer through the stack along the first direction from the end of the first space to form a second conductive structure, the end of the first space being connected to the stack; and A dielectric material is filled into the first space to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along the second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

13. The method according to claim 11 or 12, further comprising: Prior to forming the dielectric layer, an insulating layer is formed by depositing a dielectric material on the ends of the stack, wherein the insulating layer is stacked between the stack and the insulating layer. The conductive structure extends through the insulating layer and connects to the corresponding channel structure.

14. The method according to any one of claims 11 to 13, wherein, The isolation structure also includes: Etching through the dielectric layer to form a second space, wherein the second space is in contact with a corresponding conductive structure; Etching is performed along the first direction at the end of the second space through the insulating layer, the end of the second space being connected to the insulating layer; The second space is deepened by etching at least one conductive layer through the stack along the first direction from the end of the second space to form a second conductive structure; and A dielectric material is filled into the second space to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along the second direction, and wherein the isolation structure is spaced apart from the channel structures along the second direction.

15. The method according to any one of claims 11 to 14, wherein, The second conductive structure includes a first end and a second end disposed opposite to each other along the first direction, wherein, along the second direction, the length of the first end of the first conductive structure is greater than the length of the first end of the second conductive structure, and the first end of the second conductive structure is further away from the stack than the second end.

16. The method according to any one of claims 11 to 13, wherein, The isolation structure further includes an outer layer located in the dielectric layer, and wherein forming the isolation structure includes: Etching through the dielectric layer to form a third space, wherein the third space is in contact with a corresponding conductive structure; An insulating layer is deposited on the inner wall of the third space; The third space is deepened by etching at least one conductive layer through the insulating layer and the stack along the first direction from its end, the end of the third space being connected to the stack; and A dielectric material is filled into the third space to form the isolation structure, wherein the isolation structure is located between two adjacent channel structures along the second direction and is spaced apart from the channel structures along the second direction.

17. The method according to any one of claims 11 to 13 or claim 16, wherein, The semiconductor device further includes a third conductive structure partially surrounded by the isolation structure, and The third conductive structure is in contact with the outer layer of the isolation structure located in the dielectric layer along the second direction.

18. The method according to any one of claims 11 to 17, further comprising: A coupling lead-out structure is formed, wherein the first conductive structure and the second conductive structure in the dielectric layer are connected to the interconnect structure through the coupling lead-out structure.

19. The method according to any one of claims 11 to 18, wherein, Along the second direction, the length of the first end of the second conductive structure is at least twice the length of the coupling lead-out structure.

20. A memory system, comprising: Memory devices; as well as A memory controller, coupled to and configured to control the memory device. The memory device includes: A stack of conductive and insulating layers alternating with each other along a first direction; A channel structure extending through the stack, wherein the channel structure includes a first end and a second end disposed opposite to each other along the first direction; A dielectric layer, the dielectric layer being located on one side of the stack along the first direction, and comprising a first dielectric material; A first conductive structure extends through the dielectric layer, wherein the first conductive structure is connected to a corresponding channel structure, wherein the first conductive structure includes a first end and a second end disposed opposite to each other along the first direction, and Wherein, along a second direction perpendicular to the first direction, the length of the first end of the first conductive structure is greater than the length of the first end of the channel structure, the first end of the first conductive structure is farther away from the stack than the second end of the first conductive structure, and the first end of the channel structure is closer to the dielectric layer than the second end of the channel structure; and An isolation structure extending along the first direction through at least one conductive layer of the dielectric layer and the stack.

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