Method of manufacturing a semiconductor structure
By using a protective layer to cover the sidewalls of the dummy gate structure during the etching process and etching the dummy gate and fins in stages, the problem of damage to the spacer layer and electrode area caused by overlay errors is solved, thereby improving the performance and reliability of the 3D transistor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
- Filing Date
- 2024-12-05
- Publication Date
- 2026-06-05
AI Technical Summary
During the manufacturing process of 3D transistors, overlay errors can lead to inaccurate etching of the dummy gate structure, causing damage to the spacer layer and electrode region, thus affecting transistor performance.
By using a protective layer to cover the sidewalls of the dummy gate structure during the etching process, the risk of etching damage to the electrode area is reduced. The dummy gate and fins are etched in stages, reducing the overall etching time and improving etching accuracy.
It effectively protects the electrode area, improves the performance and reliability of the 3D transistor, and reduces the risk of etching damage to the fin material.
Smart Images
Figure CN122161116A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for manufacturing a semiconductor structure. Background Technology
[0002] As integrated circuits have shrunk, the performance of traditional planar transistors has degraded due to their smaller size, leading to the development of three-dimensional transistors with a three-gate structure.
[0003] In related technologies, during the manufacturing process of integrated circuits based on 3D transistors, adjacent 3D transistors are separated from each other using a single diffused interrupt (SDB) process. Summary of the Invention
[0004] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate structure, the substrate structure including: a substrate; a fin located on the substrate; isolation regions located on both sides of the fin, the upper surface of the isolation regions being lower than the upper surface of the fin; a plurality of dummy gate structures spanning the fin and located on the isolation regions, the plurality of dummy gate structures including a first dummy gate structure, a second dummy gate structure located on one side of the first dummy gate structure, and a third dummy gate structure located on the other side of the first dummy gate structure, the first dummy gate structure including a first dummy gate and spacer layers located on both sides of the first dummy gate; an electrode region located on the fin and an insulating portion located on the electrode region, the electrode region and the insulating portion being located between each of the second dummy gate structure and the third dummy gate structure and the first dummy gate structure; and a mask layer on the plurality of dummy gate structures and the insulating portion, the mask layer having a first opening, the first opening at least exposing a portion of the upper surface of the first dummy gate. The manufacturing method further includes: using the mask layer as a mask, performing a first etching to remove the first dummy gate and a portion of the fin located below the first dummy gate to form a second opening, the second opening including a first sub-opening located in the fin and a second sub-opening communicating with the first sub-opening; forming a protective layer covering at least one sidewall of the first sub-opening; and using the mask layer as a mask, performing a second etching to etch the fin so that the second opening extends downward.
[0005] According to some embodiments of this disclosure, the protective layer covers the sidewalls on both sides of the first sub-opening.
[0006] According to some embodiments of this disclosure, the protective layer also covers at least one sidewall of the second sub-opening.
[0007] According to some embodiments of this disclosure, the first dummy gate structure further includes a dummy gate dielectric layer located between the first dummy gate and the fin, the dummy gate dielectric layer including a first dummy gate dielectric layer located on the upper surface of the fin and a second dummy gate dielectric layer located on the side surface of the fin. Performing the first etching includes: performing a first sub-etch to remove a portion of the first dummy gate to expose the first dummy gate dielectric layer; performing a second sub-etch to remove the first dummy gate dielectric layer; and performing a third sub-etch to remove the remaining portion of the first dummy gate and a portion of the fin located below the first dummy gate.
[0008] According to some embodiments of this disclosure, after the first sub-etching is performed, the upper surface of the remaining portion of the first dummy gate is not lower than the upper surface of the fin.
[0009] According to some embodiments of this disclosure, the manufacturing method further includes: performing a wet cleaning process after performing the third sub-etching to remove at least a portion of the second dummy gate dielectric layer.
[0010] According to some embodiments of this disclosure, the first etching removes the portion of the fin located above the upper surface of the isolation region.
[0011] According to some embodiments of this disclosure, the protective layer includes a dielectric layer, the material of which includes at least one of oxides and nitrides.
[0012] According to some embodiments of this disclosure, in the extending direction of the fin, the size of the first opening is larger than the size of the first dummy gate.
[0013] According to some embodiments of this disclosure, the manufacturing method further includes: after performing the second etching, filling the second opening with an insulating material to form an isolation portion. Attached Figure Description
[0014] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.
[0015] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:
[0016] Figure 1 and Figure 2 This is a process diagram of performing a single diffusion interruption process in related technologies.
[0017] Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0018] Figure 4AThis is a front view of the process of providing a substrate structure according to some embodiments of the present disclosure. Figure 4B It is along Figure 4A The cross-sectional view taken from a-a' in the figure.
[0019] Figures 5A-9B This is a schematic diagram of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0020] Figure 10 This is a schematic flowchart illustrating the execution of a first etching according to some embodiments of the present disclosure.
[0021] Figures 11A-12B This is a schematic diagram of the various stages in the execution of the first etching process according to some embodiments of the present disclosure.
[0022] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation
[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values set forth in these embodiments should be interpreted as exemplary only and not as limiting.
[0024] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.
[0025] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.
[0026] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.
[0027] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0028] In related technologies, during single-diffusion interruption processes, such as Figure 1 As shown, an opening T is formed in the mask layer 400 to expose some of the underlying dummy gates 301; as Figure 2 As shown, removing these dummy gates 301 and a portion of the fins 200 below the dummy gates 301 can form a space for isolating the three-dimensional transistors on both sides.
[0029] The inventors noticed that during the process of forming patterns by photolithography, due to the influence of various factors such as prism thermal effect, wafer thermal effect, alignment offset, thin film stress and surface roughness, there will be unavoidable overlay errors, that is, the position of the actual formed pattern deviates from the ideal position.
[0030] Due to overlay errors, the opening T used to expose the dummy gate 301 (e.g.) Figure 1 The position of the opening T on the left side may be slightly offset, causing the opening T to also expose the spacer layer 302 on one side of the dummy gate 301. During the etching of the mask layer 400 to form the opening for exposing the dummy gate 301, such as... Figure 1 As indicated by the circled mark, a portion of the top of the spacer layer 302 on the sidewall of the pseudo gate 301 will also be etched.
[0031] like Figure 2 As shown, during the subsequent removal of the dummy gate 301 exposed by the opening T and a portion of the fin 200 below it, the spacer layer 302 on the sidewall of the dummy gate 301 will be further damaged or even completely removed due to the influence of the etching gas, ultimately as shown in the image. Figure 2 As indicated by the circle in the middle, this can even lead to the etching of the material of the fin 200 below the spacer layer 302, as well as damage to the electrode region 220 (e.g., source or drain region) on the side of the spacer layer 302, affecting the performance of the final formed 3D transistor.
[0032] Furthermore, even if the spacer layer 302 on the sidewall of the dummy gate 301 can protect the material of the fin 200 below the spacer layer 302 from being etched in the vertical direction, the material of the fin 200 below the spacer layer 302 may still be etched in other directions during the etching of the fin 200, thereby damaging the electrode region 220.
[0033] In view of this, the present disclosure proposes the following technical solution to reduce the risk of damage to the side electrode region at the interruption location during the single diffusion interruption process, thereby improving the performance of the 3D transistor.
[0034] Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0035] Figure 4A This is a front view of the process of providing a substrate structure according to some embodiments of the present disclosure. Figure 4B It is along Figure 4A The cross-sectional view taken from a-a' in the figure.
[0036] Figures 5A-9B This is a schematic diagram of various stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 5A , 6A 7A, 8A, and 9A are the front views of the structure obtained at each stage of the manufacturing process. Figure 5B , 6B 7B, 8B and 9B are respectively along Figure 5A , 6A The cross-sectional view of a-a' in 7A and 8A.
[0037] Next, combine Figures 3-9B The following describes a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0038] First, refer to Figure 3 In step S10, a substrate structure 10 is provided.
[0039] like Figure 5A and 5B As shown, the substrate structure 10 includes a substrate 100, a fin 200, an isolation region 210, multiple dummy gate structures 300, an electrode region 220, an insulating portion 310, and a mask layer 400.
[0040] The substrate 100 may be a semiconductor substrate. The material of the substrate 100 may be silicon, germanium, silicon germanide (e.g., silicon germanide), etc.
[0041] Fins 200 are located on substrate 100. In some embodiments, the material of fins 200 may be the same as that of substrate 100, for example, by etching an initial substrate to form substrate 100 and fins 200. In other embodiments, the material of fins 200 may be different from that of substrate 100. Fins 200 may be a single fin 200 or multiple fins 200 arranged side by side, for example, as... Figure 5B As shown, the substrate structure 10 includes four fins 200 arranged side by side.
[0042] The isolation zone 210 is located on both sides of the fin 200, and, as Figure 5B As shown, the upper surface of the isolation region 210 is lower than the upper surface of the fin 200. The material of the isolation region 210 may include oxides, such as oxides of silicon (e.g., silicon oxide).
[0043] Multiple pseudo-gate structures 300 span the fin 200 and are located on the isolation region 210. For example... Figure 5A As shown, the plurality of dummy gate structures 300 include a first dummy gate structure 300a (identified by the dashed box), a second dummy gate structure 300b located on one side of the first dummy gate structure 300a, and a third dummy gate structure 300c located on the other side of the first dummy gate structure 300a. The first dummy gate structure 300a includes a first dummy gate 301a and spacer layers 302 located on both sides of the first dummy gate 301a. It should be understood that each dummy gate structure 300 includes a dummy gate 301. For distinction, the dummy gate 301 of the first dummy gate structure 300a is referred to as the first dummy gate 301a. The material of the dummy gate 301 may include polysilicon.
[0044] In some embodiments, such as Figure 5A and 5B As shown, the first pseudo-gate structure 300a also includes a pseudo-gate dielectric layer 303 located between the first pseudo-gate 301a and the fin 200. The pseudo-gate dielectric layer 303 includes a first pseudo-gate dielectric layer 303a located on the upper surface of the fin 200 and a second pseudo-gate dielectric layer 303b located on the side surface of the fin 200.
[0045] In some embodiments, such as Figure 5A As shown, other pseudo-gate structures 300 besides the first pseudo-gate structure 300a may also include a pseudo-gate 301, spacer layers 302 located on both sides of the pseudo-gate 301, and a pseudo-gate dielectric layer 303 located between the pseudo-gate 301 and the fin 200. The pseudo-gate dielectric layer 303 of the other pseudo-gate structures 300 may also include a first pseudo-gate dielectric layer 303a located on the upper surface of the fin 200 and a second pseudo-gate dielectric layer 303b located on the side surface of the fin 200. Figure 5A In addition to the first pseudo-gate structure 300a, the second pseudo-gate structure 300b and the third pseudo-gate structure 300c, another pseudo-gate structure 300, namely the fourth pseudo-gate structure 300d, is also shown.
[0046] In some embodiments, such as Figure 5B As shown, the substrate structure 10 also includes a partition 304 that extends downward from the upper surface of the first dummy gate 301a into the isolation region 210. The partition 304 can be made of a dielectric material, such as silicon nitride. The partition 304 is used to isolate the dummy gate 301. For simplicity, in the following... Figure 6A , 7A Partition 304 is not shown in the front views shown in 8A, 11A and 12A.
[0047] The spacer layer 302 can be a single layer or multiple layers. The material of the spacer layer 302 can include at least one of silicon nitride, silicon carbonitride, and silicon oxynitride.
[0048] Electrode region 220 is located on fin 200, and insulating portion 310 is above electrode region 220. Electrode region 220 and insulating portion 310 are located between each of the second pseudo-gate structure 300b and the third pseudo-gate structure 300c and the first pseudo-gate structure 300a, that is, electrode region 220 and insulating portion 310 exist between the second pseudo-gate structure 300b and the first pseudo-gate structure 300a, and electrode region 220 and insulating portion 310 also exist between the third pseudo-gate structure 300c and the first pseudo-gate structure 300a. In some embodiments, such as Figure 5A As shown, electrode region 220 and insulating portion 310 are located on both sides of each pseudo-gate structure 300.
[0049] Electrode region 220 is the source or drain region of a three-dimensional transistor. The material of electrode region 220 can be a semiconductor material (e.g., formed by epitaxial processes), such as silicon germanide (e.g., silicon germanide), silicon phosphide (e.g., silicon phosphide), etc.
[0050] The location of the first dummy gate structure 300a serves as a breakpoint in the single-diffusion interruption process. Subsequently, an isolation portion 320 formed at this location and on the fin 200 below it is used to isolate the second dummy gate structure 300b and the third dummy gate structure 300c. Both the second dummy gate structure 300b and the third dummy gate structure 300c can be replaced with gate structures in subsequent processes, and the gate structures, together with the electrode regions 220 on either side, form a three-dimensional transistor.
[0051] The material of the insulating part 310 may include oxides, such as silicon oxide.
[0052] The mask layer 400 is located above the plurality of dummy gate structures 300 and the insulating portion 310, and the mask layer 400 has a first opening T1. Here, the first opening T1 exposes at least a portion of the upper surface of the first dummy gate 301a. The material of the mask layer 400 can be a dielectric material, such as silicon nitride.
[0053] For example, due to overlay errors, the position of the first opening T1 may shift, such as... Figure 5A As shown, the first opening T1 exposes the left portion of the first dummy gate 301a, while a portion of the right side of the first dummy gate 301a is not exposed. The first opening T1 also exposes the spacer layer 302 on the left side of the first dummy gate 301a. Alternatively, the first opening T1 may expose the entire upper surface of the first dummy gate 301a. The first opening T1 is used to expose the first dummy gate 301a for removal in a single diffusion interruption process.
[0054] In some embodiments, the size of the first opening T1 is larger than the size of the first dummy gate 301a in the extending direction of the fin 200. Thus, even if there is an overlay error, the first opening T1 exposes the entire upper surface of the first dummy gate 301a as much as possible, which is beneficial for subsequent processes to remove the first dummy gate 301a.
[0055] like Figure 5A As shown, the mask layer 400 also has another opening T, which exposes the entire dummy gate 301 of the fourth dummy gate structure 300d. It is understood that the location of the fourth dummy gate structure 300d also serves as an exemplary isolation location in a single diffusion interruption process. The following description will focus solely on the semiconductor structure manufacturing method proposed in this disclosure based on the first dummy gate structure 300a. For variations in the fourth dummy gate structure 300d and the structure surrounding it, please refer to the first dummy gate structure 300a.
[0056] In some embodiments, the substrate structure 10 may be provided in the following manner.
[0057] First, an initial structure (not shown) is provided, which does not have a mask layer 400 compared to the substrate structure 10.
[0058] Subsequently, a dielectric material is deposited on the initial structure to form an initial mask layer 400'.
[0059] Subsequently, a photolithographic layer structure 500 is formed above the initial mask layer 400'. For example... Figure 4A and 4B As shown, the photolithography layer structure 500 can be sequentially included from bottom to top as an oxide layer 501, a spin-coated carbon (SOC) layer 502, a silicon anti-reflection layer 503, and a photoresist 504, wherein the photoresist 504 has a first initial opening T1' and an initial opening T' formed by exposure and etching.
[0060] Subsequently, the silicon antireflective layer 503, the spin-coated carbon layer 502, and the oxide layer 501 are etched in sequence to transfer the first initial opening T1' and the initial opening T' to the initial mask layer 400', so as to form the first opening T1 and the other opening T respectively, thereby turning the initial mask layer 400' into the mask layer 400.
[0061] Subsequently, the etched photolithographic layer structure 500 is removed to obtain Figure 5A and Figure 5B The substrate structure 10 shown is shown.
[0062] The substrate structure 10 obtained through the above method may cause some damage to the underlying spacer layer 302 during the formation of the first opening T1' due to the slight deviation of the first initial opening T1' from the ideal position. Figure 5A As indicated by the circle in the middle.
[0063] Next, refer to Figure 3 In step S20, using the mask layer 400 as a mask, a first etching is performed to remove the first dummy gate 301a and a portion of the fin 200 located below the first dummy gate 301a, in order to form a second opening T2.
[0064] like Figure 6A As shown, the second opening T2 includes a first sub-opening ST1 located in the fin 200 and a second sub-opening ST2 communicating with the first sub-opening ST1. It should be understood that the space occupied by the second sub-opening ST2 includes at least the space formed by the removal of the first dummy gate 301a. In some cases, the space occupied by the second sub-opening ST2 also includes the space formed after the spacer layers 302 on both sides of the first dummy gate 301a are damaged.
[0065] Subsequently, reference Figure 3 In step S30, a protective layer PL is formed. For example... Figure 7A As shown, the protective layer PL covers at least one sidewall of the first sub-opening ST1.
[0066] like Figure 7A As shown, the sidewalls on both sides of the first sub-opening ST1 are close to an electrode region 220. The material of the fins 200 between the sidewalls on both sides of the first sub-opening ST1 and the nearby electrode region 220 is less. During the subsequent etching process of the fins 200, the fins 200 will also be etched away in other directions deviating from the vertical direction, thereby exposing the nearby electrode region 220 and damaging the electrode region 220.
[0067] The protective layer PL is used to protect at least one sidewall of the first sub-opening ST1 covered, such that the material of the fin 200 between the sidewall and the nearby electrode region 220 is etched less in the remaining directions away from the vertical direction, thereby reducing the risk of damage to the electrode region 220.
[0068] Subsequently, reference Figure 3 In step S40, using the mask layer 400 as a mask, a second etching is performed to etch the fin 200. For example... Figure 8A and Figure 8B As shown, the second etching causes the second opening T2 to extend downwards, i.e., the depth increases.
[0069] As one implementation method, anisotropic etching can be used to etch the fin 200 so that the etching rate of the fin 200 in the vertical direction is greater than the etching rate in the horizontal direction.
[0070] In some embodiments, such as Figure 8A and Figure 8B As shown, the second etching can cause the second opening T2 to extend downward into the substrate 100.
[0071] Through the aforementioned steps S10-S40, a second opening T2 is formed, which is used to isolate the second pseudo-gate structure 300b and the third pseudo-gate structure 300c. Since a protective layer PL is formed during the etching of the fin 200, less material of the fin 200 between at least one sidewall covered by the protective layer PL and the nearby electrode region 220 is etched during subsequent further etching of the fin 200. This reduces the risk of damage to at least one side of the electrode region 220 of the second opening T2, thereby improving the performance of the finally formed 3D transistor.
[0072] In some embodiments, such as Figure 7A As shown, the protective layer PL covers the sidewalls on both sides of the first sub-opening ST1. In this way, less material is etched between the sidewalls covered by the protective layer PL and the fins 200 between the nearby electrode regions 220, thereby reducing the risk of damage to the electrode regions 220 on both sides of the second opening T2 and further improving the performance of the finally formed 3D transistor.
[0073] In some embodiments, the protective layer PL also covers at least one sidewall of the second sub-opening ST2. For example, the protective layer PL also covers one sidewall of the second sub-opening ST2; or, for example, as... Figure 7A As shown, the protective layer PL also covers the sidewalls on both sides of the second sub-opening ST2. This allows the spacer layer 302 covered by the protective layer PL to be etched less in other directions deviating from the vertical, further reducing the risk of damage to the electrode region 220 and thus further improving the performance of the final formed 3D transistor.
[0074] In some embodiments, the protective layer PL includes a dielectric layer. As some implementations, the material of the dielectric layer may include at least one of oxides and nitrides. The oxide may be an oxide of silicon, such as silicon oxide; the nitride may be a nitride of silicon, such as silicon nitride. Thus, the material of the fin 200 between the sidewalls covered by the protective layer PL and the nearby electrode region 220 can be effectively protected from etching.
[0075] As some implementation methods, it is possible to Figure 6A and Figure 6B Based on the structure shown, a dielectric material is deposited to form a protective layer PL. At this point, as... Figure 7A As shown, the protective layer PL can cover the sidewalls of both sides of the second sub-opening ST2 and the sidewalls of both sides of the first sub-opening ST1. In some cases, the protective layer PL can also cover the bottom of the first sub-opening ST1. In other cases, for example, when the size of the first sub-opening ST1 is small, such as... Figure 7A As shown, the protective layer PL will not cover the bottom of the first sub-opening ST1, that is, the dielectric material will not be deposited at the bottom of the first sub-opening ST1.
[0076] It should be understood that when the bottom of the first sub-opening ST1 has curvature, the bottom of the first sub-opening ST1 can be regarded as a surface formed by extending upward a certain distance from the lowest position of the first sub-opening ST1, and other areas of the surface of the first sub-opening ST1 can be regarded as the sidewalls of the first sub-opening ST1.
[0077] As some implementation methods, such Figure 7A As shown, the protective layer PL can also cover the sidewalls on both sides of the first opening T1.
[0078] As one implementation, the protective layer PL can also cover the upper surface of the mask layer 400 (not shown).
[0079] In some embodiments, the method of manufacturing a semiconductor structure further includes: after performing a second etching, filling an insulating material into a second opening T2 to form an isolation portion 320.
[0080] like Figure 9A As shown, the isolation section 320 isolates the second dummy gate structure 300b and the third dummy gate structure 300c. After the second dummy gate structure 300b and the third dummy gate structure 300c are replaced with corresponding metal gate structures to form corresponding 3D transistors, the isolation section 320 isolates the 3D transistors corresponding to the second dummy gate structure 300b and the third dummy gate structure 300c respectively. This completes the single-diffusion interruption process.
[0081] like Figure 9BAs shown, when there are four fins 200 arranged side by side on the substrate 100, the isolation portion 320 can isolate the adjacent three-dimensional transistors on the four fins 200.
[0082] Figure 10 This is a schematic flowchart illustrating the execution of a first etching according to some embodiments of the present disclosure.
[0083] Figure 11A and Figure 12A This is a front view of a corresponding structure during the execution of the first etching process according to some embodiments of this disclosure. Figure 11B and Figure 12B They are along Figure 11A and Figure 12A The cross-sectional view of the corresponding structure cut off by a-a' in the diagram.
[0084] The following is combined with Figures 10-12B The method of performing a first etching according to some embodiments of the present disclosure will be described.
[0085] First, refer to Figure 10 In step S201, in Figure 5A and Figure 5B Based on the structure shown, a first sub-etch is performed to remove a portion of the first dummy gate 301a to expose the first dummy gate dielectric layer 303a located on the upper surface of the fin 200.
[0086] like Figure 11A and Figure 11B As shown, after the first sub-etch, the upper surface of the remaining portion of the first dummy gate 301a is not higher than the upper surface of the first dummy gate dielectric layer 303a. For example, the first sub-etch stops at the upper surface of the first dummy gate dielectric layer 303a, in which case the upper surface of the remaining portion of the first dummy gate 301a is flush with the upper surface of the first dummy gate dielectric layer 303a. Alternatively, the first sub-etch may over-etch the first dummy gate 301a so that the upper surface of the remaining portion of the first dummy gate 301a is lower than the upper surface of the first dummy gate dielectric layer 303a. Figure 11B The diagram schematically shows the upper surface of the remaining portion of the first dummy gate 301a flush with the upper surface of the first dummy gate dielectric layer 303a.
[0087] In some embodiments, after performing the first sub-etch, a wet cleaning process may be performed to remove polymers and the like generated during the first sub-etch.
[0088] Subsequently, reference Figure 10 In step S202, a second sub-etch is performed to remove the first pseudo-gate dielectric layer 303a.
[0089] like Figure 12A and Figure 12BAs shown, the first dummy gate dielectric layer 303a located on the upper surface of the fin 200 is removed. Figure 12B As shown, the second pseudo-gate dielectric layer 303b located on the side surface of the fin 200 is retained.
[0090] As one implementation method, dry etching can be used to remove the first pseudo-gate dielectric layer 303a.
[0091] Subsequently, reference Figure 10 In step S203, a third sub-etch is performed to remove the remaining portion of the first dummy gate 301a and a portion of the fin 200 located below the first dummy gate 301a, thereby forming as shown in the figure. Figure 6A The second opening T2 is shown.
[0092] It should be understood that the thickness of the portion of fin 200 removed by the third sub-etching can be the same as or different from the thickness of the portion of first dummy gate 301a removed by the third sub-etching. For example, if the material of the first dummy gate 301a is the same as or close to the material of fin 200, the thickness of the portions of the first dummy gate 301a and fin 200 removed during the third sub-etching process can be the same or close.
[0093] Damage to the spacer layers 302 on both sides of the first dummy gate 301a increases the risk of etching of the underlying fin 200. In related technologies, the fin 200 is etched only after the first dummy gate 301a is completely removed. The overall etching time for the first etching is relatively long, and the spacer layers 302 on both sides of the first dummy gate 301a are exposed and thus more easily damaged. Consequently, the risk of material etching of the fin 200 is high, and the risk of damage to the electrode region 220 is also high.
[0094] In the above embodiment, the first dummy gate 301a is removed by two sub-etching processes. During the second sub-etching (i.e., the third sub-etching) process (step S203), the fin 200 is etched simultaneously, thereby reducing the overall etching time. Even if the spacer layer 302 on one side of the first dummy gate 301a is exposed, the degree of damage to the exposed spacer layer 302 can be reduced, thereby reducing the risk of the material of the underlying fin 200 being etched, and thus reducing the risk of damage to the electrode region 220.
[0095] In some embodiments, after the first sub-etching is performed, the upper surface of the remaining portion of the first dummy gate 301a is lower than the upper surface of the fin 200.
[0096] In other embodiments, after the first sub-etching, the upper surface of the remaining portion of the first dummy gate 301a is not lower than the upper surface of the fin 200. In this case, the portion of the fin 200 above the upper surface of the isolation region 210 can be removed together with the remaining portion of the first dummy gate 301a in the third sub-etching, which can further reduce the overall etching time of the first etching and further reduce the risk of material of the fin 200 below the spacer layer 302 on both sides of the first dummy gate 301a being etched, thereby further reducing the risk of damage to the electrode region 220.
[0097] As some implementation methods, such Figure 11B As shown, after the first sub-etch is performed, the upper surface of the remaining portion of the first dummy gate 301a is flush with the upper surface of the first dummy gate dielectric layer 303a.
[0098] In some embodiments, in step S20, the first etching removes the portion of the fin 200 located above the upper surface of the isolation region 210. For example... Figure 6B As shown, after the first etching (e.g., after the third sub-etch), the upper surface of the fin 200 is flush with the upper surface of the isolation region 210. That is, the first etching removes the portion of the fin 200 above the upper surface of the isolation region 210, while retaining the portion of the fin 200 below the upper surface of the isolation region 210. In this way, the isolation region 210 can be used as the etching stop layer for the first etching, which is beneficial for process execution.
[0099] In some embodiments, after performing the third sub-etch in step S203, a wet cleaning process is performed to remove at least a portion of the second dummy gate dielectric layer 303b.
[0100] After performing a second sub-etch to remove the first dummy gate dielectric layer 303a, at least a portion of the second dummy gate dielectric layer 303b is retained. For example, as Figure 12B As shown, the second pseudo-gate dielectric layer 303b is entirely retained. After the third sub-etch is performed, a portion of the second pseudo-gate dielectric layer 303b will be retained.
[0101] In the above embodiments, by performing a wet cleaning process, at least a portion of the second dummy gate dielectric layer 303b can be removed (e.g., reducing the height or thickness of the second dummy gate dielectric layer 303b), thereby reducing the aspect ratio of the space enclosed by the second dummy gate dielectric layer 303b on both sides of the fin 200 and the bottom of the first sub-opening ST1 along the a-a' section. This is beneficial for the subsequent etching of the fin 200 (i.e., the second etching) process. For example, it is beneficial for the etching gas to contact the bottom of the second opening T2 so that the second opening T2 extends downward.
[0102] Furthermore, because the remaining portion of the first dummy gate 301a and a portion of the fin 200 located below the first dummy gate 301a are removed together during the third sub-etching, both sides of the second dummy gate dielectric layer 303b are exposed. The wet cleaning process performed after the third sub-etching can more effectively remove the second dummy gate dielectric layer 303b, resulting in less remaining portion of the second dummy gate dielectric layer 303b. This is more beneficial for subsequent etching of the fin 200.
[0103] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.
[0104] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, comprising: A substrate structure is provided, the substrate structure comprising: Substrate, Fins located on the substrate, The isolation zones are located on both sides of the fin, and the upper surface of the isolation zones is lower than the upper surface of the fin. A plurality of pseudo-gate structures spanning the fins and located on the isolation region, the plurality of pseudo-gate structures including a first pseudo-gate structure, a second pseudo-gate structure located on one side of the first pseudo-gate structure, and a third pseudo-gate structure located on the other side of the first pseudo-gate structure, the first pseudo-gate structure including a first pseudo-gate and spacer layers located on both sides of the first pseudo-gate. An electrode region located on the fin and an insulating portion on the electrode region, the electrode region and the insulating portion being located between each of the second and third dummy gate structures and the first dummy gate structure, and A mask layer on the plurality of dummy gate structures and the insulating portion, the mask layer having a first opening that exposes at least a portion of the upper surface of the first dummy gate; Using the mask layer as a mask, a first etching is performed to remove the first dummy gate and a portion of the fin located below the first dummy gate, to form a second opening, the second opening including a first sub-opening located in the fin and a second sub-opening communicating with the first sub-opening; A protective layer is formed, the protective layer covering at least one sidewall of the first sub-opening; and Using the mask layer as a mask, a second etching is performed to etch the fin so that the second opening extends downward.
2. The method according to claim 1, wherein, The protective layer covers the sidewalls on both sides of the first sub-opening.
3. The method according to claim 1, wherein, The protective layer also covers at least one sidewall of the second sub-opening.
4. The method according to claim 1, wherein, The first pseudo-gate structure further includes a pseudo-gate dielectric layer located between the first pseudo-gate and the fin, the pseudo-gate dielectric layer including a first pseudo-gate dielectric layer located on the upper surface of the fin and a second pseudo-gate dielectric layer located on the side surface of the fin; The execution of the first etching includes: Perform a first sub-etch to remove a portion of the first dummy gate to expose the first dummy gate dielectric layer; Perform a second sub-etch to remove the first dummy gate dielectric layer; and A third sub-etch is performed to remove the remaining portion of the first dummy gate and a portion of the fin located below the first dummy gate.
5. The method according to claim 4, wherein, After the first sub-etch is performed, the upper surface of the remaining portion of the first dummy gate is not lower than the upper surface of the fin.
6. The method according to claim 4, further comprising: After the third sub-etching is performed, a wet cleaning process is performed to remove at least a portion of the second dummy gate dielectric layer.
7. The method according to any one of claims 1-6, wherein, The first etching removes the portion of the fin located above the upper surface of the isolation zone.
8. The method according to any one of claims 1-6, wherein, The protective layer includes a dielectric layer. The material of the dielectric layer includes at least one of oxides and nitrides.
9. The method according to any one of claims 1-6, wherein, In the extending direction of the fin, the size of the first opening is larger than the size of the first pseudo-gate.
10. The method according to any one of claims 1-6, further comprising: After the second etching is performed, insulating material is filled into the second opening to form an isolation portion.