A semiconductor device and a manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES MICROELECTRONICS
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
Smart Images
Figure CN122161121A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] High electron mobility transistors (HEMTs) are a type of field-effect transistor. Depletion-type HEMTs typically consist of a substrate, an AlN buffer layer, a GaN channel layer, and an AlGaN barrier layer. In the GaN channel layer / AlGaN barrier layer heterostructure, the different lattice constants of the two materials generate stress at the interface. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas (2DEG) near the interface. At this time, the HEMT is in the on state. When a negative bias voltage is applied to the gate, the two-dimensional electron gas is depleted, causing the HEMT to turn off.
[0003] Breakdown voltage and off-state leakage current are important indicators for evaluating the performance of HEMT devices. A high breakdown voltage can improve the reliability of the device and expand its application range, while a low off-state leakage current helps to reduce the off-state loss of the device and increase the operating voltage of the device.
[0004] However, HEMTs in related technologies struggle to simultaneously achieve both high breakdown voltage and low off-state leakage current. Therefore, improvements are needed to at least partially address these issues. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To at least partially solve the above-mentioned technical problems, this application provides a semiconductor device, comprising:
[0007] Substrate;
[0008] A buffer layer is located on the substrate;
[0009] A high-resistivity layer is located on the buffer layer. The high-resistivity layer includes a first sub-high-resistivity layer disposed from bottom to top and at least one stacked structure. Each stacked structure includes a stacked second sub-high-resistivity layer and a third sub-high-resistivity layer, wherein: the first sub-high-resistivity layer is formed at a first temperature and a first V / III ratio; the second sub-high-resistivity layer is formed at a second temperature and a second V / III ratio; and the third sub-high-resistivity layer is formed at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio.
[0010] The channel layer is located on the high-resistivity layer;
[0011] A barrier layer is located on the channel layer.
[0012] For example, each of the stacked structures includes a second sub-high resistivity layer and a third sub-high resistivity layer stacked sequentially from bottom to top; or
[0013] Each of the stacked structures includes, from bottom to top, the third sub-high-resistivity layer and the second sub-high-resistivity layer.
[0014] For example, the first temperature range is 1000℃-1050℃, the second temperature range is 980℃-1020℃, and the third temperature range is 900℃-970℃;
[0015] The first V / III ratio ranges from 200 to 260, the second V / III ratio ranges from 100 to 200, and the third V / III ratio ranges from 300 to 400.
[0016] For example, the thickness of the first sub-high resistivity layer ranges from 200nm to 500nm;
[0017] The thickness of the second sub-high resistivity layer in each layer ranges from 30nm to 50nm;
[0018] The thickness of each third sub-high-resistivity layer ranges from 15nm to 30nm.
[0019] For example, the first sub-high resistivity layer, the second sub-high resistivity layer and the third sub-high resistivity layer comprise a C-doped GaN layer;
[0020] The C doping concentration of the first sub-high resistivity layer is in the range of 2E+19 atom / cm. 3 -3E+19atom / cm 3 The C doping concentration range for each of the second sub-high resistivity layers and each of the third sub-high resistivity layers is 4E+19 atom / cm³. 3 -5E+19atom / cm3 .
[0021] For example, the number of stacked structures is less than or equal to 15.
[0022] For example, it also includes:
[0023] A stress relief layer is located on the buffer layer, and the high-resistivity layer is located on the stress relief layer;
[0024] An insertion layer is located on the channel layer, and the barrier layer is located on the insertion layer;
[0025] A capping layer is located on the barrier layer.
[0026] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising:
[0027] Provide substrate;
[0028] A buffer layer is formed on the substrate;
[0029] A high-resistivity layer is formed on the buffer layer. The high-resistivity layer includes a first sub-high-resistivity layer disposed from bottom to top and at least one stacked structure. Each stacked structure includes a stacked second sub-high-resistivity layer and a third sub-high-resistivity layer. The process includes: forming the first sub-high-resistivity layer at a first temperature and a first V / III ratio; forming the second sub-high-resistivity layer at a second temperature and a second V / III ratio; and forming the third sub-high-resistivity layer at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio.
[0030] A channel layer is formed on the high-resistivity layer;
[0031] A barrier layer is formed on the channel layer.
[0032] For example, the first sub-high resistivity layer, the second sub-high resistivity layer and the third sub-high resistivity layer comprise a C-doped GaN layer;
[0033] The formation of a high-resistivity layer on the buffer layer includes:
[0034] The first sub-high resistivity layer, the second sub-high resistivity layer, and the third sub-high resistivity layer are grown in an MOCVD reaction chamber. The carrier gas is N2, H2, or a N2 / H2 mixture. The growth pressure is 50 mbar-200 mbar. The C doping source is CBr4, the N source is NH3, and the Ga source is TMGa.
[0035] For example, the V / III ratio is the molar ratio of NH3 to TMGa introduced into the MOCVD reaction chamber.
[0036] The semiconductor device and its manufacturing method disclosed in this application comprise a high-resistivity layer consisting of a first sub-high-resistivity layer, a second sub-high-resistivity layer, and a third sub-high-resistivity layer. The first sub-high-resistivity layer, the second sub-high-resistivity layer, and the third sub-high-resistivity layer are formed at different temperatures and V / III ratios, which can increase the breakdown voltage of the device while reducing the off-state leakage current of the device. Attached Figure Description
[0037] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0038] In the attached image:
[0039] Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown;
[0040] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Detailed Implementation
[0041] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0045] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as interpreted in an ideal or overly formal sense, unless expressly defined herein.
[0047] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0048] In related technologies, improvements are generally made to the growth process of the high-resistivity layer in HEMTs to increase the breakdown voltage or reduce the off-state leakage current. The high-resistivity layer is typically a carbon-doped GaN layer. One approach is to increase the growth temperature of the high-resistivity layer to improve its crystal quality, thereby reducing the off-state leakage current. However, increasing the growth temperature leads to a decrease in the carbon doping concentration of the high-resistivity layer, making it impossible to achieve a high breakdown voltage. Another approach is to increase the V / III ratio during the growth process of the high-resistivity layer to improve its crystal quality, thereby reducing the off-state leakage current. However, an increased V / III ratio leads to a decrease in the carbon doping concentration of the high-resistivity layer, making it impossible to achieve a high breakdown voltage. Yet another approach is to decrease the growth temperature of the high-resistivity layer to increase its carbon doping concentration, thereby achieving a high breakdown voltage. However, decreasing the growth temperature leads to a deterioration in the crystal quality of the high-resistivity layer, resulting in a higher off-state leakage current.
[0049] Therefore, in view of the aforementioned technical problems, this application proposes a semiconductor device, comprising:
[0050] Substrate;
[0051] A buffer layer is located on the substrate;
[0052] A high-resistivity layer is located on a buffer layer. The high-resistivity layer includes a first sub-high-resistivity layer disposed from bottom to top and at least one stacked structure. Each stacked structure includes a stacked second sub-high-resistivity layer and a third sub-high-resistivity layer, wherein: the first sub-high-resistivity layer is formed at a first temperature and a first V / III ratio; the second sub-high-resistivity layer is formed at a second temperature and a second V / III ratio; and the third sub-high-resistivity layer is formed at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio.
[0053] The channel layer is located on top of the high-resistivity layer;
[0054] The barrier layer is located above the channel layer.
[0055] The semiconductor device of this application has a high-resistivity layer composed of a first sub-high-resistivity layer, a second sub-high-resistivity layer and a third sub-high-resistivity layer. The first sub-high-resistivity layer, the second sub-high-resistivity layer and the third sub-high-resistivity layer are formed at different temperatures and V / III ratios, which can improve the breakdown voltage of the device while reducing the off-state leakage current of the device.
[0056] Example 1
[0057] Below, for reference Figure 1 The semiconductor devices in the embodiments of this application are described. Wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown.
[0058] In one example, such as Figure 1 As shown, the semiconductor device of this application includes a substrate 100, a buffer layer 110, a high-resistivity layer 120, a channel layer 130, and a barrier layer 140. The buffer layer 110 is located on the substrate 100, the high-resistivity layer 120 is located on the buffer layer 110, the channel layer 130 is located on the high-resistivity layer 120, and the barrier layer 140 is located on the channel layer 130. The high-resistivity layer 120 includes a first sub-high-resistivity layer 121 disposed from bottom to top and at least one stacked structure. Each stacked structure includes a second sub-high-resistivity layer 122 and a third sub-high-resistivity layer 123 stacked together. The first sub-high-resistivity layer 121 is formed at a first temperature and a first V / III ratio, the second sub-high-resistivity layer 122 is formed at a second temperature and a second V / III ratio, and the third sub-high-resistivity layer 123 is formed at a third temperature and a third V / III ratio. The first and second temperatures are both greater than the third temperature, and the third V / III ratio is greater than the first and second V / III ratios. For example, the V / III ratio is the molar ratio of group V sources to group III sources during the growth of a high-resistivity layer.
[0059] The semiconductor device can be any suitable device known to those skilled in the art, such as a depletion-type HEMT, and this application does not limit it.
[0060] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application. In this embodiment, substrate 100 may be p-type (111) plane silicon.
[0061] In one example, the material of the buffer layer 110 includes, but is not limited to, AlN. The buffer layer 110 is used to resolve the problem of lattice mismatch between the substrate 100 and the epitaxial layer formed on the substrate 100. Exemplarily, the buffer layer 110 may include a high-temperature AlN (HT-AlN) layer and a low-temperature AlN (LT-AlN) layer, wherein the thickness of the HT-AlN layer ranges from 150 nm to 190 nm, and the thickness of the LT-AlN layer ranges from 20 nm to 40 nm. For example, the thickness of the HT-AlN layer can be 150 nm, 160 nm, 170 nm, 180 nm, or 190 nm, and the thickness of the LT-AlN layer can be 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. Alternatively, the HT-AlN layer and the LT-AlN layer can be any other suitable thickness range.
[0062] In one example, the crystal quality of the high-resistivity layer 120 affects the off-state leakage current of the device; the better the crystal quality of the high-resistivity layer 120, the lower the off-state leakage current of the device. The high-resistivity characteristics of the high-resistivity layer 120 affect the breakdown voltage of the device; the better the high-resistivity characteristics of the high-resistivity layer 120, the higher the breakdown voltage of the device. Here, the high-resistivity characteristics of the high-resistivity layer 120 refer to the resistance value of the high-resistivity layer 120; the higher the resistance value of the high-resistivity layer 120, the better the high-resistivity characteristics of the high-resistivity layer 120.
[0063] In one example, the first sub-high resistivity layer 121, the second sub-high resistivity layer 122, and the third sub-high resistivity layer 123 include C-doped GaN layers. The high resistivity characteristics of the first sub-high resistivity layer 121, the second sub-high resistivity layer 122, and the third sub-high resistivity layer 123 are ensured by C doping. The higher the C doping concentration, the better the high resistivity characteristics.
[0064] In one example, taking a C-doped GaN layer consisting of a first sub-high resistivity layer 121, a second sub-high resistivity layer 122, and a third sub-high resistivity layer 123, the crystal quality of GaN is affected by the growth temperature and V / III ratio during its growth process. The crystal quality is positively correlated with the growth temperature and V / III ratio; both a higher growth temperature and a higher V / III ratio can improve the crystal quality of GaN, thereby reducing the off-state leakage current of the device. Meanwhile, the high resistivity characteristics of the C-doped GaN layer are positively correlated with the C doping concentration. The C doping concentration is also affected by the growth temperature and V / III ratio during the growth process of the first sub-high resistivity layer 121, the second sub-high resistivity layer 122, and the third sub-high resistivity layer 123. The C doping concentration is negatively correlated with the growth temperature and V / III ratio; both a lower growth temperature and a lower V / III ratio can increase the C doping concentration, thereby achieving good high resistivity characteristics and improving the breakdown voltage of the device.
[0065] In one example, taking the first sub-high resistivity layer 121 as a C-doped GaN layer, the first sub-high resistivity layer 121 is formed at a first temperature and a first V / III ratio. The first temperature range is 1000℃-1050℃, for example, the first temperature can be 1000℃, 1010℃, 1020℃, 1030℃, 1040℃ or 1050℃, and the first V / III ratio range is 200-260, for example, the first V / III ratio can be 200, 210, 220, 230, 240, 250 or 260. Growing the first sub-high-resistivity layer 121 within this first temperature range can effectively reduce the defect density during GaN growth, thereby improving crystal quality and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the off-state leakage current of the device. Simultaneously, growing the first sub-high-resistivity layer 121 within this first temperature range and the first V / III ratio range also ensures that the C doping concentration is not too low; for example, the C doping concentration range of the first sub-high-resistivity layer 121 is 2E+19 atom / cm³. 3 -3E+19atom / cm 3 .
[0066] In one example, taking the second sub-high resistivity layer 122 as a C-doped GaN layer, the second sub-high resistivity layer 122 is formed at a second temperature and a second V / III ratio. The second temperature ranges from 980℃ to 1020℃, for example, the second temperature can be 980℃, 990℃, 1000℃, 1010℃ or 1020℃. The second V / III ratio ranges from 100 to 200, for example, the second V / III ratio can be 100, 110, 120, 130, 140, 150, 160, 170, 180, 190 or 200. Growing the second sub-high resistivity layer 122 within this second temperature range effectively reduces the defect density during GaN growth, thereby improving crystal quality and interface quality, and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the device's off-state leakage current. Simultaneously, growth within this second temperature range leads to a relatively lower C doping concentration. By controlling the V / III ratio during the growth of the second sub-high resistivity layer 122 to the aforementioned second V / III ratio range, a low V / III ratio growth condition is achieved, thereby increasing the C doping concentration. Therefore, by forming the second sub-high resistivity layer 122 at the second temperature and the second V / III ratio, a higher C doping concentration is achieved while improving the crystal quality of the second sub-high resistivity layer 122. For example, the C doping concentration range of the second sub-high resistivity layer 122 is 4E+19 atom / cm². 3 -5E+19atom / cm 3 This enables the achievement of good high-resistivity characteristics, thereby improving the breakdown voltage of the device.
[0067] In one example, taking a C-doped GaN layer as an example, the third sub-high resistivity layer 123 is formed at a third temperature and a third V / III ratio. The third temperature ranges from 900℃ to 970℃, for example, the third temperature can be 900℃, 910℃, 920℃, 930℃, 940℃, 950℃, 960℃ or 970℃. The third V / III ratio ranges from 300 to 400, for example, the third V / III ratio can be 300, 310, 320, 330, 340, 350, 360, 370, 380, 390 or 400. Growing the third sub-high resistivity layer 123 within this third V / III ratio range effectively reduces the defect density during GaN growth, thereby improving crystal quality and interface quality, and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the device's off-state leakage current. Simultaneously, growth within this third V / III ratio range results in a relatively lower C doping concentration. By controlling the growth temperature of the third sub-high resistivity layer 123 within the aforementioned third temperature range, a lower growth temperature is achieved to increase the C doping concentration. Therefore, by forming the third sub-high resistivity layer 123 at the third temperature and third V / III ratio, a higher C doping concentration can be achieved while improving the crystal quality of the third sub-high resistivity layer 123. For example, the C doping concentration range of the third sub-high resistivity layer 123 is 4E+19 atom / cm³. 3 -5E+19atom / cm 3 This enables the achievement of good high-resistivity characteristics, thereby improving the breakdown voltage of the device.
[0068] In one example, due to lattice mismatch between the silicon substrate 100 and the GaN high-resistivity layer 120, defects are generated in the high-resistivity layer 120 during growth. The defects are more severe closer to the substrate 100. That is, the defects in the first sub-high-resistivity layer 121 are more severe than those in the second sub-high-resistivity layer 122 and the third sub-high-resistivity layer 123. Therefore, when forming the first sub-high-resistivity layer 121, more emphasis is placed on improving its crystal quality. In this application, the first sub-high-resistivity layer 121 is formed at the first temperature and the first V / III ratio, which can effectively improve the crystal quality of the first sub-high-resistivity layer 121. The C doping concentration sacrificed for this purpose is compensated by the second sub-high-resistivity layer 122 and the third sub-high-resistivity layer 123.
[0069] In one example, such as Figure 1As shown, each stacked structure includes a second sub-high resistivity layer 122 and a third sub-high resistivity layer 123 stacked sequentially from bottom to top; or, each stacked structure includes a third sub-high resistivity layer 123 and a second sub-high resistivity layer 122 stacked sequentially from bottom to top. Exemplarily, the interface of the alternately periodically grown second sub-high resistivity layer 122 and third sub-high resistivity layer 123 can reduce penetration misalignment caused by large lattice mismatch between silicon and GaN (between substrate 100 and high resistivity layer 120), thereby improving crystal quality and reducing device off-state leakage current. It is worth noting that... Figure 1 The illustrated stacked structure has two elements. In other embodiments, the high-resistivity layer 120 may also include one, three, or more stacked structures. Exemplarily, the number of stacked structures is less than or equal to 15, as too many stacked structures would result in excessively long growth times.
[0070] In one example, the high-resistivity layer 120 includes a first sub-high-resistivity layer 121, a second sub-high-resistivity layer 122, and a third sub-high-resistivity layer 123, thereby enabling good high-resistivity characteristics while having high crystal quality, which in turn reduces the off-state leakage current of the device and improves the breakdown voltage of the device.
[0071] In one example, the thickness of the first sub-high resistivity layer 121 ranges from 200nm to 500nm, for example, it can be 200nm, 300nm, 400nm, or 500nm, or any other suitable thickness range. Exemplarily, the thickness of each second sub-high resistivity layer 122 ranges from 30nm to 50nm, for example, it can be 30nm, 35nm, 40nm, 45nm, or 50nm, or any other suitable thickness range. Exemplarily, the thickness of each third sub-high resistivity layer 123 ranges from 15nm to 30nm, for example, it can be 15nm, 20nm, 25nm, or 30nm, or any other suitable thickness range.
[0072] In one example, the channel layer 130 is made of materials including, but not limited to, GaN, and the barrier layer 140 is made of materials including, but not limited to, AlGaN. In the GaN channel layer / AlGaN barrier layer heterostructure, stress is generated at the interface due to the difference in lattice constants between the two materials. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas near the interface.
[0073] In one example, such as Figure 1As shown, the semiconductor device of this application further includes: a stress relief layer 150 located on a buffer layer 110, a high-resistivity layer 120 located on the stress relief layer 150; an insertion layer 160 located on a channel layer 130, a barrier layer 140 located on the insertion layer 160; and a capping layer 170 located on the barrier layer 140. The stress relief layer 150 is a compositionally graded AlGaN layer, which can be used to alleviate stress; the insertion layer 160 is made of AlN, which can improve mobility and suppress current collapse effects; and the capping layer 170 is made of GaN, which protects against and improves stress.
[0074] In one example, the semiconductor device of this application may further include a gate, a source, and a drain (not shown). Taking a depletion-type HEMT as an example, the source and drain are normally connected, and when a negative bias voltage is applied to the gate, the source and drain are not connected.
[0075] This concludes the introduction to the structure of the semiconductor device of this application. A complete semiconductor device may also include other components, which will not be elaborated here.
[0076] In summary, the semiconductor device of this application has a high-resistivity layer composed of a first sub-high-resistivity layer, a second sub-high-resistivity layer, and a third sub-high-resistivity layer. The first sub-high-resistivity layer, the second sub-high-resistivity layer, and the third sub-high-resistivity layer are formed at different temperatures and V / III ratios, which can improve the breakdown voltage of the device while reducing the off-state leakage current of the device.
[0077] Example 2
[0078] In another embodiment of this application, a method for manufacturing a semiconductor device is also provided, the method being used to manufacture the semiconductor device described in Embodiment 1.
[0079] The following reference Figure 1 and Figure 2 A method for manufacturing a semiconductor device according to embodiments of this application is described, wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. First, step S1 is performed, in which a substrate 100 is provided.
[0080] The semiconductor device can be any suitable device known to those skilled in the art, such as a depletion-type HEMT, and this application does not limit it.
[0081] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application.
[0082] Next, step S2 is performed to form a buffer layer 110 on the substrate 100.
[0083] In one example, an epitaxial structure on substrate 100 can be grown in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, with N2, H2 or a mixture of N2 and H2 as the carrier gas, NH3 as the N source, trimethylgallium (TMGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, and CBr4 as the C doping source. For example, a buffer layer 110 is grown in an MOCVD reaction chamber: the substrate 100 is first treated in a hydrogen atmosphere for 5 min-15 min to clean the impurities on the surface of the substrate 100. The reaction chamber temperature is controlled at 1110℃-1180℃. Then, the reaction chamber temperature is reduced to 850℃-950℃ to pre-lay Al for 2 min-5 min. The reaction chamber temperature is then adjusted to 900℃-1000℃ and 1160℃-1220℃ respectively to grow LT-Al layers with a thickness of 20nm-40nm and HT-Al layers with a thickness of 150nm-190nm respectively. The LT-Al layer and the HT-Al layer are collectively referred to as the buffer layer 110. The pressure is controlled at 50mbar during this growth process.
[0084] Next, step S3 is performed to form a high-resistivity layer 120 on the buffer layer 110. The high-resistivity layer 120 includes a first sub-high-resistivity layer 121 disposed from bottom to top and at least one stacked structure. Each stacked structure includes a second sub-high-resistivity layer 122 and a third sub-high-resistivity layer 123 stacked together. The process includes: forming the first sub-high-resistivity layer 121 at a first temperature and a first V / III ratio; forming the second sub-high-resistivity layer 122 at a second temperature and a second V / III ratio; and forming the third sub-high-resistivity layer 123 at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio.
[0085] In one example, the first sub-high resistivity layer 121, the second sub-high resistivity layer 122, and the third sub-high resistivity layer 123 comprise C-doped GaN layers; forming a high resistivity layer 120 on the buffer layer 110 includes: growing the first sub-high resistivity layer 121, the second sub-high resistivity layer 122, and the third sub-high resistivity layer 123 in an MOCVD reaction chamber, wherein the carrier gas is N2, H2, or an N2 / H2 mixture, the growth pressure is 50 mbar-200 mbar, the C doping source is CBr4, the N source is NH3, and the Ga source is TMGa. Exemplarily, the V / III ratio is the molar ratio of NH3 to TMGa introduced into the MOCVD reaction chamber.
[0086] In one example, taking the first sub-high resistivity layer 121 as a C-doped GaN layer, the first sub-high resistivity layer 121 is formed at a first temperature and a first V / III ratio. The first temperature range is 1000℃-1050℃, for example, the first temperature can be 1000℃, 1010℃, 1020℃, 1030℃, 1040℃ or 1050℃, and the first V / III ratio range is 200-260, for example, the first V / III ratio can be 200, 210, 220, 230, 240, 250 or 260. Growing the first sub-high-resistivity layer 121 within this first temperature range can effectively reduce the defect density during GaN growth, thereby improving crystal quality and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the off-state leakage current of the device. Simultaneously, growing the first sub-high-resistivity layer 121 within this first temperature range and the first V / III ratio range also ensures that the C doping concentration is not too low; for example, the C doping concentration range of the first sub-high-resistivity layer 121 is 2E+19 atom / cm³. 3 -3E+19atom / cm 3 .
[0087] In one example, taking the second sub-high resistivity layer 122 as a C-doped GaN layer, the second sub-high resistivity layer 122 is formed at a second temperature and a second V / III ratio. The second temperature ranges from 980℃ to 1020℃, for example, the second temperature can be 980℃, 990℃, 1000℃, 1010℃ or 1020℃. The second V / III ratio ranges from 100 to 200, for example, the second V / III ratio can be 100, 110, 120, 130, 140, 150, 160, 170, 180, 190 or 200. Growing the second sub-high resistivity layer 122 within this second temperature range effectively reduces the defect density during GaN growth, thereby improving crystal quality and interface quality, and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the device's off-state leakage current. Simultaneously, growth within this second temperature range leads to a relatively lower C doping concentration. By controlling the V / III ratio during the growth of the second sub-high resistivity layer 122 to the aforementioned second V / III ratio range, a low V / III ratio growth condition can be achieved (e.g., by reducing the amount of NH3 as a V-group source), thereby increasing the C doping concentration. Therefore, by forming the second sub-high resistivity layer 122 at the second temperature and the second V / III ratio, a higher C doping concentration is achieved while simultaneously improving the crystal quality of the second sub-high resistivity layer 122. For example, the C doping concentration range of the second sub-high resistivity layer 122 is 4E+19 atom / cm². 3 -5E+19atom / cm 3 This enables the achievement of good high-resistivity characteristics, thereby improving the breakdown voltage of the device.
[0088] In one example, taking a C-doped GaN layer as an example, the third sub-high resistivity layer 123 is formed at a third temperature and a third V / III ratio. The third temperature ranges from 900℃ to 970℃, for example, the third temperature can be 900℃, 910℃, 920℃, 930℃, 940℃, 950℃, 960℃ or 970℃. The third V / III ratio ranges from 300 to 400, for example, the third V / III ratio can be 300, 310, 320, 330, 340, 350, 360, 370, 380, 390 or 400. Growing the third sub-high resistivity layer 123 within this third V / III ratio range effectively reduces the defect density during GaN growth, thereby improving crystal quality and interface quality, and mitigating the off-state leakage current problem caused by defect-trapped electrons, thus reducing the device's off-state leakage current. Simultaneously, growth within this third V / III ratio range results in a relatively lower C doping concentration. By controlling the growth temperature of the third sub-high resistivity layer 123 within the aforementioned third temperature range, a lower growth temperature is achieved to increase the C doping concentration. Therefore, by forming the third sub-high resistivity layer 123 at the third temperature and third V / III ratio, a higher C doping concentration can be achieved while improving the crystal quality of the third sub-high resistivity layer 123. For example, the C doping concentration range of the third sub-high resistivity layer 123 is 4E+19 atom / cm³. 3 -5E+19atom / cm 3 This enables the achievement of good high-resistivity characteristics, thereby improving the breakdown voltage of the device.
[0089] In one example, such as Figure 1 As shown, each stacked structure includes a second sub-high resistivity layer 122 and a third sub-high resistivity layer 123 stacked sequentially from bottom to top; or, each stacked structure includes a third sub-high resistivity layer 123 and a second sub-high resistivity layer 122 stacked sequentially from bottom to top. Exemplarily, the interface of the alternately periodically grown second sub-high resistivity layer 122 and third sub-high resistivity layer 123 can reduce penetration misalignment caused by large lattice mismatch between silicon and GaN (between substrate 100 and high resistivity layer 120), thereby improving crystal quality and reducing device off-state leakage current.
[0090] In one example, after forming the buffer layer 110 and before forming the high-resistivity layer 120, a stress relief layer 150 is formed. The stress relief layer 150 is grown in the MOCVD reaction chamber: the reaction chamber temperature is controlled at 1230℃-1250℃, 1220℃-1240℃, 1210℃-1230℃ and 1190℃-1210℃ respectively, and the stress relief layer 150 of AlGaN material with graded composition is grown sequentially, with the corresponding composition changes being 75%, 50%, 30% and 10%, respectively. The growth pressure is controlled at 50 mbar, and the total thickness of the stress relief layer 150 is 1.8um-2.5um.
[0091] Next, step S4 is performed to form a channel layer 130 on the high-resistivity layer 120. Exemplarily, the channel layer 130 is grown and formed in an MOCVD reaction chamber: the carrier gas is pure hydrogen, the growth temperature is 1040℃-1070℃, the growth pressure is 200mbar, and the thickness of the channel layer 130 is 260nm-500nm.
[0092] Next, step S5 is performed to form a barrier layer 140 on the channel layer 130. Exemplarily, the barrier layer 140 is grown in an MOCVD reaction chamber: the carrier gas is pure hydrogen, the growth temperature is 1030℃-1080℃, the growth pressure is 100mbar, and the growth thickness is 22nm-30nm.
[0093] In one example, after forming the channel layer 130 and before forming the barrier layer 140, the step of forming an insertion layer 160 is included, in which the insertion layer 160 is grown in an MOCVD reaction chamber: the carrier gas is pure hydrogen, the growth temperature is 1030℃-1080℃, the growth pressure is 100mbar, and the growth thickness is 1nm-2nm.
[0094] In one example, after forming the barrier layer 140, the process includes forming a capping layer 170 on the barrier layer 140. The capping layer 170 is grown in an MOCVD reaction chamber using pure hydrogen as the carrier gas, at a growth temperature of 1030°C-1080°C, a growth pressure of 100 mbar, and a growth thickness of 1 nm-3 nm. Exemplarily, after the capping layer 170 has grown, the temperature of the MOCVD reaction chamber is lowered to below 150°C to terminate the epitaxial growth process.
[0095] This concludes the description of the key steps in the manufacturing method of the semiconductor device of this application. The manufacturing of a complete semiconductor device may also include other steps, such as the steps of forming the gate, source and drain, which will not be elaborated here.
[0096] In summary, the semiconductor device manufacturing method of this application comprises a first sub-high resistivity layer, a second sub-high resistivity layer, and a third sub-high resistivity layer. The first sub-high resistivity layer, the second sub-high resistivity layer, and the third sub-high resistivity layer are formed at different temperatures and V / III, which can improve the breakdown voltage of the device while reducing the off-state leakage current of the device.
[0097] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A buffer layer is located on the substrate; A high-resistivity layer is located on the buffer layer. The high-resistivity layer includes a first sub-high-resistivity layer disposed from bottom to top and at least one stacked structure. Each stacked structure includes a stacked second sub-high-resistivity layer and a third sub-high-resistivity layer, wherein: the first sub-high-resistivity layer is formed at a first temperature and a first V / III ratio; the second sub-high-resistivity layer is formed at a second temperature and a second V / III ratio; and the third sub-high-resistivity layer is formed at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio. The channel layer is located on the high-resistivity layer; A barrier layer is located on the channel layer.
2. The semiconductor device according to claim 1, characterized in that, Each of the stacked structures includes, from bottom to top, a second sub-high-resistivity layer and a third sub-high-resistivity layer; or Each of the stacked structures includes, from bottom to top, the third sub-high-resistivity layer and the second sub-high-resistivity layer.
3. The semiconductor device according to claim 1, characterized in that, The first temperature range is 1000℃-1050℃, the second temperature range is 980℃-1020℃, and the third temperature range is 900℃-970℃; The first V / III ratio ranges from 200 to 260, the second V / III ratio ranges from 100 to 200, and the third V / III ratio ranges from 300 to 400.
4. The semiconductor device according to claim 1, characterized in that, The thickness of the first sub-high resistivity layer ranges from 200nm to 500nm; The thickness of the second sub-high resistivity layer in each layer ranges from 30nm to 50nm; The thickness of each third sub-high-resistivity layer ranges from 15nm to 30nm.
5. The semiconductor device according to claim 1, characterized in that, The first sub-high resistivity layer, the second sub-high resistivity layer and the third sub-high resistivity layer comprise C-doped GaN layers; The C doping concentration of the first sub-high resistivity layer is in the range of 2E+19 atom / cm. 3 -3E+19atom / cm 3 The C doping concentration range for each of the second sub-high resistivity layers and each of the third sub-high resistivity layers is 4E+19 atom / cm³. 3 -5E+19atom / cm 3 .
6. The semiconductor device according to claim 1, characterized in that, The number of stacked structures is less than or equal to 15.
7. The semiconductor device according to claim 1, characterized in that, Also includes: A stress relief layer is located on the buffer layer, and the high-resistivity layer is located on the stress relief layer; An insertion layer is located on the channel layer, and the barrier layer is located on the insertion layer; A capping layer is located on the barrier layer.
8. A method for manufacturing a semiconductor device, characterized in that, The method includes: Provide substrate; A buffer layer is formed on the substrate; A high-resistivity layer is formed on the buffer layer. The high-resistivity layer includes a first sub-high-resistivity layer disposed from bottom to top and at least one stacked structure. Each stacked structure includes a stacked second sub-high-resistivity layer and a third sub-high-resistivity layer. The process includes: forming the first sub-high-resistivity layer at a first temperature and a first V / III ratio; forming the second sub-high-resistivity layer at a second temperature and a second V / III ratio; and forming the third sub-high-resistivity layer at a third temperature and a third V / III ratio. The first temperature and the second temperature are both greater than the third temperature, and the third V / III ratio is greater than the first V / III ratio and the second V / III ratio. A channel layer is formed on the high-resistivity layer; A barrier layer is formed on the channel layer.
9. The manufacturing method according to claim 8, characterized in that, The first sub-high resistivity layer, the second sub-high resistivity layer and the third sub-high resistivity layer comprise C-doped GaN layers; The formation of a high-resistivity layer on the buffer layer includes: The first sub-high resistivity layer, the second sub-high resistivity layer, and the third sub-high resistivity layer are grown in an MOCVD reaction chamber. The carrier gas is N2, H2, or a N2 / H2 mixture. The growth pressure is 50 mbar-200 mbar. The C doping source is CBr4, the N source is NH3, and the Ga source is TMGa.
10. The manufacturing method according to claim 9, characterized in that, The V / III ratio is the molar ratio of NH3 to TMGa introduced into the MOCVD reaction chamber.