A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; an Al x Ga (1‑x) N component gradient layer on the barrier layer, wherein 0≤x≤1 and x gradually decreases from bottom to top; a P-GaN layer on the Al x Ga (1‑x) N component gradient layer; and an Al y Ga (1‑y) N component gradient layer on the P-GaN layer, wherein 0≤y≤1 and y gradually increases from bottom to top. The Al x Ga (1‑x) N component gradient layer between the barrier layer and the P-GaN layer and the Al y Ga (1‑y) N component gradient layer on the P-GaN layer can build a gradually increasing contact potential barrier on both sides of the P-GaN layer, thereby reducing the forward and reverse leakage of the gate, and improving the performance and reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] GaN, as a typical wide bandgap semiconductor material, is widely used in power devices and microwave RF devices due to its excellent physical properties such as large bandgap, high breakdown field strength, high thermal conductivity and high electron mobility. Among them, the high electron mobility transistor (HEMT) is a typical GaN device.

[0003] HEMT is a type of field-effect transistor. Enhancement-mode HEMT generally includes a substrate, a GaN channel layer, an AlGaN barrier layer, a P-GaN layer, and a gate located on the P-GaN layer. In the GaN channel layer / AlGaN barrier layer heterostructure, due to the difference in lattice constants between the two materials, stress is generated at the interface. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas (2DEG) near the interface. The energy band structure at the GaN channel layer / AlGaN barrier layer heterojunction is controlled by the P-GaN layer to deplete the two-dimensional electron gas. When a certain bias voltage is applied to the gate, the two-dimensional electron gas reappears, thereby achieving the enhancement-mode performance of the device.

[0004] However, enhanced HEMTs in related technologies suffer from significant forward and reverse gate leakage currents during power-on. Therefore, improvements are needed to at least partially address these issues. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above-mentioned technical problems, this application provides a semiconductor device, comprising:

[0007] Substrate;

[0008] A buffer layer is located on the substrate;

[0009] A channel layer is located on the buffer layer;

[0010] A barrier layer is located on the channel layer;

[0011] Al x Ga(1-x) An N-component graded layer is located on the barrier layer, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top;

[0012] A P-GaN layer is located on the Al x Ga (1-x) N-component graded layer;

[0013] Al y Ga (1-y) An N-component graded layer is located on the P-GaN layer, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top.

[0014] Exemplarily, x gradually decreases from 1 to 0 from bottom to top;

[0015] y gradually increases from 0 to 1 from bottom to top.

[0016] Exemplarily, the P-GaN layer includes a first sub-P-GaN layer doped with Mg and a second sub-P-GaN layer not doped with Mg, which are stacked from bottom to top.

[0017] Exemplarily, it further includes:

[0018] Al z Ga (1-z) An N-component graded layer is located between the barrier layer and the Al x Ga (1-x) N-component graded layer, where 0 < z ≤ 1 and z gradually increases from bottom to top;

[0019] A cap layer is located on the Al y Ga (1-y) N-component graded layer.

[0020] Exemplarily,

[0021] The thickness range of the Al x Ga (1-x) N-component graded layer is 3 nm - 10 nm;

[0022] The thickness range of the Al y Ga (1-y) N-component graded layer is 3 nm - 10 nm.

[0023] On the other hand, the present application provides a manufacturing method of a semiconductor device, including:

[0024] Providing a substrate;

[0025] Forming a buffer layer on the substrate;

[0026] Forming a channel layer on the buffer layer;

[0027] Form a barrier layer on the channel layer;

[0028] Form Al x Ga (1-x) N compositionally graded layer, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top;

[0029] Form a P-GaN layer on the Al x Ga (1-x) N compositionally graded layer;

[0030] Form Al y Ga (1-y) N compositionally graded layer on the P-GaN layer, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top.

[0031] Exemplarily, after forming the barrier layer and before forming the Al x Ga (1-x) N compositionally graded layer, it further includes the step of forming an Al z Ga (1-z) N compositionally graded layer on the barrier layer, and the Al x Ga (1-x) N compositionally graded layer is located on the Al z Ga (1-z) N compositionally graded layer, where 0 < z ≤ 1 and z gradually increases from bottom to top;

[0032] After forming the P-GaN layer, it further includes the step of forming a cap layer on the P-GaN layer.

[0033] Exemplarily, after forming the P-GaN layer, it further includes the step of annealing the P-GaN layer.

[0034] Exemplarily, annealing the P-GaN layer includes: performing RTA annealing on the P-GaN layer in an oxygen atmosphere, with an annealing temperature of 600°C - 750°C and an annealing time of 5 min - 10 min.

[0035] Exemplarily, grow and form the Al x Ga (1-x) N compositionally graded layer and the Al y Ga (1-y) N compositionally graded layer in a MOCVD reaction chamber, with a carrier gas of H2, an Al source of TMAl, a Ga source of TMGa, a N source of NH3, a growth pressure of 50 mbar - 150 mbar, a growth temperature of 1100 mbar - 1300 mbar, a TMGa flow rate of 0 sccm - 300 sccm, and a TMAl flow rate range of 0 sccm - 1000 sccm.

[0036] The semiconductor device and its manufacturing method described in this application form an Al layer between the barrier layer and the P-GaN layer. x Ga (1-x) An N-component graded layer was formed, and Al was formed on the P-GaN layer. y Ga (1-y) The N-component gradient layer can build a gradually increasing contact barrier on both sides of the P-GaN layer, thereby reducing the forward and reverse leakage current of the gate and improving the performance and reliability of the device. Attached Figure Description

[0037] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0038] In the attached image:

[0039] Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown;

[0040] Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown;

[0041] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown;

[0042] Figure 4A The surface morphology of the P-GaN layer in a semiconductor device in the related art is shown;

[0043] Figure 4B The diagram shows the surface topography of the P-GaN layer of a semiconductor device according to an exemplary embodiment of this application. Detailed Implementation

[0044] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0050] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0051] In related technologies, the gate leakage current of enhancement-mode HEMTs during turn-on is generally reduced by improving the crystal quality of the epitaxial film (such as P-GaN layer, AlGaN barrier layer) or by surface passivation treatment.

[0052] However, methods to improve the crystal quality of epitaxial films only improve the reliability of materials from the perspective of epitaxial materials, without considering the impact on subsequent device manufacturing processes, which can easily lead to device failure; while surface passivation treatment increases the complexity of the process and increases manufacturing costs.

[0053] Therefore, in view of the aforementioned technical problems, this application proposes a semiconductor device, comprising:

[0054] Substrate;

[0055] A buffer layer, located on the substrate;

[0056] The channel layer is located above the buffer layer;

[0057] The barrier layer is located above the channel layer;

[0058] Al x Ga(1-x) An N-component graded layer is located on the barrier layer, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top;

[0059] P-GaN layer, located in Al x Ga (1-x) On the N-component gradient layer;

[0060] Al y Ga (1-y) An N-component graded layer is located on a P-GaN layer, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top.

[0061] The semiconductor device of this application has an Al layer formed between the barrier layer and the P-GaN layer. x Ga (1-x) An N-component graded layer was formed, and Al was formed on the P-GaN layer. y Ga (1-y) The N-component gradient layer can build a gradually increasing contact barrier on both sides of the P-GaN layer, thereby reducing the forward and reverse leakage current of the gate and improving the performance and reliability of the device.

[0062] Example 1

[0063] Below, for reference Figure 1 and Figure 2 The semiconductor devices in the embodiments of this application are described. Wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown.

[0064] In one example, such as Figure 1 and Figure 2 As shown, the semiconductor device of this application includes a substrate 100, a buffer layer 101, a channel layer 102, a barrier layer 103, and Al. x Ga (1-x) N-component graded layer 104, P-GaN layer 105 and Al y Ga (1-y) An N-component graded layer, wherein: a buffer layer 101 is located on a substrate 100; a channel layer 102 is located on the buffer layer 101; a barrier layer 103 is located on the channel layer 102; Al x Ga (1-x) The N-component graded layer 104 is located on the barrier layer 103, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top; the P-GaN layer 105 is located on Al x Ga (1-x) N-component graded layer 104; Al y Ga (1-y)The N-component graded layer 106 is located on the P-GaN layer 105, where 0≤y≤1 and y gradually increases from bottom to top.

[0065] The semiconductor device can be any suitable device known to those skilled in the art, such as an enhanced HEMT, and this application does not limit it.

[0066] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application.

[0067] In one example, the buffer layer 101 may be a composite film layer, which may be composed of, but is not limited to, AlGaN gradient layers, AlN / GaN superlattice structures and GaN high-resistivity layers, to alleviate the stress between the substrate 100 and the epitaxial layer formed on the substrate 100 due to the mismatch of lattice constants and the difference in thermal expansion coefficients.

[0068] In one example, the channel layer 102 is made of materials including, but not limited to, GaN, and the barrier layer 103 is made of materials including, but not limited to, AlGaN. In the GaN channel layer / AlGaN barrier layer heterostructure, stress is generated at the interface due to the difference in lattice constants between the two materials. This stress leads to a polarization effect, which in turn forms a high concentration of two-dimensional electron gas near the interface.

[0069] The semiconductor device in this application also includes a location located in Al y Ga (1-y) The gate is located on the N-component graded layer 106, and the source and drain are located on the barrier layer 103, with the source and drain positioned on opposite sides of the gate. In one example, when no bias voltage is applied to the gate, the semiconductor device is in the off state, and the two-dimensional electron gas at the GaN channel layer / AlGaN barrier layer heterojunction below the P-GaN layer 105 is depleted. When a certain bias voltage is applied to the gate, the semiconductor device is in the on state, and the two-dimensional electron gas reappears, thereby achieving the enhancement-mode performance of the device. The P-GaN layer 105 requires Mg doping during epitaxial growth.

[0070] In one example, Al x Ga(1-x) The conduction band position of the N-component graded layer 104 increases with the increase of Al content, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top (x gradually decreases along the direction from the barrier layer 103 to the P-GaN layer 105), i.e., Al x Ga (1-x) In the N-component graded layer 104, the Al component gradually decreases during growth. x Ga (1-x) During the growth of the N-component graded layer 104, the conduction band position gradually decreases. When a certain forward bias voltage is applied to the gate, the semiconductor device is forward-biased, and Al... x Ga (1-x) The N-component graded layer 104 gradually increases in conduction band position along the direction from the P-GaN layer 105 to the barrier layer 103, thereby constructing a gradually increasing contact barrier between the P-GaN layer 105 and the barrier layer 103 (along the direction from the P-GaN layer 105 to the barrier layer 103). This effectively blocks and captures electrons moving from the P-GaN layer 105 to the barrier layer 103, thereby reducing the forward leakage current of the gate. Exemplarily, multiple Al layers can be formed between the barrier layer 103 and the P-GaN layer 105. x Ga (1-x) N-component graded layers 104, wherein each Al layer x Ga (1-x) The Al composition in the N-component gradient layer 104 gradually decreases from bottom to top, thereby enabling the construction of multiple gradually increasing contact barriers between the barrier layer 103 and the P-GaN layer 105, further enhancing the ability to block and capture electrons, and thus further reducing the forward leakage current of the gate.

[0071] In one example, x decreases from 1 to 0 from bottom to top, i.e., Al x Ga (1-x) In the N-component graded layer 104, the Al component gradually decreases from 1 to 0 from bottom to top. x Ga (1-x) The N-component graded layer 104 achieves graded growth from AlN to GaN during the growth process, at which point Al... x Ga (1-x) Between the two surfaces of the N-component graded layer 104 (Al) x Ga (1-x) The surface where the N-component graded layer 104 contacts the barrier layer 103 and Al x Ga (1-x) The conduction band difference is largest at the surface where the N-component gradient layer 104 contacts the P-GaN layer 105, resulting in the highest raised barrier height, which further enhances the ability to block and capture electrons, thereby further reducing the forward leakage current of the gate.

[0072] In one example, Al x Ga (1-x) The thickness of the N-component graded layer 104 ranges from 3 nm to 10 nm, for example, it can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, or any other suitable thickness range. This is especially true when multiple Al layers are formed. x Ga (1-x) When the N-component graded layer is 104, the multilayer Al x Ga (1-x) The total thickness of the N-component graded layer 104 ranges from 3 nm to 10 nm.

[0073] In one example, Al y Ga (1-y) The conduction band position of the N-component graded layer 106 increases with the increase of Al content, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top (y gradually increases along the direction from the P-GaN layer 105 towards the gate), i.e., Al y Ga (1-y) In the N-component graded layer 106, the Al component gradually increases during growth, then Al y Ga (1-y) During the growth of the N-component graded layer 106, the conduction band position gradually increases. When a certain negative bias voltage is applied to the gate, the semiconductor device is reverse-biased and turned on, at which point Al... y Ga (1-y) The N-component graded layer 106 gradually increases in conduction band position along the direction from the P-GaN layer 105 toward the gate, thereby constructing a gradually increasing contact barrier between the P-GaN layer 105 and the gate (along the direction from the P-GaN layer 105 toward the gate). This effectively blocks and traps electrons moving from the P-GaN layer 105 to the gate, thereby reducing reverse leakage current at the gate. Exemplarily, multiple Al layers can be formed between the barrier layer 103 and the gate. y Ga (1-y) N-component graded layers 106, wherein each Al layer y Ga (1-y) The Al composition in the N-component gradient layer 106 gradually increases from bottom to top, thereby enabling the construction of multiple gradually rising contact barriers between the barrier layer 103 and the gate, further enhancing the ability to block and capture electrons, and thus further reducing the reverse leakage current of the gate.

[0074] In one example, y increases from 0 to 1 from bottom to top, i.e., Al y Ga (1-y) In the N-component graded layer 106, the Al component gradually increases from 0 to 1 from bottom to top. y Ga (1-y)The N-component graded layer 106 realizes the graded growth from GaN to AlN during the growth process. At this time, Al y Ga (1-y) The conduction band difference between the two surfaces of the N-component graded layer 106 (Al y Ga (1-y) The surface of the N-component graded layer 106 in contact with the gate and Al y Ga (1-y) The surface of the N-component graded layer 106 in contact with the P-GaN layer 105) is the largest, so that the raised barrier height is the highest, which can further enhance the ability to block and capture electrons, thereby further reducing the reverse leakage current of the gate.

[0075] In one example, the thickness range of the Al y Ga (1-y) N-component graded layer 106 is 3 nm - 10 nm. For example, it can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm. Or, it can also be any other suitable thickness range. Among them, when multiple layers of Al y Ga (1-y) N-component graded layers 106 are formed, the total thickness range of the multiple layers of Al y Ga (1-y) N-component graded layers 106 is 3 nm - 10 nm.

[0076] In one example, the P-GaN layer 105 includes a first sub-P-GaN layer doped with Mg and a second sub-P-GaN layer not doped with Mg, which are stacked from bottom to top (in the direction from the Al x Ga (1-x) N-component graded layer 104 to the Al y Ga (1-y) N-component graded layer 106). The second sub-P-GaN layer not doped with Mg is close to the gate, which can reduce the possibility of electron F-N tunneling, thereby reducing current collapse; at the same time, the second sub-P-GaN layer not doped with Mg can also raise the Schottky barrier height in contact with the gate, thereby reducing the off-state leakage current of the gate.

[0077] In one example, as Figure 2 shown, the semiconductor device of the present application further includes an Al z Ga (1-z) N-component graded layer 107 and a cap layer 108, where: the Al z Ga (1-z) N-component graded layer 107 is located between the barrier layer 103 and the Al x Ga (1-x) N-component graded layer 104, 0 < z ≤ 1 and z increases gradually from bottom to top; the cap layer 108 is located on the Al y Ga(1-y) N-component gradient layer 106. Exemplarily, when a capping layer 108 is formed, the gate is located on the capping layer 108. Exemplarily, the capping layer 108 is made of GaN and serves to protect, passivate, and improve the surface.

[0078] In one example, z gradually increases from bottom to top, i.e., Al z Ga (1-z) The Al component in the N-component graded layer 107 gradually increases, making Al z Ga (1-z) The N-component graded layer 107 can reduce the barrier layer 103 and Al x Ga (1-x) Lattice mismatch exists between the N-component graded layers 104. For example, the Al composition in the AlGaN barrier layer 103 is 0.15-0.25, and the Al content is... z Ga (1-z) Taking the Al component in the N-component graded layer 107 as an example, which gradually increases from bottom to top to 1, Al z Ga (1-z) In the N-component graded layer 107, the Al component gradually increases from 0.15-0.25 to 1 from bottom to top, meaning that at this point, Al... z Ga (1-z) The surface of the N-component gradient layer 107 in contact with the barrier layer 103 is made of the same material as the barrier layer 103, and Al z Ga (1-z) N-component graded layer 107 and Al x Ga (1-x) The material in contact with the N-component gradient layer 104 and Al x Ga (1-x) The N-component graded layer 104 is identical, thereby minimizing the difference between the barrier layer 103 and Al. x Ga (1-x) Lattice mismatch between N-component graded layers 104.

[0079] This concludes the introduction to the structure of the semiconductor device of this application. A complete semiconductor device may also include other components, which will not be elaborated here.

[0080] In summary, the semiconductor device of this application has an Al layer formed between the barrier layer and the P-GaN layer. x Ga (1-x) An N-component graded layer was formed, and Al was formed on the P-GaN layer. y Ga (1-y)The N-component gradient layer can construct a gradually increasing contact barrier on both sides of the P-GaN layer, thereby reducing the forward and reverse leakage current of the gate and improving the performance and reliability of the device. For example, the P-GaN layer 105 includes a Mg-doped first sub-P-GaN layer and an undoped second sub-P-GaN layer stacked from bottom to top, which can reduce the possibility of electron FN tunneling, thereby reducing current collapse; at the same time, the undoped second sub-P-GaN layer can also raise the height of the Schottky barrier in contact with the gate, thereby reducing the off-state leakage current of the gate.

[0081] Example 2

[0082] In another embodiment of this application, a method for manufacturing a semiconductor device is also provided, the method being used to manufacture the semiconductor device described in Embodiment 1.

[0083] The following reference Figure 1 , Figure 2 , Figure 3 and Figure 4B A method for manufacturing a semiconductor device according to embodiments of this application is described, wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown. Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Figure 4B The diagram shows the surface topography of a P-GaN layer in a semiconductor device according to an exemplary embodiment of this application. First, step S1 is performed, in which a substrate 100 is provided.

[0084] The semiconductor device can be any suitable device known to those skilled in the art, such as an enhanced HEMT, and this application does not limit it.

[0085] In one example, substrate 100 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of this application.

[0086] Next, step S2 is performed to form a buffer layer 101 on the substrate 100. The buffer layer 101 can be a composite film layer, which can be composed of, but is not limited to, AlGaN graded layers, AlN / GaN superlattice structures and GaN high-resistivity layers, to alleviate the stress between the substrate 100 and the epitaxial layer formed on the substrate 100 due to the mismatch of lattice constants and the difference in thermal expansion coefficients.

[0087] In one example, a buffer layer 101 can be grown in a metal-organic chemical vapor deposition (MOCVD) reaction chamber at a growth temperature of 700℃-1100℃, for example, 700℃, 800℃, 900℃, 1000℃ or 1100℃; a growth pressure of 50mbar-200mbar, for example, 50mbar, 70mbar, 100mbar, 150mbar or 200mbar; a thickness range of 2um-4um, for example, 2um, 2.5um, 3um, 3.5um or 4um; an Al source of TMAl (trimethylaluminum) and a Ga source of TMGa (trimethylgallium).

[0088] In one example, before forming the buffer layer 101, a step of treating the substrate 100 in a hydrogen atmosphere at a temperature of 900°C-1200°C for 10 min-30 min is included. This step removes contaminants from the surface of the substrate 100 and repairs stress damage caused during mechanical cutting and polishing, thereby facilitating the subsequent epitaxial growth of the film layer.

[0089] Next, step S3 is performed to form a channel layer 102 on the buffer layer 101, wherein the material of the channel layer 102 includes GaN. Exemplarily, the channel layer 102 is grown in an MOCVD reaction chamber at a growth temperature of 1000℃-1200℃, for example, 1000℃, 1050℃, 1100℃, 1150℃, or 1200℃; a growth pressure of 100mbar-200mbar, for example, 100mbar, 130mbar, 150mbar, 180mbar, or 200mbar; a flow rate of TMGa as the Ga source of 100sccm-300sccm, for example, 100sccm, 150sccm, 200sccm, 250sccm, or 300sccm; and a growth time of 10min-40min, for example, 10min, 20min, 30min, or 40min.

[0090] Next, step S4 is performed to form a barrier layer 103 on the channel layer 102. The material of the barrier layer 103 includes AlGaN. Exemplarily, the barrier layer 103 is grown in an MOCVD reaction chamber at a growth temperature of 1000℃-1200℃, such as 1000℃, 1050℃, 1100℃, 1150℃, or 1200℃; the growth pressure is 50mbar-200mbar, such as 50mbar, 70mbar, 100mbar, 130mbar, 150mbar, 180mbar, or 200mbar; the Ga source is TMGa; the flow rate of TMAl as the Al source is 50sccm-150sccm, such as 50sccm, 80sccm, 100sccm, 120sccm, or 150sccm; and the growth time is 1min-5min, such as 1min, 2min, 30min, 4min, or 5min. For example, the Al composition in the barrier layer 103 of AlGaN material ranges from 0.15 to 0.25.

[0091] Next, step S5 is performed to form Al on the barrier layer 103. x Ga (1-x) N-component graded layer 104, wherein 0 ≤ x ≤ 1 and x gradually decreases from bottom to top. Exemplarily, Al is grown in an MOCVD reaction chamber to form... x Ga (1-x) The N-component graded layer is 104, with H2 as the carrier gas, TMAl as the Al source, TMGa as the Ga source, and NH3 as the N source; the growth pressure is 50 mbar-150 mbar, for example, 50 mbar, 70 mbar, 100 mbar, 130 mbar, or 150 mbar; the growth temperature is 1100 mbar-1300 mbar, for example, 1100, 1150, 1200, 1250, or 1300 mbar; the TMGa flow rate is 0 sccm-300 sccm, and the TMAl flow rate ranges from 0 sccm-1000 sccm. Specifically, in the Al... x Ga (1-x) During the growth of the N-component graded layer 104, the TMGa flow rate gradually increases while the TMAl flow rate gradually decreases.

[0092] In one example, Al x Ga (1-x) The conduction band position of the N-component graded layer 104 increases with the increase of Al content, where 0 ≤ x ≤ 1 and x gradually decreases from bottom to top (x gradually decreases along the direction from the barrier layer 103 to the P-GaN layer 105), i.e., Al x Ga (1-x) In the N-component graded layer 104, the Al component gradually decreases during growth.x Ga (1-x) During the growth of the N-component graded layer 104, the conduction band position gradually decreases. When a certain forward bias voltage is applied to the gate, the semiconductor device is forward-biased, and Al... x Ga (1-x) The N-component graded layer 104 gradually increases in conduction band position along the direction from the P-GaN layer 105 to the barrier layer 103, thereby constructing a gradually increasing contact barrier between the P-GaN layer 105 and the barrier layer 103 (along the direction from the P-GaN layer 105 to the barrier layer 103). This effectively blocks and captures electrons moving from the P-GaN layer 105 to the barrier layer 103, thereby reducing the forward leakage current of the gate. Exemplarily, multiple Al layers can be formed between the barrier layer 103 and the P-GaN layer 105. x Ga (1-x) N-component graded layers 104, wherein each Al layer x Ga (1-x) The Al composition in the N-component gradient layer 104 gradually decreases from bottom to top, thereby enabling the construction of multiple gradually increasing contact barriers between the barrier layer 103 and the P-GaN layer 105, further enhancing the ability to block and capture electrons, and thus further reducing the forward leakage current of the gate.

[0093] In one example, x decreases from 1 to 0 from bottom to top, i.e., Al x Ga (1-x) In the N-component graded layer 104, the Al component gradually decreases from 1 to 0 from bottom to top. x Ga (1-x) The N-component graded layer 104 achieves graded growth from AlN to GaN during the growth process, at which point Al... x Ga (1-x) Between the two surfaces of the N-component graded layer 104 (Al) x Ga (1-x) The surface where the N-component graded layer 104 contacts the barrier layer 103 and Al x Ga (1-x) The conduction band difference is largest at the surface where the N-component gradient layer 104 contacts the P-GaN layer 105, resulting in the highest raised barrier height, which further enhances the ability to block and capture electrons, thereby further reducing the forward leakage current of the gate.

[0094] In one example, after the formation of barrier layer 103, and after the formation of Al x Ga (1-x) Before the N-component graded layer 104, Al is also formed on the barrier layer 103. z Ga (1-z) The steps of N-component graded layer 107, Al x Ga(1-x) The N-component graded layer 104 is located on the Al z Ga (1-z) N-component graded layer 107, where 0 < z ≤ 1 and z increases gradually from bottom to top. Exemplarily, Al z Ga (1-z) N-component graded layer 107 is grown in a MOCVD reaction chamber at a growth temperature of 1100°C - 1300°C, for example, it can be 1100°C, 1150°C, 1200°C, 1250°C or 1300°C; the growth pressure is 50 mbar - 150 mbar, for example, it can be 50 mbar, 70 mbar, 100 mbar, 130 mbar or 150 mbar; the Ga source is TMGa; the Al source is TMAl; the Al z Ga (1-z) The thickness range of the N-component graded layer 107 is 2 nm - 8 nm, for example, it can be 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm or 8 nm. Exemplarily, during the growth of the Al z Ga (1-z) N-component graded layer 107, the flow rate of TMAl gradually increases and the TMGa gradually decreases.

[0095] In one example, z increases gradually from bottom to top, that is, the Al z Ga (1-z) component in the N-component graded layer 107 gradually increases, so that the Al z Ga (1-z) N-component graded layer 107 can reduce the lattice mismatch between the barrier layer 103 and the Al x Ga (1-x) N-component graded layer 104.

[0096] Next, step S6 is executed to form a P-GaN layer 105 on the Al x Ga (1-x) N-component graded layer 104. The material of the P-GaN layer 105 includes GaN doped with Mg. Exemplarily, the P-GaN layer 105 is grown in a MOCVD reaction chamber at a growth temperature of 900°C - 1100°C, for example, it can be 900°C, 950°C, 1000°C, 1050°C or 1100°C; the growth pressure is 200 mbar - 300 mbar, for example, it can be 200 mbar, 230 mbar, 2350 mbar, 280 mbar or 300 mbar; the Ga source is TMGa; the Mg source is Cp2Mg (bis(cyclopentadienyl)magnesium); the carrier gas is hydrogen; the thickness range is 80 nm - 100 nm, for example, it can be 80 nm, 85 nm, 90 nm, 95 nm or 100 nm.

[0097] In one example, the P-GaN layer 105 includes a bottom-up (along Al) layer. x Ga (1-x) N-component graded layer 104 points to Al y Ga (1-y) A first Mg-doped P-GaN layer and a second Mg-undoped P-GaN layer are stacked in the direction of the N-component graded layer 106. The second Mg-undoped P-GaN layer is close to the gate, which can reduce the possibility of electron FN tunneling and thus reduce current collapse. At the same time, the second Mg-undoped P-GaN layer can also raise the Schottky barrier height in contact with the gate, thereby reducing the off-state leakage current of the gate. Exemplarily, the growth of the first Mg-doped P-GaN layer and the second Mg-undoped P-GaN layer can be achieved by adjusting the Cp2Mg ingress time. Exemplarily, the thickness of the first P-GaN layer is in the range of 60nm-80nm, for example, 60nm, 65nm, 70nm, 75nm or 80nm; the thickness of the second P-GaN layer is in the range of 10nm-20nm, for example, 10nm, 12nm, 15nm, 17nm or 20nm.

[0098] Next, step S7 is performed to form Al on the P-GaN layer 105. y Ga (1-y) N-component graded layers 106, wherein 0 ≤ y ≤ 1 and y gradually increases from bottom to top. Exemplarily, Al is grown in an MOCVD reaction chamber to form... y Ga (1-y) The N-component graded layer is 106, the carrier gas is H2, the Al source is TMAl, the Ga source is TMGa, and the N source is NH3; the growth pressure is 50 mbar-150 mbar, for example, 50 mbar, 70 mbar, 100 mbar, 130 mbar, or 150 mbar; the growth temperature is 1100 mbar-1300 mbar, for example, 1100, 1150, 1200, 1250, or 1300 mbar; the TMGa flow rate is 0 sccm-300 sccm, and the TMAl flow rate ranges from 0 sccm-1000 sccm. Specifically, in the Al... y Ga (1-y) During the growth of the N-component graded layer 106, the TMGa flow rate gradually decreases while the TMAl flow rate gradually increases.

[0099] In one example, Al y Ga (1-y) The conduction band position of the N-component graded layer 106 increases with the increase of Al content, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top (y gradually increases along the direction from the P-GaN layer 105 towards the gate), i.e., Al y Ga(1-y) In the N-component graded layer 106, the Al component gradually increases during growth, then Al y Ga (1-y) During the growth of the N-component graded layer 106, the conduction band position gradually increases. When a certain negative bias voltage is applied to the gate, the semiconductor device is reverse-biased and turned on, at which point Al... y Ga (1-y) The N-component graded layer 106 gradually increases in conduction band position along the direction from the P-GaN layer 105 toward the gate, thereby constructing a gradually increasing contact barrier between the P-GaN layer 105 and the gate (along the direction from the P-GaN layer 105 toward the gate). This effectively blocks and traps electrons moving from the P-GaN layer 105 to the gate, thereby reducing reverse leakage current at the gate. Exemplarily, multiple Al layers can be formed between the barrier layer 103 and the gate. y Ga (1-y) N-component graded layers 106, wherein each Al layer y Ga (1-y) The Al composition in the N-component gradient layer 106 gradually increases from bottom to top, thereby enabling the construction of multiple gradually rising contact barriers between the barrier layer 103 and the gate, further enhancing the ability to block and capture electrons, and thus further reducing the reverse leakage current of the gate.

[0100] In one example, y increases from 0 to 1 from bottom to top, i.e., Al y Ga (1-y) In the N-component graded layer 106, the Al component gradually increases from 0 to 1 from bottom to top. y Ga (1-y) The N-component graded layer 106 achieves graded growth from GaN to AlN during the growth process, at which point Al... y Ga (1-y) Between the two surfaces of the N-component graded layer 106 (Al) y Ga (1-y) The surface of the N-component graded layer 106 in contact with the gate and Al y Ga (1-y) The conduction band difference is largest at the surface where the N-component gradient layer 106 contacts the P-GaN layer 105, resulting in the highest raised barrier height, which further enhances the ability to block and capture electrons, thereby further reducing the reverse leakage current of the gate.

[0101] In one example, it also includes Al y Ga (1-y) The steps include forming a gate on the N-component gradient layer 106 and forming a source and drain on the barrier layer 103, wherein the source and drain are located on opposite sides of the gate.

[0102] In one example, it also includes Al yGa (1-y) The step of forming a capping layer 108 on the N-component graded layer 106, wherein the material of the capping layer 108 includes GaN. Exemplarily, the capping layer 108 is grown in an MOCVD reaction chamber at a growth temperature of 1000℃-1200℃, for example, 1000℃, 1050℃, 1100℃, 1150℃, or 1200℃; a growth pressure of 100mbar-200mbar, for example, 100mbar, 130mbar, 150mbar, 180mbar, or 200mbar; a G source of TMGa, with a flow rate of TMGa of 100sccm-300sccm, for example, 100sccm, 150sccm, 200sccm, 250sccm, or 300sccm; a carrier gas of hydrogen; and a thickness of 1nm-3nm, for example, 1nm, 1.5nm, 2nm, 2.5nm, or 3nm. Exemplarily, when the capping layer 108 is formed, the gate is located on the capping layer 108. Exemplarily, the capping layer 108 serves to protect, passivate, and improve the surface. Exemplarily, after the capping layer 108 is grown, the MOCVD reaction chamber temperature is lowered to below 150°C.

[0103] In one example, after forming the P-GaN layer 105, the process further includes an annealing step to activate the Mg in the P-GaN layer 105. Specifically, annealing the P-GaN layer 105 includes: performing RTA (Rapid Thermal Annealing) annealing on the P-GaN layer 105 in an oxygen atmosphere at an annealing temperature of 600℃-750℃, for example, the annealing temperature can be 600℃, 650℃, 700℃, or 750℃; and an annealing time of 5 min-10 min, for example, the annealing time can be 5 min, 6 min, 7 min, 8 min, 9 min, or 10 min. For example, as... Figure 4A As shown, the surface morphology of the P-GaN layer in related semiconductor devices exhibits significant unevenness and protrusions, indicating high surface roughness. This results in an incomplete contact surface with the gate, leading to an increased leakage channel at the gate. In contrast, this application utilizes RTA annealing of the P-GaN layer 105 in an oxygen atmosphere at a temperature of 600℃-750℃ for 5-10 minutes. This effectively prevents secondary crystallization of the P-GaN layer 105, thereby achieving a more efficient and stable surface. Figure 4B The smooth surface shown makes the contact surface with the gate more complete and effective, reducing the leakage path of the gate. For example, the above annealing step is performed after the capping layer 108 is grown.

[0104] This concludes the description of the key steps in the manufacturing method of the semiconductor device of this application. Other steps may also be included in the complete manufacturing of the semiconductor device, which will not be elaborated here.

[0105] In summary, the semiconductor device manufacturing method of this application forms an Al layer between the barrier layer and the P-GaN layer. x Ga (1-x) N-component graded layer, and Al formed on P-GaN layer. y Ga (1-y) The N-component gradient layer can construct a gradually increasing contact barrier on both sides of the P-GaN layer, thereby reducing the forward and reverse leakage current of the gate and improving the performance and reliability of the device. For example, the P-GaN layer 105 includes a Mg-doped first sub-P-GaN layer and an undoped second sub-P-GaN layer stacked from bottom to top, which can reduce the possibility of electron FN tunneling, thereby reducing current collapse; at the same time, the undoped second sub-P-GaN layer can also raise the height of the Schottky barrier at the gate contact, thereby reducing the gate's off-state leakage current. For example, by performing RTA annealing on the P-GaN layer 105 in an oxygen atmosphere at a temperature of 600℃-750℃ and an annealing time of 5min-10min, secondary crystallization of the P-GaN layer 105 can be effectively prevented, thereby obtaining a flat surface, making the contact surface with the gate more complete and effective, and reducing the leakage path of the gate.

[0106] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A buffer layer is located on the substrate; A channel layer is located on the buffer layer; A barrier layer is located on the channel layer; Al x Ga (1-x) An N-component gradient layer is located on the barrier layer, wherein 0 ≤ x ≤ 1 and x gradually decreases from bottom to top; The P-GaN layer is located in the Al x Ga (1-x) On the N-component graded layer; Al y Ga (1-y) An N-component gradient layer is located on the P-GaN layer, wherein 0 ≤ y ≤ 1 and y gradually increases from bottom to top.

2. The semiconductor device according to claim 1, characterized in that, x decreases from 1 to 0 from bottom to top; y increases from 0 to 1 from bottom to top.

3. The semiconductor device according to claim 1, characterized in that, The P-GaN layer comprises a first sub-P-GaN layer doped with Mg and a second sub-P-GaN layer undoped with Mg, stacked from bottom to top.

4. The semiconductor device according to claim 1, characterized in that, Also includes: Al z Ga (1-z) N composition graded layer, located between the barrier layer and the Al x Ga (1-x) N composition graded layer, where 0 < z ≤ 1 and z increases gradually from bottom to top; Cap layer, located in Al y Ga (1-y) On the N-component gradient layer.

5. The semiconductor device according to claim 1, characterized in that, The Al x Ga (1-x) The thickness range of the N-component graded layer is 3nm-10nm; The Al y Ga (1-y) The thickness of the N-component graded layer ranges from 3 nm to 10 nm.

6. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A buffer layer is formed on the substrate; A channel layer is formed on the buffer layer; A barrier layer is formed on the channel layer; Al is formed on the barrier layer x Ga (1-x) N-component gradient layers, where 0≤x≤1 and x gradually decreases from bottom to top; In the Al x Ga (1-x) A P-GaN layer is formed on the N-component graded layer; Al is formed on the P-GaN layer y Ga (1-y) N components form a gradient layer, where 0 ≤ y ≤ 1 and y gradually increases from bottom to top.

7. The manufacturing method according to claim 6, characterized in that, After forming the barrier layer and before forming the Al x Ga (1-x) N composition graded layer, it further includes the step of forming an Al z Ga (1-z) N composition graded layer on the barrier layer, the Al x Ga (1-x) N composition graded layer is located on the Al z Ga (1-z) N composition graded layer, where 0 < z ≤ 1 and z increases gradually from bottom to top; After forming the P-GaN layer, the method further includes the step of forming a capping layer on the P-GaN layer.

8. The manufacturing method according to claim 6, characterized in that, After forming the P-GaN layer, the process also includes an annealing step for the P-GaN layer.

9. The manufacturing method according to claim 8, characterized in that, Annealing the P-GaN layer includes: performing RTA annealing on the P-GaN layer in an oxygen atmosphere, with an annealing temperature of 600℃-750℃ and an annealing time of 5min-10min.

10. The manufacturing method according to claim 6, characterized in that, The Al was grown in the MOCVD reaction chamber. x Ga (1-x) N-component graded layer and Al y Ga (1-y) The N-component graded layer has H2 as the carrier gas, TMAl as the Al source, TMGa as the Ga source, NH3 as the N source, a growth pressure of 50 mbar-150 mbar, a growth temperature of 1100 mbar-1300 mbar, a TMGa flow rate of 0 sccm-300 sccm, and a TMAl flow rate of 0 sccm-1000 sccm.

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