Semiconductor structure and semiconductor device

Abstract

The present application provides a semiconductor structure and a semiconductor device, comprising a substrate, a seed layer on the substrate, and a buffer layer on the seed layer. The buffer layer comprises at least one superlattice portion on the seed layer and at least one barrier layer on the superlattice portion. The thickness of the barrier layer is 10-600 nm. The superlattice portion is N1, and the barrier layer is N2. N1 and N2 are positive integers and are greater than or equal to 1.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures and semiconductor devices that can reduce lattice dislocations. Background Technology

[0002] In recent years, semiconductor devices have been used in various electronic products, such as high-power devices, computers, mobile phones, digital cameras, and other electronic devices. Among these, high-electron-mobility transistors (HEMTs) are widely used in light-emitting diodes (LEDs), high-frequency devices, and other applications due to their use of gallium nitride (GaN-based) semiconductor materials, which possess many excellent material properties such as high heat resistance, wide bandgap, and high electron saturation velocity.

[0003] While existing high electron mobility transistor (HEM) devices largely meet their intended applications, they do not completely fulfill all requirements. For example, lattice dislocations easily occur during the epitaxial growth of semiconductor materials in current devices, leading to performance degradation. Therefore, developing structures that can further improve the performance and reliability of HEM devices remains a key research focus for the industry. Summary of the Invention

[0004] This invention provides a semiconductor structure comprising a substrate, a seed layer on the substrate, and a buffer layer on the seed layer. The buffer layer includes at least one superlattice portion on the seed layer and at least one barrier layer on the superlattice portion. The thickness of the barrier layer is 10 nanometers to 600 nanometers. There are N1 superlattice portions and N2 barrier layers. N1 and N2 are positive integers greater than or equal to 1.

[0005] In some embodiments, the thickness of the barrier layer is 30 nanometers to 100 nanometers. In some embodiments, the barrier layer is aluminum nitride.

[0006] In some embodiments, N1 is greater than N2 (N1>N2). In some embodiments, the difference between N1 and N2 is 1 (N1-N2=1).

[0007] In some embodiments, the barrier layer is sandwiched between any two superlattice portions. In some embodiments, the barrier layer and the superlattice portions are stacked alternately.

[0008] In some embodiments, the superlattice portion includes a plurality of repeating units that are stacked m1 times, and each of these repeating units includes: a first sub-layer and a second sub-layer located on the first sub-layer. The first sub-layer has a thickness of a1 nanometers. The second sub-layer has a thickness of a2 nanometers. m1 is a positive integer. In some embodiments, a1 is less than a2 (a1 < a2). In some embodiments, m1 is from 20 to 120. In some embodiments, the first sub-layer is aluminum nitride, and the second sub-layer is aluminum gallium nitride.

[0009] In some embodiments, when N1 is 2 or more (N1 ≥ 2), it has the following characteristics:

[0010] (1) The total thickness of the superlattice portion closer to the substrate is less than the total thickness of the superlattice portion farther from the substrate.

[0011] (2) Let the thickness of the first sub-layer in each repeating unit in the superlattice portion closer to the substrate be a11 nanometers, and let the thickness of the first sub-layer in each repeating unit in the superlattice portion farther from the substrate be a12 nanometers. a11 is less than a12 (a11 < a12).

[0012] (3) Let the thickness of the second sub-layer in each repeating unit in the superlattice portion closer to the substrate be a21 nanometers, and let the thickness of the second sub-layer in each repeating unit in the superlattice portion farther from the substrate be a22 nanometers. a21 is equal to a22 (a21 = a22).

[0013] (4) The second sub-layer in each repeating unit in the superlattice portion closer to the substrate is Alx1Ga1-x1N, and the second sub-layer in each repeating unit in the superlattice portion farther from the substrate is Alx2Ga1-x2N, where x1 is less than x2.

[0014] (5) The second sub-layer in each repeating unit in the superlattice portion closer to the substrate has a first dopant with a first dopant concentration, and the second sub-layer in each repeating unit in the superlattice portion farther from the substrate has a second dopant with a second dopant concentration. The second dopant concentration is greater than, equal to, or less than the first dopant concentration. The first dopant and the second dopant are independently selected from carbon or iron. Alternatively, the first dopant and the second dopant can also be carbon and iron.

[0015] In some embodiments, the substrate includes a substrate material and at least one insulating material. The at least one insulating material coats all surfaces of the substrate material.

[0016] In some embodiments, the semiconductor structure further includes a channel layer located on the buffer layer, a blocking layer located on the channel layer, a first compound semiconductor layer located between the buffer layer and the channel layer, and a second compound semiconductor layer located on the blocking layer.

[0017] This invention provides a semiconductor device comprising the aforementioned semiconductor structure, a gate electrode located on a barrier layer, and source and drain electrodes located on opposite sides of the gate electrode. This semiconductor device is a high-electron mobility transistor (HEMT).

[0018] This invention provides a buffer layer including a barrier layer, which can prevent lattice dislocations from extending to the upper channel layer, thereby improving the performance of the semiconductor device. Furthermore, by increasing the thickness of the barrier layer to a specific range, the occurrence of lattice dislocations in the film layer above the barrier layer can be further reduced. In addition, by sandwiching the barrier layer between multiple superlattice portions, the occurrence of lattice dislocations in the upper film layer can be reduced even more effectively. Furthermore, by alternating the stacking of multiple barrier layers and multiple superlattice portions, the occurrence of lattice dislocations in the upper film layer can be further reduced, thereby improving semiconductor performance. Attached Figure Description

[0019] Figure 1 , Figure 2 , Figure 3 , Figure 4 A schematic cross-sectional view of a semiconductor structure is shown for some embodiments of the present invention.

[0020] Figure 5 A schematic cross-sectional view of a semiconductor device is shown for some embodiments of the present invention.

[0021] Symbol Explanation

[0022] 102: Substrate

[0023] 102C: Substrate

[0024] 102M: Insulating material

[0025] 104: Seed layer

[0026] 104H: High-temperature layer

[0027] 104L: Low Temperature Layer

[0028] 106: Buffer layer

[0029] 108: First compound semiconductor layer

[0030] 110: Channel Layer

[0031] 112: Barrier layer

[0032] 114: Second compound semiconductor layer

[0033] BL1: First Barrier Layer

[0034] BL2: Second Barrier Layer

[0035] BL3: Third Barrier Layer

[0036] D: Drain electrode

[0037] G: Gate electrode

[0038] S: Source electrode

[0039] SL1: First superlattice section

[0040] SL2: Second superlattice

[0041] SL3: Third superlattice

[0042] SL4: Fourth Superlattice

[0043] SLU: Repeating Unit

[0044] SLU1: First Sublayer

[0045] SLU2: Second Sublayer

[0046] TBL1: Thickness of the first barrier layer

[0047] TSL1: Thickness of the first superlattice portion

[0048] TSL2: Thickness of the second superlattice Detailed Implementation

[0049] The following provides a detailed description of the semiconductor structure and its formation method disclosed herein. It should be understood that the following description provides different embodiments or examples for implementing different configurations of this disclosure. The specific elements and arrangements described below are merely for illustrative purposes and are not intended to limit the scope of this disclosure. Furthermore, if the description mentions that a first element is formed on top of a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements so that they are not in direct contact. Additionally, reference numerals and / or letters may be repeated in different examples of embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0050] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0051] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0052] Here, the terms "about" or "approximately" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%. The quantities given here are approximate, meaning that the meaning of "about" or "approximately" may be implied even without specific specification.

[0053] Embodiments of the present invention provide a semiconductor structure. This semiconductor structure includes a substrate, a seed layer on the substrate, and a buffer layer on the seed layer. The buffer layer includes at least one superlattice portion on the seed layer and at least one barrier layer on the superlattice portion. The thickness of the barrier layer is from 10 nanometers to 600 nanometers.

[0054] This invention improves semiconductor device performance by providing a barrier layer on the superlattice portion to prevent lattice dislocations from extending to subsequent epitaxially grown channel layers, barrier layers, etc. Furthermore, by increasing the thickness of the barrier layer to a specific range, the occurrence of lattice dislocations in the film layers on the barrier layer can be further reduced, thus more effectively improving the performance of the semiconductor device.

[0055] The present invention will now be described in detail with reference to specific embodiments. Figure 1 , Figure 2 , Figure 3 , Figure 4 An exemplary cross-sectional view illustrating the semiconductor structure in this embodiment is provided. Figure 5 An exemplary cross-sectional view of the semiconductor device in the embodiments of this case is provided.

[0056] like Figure 1 As shown, a substrate 102 is provided. In some embodiments, the substrate 102 may be silicon-on-insulator (SOI).

[0057] In some embodiments, substrate 102 includes a substrate 102C and an insulating material 102M encapsulating the substrate 102C. The insulating material 102M prevents diffusion of the substrate 102C and also blocks the substrate 102C from interacting with other film layers or process equipment. In some embodiments, substrate 102C may comprise a ceramic material. The ceramic material comprises a metallic inorganic material. In some embodiments, substrate 102C may comprise silicon carbide, aluminum nitride (AlN), sapphire, or other suitable materials. The sapphire substrate is aluminum oxide. In some embodiments, the insulating material 102M may be a single or multiple insulating material layers covering all surfaces (including the top and bottom surfaces and all sides) of substrate 102C. The insulating material layers are, for example, oxides, nitrides, or other suitable insulating materials. In some other embodiments, the insulating material 102M surrounding substrate 102C may include, in addition to multiple insulating material layers, other suitable material layers, such as semiconductor layers. In some embodiments, the semiconductor layer, for example, is a polycrystalline silicon layer disposed between these insulating material layers. To simplify the illustrations, only a single layer of insulating material 102M is shown in the accompanying drawings to clearly illustrate the method of forming the semiconductor structure.

[0058] like Figure 1 As shown, a seed layer 104 is formed on a substrate 102. In some embodiments, the seed layer 104 may be formed of silicon (Si), aluminum nitride (AlN), or other suitable materials. In some embodiments, the seed layer 104 may comprise one or more layers of suitable materials. In some embodiments, the seed layer 104 may comprise a low-temperature layer 104L grown at a low temperature and a high-temperature layer 104H grown at a high temperature on the substrate 102. In some embodiments, both the low-temperature layer 104L and the high-temperature layer 104H are aluminum nitride (AlN). In some embodiments, the low-temperature layer 104L has a thickness of about 0.5 to 2 nanometers (nm), and the high-temperature layer 104H has a thickness of about 100 to 300 nanometers (nm). In some embodiments, island-shaped alumina (low-temperature layer 104L) is first formed at a low temperature, followed by the formation of a higher-quality alumina (high-temperature layer 104H) at a high temperature to reduce the subsequent generation of lattice dislocations.

[0059] In some embodiments, the method for forming the seed layer 104 may include selective areagrowth (SAG), chemical vapor deposition (CVD), molecular-beam epitaxy (MBE), solid-phase epitaxial recrystallization (SPER) after deposition of a doped amorphous semiconductor (e.g., Si), direct seeding, or other suitable processes. Chemical vapor deposition processes include, for example, vapor-phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHV-CVD), or other suitable processes.

[0060] like Figure 1 As shown, a buffer layer 106 is formed on the seed layer 104. The buffer layer 106 can reduce the strain caused by the stress of the channel layer subsequently formed above the buffer layer and prevent defects (e.g., lattice dislocations) from forming in the channel layer above it.

[0061] In some embodiments, the buffer layer 106 includes at least one superlattice portion SL1 and at least one blocking layer BL1 located on the at least one superlattice portion SL1. Specifically, there may be N1 superlattice portions SL1 and N2 blocking layers BL1, where N1 and N2 are positive integers greater than or equal to 1. The relationship between the number of superlattice portions and the number of blocking layers will be described in detail below with reference to various embodiments. For example, Figure 1 The embodiment discloses a superlattice section and a barrier layer (N1=1 & N2=1); Figure 2 The embodiments reveal two superlattice sections and one barrier layer (N1=2 & N2=1); Figure 3 The embodiments reveal two superlattice sections and two barrier layers (N1=2 & N2=2); Figure 4 The embodiments disclosed have 4 superlattice portions and 3 barrier layers (N1=4 & N2=3). It should be noted that although the embodiments of this application only disclose the number of superlattice portions and barrier layers as described above, those skilled in the art to which this invention pertains can arbitrarily increase or adjust the number of superlattice portions and barrier layers by applying the inventive concept of this application, as long as they do not exceed the scope of the claims of this application.

[0062] In Figure 1 the embodiment, the buffer layer 106 includes a superlattice portion SL1 and a blocking layer BL1. That is, N1 is 1 (N1 = 1) and N2 is 1 (N2 = 1). At this time, N1 is equal to N2 (N1 = N2). Subsequently, for simplicity of description, the superlattice portion SL1 may also be referred to as the first superlattice portion SL1, and the blocking layer BL1 may also be referred to as the first blocking layer BL1.

[0063] In some embodiments, the thickness TSL1 of the first superlattice portion SL1 may be 800 to 6000 nanometers, or 1000 to 5000 nanometers, or 1500 to 4000 nanometers. In some embodiments, the first superlattice portion SL1 may include a plurality of repeating units (unit) SLU stacked m1 times, where m1 is a positive integer. In some embodiments, m1 may be 20 to 120, or 30 to 100, or 40 to 80.

[0064] In some embodiments, any one of the repeating units SLU in the first superlattice portion SL1 includes a first sub-layer SLU1 and a second sub-layer SLU2 on the first sub-layer SLU1. The first sub-layer SLU1 has a thickness of a1 nanometers, and the second sub-layer SLU2 has a thickness of a2 nanometers.

[0065] In some embodiments, the first sub-layer SLU1 is thinner than the second sub-layer SLU2. That is, a1 is less than a2 (a1 < a2). In some embodiments, a1 may be 1 - 14, and a2 may be 1 - 20.

[0066] In some embodiments, the first sub-layer SLU1 and the second sub-layer SLU2 may be III-V semiconductor materials, such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), gallium nitride (GaN), indium gallium nitride (InGaN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or a combination of the above. In the embodiments of the present invention, the first sub-layer SLU1 is aluminum nitride (AlN) and the second sub-layer SLU2 is aluminum gallium nitride (AlGaN).

[0067] In some embodiments, the first sub-layer SLU1 and the second sub-layer SLU2 may be formed by hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (metalorganic chemical vapordeposition, MOCVD), a combination of the foregoing methods, or a similar method.

[0068] In some embodiments, a first barrier layer BL1 is formed on the first superlattice portion SL1. In some embodiments, the thickness of the first barrier layer BL1 can be from 10 nanometers to 600 nanometers, preferably from 20 nanometers to 300 nanometers, and more preferably from 30 nanometers to 120 nanometers. It should be noted that when expressing a numerical range as "X1 to X2," it can include values ​​between X1 and X2 itself, as well as values ​​between X1 and X2, or it can exclude X1 and X2 themselves and only include values ​​between X1 and X2. See Table 1 below for reference:

[0069] [Table 1]

[0070] Thickness of the barrier layer none 33nm 50nm 66nm 100nm Enhanced efficiency - 13％ 20％ 26％ 36％

[0071] As mentioned above, without a barrier layer, the barrier layer thickness is displayed as "none". Compared to not having a barrier layer, setting the barrier layer thickness to 33nm, 50nm, 66nm, and 100nm can improve performance by 13%, 20%, 26%, and 36%, respectively.

[0072] In some embodiments, the barrier layer BL1 can be a III-V semiconductor material, such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), gallium nitride (GaN), indium gallium nitride (InGaN), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. In this embodiment of the invention, since AlN is a superlattice material, aluminum nitride (AlN) is used as the material of the barrier layer BL1. This reduces the generation of surface defects and provides better adhesion.

[0073] In some embodiments, the barrier layer BL1 may be doped or undoped. If it is doped, the dopant may be carbon or iron to further reduce lattice dislocations in the overlying channel layer. In some embodiments, the dopant concentration may be 1E15-1E20.

[0074] In some embodiments, the barrier layer BL1 may be formed by hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), a combination of the foregoing methods, or similar methods.

[0075] Continuing from the above, by setting a barrier layer BL1 on the superlattice section SL1, defects can be prevented from extending into the upper channel layer. Furthermore, by increasing the thickness of the barrier layer BL1 to a certain range, defects in the upper channel layer can be reduced, thereby improving performance by 10% to 50%.

[0076] Next, refer to Figure 2 . Figure 2 Similar to Figure 1 , the difference is that the buffer layer 106 includes two superlattice portions SL1 and SL2. Specifically, in Figure 2 of the embodiment, the buffer layer 106 includes two superlattice portions SL1 and SL2 and a barrier layer BL1. That is, N1 is 2 (N1 = 2) and N2 is 1 (N2 = 1). At this time, N1 is greater than N2 (N1 > N2) and the difference between N1 and N2 is 1 (N1 - N2 = 1). Here, the superlattice portion SL2 disposed on the barrier layer BL1 can also be referred to as the second superlattice portion SL2. In Figure 2 of the embodiment, the first barrier layer BL1 is sandwiched between the first superlattice portion SL1 and the second superlattice portion SL2.

[0077] In some embodiments, the thickness TSL2 of the second superlattice portion SL2 is greater than or equal to the thickness TSL1 of the first superlattice portion SL1 (TSL2 ≥ TSL1). In other words, the thickness TSL1 of the first superlattice portion SL1 close to the substrate 100 is less than or equal to the thickness TSL2 of the second superlattice portion SL2 away from the substrate 100 (TSL1 ≤ TSL2). In some embodiments, the thickness TSL2 of the second superlattice portion SL2 can be 1000 to 7000 nanometers, or 1500 to 6000 nanometers, or 2000 to 5000 nanometers. In some embodiments, the second superlattice portion SL2 can include multiple repeating units (unit) SLU stacked m2 times, where m2 is a positive integer. In some embodiments, m2 can be the same as m1 (m2 = m1), for example, m2 can be 20 to 120, or 30 to 100, or 40 to 80. Or, m2 can be greater than m1 (m2 > m1), for example, m2 can be 30 to 150, or 40 to 120, or 50 to 100.

[0078] In some embodiments, any repeating unit SLU in the second superlattice portion SL2 is similar to any repeating unit SLU in the first superlattice portion SL1. Specifically, the third sublayer SLU3 and the fourth sublayer SLU4 included in any repeating unit SLU in the second superlattice portion SL2 are similar to the first sublayer SLU1 and the second sublayer SLU2. The third sublayer SLU3 has a thickness of a3 nanometers, and the fourth sublayer SLU4 has a thickness of a4 nanometers.

[0079] In some embodiments, the third sublayer SLU3 is thinner than the fourth sublayer SLU4. That is, a3 is less than a4 (a3 < a4). In some embodiments, a3 can be 1 - 20, and a4 can be 1 - 20.

[0080] In some embodiments, the thickness of the first sub-layer SLU1 is less than the thickness of the third sub-layer SLU3. That is, a1 is less than a3 (a1 < a3). In other words, the thickness of the first sub-layer SLU1 in the first superlattice portion SL1 close to the substrate 100 is less than the thickness of the third sub-layer SLU3 in the second superlattice portion SL2 away from the substrate 100.

[0081] In some embodiments, the thickness of the second sub-layer SLU2 is equal to the thickness of the fourth sub-layer SLU4. That is, a2 is equal to a4 (a2 = a4). In other words, the thickness of the second sub-layer SLU2 in the first superlattice portion SL1 close to the substrate 100 is approximately equal to the thickness of the fourth sub-layer SLU4 in the second superlattice portion SL2 away from the substrate 100.

[0082] In some embodiments, the materials of the third sub-layer SLU3 and the fourth sub-layer SLU4 can be similar to or the same as those of the first sub-layer SLU1 and the second sub-layer SLU2. For example, the third sub-layer SLU3 is aluminum nitride (AlN) and the fourth sub-layer SLU4 is aluminum gallium nitride (AlGaN). In some other embodiments, the second sub-layer SLU2 and the fourth sub-layer SLU4 can have different composition ratios of aluminum gallium nitride (AlGaN). For example, the second sub-layer SLU2 can be Alx1Ga1-x1N, and the fourth sub-layer SLU4 can be Alx2Ga1-x2N, where x1 is less than x2 (x1 < x2). In other words, the second sub-layer SLU2 of the first superlattice portion SL1 close to the substrate 100 has a lower aluminum (Al) molar fraction, and the fourth sub-layer SLU4 of the second superlattice portion SL2 away from the substrate 100 has a higher aluminum (Al) molar fraction.

[0083] In some embodiments, the first sub-layer SLU1 and the second sub-layer SLU2 of the first superlattice portion SL1 and the third sub-layer SLU3 and the fourth sub-layer SLU4 of the second superlattice portion SL2 can be doped or undoped respectively. In the case where it is doped, the dopants can be independently carbon or iron to further reduce the lattice misalignment in the upper channel layer.

[0084] In some other embodiments, the dopant concentration of the second sub-layer SLU2 of the first superlattice portion SL1 close to the substrate 100 can be less than the dopant concentration of the fourth sub-layer SLU4 of the second superlattice portion SL2 away from the substrate 100. Thereby further reducing the lattice misalignment in the upper channel layer.

[0085] In some embodiments, the formation of the second superlattice portion SL2 is similar to the formation of the first superlattice portion SL1, which will not be elaborated here.

[0086] In other embodiments, when a first barrier layer BL1 is already provided between the first superlattice portion SL1 and the second superlattice portion SL2, a third superlattice portion (not shown) or a fourth superlattice portion (not shown) may also be formed directly on the second superlattice portion SL2 to facilitate stress buffering.

[0087] Continuing from the above, by including two (or more) superlattice sections in the buffer layer, stress buffering is more effective in preventing defects from forming in the upper channel layer.

[0088] Next, refer to Figure 3 . Figure 3 Similar to Figure 2 The difference lies in that the buffer layer 106 includes two blocking layers BL1 and BL2. Specifically, in Figure 3 In this embodiment, the buffer layer 106 includes two superlattice portions SL1 and SL2 and two barrier layers BL1 and BL2. That is, N1 is 2 (N1 = 2) and N2 is 2 (N2 = 2). At this time, N1 equals N2 (N1 = N2) and the difference between N1 and N2 is 0 (N1 - N2 = 0). Here, the barrier layer BL2 disposed on the second superlattice portion SL2 can also be referred to as the second barrier layer BL2. Figure 3 In this embodiment, the layers are arranged from bottom to top as follows: a first superlattice portion SL1, a first barrier layer BL1, a second superlattice portion SL2, and a second barrier layer BL2. That is, the barrier layers BL1 and BL2 are stacked alternately with the superlattice portions SL1 and SL2. This further reduces the extension of lattice dislocations in the superlattice portion into the upper channel layer.

[0089] In some embodiments, the thickness TBL2 of the second barrier layer BL2 may be greater than, equal to, or less than the thickness TBL1 of the first barrier layer BL1. In some embodiments, the thickness TBL2 of the second barrier layer BL2 is approximately equal to the thickness TBL1 of the first barrier layer BL1 (TBL2 = TBL1), thereby reducing costs while minimizing the formation of defects in the overlying channel layer. In some embodiments, the second barrier layer BL2 may be made of a material similar to the first barrier layer BL1, such as aluminum nitride (AlN), which will not be elaborated further here.

[0090] Continuing from the above, by including two (or more) barrier layers in the buffer layer, it is more effective in preventing defects from forming in the upper channel layer.

[0091] Next, refer to Figure 4 . Figure 4 Similar to Figure 3The difference lies in that the buffer layer 106 includes four superlattice sections SL1, SL2, SL3, and SL4, and three barrier layers BL1, BL2, and BL3. That is, N1 is 4 (N1 = 4) and N2 is 3 (N2 = 3). In this case, N1 is greater than N2 (N1 > N2) and the difference between N1 and N2 is 1 (N1 - N2 = 1). Here, the superlattice section SL3, the barrier layer BL3, and the superlattice section SL4 disposed on the second barrier layer BL2 can also be referred to as the third superlattice section SL3, the third barrier layer BL3, and the fourth superlattice section SL4, respectively. Figure 4 In the embodiment, the first barrier layer BL1, the second barrier layer BL2, and the third barrier layer BL3 are respectively sandwiched between the first superlattice portion SL1 and the second superlattice portion SL2, between the second superlattice portion SL2 and the third superlattice portion SL3, and between the third superlattice portion SL3 and the fourth superlattice portion SL4. It should be noted that, to better highlight... Figure 4 The embodiment is characterized by omitting the repeating units in all superlattice sections, and also simplifying the substrate 102 and seed layer 104 as a single layer.

[0092] The table below will explore the improved semiconductor performance of other numbers of superlattice sections and barrier layers, based on one superlattice section (N1) and one barrier layer (N2).

[0093] [Table 2]

[0094] Number of superlattice units (N1) 1 2 2 4 Number of barrier layers (N2) 1 1 2 3 Enhanced efficiency - 10％ 20％ 30％

[0095] Continuing from the above, increasing the number of superlattice units (N1) and barrier layers (N2) can more effectively improve semiconductor performance. This is because by staggering multiple superlattice units and multiple barrier layers, the formation of defects in the channel layer can be more effectively reduced, and stress buffering is more beneficial.

[0096] Next, refer to Figure 5 . Figure 5 This is an example of a semiconductor device. This semiconductor device can be, for example, a high-electron-mobility transistor (HEMT). In some embodiments, Figure 5 Applications of semiconductor devices Figure 4 The semiconductor structure. That is, Figure 5 The semiconductor device further includes a channel layer 110 and a barrier layer 112 formed on the buffer layer 106.

[0097] like Figure 5As shown, a channel layer 110 is formed on a buffer layer 106. In some embodiments, the channel layer 110 comprises an undoped III-V semiconductor material. For example, the channel layer 110 may be formed of undoped gallium nitride (GaN), but the present invention is not limited thereto. In some other embodiments, the channel layer 110 is formed of unintentionally doped (UID) gallium nitride (GaN) and thus has free carriers therein. In some other embodiments, the channel layer 110 comprises aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), gallium nitride (GaN), indium gallium nitride (InGaN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or a combination of the above. In some embodiments, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), other suitable methods, or a combination of the above methods may be used to form the channel layer 110.

[0098] As Figure 5 As shown, a blocking layer 112 is formed on the channel layer 110. In some embodiments, the blocking layer 112 may comprise a doped or undoped III-V semiconductor material. For example, the blocking layer 112 may be formed of undoped aluminum gallium nitride (AlxGa1-xN, where 0 < x < 1), but the present invention is not limited thereto. In some other embodiments, the blocking layer 112 may also comprise aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), gallium nitride (GaN), indium gallium nitride (InGaN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or a combination of the above. For example, molecular beam epitaxy, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the above methods may be used to form the blocking layer 112 on the channel layer 110.

[0099] In some embodiments, the channel layer 110 and the barrier layer 112 may comprise different materials, such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN), respectively, to form a heterogeneous interface between the channel layer 110 and the barrier layer 112. The band gap difference between the heterogeneous materials allows a two-dimensional electron gas (2DEG) (not shown) to be formed on this heterogeneous interface. Semiconductor devices formed according to some embodiments, such as high electron mobility transistor (HEMT) devices, can utilize the two-dimensional electron gas as a conductive charge carrier.

[0100] In addition to the channel layer 110 and the barrier layer 112, Figure 5 Embodiments may further include a first compound semiconductor layer 108 doped with carbon to improve the breakdown voltage of the semiconductor structure. For example... Figure 5 As shown, a first compound semiconductor layer 108 is formed on the buffer layer 106 to serve as an electrical buffer layer. In some embodiments, the first compound semiconductor layer 108 may be carbon-doped gallium nitride (C-GaN).

[0101] In addition to the channel layer 110 and the barrier layer 112, Figure 5 Embodiments may further include a second compound semiconductor layer 114 to serve as a switch for a semiconductor device. Figure 5 In some embodiments, the fabrication of an enhanced-mode (i.e., normally-off) high electron mobility transistor is used as an example. In some embodiments, the second compound semiconductor layer 114 can be a P-type doped III-V semiconductor material, such as P-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium (InGaAs), other suitable III-V materials, or combinations thereof. In some embodiments, the second compound semiconductor layer 114 can be formed of P-type doped gallium nitride (P-GaN). In some embodiments, the method for forming the second compound semiconductor layer 114 can include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial processes, ion implantation, or in-situ doping processes.

[0102] also, Figure 5 An embodiment may further include a gate electrode G, and a source electrode S and a drain electrode D formed on opposite sides of the gate electrode G, respectively.

[0103] In some embodiments, the gate electrode G is connected to the second compound semiconductor layer 114. A Schottky contact is formed between the gate electrode G and the second compound semiconductor layer 114. In some embodiments, the gate electrode G may comprise a metallic material, a metal silicide, polysilicon, other suitable conductive materials, or a combination thereof. In some embodiments, the gate electrode G may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (such as sputtering), or similar processes.

[0104] In some embodiments, a source electrode S and a drain electrode D are formed on opposite sides of the gate electrode G. In some embodiments, as shown in Figure 1E, the source electrode S and the drain electrode D are located on the channel layer 110 and are electrically contacted with the channel layer 110. In some embodiments, the source electrode S and the drain electrode D comprise conductive materials, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi2), combinations thereof, or similar materials. In some embodiments, the source electrode S and the drain electrode D may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (such as sputtering), electron beam evaporation, or similar processes. In some embodiments, after depositing material layers to form the source electrode S and the drain electrode D, a high-temperature thermal process, such as rapid thermal annealing, is performed to form source-drain ohmic contacts.

[0105] In summary, the embodiments of the present invention provide a buffer layer including a barrier layer, which can prevent lattice dislocations from extending to the upper channel layer, thereby improving the performance of the semiconductor device. Furthermore, by increasing the thickness of the barrier layer to a specific range, the occurrence of lattice dislocations in the film layer above the barrier layer can be further reduced. In addition, by sandwiching the barrier layer between multiple superlattice portions, lattice dislocations in the upper film layer can be reduced even more effectively. Furthermore, by alternating the stacking of multiple barrier layers and multiple superlattice portions, the occurrence of lattice dislocations in the upper film layer can be further reduced, thereby improving semiconductor performance.

[0106] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of these embodiments. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this invention.

Claims

1. A semiconductor structure, characterized in that, include: One substrate; A seed layer is located on the substrate; as well as A buffer layer is located above the seed layer, wherein the buffer layer comprises: At least one superlattice portion is located on the seed layer, wherein there are N1 superlattice portions; and At least one barrier layer is located on the superlattice portion, wherein there are N² barrier layers, and the thickness of the at least one barrier layer is from 10 nanometers to 600 nanometers. Where N1 and N2 are positive integers that are greater than or equal to 1.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer ranges from 30 nanometers to 120 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The barrier layer is AlN.

4. The semiconductor structure as described in claim 1, characterized in that, N1 is greater than or equal to N2.

5. The semiconductor structure as described in claim 1, characterized in that, The difference between N1 and N2 is 1.

6. The semiconductor structure as described in claim 5, characterized in that, The at least one barrier layer is sandwiched between any two superlattice portions in the at least one superlattice portion.

7. The semiconductor structure as described in claim 5, characterized in that, The barrier layer is stacked alternately with the superlattice.

8. The semiconductor structure as described in claim 1, characterized in that, When N1 is 2 or higher, the thickness of the superlattice portion closer to the substrate is less than the thickness of the superlattice portion farther from the substrate.

9. The semiconductor structure as described in claim 1, characterized in that, The superlattice comprises multiple repeating units stacked m1 times, each of the multiple repeating units comprising: A first sublayer having a thickness of a1 nanometers; and A second sublayer is located on the first sublayer and has a thickness of a2 nanometers, where m1 is a positive integer.

10. The semiconductor structure as described in claim 9, characterized in that, The first sublayer is aluminum nitride, and the second sublayer is AlGaN.

11. The semiconductor structure as described in claim 9, characterized in that, a1 is less than a2.

12. The semiconductor structure as claimed in claim 9, characterized in that, m1 ranges from 20 to 120.

13. The semiconductor structure as described in claim 9, characterized in that, When N1 is 2 or more, the thickness of the first sublayer in each repeating unit of the superlattice portion close to the substrate is set to a11 nanometers, and the thickness of the first sublayer in each repeating unit of the superlattice portion away from the substrate is set to a12 nanometers, wherein a11 is less than a12.

14. The semiconductor structure as claimed in claim 9, characterized in that, When N1 is 2 or more, the thickness of the second sublayer in each repeating unit of the superlattice portion close to the substrate is set to a21 nanometers, and the thickness of the second sublayer in each repeating unit of the superlattice portion away from the substrate is set to a22 nanometers, where a21 is equal to a22.

15. The semiconductor structure as described in claim 9, characterized in that, When N1 is 2 or more, the second sublayer in each repeating unit of the superlattice portion close to the substrate has a first dopant with a first dopant concentration, and the second sublayer in each repeating unit of the superlattice portion away from the substrate has a second dopant with a second dopant concentration, wherein the second dopant concentration is greater than or equal to the first dopant concentration.

16. The semiconductor structure as claimed in claim 15, characterized in that, The first dopant and the second dopant are independently carbon or iron or a combination of carbon and iron.

17. The semiconductor structure as claimed in claim 1, characterized in that, The substrate includes a base material and at least one insulating material, wherein the at least one insulating material covers the base material.

18. The semiconductor structure as claimed in claim 1, characterized in that, Including: A channel layer is located on top of this buffer layer; A barrier layer is located on top of the channel layer; A first compound semiconductor layer is located between the buffer layer and the channel layer; and A second compound semiconductor layer is located on the barrier layer.

19. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 18; A gate electrode is located on the barrier layer; as well as A source electrode and a drain electrode are located on opposite sides of the gate electrode.

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