Chip, preparation method thereof, and electronic device

Abstract

The application provides a chip and a preparation method thereof and an electronic device, relates to the technical field of semiconductors, and improves the channel carrier mobility by using germanium, improves the interface quality between the first electrode (and / or the second electrode) and the channel, and improves the performance of the vertical transistor. The chip comprises a substrate, a vertical transistor and a buffer layer arranged on the substrate, and the vertical transistor comprises a first electrode, a second electrode, a channel and a gate structure. In the direction of the substrate pointing to the vertical transistor, the first electrode, the channel and the second electrode are sequentially arranged in layers; the gate structure is located on at least one side of the sidewall of the channel, and the gate structure comprises a gate electrode and a gate dielectric for isolating the gate electrode from the channel. The materials of the channel and the buffer layer both comprise germanium silicon, the atomic percentage of germanium in the germanium silicon of the buffer layer is less than the atomic percentage of germanium in the germanium silicon of the channel; the buffer layer comprises a first buffer layer and / or a second buffer layer, the first buffer layer is located between the first electrode and the channel, and the second buffer layer is located between the channel and the second electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, and an electronic device. Background Technology

[0002] Vertical transistors are a key technology for achieving chip miniaturization. One of their core advantages is that by defining the critical dimension (CD) in a direction perpendicular to the substrate, the limitation of gate length on the contacted gate pitch (CGP) is solved, thereby significantly reducing parasitic capacitance in the chip, improving the performance of vertical transistors, and reducing power consumption.

[0003] For vertical transistors, due to their bottom-up process, the source and drain of the vertical transistor cannot generate stress on the channel, and the stress cannot be used to improve the mobility of charge carriers in the channel, thus reducing the driving characteristics of the vertical transistor. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip and its fabrication method, as well as an electronic device. In addition to utilizing germanium to improve the carrier mobility in the channel, it can also improve the interface quality between the first electrode and the channel, and / or the interface quality between the second electrode and the channel, thereby improving the performance of the vertical transistor.

[0005] In a first aspect, this application provides a chip comprising a substrate, a vertical transistor disposed on the substrate, and a buffer layer. The vertical transistor includes a first electrode, a second electrode, a channel, and a gate structure. The first electrode, channel, and second electrode are sequentially stacked along the direction from the substrate to the vertical transistor. The gate structure is located on at least one side of the channel sidewall and includes a gate electrode and a gate dielectric for isolating the gate electrode from the channel. Both the channel and the buffer layer are made of germanium-silicon, and the atomic percentage of germanium in the germanium-silicon of the buffer layer is less than the atomic percentage of germanium in the germanium-silicon of the channel. The buffer layer includes a first buffer layer and / or a second buffer layer, the first buffer layer being located between the first electrode and the channel, and the second buffer layer being located between the channel and the second electrode.

[0006] In this application, by increasing the atomic percentage of germanium (Ge) in the channel, the carrier mobility of the channel is improved, thereby enhancing the switching characteristics of the vertical transistor.

[0007] Based on this, in the case where the buffer layer includes a first buffer layer but does not include a second buffer layer, the first buffer layer is located between the first electrode and the channel. Since the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer is less than the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel, the first buffer layer can be used to buffer the flow, improve the interface contact quality between the first electrode and the channel, and also help to reduce lattice defects in the channel, improve the lattice quality of the channel, thereby improving the performance of the vertical transistor.

[0008] Alternatively, if the buffer layer includes a second buffer layer but does not include a first buffer layer, the second buffer layer is located between the channel and the second electrode. Since the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer is less than the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel, the second buffer layer can be used to buffer the flow, improve the interface contact quality between the second electrode and the channel, and thus improve the performance of the vertical transistor.

[0009] Alternatively, in the case where the buffer layer includes a first buffer layer and a second buffer layer, the first buffer layer is located between the first electrode and the channel, and the second buffer layer is located between the channel and the second electrode. Since the atomic percentage of germanium (Ge) in both the first and second buffer layers is less than the atomic percentage of germanium (Ge) in the channel, the first and second buffer layers can act as buffers, improving the interface contact quality between the first electrode and the channel, as well as the interface contact quality between the second electrode and the channel. This also helps to reduce lattice defects in the channel, improve the lattice quality of the channel, and thus improve the performance of the vertical transistor.

[0010] In some possible implementations, the first buffer layer comprises multiple stacked first sub-buffer layers, wherein germanium occupies the same atomic percentage in the same first sub-buffer layer, and the atomic percentage of germanium in the germanium-silicon of the multiple first sub-buffer layers differs, with the atomic percentage of germanium gradually increasing in the germanium-silicon of the multiple first sub-buffer layers along the direction from the first electrode to the channel. Alternatively, the atomic percentage of germanium in the germanium-silicon of the first buffer layer gradually increases along the direction from the first electrode to the channel.

[0011] Compared to the scheme where the atomic percentage of germanium (Ge) is the same at all positions in the germanium-silicon (SiGe) first buffer layer, the scheme where the atomic percentage of germanium (Ge) gradually increases in the germanium-silicon (SiGe) first buffer layer can not only improve the performance of the vertical transistor by improving the interface contact quality between the first electrode and the channel and improving the lattice quality of the channel, but also ensure the interface quality between the first buffer layer and the first electrode, thereby ensuring the electrical properties of the vertical transistor.

[0012] In some possible implementations, the second buffer layer comprises multiple stacked second sub-buffer layers, where germanium occupies the same atomic percentage in each second sub-buffer layer, but the atomic percentage of germanium differs in each of the multiple germanium-silicon layers, and the atomic percentage of germanium gradually increases in the germanium-silicon layers of the multiple second sub-buffer layers along the direction from the second electrode to the channel. Alternatively, the atomic percentage of germanium in the germanium-silicon layers of the second buffer layer gradually increases along the direction from the second electrode to the channel.

[0013] Compared to the scheme where the atomic percentage of germanium (Ge) is the same at all positions in the germanium-silicon (SiGe) layer of the second buffer layer, the scheme where the atomic percentage of germanium (Ge) gradually increases in the germanium-silicon (SiGe) layer of the second buffer layer can not only improve the performance of the vertical transistor by improving the interface contact quality between the second electrode and the channel, but also ensure the interface quality between the first buffer layer and the second electrode, thereby ensuring the electrical properties of the vertical transistor.

[0014] In some possible implementations, germanium accounts for more than 50% of the atomic percentage in the germanium-silicon of the channel, and less than or equal to 50% of the atomic percentage in the germanium-silicon of the buffer layer, to ensure that the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel is large enough to improve the mobility of charge carriers in the channel and improve the driving characteristics of the vertical transistor.

[0015] In some possible implementations, the gate dielectric material includes oxide. The chip also includes a capping layer disposed between the channel and the gate structure, and the capping layer is made of silicon. Because the interface trap density of germanium (Ge) and silicon (Si) is low, the quality is good, and there are fewer defects, the current drive characteristics of the vertical transistor can be effectively improved.

[0016] Optionally, the thickness of the capping layer ranges from 1 nm to 4 nm along the direction of the gate structure between the channels.

[0017] In some possible implementations, the vertical transistor is a single-gate vertical transistor, a ring-gate vertical transistor, or a dual-gate vertical transistor.

[0018] In some possible implementations, the vertical transistor is a P-type vertical transistor to improve the carrier mobility of the P-type transistor.

[0019] Alternatively, the vertical transistor includes P-type and N-type vertical transistors, with the channel of the P-type vertical transistor being the first channel and the channel of the N-type vertical transistor being the second channel. The atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first channel is greater than that of germanium in the germanium-silicon (SiGe) of the second channel. In this way, by adjusting the atomic percentage of germanium (Ge) in germanium-silicon (SiGe), the carrier mobility of the P-type vertical transistor can be improved, making the driving characteristics of the P-type and N-type vertical transistors consistent.

[0020] Secondly, this application provides a method for fabricating a chip, comprising: forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on a substrate; sequentially stacking the first electrode, channel, and second electrode along a direction from the substrate to the first electrode; the buffer layer comprising a first buffer layer and / or a second buffer layer, the first buffer layer being located between the first electrode and the channel, and the second buffer layer being located between the channel and the second electrode; both the channel and the buffer layer being made of germanium-silicon, wherein the atomic percentage of germanium in the germanium-silicon of the buffer layer is less than the atomic percentage of germanium in the germanium-silicon of the channel; removing the dummy gate; forming a gate structure at the location of the removed dummy gate, the gate structure being located on at least one side of the channel sidewall, the gate structure comprising a gate and a gate dielectric for isolating the gate and the channel.

[0021] In some possible implementations, forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on a substrate includes: sequentially forming multiple layers of first buffer films on the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same first buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multiple layers of first buffer films is different, and the atomic percentage of germanium in the germanium-silicon of the multiple layers of first buffer films gradually increases along the direction from the first electrode to the channel. A semiconductor layer and a hard mask are sequentially formed on the side of the multiple layers of first buffer films facing away from the substrate. Under the protection of the hard mask, the semiconductor layer and the multiple layers of first buffer films are etched to obtain the channel and the first buffer layer, the first buffer layer including multiple first sub-buffer layers. The first electrode is formed using ion implantation or selective epitaxy. A dummy gate is formed on the sidewall of the channel and on the side of the first electrode facing away from the substrate. The hard mask is removed, and the second electrode is formed on the side of the channel facing away from the substrate.

[0022] In some possible implementations, a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate are formed on a substrate, including: sequentially forming a semiconductor layer, multiple layers of second buffer films, and a hard mask on the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same second buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multiple layers of second buffer films is different, and the atomic percentage of germanium in the germanium-silicon of the multiple layers of second buffer films gradually increases along the direction from the second electrode to the channel. Under the protection of the hard mask, the multiple layers of second buffer films and the semiconductor layer are etched to obtain the second buffer layer and the channel, the second buffer layer including multiple layers of second sub-buffer layers. The first electrode is formed using ion implantation or selective epitaxy. A dummy gate is formed on the sidewalls of the channel and on the side of the first electrode facing away from the substrate. The hard mask is removed, and the second electrode is formed on the side of the channel facing away from the substrate.

[0023] In some possible implementations, forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on a substrate includes: sequentially forming multiple layers of first buffer films on the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same first buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multiple first buffer films is different, and the atomic percentage of germanium in the germanium-silicon of the multiple first buffer films gradually increases along the direction from the first electrode to the channel. A semiconductor layer is formed on the side of the multiple first buffer films facing away from the substrate. Multiple layers of second buffer films and a hard mask are sequentially formed on the side of the semiconductor layer facing away from the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same second buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multiple second buffer films is different, and the atomic percentage of germanium in the germanium-silicon of the multiple second buffer films gradually increases along the direction from the second electrode to the channel. Under the protection of a hard mask, the multilayer second buffer film, semiconductor layer, and first buffer film layer are etched to obtain the second buffer layer, channel, and first buffer layer. The first buffer layer includes multiple first sub-buffer layers, and the second buffer layer includes multiple second sub-buffer layers. An ion implantation or selective epitaxy process is used to form the first electrode. A dummy gate is formed on the sidewall of the channel. The hard mask is removed, and the second electrode is formed on the side of the channel facing away from the substrate.

[0024] In some possible implementations, after forming a dummy gate on the sidewall of the channel and before forming the second electrode on the side of the channel away from the substrate, the chip fabrication method further includes: forming a sacrificial layer on at least one sidewall of a hard mask; filling a dielectric layer into the region between adjacent sacrificial layers; removing the hard mask and sacrificial layers to form a cutout; and forming the second electrode on the side of the channel away from the substrate, including filling the cutout with the second electrode. In this way, during the etching of the second spacer layer, a protective layer can be used to protect the second electrode, preventing damage to the second electrode from the etching material used to etch the second spacer layer.

[0025] In some possible implementations, after removing the dummy gate and before forming the gate structure at the location of the removed dummy gate, the chip fabrication method further includes: forming a capping layer located between the channel and the gate structure; the capping layer is made of silicon.

[0026] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0027] Thirdly, this application provides an electronic device, including a circuit board and the chip described in the first aspect, wherein the chip is disposed on the circuit board.

[0028] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0029] Figure 1a A schematic diagram of an electronic device provided in an embodiment of this application;

[0030] Figure 1b An interaction diagram of the various modules in the memory provided in the embodiments of this application;

[0031] Figure 2 A structural diagram of a vertical transistor provided for related technologies;

[0032] Figures 3a-3c This is a structural diagram of the chip provided in an embodiment of this application;

[0033] Figures 4a-4d This is a structural diagram of the chip provided in an embodiment of this application;

[0034] Figure 5 This is a structural diagram of the chip provided in an embodiment of this application;

[0035] Figure 6 This is a structural diagram of the chip provided in an embodiment of this application;

[0036] Figure 7 This is a flowchart illustrating the fabrication process of the chip provided in an embodiment of this application.

[0037] Figures 8a-8e This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0038] Figure 9 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0039] Figure 10 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0040] Figures 11a-11h This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0041] Figures 12a-12c The preparation process diagram provided for the embodiments of this application;

[0042] Figures 13a-13c The preparation process diagram provided for the embodiments of this application;

[0043] Figure 14 A flowchart illustrating the fabrication process of the chip provided in this application embodiment;

[0044] Figures 15a-15d This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0045] Figure 16 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0046] Figure 17 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0047] Figures 18a-18g This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0048] Figures 19a-19c The preparation process diagram provided for the embodiments of this application;

[0049] Figures 20a-20b The preparation process diagram provided for the embodiments of this application;

[0050] Figure 21 A flowchart illustrating the fabrication process of the chip provided in this application embodiment;

[0051] Figures 22a-22d This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0052] Figure 23 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0053] Figure 24 This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0054] Figures 25a-25g This is a diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0055] Figures 26a-26c The preparation process diagram provided for the embodiments of this application;

[0056] Figures 27a-27c This is a diagram illustrating the preparation process provided in the embodiments of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0059] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0060] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0061] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0062] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or other device containing vertical transistors.

[0063] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other devices containing vertical transistors.

[0064] Take the memory in electronic devices as an example. Figure 1aThis application provides a schematic diagram of the structure of a memory in an electronic device. The electronic device includes a circuit board, a memory, and other chips or independent devices. The other chips or independent devices may include a processor. The memory and other chips or independent devices are disposed on the circuit board. The memory in the embodiments of this application may be DRAM, resistive random-access memory (RRAM), magnetic random-access memory (MRAM), ferroelectric random-access memory (FeRAM), etc.

[0065] like Figure 1b As shown, the memory includes a storage array, a controller, row decoders, column decoders, etc. The processor can send the address of the selected storage cell to the row decoders and column decoders through the controller. After decoding the received address, the row decoders and column decoders determine the storage cell in the storage array as the selected storage cell, and then perform read and write operations on the selected storage cell. The storage cell includes transistors and capacitors.

[0066] The transistors in the memory cell can be vertical transistors. Vertical transistors are a key technology for achieving chip miniaturization. One of their core advantages is that by defining the critical dimension (CD) in a direction perpendicular to the substrate, the limitation of gate length on the contacted gate pitch (CGP) is solved, thereby significantly reducing parasitic capacitance in the chip, improving the performance of vertical transistors, and reducing power consumption.

[0067] Vertical transistors solve the limitation of gate length on gate spacing. This means that because the gate length of a vertical transistor is perpendicular to the horizontal direction, even a longer gate length will not affect the transistor's dimensions in the planar direction, and thus will not affect the area of ​​the memory chip in the planar direction. The vertical direction is the direction from the chip substrate to the vertical transistor; the planar direction is perpendicular to the vertical direction.

[0068] Furthermore, vertical transistors can also be applied to other modules of electronic devices, and this application does not limit this application. For example, vertical transistors can be applied to logic circuits such as central processing units (CPUs) and static random-access memory (SRAM).

[0069] However, as Figure 2As shown in the background section, since the fabrication process of the first electrode 13, channel 12, and second electrode 18 in a vertical transistor involves sequentially forming the first electrode 13, channel 12, and second electrode 18, and these electrodes are stacked sequentially, i.e., the vertical transistor's process flow is from bottom to top, the stress exerted by the first electrode 13 and second electrode 18 on the channel 12 is easily released. Even if the materials of the first electrode 13 and second electrode 18 contain germanium-silicon (SiGe), the stress exerted by the first electrode 13 and second electrode 18 on the channel 12 cannot be retained. That is, the first electrode 13 and second electrode 18 cannot generate stress on the channel 12, and therefore cannot utilize stress to improve the carrier mobility in the channel 12, resulting in a decrease in the driving characteristics of the vertical transistor, for example, a slower turn-on speed. Here, the first electrode 13 is the source, and the second electrode 18 is the drain; or, the first electrode 13 is the drain, and the second electrode 18 is the source.

[0070] Because germanium has a high carrier mobility, germanium-silicon (SiGe) can be used as the material for channel 12. The atomic percentage of germanium-Ge in germanium-silicon (SiGe) varies, affecting the electrical performance of the vertical transistor.

[0071] If the atomic percentage of germanium (Ge) in germanium-silicon (SiGe) is low, then under stress-free conditions in channel 12, alloy scattering in the germanium-silicon (SiGe) of channel 12 will dominate, affecting the electrical and thermal properties of channel 12 and providing almost no improvement to the electrical performance of the vertical transistor. If the atomic percentage of germanium (Ge) in germanium-silicon (SiGe) is high, although it increases the carrier mobility in channel 12 of the vertical transistor, a high concentration of germanium (Ge) will lead to a deterioration in the interface contact quality between channel 12 and the first electrode 13, as well as the interface contact quality between channel 12 and the second electrode 18, thus weakening the electrical performance of the vertical transistor.

[0072] Based on this, embodiments of this application provide a chip, such as... Figures 3a-3c As shown, the chip includes a substrate 10 and a buffer layer in addition to vertical transistors, with the buffer layer and vertical transistors disposed on the substrate. The buffer layer includes a first buffer layer 11 and / or a second buffer layer 30.

[0073] For a vertical transistor, a first electrode 13, a channel 12, and a second electrode 18 are sequentially stacked along the direction from the substrate 10 to the vertical transistor. The gate structure is located on at least one side of the sidewall of the channel 12. The gate structure includes a gate 20 and a gate dielectric 19 for isolating the gate 20 from the channel 12. If the gate structure is located on one side of the sidewall of the channel 12, the vertical transistor is a single-gate vertical transistor; if the gate structure is located on both sides of the sidewall of the channel 12 (e.g., on opposite sides of the channel 12), the vertical transistor is a double-gate vertical transistor; if the gate structure surrounds the channel 12, the vertical transistor is a ring-gate vertical transistor.

[0074] Both the channel 12 and the buffer layer are made of germanium-silicon (SiGe). The atomic percentage of germanium-Ge in the buffer layer is less than that in the channel 12. For example, the atomic percentage of germanium-Ge in the buffer layer is 40%, while that in the channel 12 is 55%. By increasing the atomic percentage of germanium-Ge in the channel 12, the carrier mobility of the channel 12 is improved, thereby enhancing the switching characteristics of the vertical transistor.

[0075] Based on this, such as Figure 3a As shown, when the buffer layer includes a first buffer layer 11 but excludes a second buffer layer 30, the first buffer layer 11 is located between the first electrode 13 and the channel 12. Since the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer 11 is less than the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel 12, the first buffer layer 11 can be used to buffer the flow, improve the interface contact quality between the first electrode 13 and the channel 12, and also help to reduce lattice defects in the channel 12, improve the lattice quality of the channel 12, thereby improving the performance of the vertical transistor.

[0076] Or, such as Figure 3b As shown, when the buffer layer includes a second buffer layer 30 but excludes the first buffer layer 11, the second buffer layer 30 is located between the channel 12 and the second electrode 18. Since the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30 is less than the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel 12, the second buffer layer 30 can be used to buffer the flow, improve the interface contact quality between the second electrode 18 and the channel 12, and thus improve the performance of the vertical transistor.

[0077] Or, such as Figure 3c As shown, when the buffer layer includes a first buffer layer 11 and a second buffer layer 30, the first buffer layer 11 is located between the first electrode 13 and the channel 12, and the second buffer layer 30 is located between the channel 12 and the second electrode 18. Since the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer 11 and the second buffer layer 30 is smaller than the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the channel 12, the first buffer layer 11 and the second buffer layer 30 can be used to buffer the transistor, improve the interface contact quality between the first electrode 13 and the channel 12, and the interface contact quality between the second electrode 18 and the channel 12, and also help to reduce lattice defects in the channel 12, improve the lattice quality of the channel 12, thereby improving the performance of the vertical transistor.

[0078] In some possible implementations, the first buffer layer 11 can be a single-layer structure or a stacked structure.

[0079] like Figure 3a As shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is 60%.

[0080] Or, such as Figure 4a As shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 gradually increases along the direction from the first electrode 13 to the channel 12. For example, along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 increases from 52% to 70%. Figure 4a The darker the black filling in the first buffer layer 11, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer 11.

[0081] like Figure 4b As shown, when the first buffer layer 11 is a stacked structure, the first buffer layer 11 may include multiple stacked first sub-buffer layers. The atomic percentage of germanium (Ge) in the same first sub-buffer layer (GeSiGe) is the same, while the atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) is different. Furthermore, along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) gradually increases. Figure 4b The darker the black filling in the first sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first sub-buffer layer.

[0082] Compared to Figure 3a The scheme shown has the same atomic percentage of germanium (Ge) at all positions in the germanium-silicon (SiGe) layer 11. Figure 4a and Figure 4b The scheme shown, in which the atomic percentage of germanium (Ge) in the first buffer layer 11 gradually increases, can not only improve the performance of the vertical transistor by improving the interface contact quality between the first electrode 13 and the channel 12 and improving the lattice quality of the channel 12, but also ensure the interface quality between the first buffer layer 11 and the first electrode 13, thereby ensuring the electrical properties of the vertical transistor.

[0083] Correspondingly, the second buffer layer 30 can be a single-layer structure or a stacked structure.

[0084] like Figure 3bAs shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is 70%.

[0085] Or, such as Figure 4c As shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30 gradually increases along the direction from the second electrode 18 to the channel 12. For example, along the direction from the second electrode 18 to the channel 12, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30 increases from 55% to 65%. Figure 4c The darker the black filling in the second buffer layer 30, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30.

[0086] like Figure 4d As shown, when the second buffer layer 30 is a stacked structure, the second buffer layer 30 may include multiple stacked second sub-buffer layers. The atomic percentage of germanium (Ge) in the same second sub-buffer layer (GeSiGe) is the same. The atomic percentage of germanium (Ge) in the multiple second sub-buffer layers (GeSiGe) is different, and along the direction from the second electrode 18 to the channel 12, the atomic percentage of germanium (Ge) in the multiple second sub-buffer layers (GeSiGe) gradually increases. Figure 4d The darker the black filling in the second sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) sub-buffer layer.

[0087] Compared to Figure 3b The scheme shown has the same atomic percentage of germanium (Ge) at all positions in the germanium-silicon (SiGe) layer 30 of the second buffer layer 30. Figure 4c and Figure 4d The scheme shown, in which the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 30 gradually increases, can not only improve the performance of the vertical transistor by improving the interface contact quality between the second electrode 18 and the channel 12, but also ensure the interface quality between the first buffer layer 11 and the second electrode 18, thereby ensuring the electrical properties of the vertical transistor.

[0088] Of course, the configuration of the first buffer layer 11 and the second buffer layer 30 can also be other, and this application embodiment does not limit this, as long as the atomic percentage of germanium Ge in the germanium-silicon SiGe of the first buffer layer 11 and the atomic percentage of germanium Ge in the germanium-silicon SiGe of the second buffer layer 30 are both less than the atomic percentage of Ge in the germanium-silicon SiGe of the channel 12.

[0089] Optionally, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) buffer layer is less than or equal to 50%, and the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) channel 12 is greater than 50%, to ensure that the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) channel 12 is large enough, thereby improving the carrier mobility in the channel 12 and improving the driving characteristics of the vertical transistor.

[0090] In some embodiments, the material of the gate dielectric 19 typically includes oxides. Ge-O bonds are formed at the interface between the channel 12 and the gate dielectric 19. However, the interface trap density of germanium (Ge) and oxygen (O) is relatively high, the quality is relatively poor, and there are many defects. Therefore, the subthreshold characteristics, mobility, and reliability of the vertical transistor are all affected.

[0091] Based on this, such as Figure 6 As shown, the chip also includes a capping layer 40, which is disposed between the channel 12 and the gate structure. The material of the capping layer 40 includes silicon. Since the interface trap density of germanium (Ge) and silicon (Si) is low, the quality is good, and there are fewer defects, the current drive characteristics of the vertical transistor can be effectively improved.

[0092] In some possible implementations, the thickness of the capping layer 40 is not limited in the embodiments of this application. Optionally, the thickness of the capping layer 40 in the direction from the channel 12 to the gate structure is in the range of 1 nm to 4 nm.

[0093] In some embodiments, the carrier mobility of a P-type vertical transistor is lower than that of an N-type vertical transistor. Therefore, the vertical transistor provided in this application embodiment can be a P-type transistor to improve the carrier mobility of the P-type transistor.

[0094] Alternatively, if the chip includes both N-type and P-type vertical transistors, then the driving characteristics of the P-type and N-type vertical transistors are inconsistent.

[0095] In the embodiments of this application, the carrier mobility of the vertical transistor can be improved by increasing the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of channel 12. Therefore, for a P-type vertical transistor, the carrier mobility of the P-type vertical transistor can be improved by increasing the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of channel 12, thereby improving the switching characteristics of the P-type vertical transistor and making the driving characteristics of the P-type vertical transistor and the N-type vertical transistor consistent.

[0096] Optionally, the channel 12 of the P-type vertical transistor is the first channel, and the channel 12 of the N-type vertical transistor is the second channel. The atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first channel is greater than that in the germanium-silicon (SiGe) of the second channel. In this way, by adjusting the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe), the carrier mobility of the P-type vertical transistor can be improved, making the driving characteristics of the P-type and N-type vertical transistors consistent.

[0097] In some embodiments, such as Figure 6 As shown, the chip may also include a protective layer 25, which is disposed on the side of the second electrode 18 away from the substrate 10 and on the sidewall of the second electrode 18, so as to protect the second electrode 18 when etching other structures (such as the dielectric layer and the second spacer layer mentioned below) and prevent the etching material from damaging the second electrode 18.

[0098] In another embodiment, this application also provides a method for fabricating a chip, wherein the buffer layer in the chip includes a first buffer layer but does not include a second buffer layer, such as... Figure 7 As shown, this can be achieved through the following steps:

[0099] S110 forms a first electrode 13, a buffer layer, and a channel 12 on a substrate 10.

[0100] Specifically, such as Figures 8a-8c As shown, a first buffer film 111, a semiconductor layer 121, and a hard mask 22 can be formed sequentially on the substrate 10, and the first buffer film 111, the semiconductor layer 121, and the hard mask 22 are stacked together.

[0101] In some possible ways of implementation, such as Figure 8c As shown, after forming the semiconductor layer 121 and before forming the hard mask 22, an oxide layer 21 can also be formed on the semiconductor layer 121 to utilize the oxide layer 21 as a buffer to avoid the hard mask 22 from generating stress on the vertical transistor.

[0102] Next, as Figure 8d As shown, the hard mask 22 (or the hard mask 22 and the oxide layer 21) is patterned, and under the protection of the hard mask 22 (or the hard mask 22 and the oxide layer 21), the semiconductor layer 121 and the first buffer film 111 are etched using self-aligned X patterning technology to obtain the patterned channel 12 and the first buffer layer 11.

[0103] Next, as Figure 8e As shown, the first pole 13 is formed by means of injection or selective epitaxy.

[0104] It should be understood that if the number of vertical transistors is one, then subsequent steps do not require... Figure 8e The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically connected, then subsequent steps do not require etching. Figure 8e The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically isolated, then after the gate is formed, further etching is required. Figure 8e The first electrode 13 shown is etched to obtain the first electrode 13 of each vertical transistor.

[0105] Of course, other processes can also be used to form the first electrode 13, the first buffer layer 11, and the channel 12, and this application embodiment does not limit this.

[0106] In some possible implementations, the first buffer layer 11 can be a single-layer structure or a stacked structure.

[0107] like Figure 3a As shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is 60%.

[0108] Or, such as Figure 4a As shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 gradually increases along the direction from the first electrode 13 to the channel 12. For example, along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 increases from 52% to 70%. Figure 4a The darker the black filling in the first buffer layer 11, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer 11.

[0109] like Figure 4b As shown, when the first buffer layer 11 has a stacked structure, multiple first buffer films 111 are formed. Under the protection of a hard mask 22, the multiple first buffer films 111 are etched to obtain a first buffer layer 11 containing multiple first sub-buffer layers. The atomic percentage of germanium (Ge) in the same first sub-buffer layer (GeSiGe) is the same. The atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) is different, and along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) gradually increases. Figure 4bThe darker the black filling in the first sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first sub-buffer layer.

[0110] S120, such as Figure 9 As shown, a first spacer layer 14 is formed on the side of the first electrode 13 away from the substrate 10, so as to isolate the first electrode 13 from the gate 20 to be formed, and prevent the first electrode 13 from being electrically connected to the gate 20 to be formed.

[0111] Optionally, after depositing the first spacer layer 14, the first spacer layer 14 can also be planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize the first spacer layer 14 so that the surface of the first spacer layer 14 facing away from the substrate 10 is relatively flat, thereby achieving that the gate length of the gate 20 disposed on the first spacer layer 14 is consistent at each position.

[0112] S130, such as Figure 10 As shown, a gate oxide layer 15 and a dummy gate 16 are formed on the side of the first spacer layer 14 opposite to the substrate 10. The gate oxide layer 15 is disposed between the channel 12 and the dummy gate 16.

[0113] In some possible implementations, the material of the dummy gate 16 may include amorphous silicon, polycrystalline silicon, etc. After forming the film layer of the dummy gate 16, a chemical mechanical polishing (CMP) process can be used to planarize the dummy gate 16 to obtain a dummy gate 16 with a smooth surface.

[0114] S140, such as Figures 11a-11c As shown, a second spacer layer 17 and a dielectric layer 24 are sequentially formed on the side of the gate oxide layer 15 and the dummy gate 16 facing away from the substrate 10. The second spacer layer 17 isolates the gate 20 to be formed and the second electrode 18, preventing the gate 20 from being electrically connected to the second electrode 18. The dielectric layer 24 fills the spaces between adjacent hard masks 22 (or between adjacent hard masks 22 and between adjacent oxide layers 21).

[0115] In some possible ways of implementation, such as Figures 11b-11c As shown, after forming the second spacer layer 17 and before forming the dielectric layer 24, a sacrificial layer 23 may be formed on at least one sidewall of the hard mask 22. The specific location and size of the sacrificial layer 23 are related to the location and size of the second electrode 18 to be formed, and are not limited in this embodiment.

[0116] S150, such as Figure 11d and Figure 11eAs shown, the hard mask 22 is removed to form a cutout, and a second electrode 18 is filled into the cutout. The second electrode 18 is positioned where the original hard mask 22 was. Next, as... Figure 11f and Figure 11h As shown, the dielectric layer 24 is removed, and the second spacer layer 17 is etched.

[0117] In some possible implementations, if a sacrificial layer 23 is also formed on at least one sidewall of the hard mask 22, then after forming the dielectric layer 24, the sacrificial layer 23 is removed in addition to removing the hard mask 22. After removing the hard mask 22 and the sacrificial layer 23, a cutout is formed, and a second electrode 18 is formed in the cutout. The second electrode 18 is disposed at the original location of the hard mask 22 and the sacrificial layer 23. In this way, the size and position of the second electrode 18 can be determined according to the size and position of the sacrificial layer 23 and the hard mask 22.

[0118] In some possible ways of implementation, such as Figure 11e As shown, in addition to filling the hollow portion with the second electrode 18, a protective layer 25 can also be filled into the hollow portion. The protective layer 25 is disposed on the side of the second electrode 18 facing away from the substrate 10. Furthermore, as... Figure 11g As shown, after removing the dielectric layer 24, a protective layer 25 can also be formed on the sidewall of the second electrode 18, thus, as Figure 11h As shown, during the etching process of the second spacer layer 17, the protective layer 25 can be used to protect the second electrode 18 and prevent the second electrode 18 from being damaged by the etching material used to etch the second spacer layer 17.

[0119] It should be understood that if the protective layer 25 is not formed before etching the second spacer layer 17, the orthogonal projection of the edge of the etched second spacer layer 17 onto the substrate 10 coincides with the orthogonal projection of the edge of the second electrode 18 onto the substrate 10. If the protective layer 25 is formed before etching the second spacer layer 17, the orthogonal projection of the edge of the etched second spacer layer 17 onto the substrate 10 coincides with the orthogonal projection of the edge of the protective layer 25 onto the substrate 10.

[0120] S160, such as Figure 12a As shown, the dummy gate 16 and gate oxide layer 15 are removed. Next, as... Figure 12b and Figure 12c As shown, a gate dielectric 19 and a gate 20 are sequentially formed on at least one side of the channel 12.

[0121] If the gate structure is located on one side of the sidewall of the channel 12, the vertical transistor is a single-gate vertical transistor; if the gate structure is located on both sides of the sidewall of the channel 12 (for example, the gate structure is located on opposite sides of the channel 12), the vertical transistor is a double-gate vertical transistor; if the gate structure is located around the channel 12, the vertical transistor is a ring-gate vertical transistor.

[0122] In some possible implementations, as mentioned in step S110, if there is only one vertical transistor, then etching of the first electrode 13 is not required after step S160. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically connected, then etching of the first electrode 13 is also not required after step S160. Figure 13a As shown, if there are multiple vertical transistors and the first electrode 13 of the multiple vertical transistors is electrically isolated, then after forming the gate 20 in step S160, the first electrode 13 needs to be etched to obtain the first electrode 13 of each vertical transistor.

[0123] Next, as Figure 13b As shown, an interlayer spacer layer 26 is formed between adjacent vertical transistors to isolate them.

[0124] Next, as Figure 13c As shown, a dielectric layer 27 and a conductive layer 28 are sequentially formed on the side of the vertical transistor facing away from the substrate 10. A via is formed in the dielectric layer 27, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the via in the dielectric layer 27. If the chip also includes a protective layer 25, a via is also formed in the protective layer 25, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the vias in the dielectric layer 27 and the protective layer 25.

[0125] In another embodiment, this application also provides a method for fabricating a chip, wherein the buffer layer in the chip includes a second buffer layer but does not include a first buffer layer, such as... Figure 14 As shown, this can be achieved through the following steps:

[0126] S210, a first electrode 13, a channel 12, and a buffer layer are formed on the substrate 10.

[0127] Specifically, such as Figures 15a-15c As shown, a semiconductor layer 121, a second buffer film 301, and a hard mask 22 can be formed sequentially on a substrate 10, and the semiconductor layer 121, the second buffer film 301, and the hard mask 22 are stacked together.

[0128] In some possible ways of implementation, such as Figure 15b As shown, after forming the semiconductor layer 121 and before forming the hard mask 22, an oxide layer 21 can also be formed on the semiconductor layer 121 to utilize the oxide layer 21 as a buffer to avoid the hard mask 22 from generating stress on the vertical transistor.

[0129] Next, as Figure 15cAs shown, the hard mask 22 (or the hard mask 22 and the oxide layer 21) is patterned, and under the protection of the hard mask 22 (or the hard mask 22 and the oxide layer 21), the second buffer film 301 and the semiconductor layer 121 are etched using self-aligned X patterning technology to obtain the patterned second buffer layer 30 and the channel 12.

[0130] Next, as Figure 15d As shown, the first pole 13 is formed by means of injection or selective epitaxy.

[0131] It should be understood that if the number of vertical transistors is one, then subsequent steps do not require... Figure 15d The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically connected, then subsequent steps do not require etching. Figure 15d The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically isolated, then after the gate is formed, further etching is required. Figure 15d The first electrode 13 shown is etched to obtain the first electrode 13 of each vertical transistor.

[0132] Of course, other processes can also be used to form the first electrode 13, the channel 12, and the second buffer layer 30, and this application embodiment does not limit this.

[0133] In some possible implementations, the second buffer layer 30 can be a single-layer structure or a stacked structure.

[0134] like Figure 3b As shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is 60%.

[0135] Or, such as Figure 4c As shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 30 gradually increases along the direction from the channel 12 to the first electrode 13. For example, along the direction from the channel to the first electrode 13, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 30 increases from 52% to 70%. Figure 4c The darker the black filling in the second buffer layer 30, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30.

[0136] like Figure 4dAs shown, when the second buffer layer 30 has a stacked structure, multiple layers of second buffer films 301 are formed. Under the protection of a hard mask 22, the multiple layers of second buffer films 301 are etched to obtain a second buffer layer 30 containing multiple second sub-buffer layers. The atomic percentage of germanium (Ge) in the same second sub-buffer layer (GeSiGe) is the same. The atomic percentage of germanium (Ge) in the multiple layers of second sub-buffer layers (GeSiGe) is different, and along the direction from the channel 12 to the first electrode 13, the atomic percentage of germanium (Ge) gradually increases in the multiple layers of second sub-buffer layers (GeSiGe). Figure 4d The darker the black filling in the second sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) sub-buffer layer.

[0137] S220, such as Figure 16 As shown, a first spacer layer 14 is formed on the side of the first electrode 13 away from the substrate 10, so as to isolate the first electrode 13 from the gate 20 to be formed, and prevent the first electrode 13 from being electrically connected to the gate 20 to be formed.

[0138] Optionally, after depositing the first spacer layer 14, the first spacer layer 14 can also be planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize the first spacer layer 14 so that the surface of the first spacer layer 14 facing away from the substrate 10 is relatively flat, thereby achieving that the gate length of the gate 20 disposed on the first spacer layer 14 is consistent at each position.

[0139] S230, such as Figure 17 As shown, a gate oxide layer 15 and a dummy gate 16 are formed on the side of the first spacer layer 14 opposite to the substrate 10. The gate oxide layer 15 is disposed between the channel 12 and the dummy gate 16.

[0140] In some possible implementations, the material of the dummy gate 16 may include amorphous silicon, polycrystalline silicon, etc. After forming the film layer of the dummy gate 16, a chemical mechanical polishing (CMP) process can be used to planarize the dummy gate 16 to obtain a dummy gate 16 with a smooth surface.

[0141] S240, such as Figures 18a-18c As shown, a second spacer layer 17 and a dielectric layer 24 are sequentially formed on the side of the gate oxide layer 15 and the dummy gate 16 facing away from the substrate 10. The second spacer layer 17 isolates the gate 20 to be formed and the second electrode 18, preventing the gate 20 from being electrically connected to the second electrode 18. The dielectric layer 24 fills the spaces between adjacent hard masks 22 (or between adjacent hard masks 22 and between adjacent oxide layers 21).

[0142] In some possible ways of implementation, such as Figures 18b-18cAs shown, after forming the second spacer layer 17 and before forming the dielectric layer 24, a sacrificial layer 23 may be formed on at least one sidewall of the hard mask 22. The specific location and size of the sacrificial layer 23 are related to the location and size of the second electrode 18 to be formed, and are not limited in this embodiment.

[0143] S250, such as Figure 18d and Figure 18e As shown, the hard mask 22 is removed to form a cutout, and a second electrode 18 is filled into the cutout. The second electrode 18 is positioned where the original hard mask 22 was. Next, as... Figure 18f and Figure 18g As shown, the dielectric layer 24 is removed, and the second spacer layer 17 is etched.

[0144] In some possible implementations, if a sacrificial layer 23 is also formed on at least one sidewall of the hard mask 22, then after forming the dielectric layer 24, the sacrificial layer 23 is removed in addition to removing the hard mask 22. After removing the hard mask 22 and the sacrificial layer 23, a cutout is formed, and a second electrode 18 is formed in the cutout. The second electrode 18 is disposed at the original location of the hard mask 22 and the sacrificial layer 23. In this way, the size and position of the second electrode 18 can be determined according to the size and position of the sacrificial layer 23 and the hard mask 22.

[0145] In some possible ways of implementation, such as Figure 18e As shown, in addition to filling the hollow portion with the second electrode 18, a protective layer 25 can also be filled into the hollow portion. The protective layer 25 is disposed on the side of the second electrode 18 facing away from the substrate 10. Furthermore, as... Figure 18g As shown, after removing the dielectric layer 24, a protective layer 25 can also be formed on the sidewall of the second electrode 18, thus, as Figure 18g As shown, during the etching process of the second spacer layer 17, the protective layer 25 can be used to protect the second electrode 18 and prevent the second electrode 18 from being damaged by the etching material used to etch the second spacer layer 17.

[0146] It should be understood that if the protective layer 25 is not formed before etching the second spacer layer 17, the orthogonal projection of the edge of the etched second spacer layer 17 onto the substrate 10 coincides with the orthogonal projection of the edge of the second electrode 18 onto the substrate 10. If the protective layer 25 is formed before etching the second spacer layer 17, the orthogonal projection of the edge of the etched second spacer layer 17 onto the substrate 10 coincides with the orthogonal projection of the edge of the protective layer 25 onto the substrate 10.

[0147] S260, such as Figure 19a As shown, the dummy gate 16 and gate oxide layer 15 are removed. Next, as... Figure 19b and Figure 19cAs shown, a gate dielectric 19 and a gate 20 are sequentially formed on at least one side of the channel 12.

[0148] If the gate structure is located on one side of the sidewall of the channel 12, the vertical transistor is a single-gate vertical transistor; if the gate structure is located on both sides of the sidewall of the channel 12 (for example, the gate structure is located on opposite sides of the channel 12), the vertical transistor is a double-gate vertical transistor; if the gate structure is located around the channel 12, the vertical transistor is a ring-gate vertical transistor.

[0149] In some possible implementations, as mentioned in step S210, if there is only one vertical transistor, then etching of the first electrode 13 is not required after step S260. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically connected, then etching of the first electrode 13 is also not required after step S260. Figure 19c As shown, if there are multiple vertical transistors and the first electrode 13 of the multiple vertical transistors is electrically isolated, then after forming the gate 20 in step S260, the first electrode 13 needs to be etched to obtain the first electrode 13 of each vertical transistor.

[0150] Next, as Figure 20a As shown, an interlayer spacer layer 26 is formed between adjacent vertical transistors to isolate them.

[0151] Next, as Figure 20b As shown, a dielectric layer 27 and a conductive layer 28 are sequentially formed on the side of the vertical transistor facing away from the substrate 10. A via is formed in the dielectric layer 27, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the via in the dielectric layer 27. If the chip also includes a protective layer 25, a via is also formed in the protective layer 25, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the vias in the dielectric layer 27 and the protective layer 25.

[0152] In another embodiment, this application also provides a method for fabricating a chip, wherein the buffer layer in the chip includes a first buffer layer and a second buffer layer, such as... Figure 21 As shown, this can be achieved through the following steps:

[0153] S310 forms a first electrode 13, a buffer layer, and a channel 12 on a substrate 10.

[0154] Specifically, such as Figures 22a-22c As shown, a first buffer film 111, a semiconductor layer 121, a second buffer film 301, and a hard mask 22 can be formed sequentially on the substrate 10, and the first buffer film 111, the semiconductor layer 121, the second buffer film 301, and the hard mask 22 are stacked.

[0155] In some possible ways of implementation, such as Figure 22c As shown, after forming the semiconductor layer 121 and before forming the hard mask 22, an oxide layer 21 can also be formed on the semiconductor layer 121 to utilize the oxide layer as a buffer to avoid the hard mask 22 from generating stress on the vertical transistor.

[0156] Next, as Figure 22c As shown, the hard mask 22 (or the hard mask 22 and the oxide layer 21) is patterned, and under the protection of the hard mask 22 (or the hard mask 22 and the oxide layer 21), the second buffer film 301, the semiconductor layer 121 and the first buffer film 111 are etched using self-aligned X patterning technology to obtain the patterned second buffer layer 30, the channel 12 and the first buffer layer 11.

[0157] Next, as Figure 22d As shown, the first pole 13 is formed by means of injection or selective epitaxy.

[0158] It should be understood that if the number of vertical transistors is one, then subsequent steps do not require... Figure 22d The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically connected, then subsequent steps do not require etching. Figure 22d The first electrode 13 shown is etched. If there are multiple vertical transistors, and the first electrodes 13 of the multiple vertical transistors are electrically isolated, then after the gate is formed, further etching is required. Figure 22d The first electrode 13 shown is etched to obtain the first electrode 13 of each vertical transistor.

[0159] Of course, other processes can also be used to form the first electrode 13, the first buffer layer 11, the channel 12, and the second buffer layer 30. This application does not limit this.

[0160] In some possible implementations, the first buffer layer 11 can be a single-layer structure or a stacked structure.

[0161] like Figure 3a As shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the first buffer layer 11 is 60%.

[0162] Or, such as Figure 4aAs shown, when the first buffer layer 11 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 gradually increases along the direction from the first electrode 13 to the channel 12. For example, along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 11 increases from 52% to 70%. Figure 4a The darker the black filling in the first buffer layer 11, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first buffer layer 11.

[0163] like Figure 4b As shown, when the first buffer layer 11 has a stacked structure, multiple first buffer films 111 are formed. Under the protection of a hard mask 22, the multiple first buffer films 111 are etched to obtain a first buffer layer 11 containing multiple first sub-buffer layers. The atomic percentage of germanium (Ge) in the same first sub-buffer layer (GeSiGe) is the same. The atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) is different, and along the direction from the first electrode 13 to the channel 12, the atomic percentage of germanium (Ge) in the multiple first sub-buffer layers (GeSiGe) gradually increases. Figure 4b The darker the black filling in the first sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the first sub-buffer layer.

[0164] Correspondingly, the second buffer layer 30 can be a single-layer structure or a stacked structure.

[0165] like Figure 3b As shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is the same. For example, the atomic percentage of germanium (Ge) at each position in the germanium-silicon (SiGe) of the second buffer layer 30 is 70%.

[0166] Or, such as Figure 4c As shown, when the second buffer layer 30 is a single-layer structure, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 30 gradually increases along the direction from the channel 12 to the first electrode 13. For example, along the direction from the channel 12 to the first electrode 13, the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) layer 30 increases from 55% to 65%. Figure 4c The darker the black filling in the second buffer layer 30, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) of the second buffer layer 30.

[0167] like Figure 4dAs shown, when the second buffer layer 30 is a stacked structure, the second buffer layer 30 may include multiple stacked second sub-buffer layers. The atomic percentage of germanium (Ge) in the same second sub-buffer layer (GeSiGe) is the same. The atomic percentage of germanium (Ge) in the multiple second sub-buffer layers (GeSiGe) is different, and along the direction from the channel 12 to the first electrode 13, the atomic percentage of germanium (Ge) in the multiple second sub-buffer layers (GeSiGe) gradually increases. Figure 4d The darker the black filling in the second sub-buffer layer, the greater the atomic percentage of germanium (Ge) in the germanium-silicon (SiGe) sub-buffer layer.

[0168] S320, such as Figure 23 As shown, a first spacer layer 14 is formed on the side of the first electrode 13 away from the substrate 10, so as to isolate the first electrode 13 from the gate 20 to be formed, and prevent the first electrode 13 from being electrically connected to the gate 20 to be formed.

[0169] S330, such as Figure 24 As shown, a gate oxide layer 15 and a dummy gate 16 are formed on the side of the first spacer layer 14 opposite to the substrate 10. The gate oxide layer 15 is disposed between the channel 12 and the dummy gate 16.

[0170] S340, such as Figures 25a-25c As shown, a second spacer layer 17 and a dielectric layer 24 are sequentially formed on the side of the gate oxide layer 15 and the dummy gate 16 facing away from the substrate 10. The second spacer layer 17 isolates the gate 20 to be formed and the second electrode 18, preventing the gate 20 from being electrically connected to the second electrode 18. The dielectric layer 24 fills the spaces between adjacent hard masks 22 (or between adjacent hard masks 22 and between adjacent oxide layers 21).

[0171] S350, such as Figure 25d and Figure 25e As shown, the hard mask 22 is removed to form a cutout, and a second electrode 18 is filled into the cutout. The second electrode 18 is positioned where the original hard mask 22 was. Next, as... Figure 25f and Figure 25g As shown, the dielectric layer 24 is removed, and the second spacer layer 17 is etched.

[0172] S360, such as Figure 26a As shown, the dummy gate 16 and gate oxide layer 15 are removed. Next, as... Figure 26b and Figure 26c As shown, a gate dielectric 19 and a gate 20 are sequentially formed on at least one side of the channel 12.

[0173] Next, as Figure 27a As shown, an interlayer spacer layer 26 is formed between adjacent vertical transistors to isolate them.

[0174] Next, as Figure 27b As shown, a dielectric layer 27 and a conductive layer 28 are sequentially formed on the side of the vertical transistor facing away from the substrate 10. A via is formed in the dielectric layer 27, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the via in the dielectric layer 27. If the chip also includes a protective layer 25, a via is also formed in the protective layer 25, and the conductive layer 28 is electrically connected to the second electrode 18 of the vertical transistor through the vias in the dielectric layer 27 and the protective layer 25.

[0175] Furthermore, the other explanations and beneficial effects of steps S320-S360 are the same as those of steps S120-S160 and S220-S260 mentioned above, and will not be repeated here.

[0176] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, It includes a substrate, a vertical transistor disposed on the substrate, and a buffer layer, wherein the vertical transistor includes a first electrode, a second electrode, a channel, and a gate structure; Along the direction from the substrate to the vertical transistor, the first electrode, the channel, and the second electrode are stacked sequentially; the gate structure is located on at least one side of the channel sidewall, and the gate structure includes a gate and a gate dielectric for isolating the gate from the channel; The channel and the buffer layer are both made of germanium-silicon, and the atomic percentage of germanium in the germanium-silicon of the buffer layer is less than the atomic percentage of germanium in the germanium-silicon of the channel; the buffer layer includes a first buffer layer and / or a second buffer layer, the first buffer layer being located between the first electrode and the channel, and the second buffer layer being located between the channel and the second electrode.

2. The chip according to claim 1, characterized in that, The first buffer layer comprises multiple stacked first sub-buffer layers, wherein the atomic percentage of germanium is the same in each of the same first sub-buffer layers, and the atomic percentage of germanium in the germanium-silicon of each of the multiple first sub-buffer layers is different. Furthermore, along the direction from the first electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multiple first sub-buffer layers gradually increases; or... Along the direction from the first electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the first buffer layer gradually increases.

3. The chip according to claim 1 or 2, characterized in that, The second buffer layer comprises multiple stacked second sub-buffer layers, wherein the atomic percentage of germanium is the same in each of the same second sub-buffer layers, and the atomic percentage of germanium in the germanium-silicon of each of the multiple second sub-buffer layers is different. Furthermore, along the direction from the second electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multiple second sub-buffer layers gradually increases; or... Along the direction from the second electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the second buffer layer gradually increases.

4. The chip according to any one of claims 1-3, characterized in that, The atomic percentage of germanium in the germanium-silicon of the channel is greater than 50%, while the atomic percentage of germanium in the germanium-silicon of the buffer layer is less than or equal to 50%.

5. The chip according to any one of claims 1-4, characterized in that, The material of the gate dielectric includes oxides; The chip also includes a capping layer disposed between the channel and the gate structure, the capping layer being made of silicon.

6. The chip according to claim 5, characterized in that, Along the direction of the gate structure between the channels, the thickness of the capping layer ranges from 1 nm to 4 nm.

7. The chip according to claim 5 or 6, characterized in that, The vertical transistor is a single-gate vertical transistor, a ring-gate vertical transistor, or a dual-gate vertical transistor.

8. The chip according to any one of claims 1-7, characterized in that, The vertical transistor is a P-type vertical transistor; or... The vertical transistor includes a P-type vertical transistor and an N-type vertical transistor. The channel of the P-type vertical transistor is a first channel, and the channel of the N-type vertical transistor is a second channel. The atomic percentage of germanium in the germanium-silicon of the first channel is greater than the atomic percentage of germanium in the germanium-silicon of the second channel.

9. A method for fabricating a chip, characterized in that, include: A first electrode, a buffer layer, a channel, a second electrode, and a dummy gate are formed on the substrate; Along the direction from the substrate to the first electrode, the first electrode, the channel, and the second electrode are sequentially stacked. The buffer layer includes a first buffer layer and / or a second buffer layer. The first buffer layer is located between the first electrode and the channel, and the second buffer layer is located between the channel and the second electrode. The materials of the channel and the buffer layer both include germanium-silicon, and the atomic percentage of germanium in the germanium-silicon of the buffer layer is less than the atomic percentage of germanium in the germanium-silicon of the channel. Remove the dummy gate; A gate structure is formed at the location of the removed dummy gate, the gate structure being located on at least one side of the channel sidewall, the gate structure including a gate and a gate dielectric for isolating the gate from the channel.

10. The method for fabricating a chip according to claim 9, characterized in that, The process of forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on the substrate includes: The multilayer first buffer film is formed sequentially on the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same first buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multilayer first buffer film is different, and along the direction from the first electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multilayer first buffer film gradually increases. A semiconductor layer and a hard mask are sequentially formed on the side of the multilayer first buffer film facing away from the substrate; Under the protection of the hard mask, the semiconductor layer and the multilayer first buffer film are etched to obtain the channel and the first buffer layer, wherein the first buffer layer includes multiple first sub-buffer layers; The first electrode is formed using ion implantation or selective epitaxy. The dummy gate is formed on the sidewall of the channel and on the side of the first electrode facing away from the substrate; Remove the hard mask and form the second electrode on the side of the channel away from the substrate.

11. The method for fabricating a chip according to claim 9, characterized in that, The process of forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on the substrate includes: A semiconductor layer, multiple layers of second buffer film, and a hard mask are sequentially formed on the substrate; wherein, the atomic percentage of germanium in the germanium-silicon of the same second buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multiple layers of second buffer films is different, and along the direction from the second electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multiple layers of second buffer films gradually increases. Under the protection of the hard mask, the multilayer second buffer film layer and the semiconductor layer are etched to obtain the second buffer layer and the channel. The second buffer layer includes multiple second sub-buffer layers. The first electrode is formed using ion implantation or selective epitaxy. The dummy gate is formed on the sidewall of the channel and on the side of the first electrode facing away from the substrate; Remove the hard mask and form the second electrode on the side of the channel away from the substrate.

12. The method for fabricating a chip according to claim 9, characterized in that, The process of forming a first electrode, a buffer layer, a channel, a second electrode, and a dummy gate on the substrate includes: The multilayer first buffer film is formed sequentially on the substrate; wherein the atomic percentage of germanium in the germanium-silicon of the same first buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multilayer first buffer film is different, and along the direction from the first electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multilayer first buffer film gradually increases. A semiconductor layer is formed on the side of the multilayer first buffer film facing away from the substrate; A multilayer second buffer film and a hard mask are sequentially formed on the side of the semiconductor layer away from the substrate; wherein, the atomic percentage of germanium in the germanium-silicon of the same second buffer film is the same, the atomic percentage of germanium in the germanium-silicon of the multilayer second buffer film is different, and along the direction from the second electrode to the channel, the atomic percentage of germanium in the germanium-silicon of the multilayer second buffer film gradually increases. Under the protection of the hard mask, the multilayer second buffer film, the semiconductor layer, and the first buffer film layer are etched to obtain the second buffer layer, the channel, and the first buffer layer. The first buffer layer includes multiple first sub-buffer layers, and the second buffer layer includes multiple second sub-buffer layers. The first electrode is formed using ion implantation or selective epitaxy. The dummy gate is formed on the sidewall of the channel; Remove the hard mask and form the second electrode on the side of the channel away from the substrate.

13. The method for fabricating a chip according to any one of claims 10-12, characterized in that, After forming the dummy gate on the sidewall of the channel and before forming the second electrode on the side of the channel away from the substrate, the chip fabrication method further includes: A sacrificial layer is formed on at least one sidewall of the hard mask; A dielectric layer is filled into the region between adjacent sacrificial layers; Remove the hard mask and the sacrificial layer to form a cutout; The formation of the second electrode on the side of the channel away from the substrate includes: The second pole is filled into the hollowed-out portion.

14. The method for fabricating a chip according to any one of claims 9-13, characterized in that, After removing the dummy gate and before forming a gate structure at the location of the removed dummy gate, the chip fabrication method further includes: A capping layer is formed between the channel and the gate structure; the material of the capping layer includes silicon.

15. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-8, the chip being disposed on the circuit board.

Images