LDMOS and LDMOS devices in a BCD process platform

Abstract

The application discloses an LDMOS and an LDMOS device in a BCD process platform, the LDMOS comprising a P-type well region and an N-type drift region prepared in a substrate, and respectively provided with a source region and a drain region. A gate region of the LDMOS is arranged on an upper surface of the substrate and is separated from the P-type well region and the N-type drift region through a gate oxide region. The gate region and the gate oxide region are sequentially arranged on the substrate, the gate region extends to the N-type drift region side with a length less than the extension length of the gate oxide region to the N-type drift region side, and a region of the gate oxide region not covered by the gate region is covered by an insulating layer. Since the added insulating layer spatially separates the gate region and the N-type drift region, the dispersion surface local electric field peak value is reduced, the drift region electric field distribution is optimized, the surface early breakdown is inhibited, and the withstand voltage margin is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOS and LDMOS device in a BCD process platform. Background Technology

[0002] DMOS stands for Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, primarily consisting of two types: VDMOS and LDMOS (Laterally Diffused MOSFET). LDMOS, with its advantages of high voltage withstand capability, high transconductance, and high gain, is widely used as a high-voltage power device in radio frequency power integrated circuits. An LDMOS device is composed of hundreds or thousands of individual LDMOS cells. In the 60nm BCD (Bipolar-CMOS-DMOS) process platform, the LDMOS device is the core component for achieving "high-voltage / high-current power switching capability," working in conjunction with on-chip low-voltage CMOS control and logic, as well as BJTs, ESD protection devices, and isolation devices to complete power conversion and intelligent control on the same chip. A crucial parameter for LDMOS devices is their breakdown voltage. Power semiconductor devices are preferably those capable of operating at voltages close to the theoretical breakdown voltage of semiconductors. In transistors integrating high voltage, the punch-through voltage between the drain / source and the semiconductor substrate, as well as the breakdown voltage between the drain / source and the well or substrate, must be greater than the operating voltage. As IC integration density increases and device feature sizes decrease, the gate oxide layer becomes increasingly thinner, significantly reducing its gate breakdown voltage. The breakdown voltage of LDMOS is a crucial parameter and a key aspect of its reliability. Although LDMOS possesses a low-doped drift region, giving it a higher breakdown voltage compared to other MOS devices, the increasing demand for high-voltage, high-power applications necessitates measures to further enhance its breakdown voltage to meet the requirements of high-frequency, high-voltage operation. Summary of the Invention

[0003] The main technical problem this invention addresses is how to improve the breakdown voltage of LDMOS.

[0004] According to a first aspect, one embodiment provides an LDMOS in a BCD process platform, including a P-type well region and an N-type drift region fabricated in a substrate; the source region of the LDMOS is disposed in the P-type well region, and the drain region of the LDMOS is disposed in the N-type drift region; the gate region of the LDMOS is disposed on the upper surface of the substrate and is isolated between the P-type well region and the N-type drift region by a gate oxide region.

[0005] The gate oxide region covers the substrate, the gate region covers the gate oxide region, the length of the gate region extending toward the N-type drift region is less than the length of the gate oxide region extending toward the N-type drift region, and the area of ​​the gate oxide region not covered by the gate region is covered by an insulating layer with a covering thickness greater than the thickness of the gate region covering the gate oxide region, and the insulating layer is used to spatially isolate the gate region and the N-type drift region.

[0006] In one embodiment, the extension length of the gate region toward the P-type well region is less than the extension length of the gate oxide region toward the P-type well region, and the area of ​​the gate oxide region not covered by the gate region is covered by an insulating layer with a covering thickness greater than the thickness of the gate region covering the gate oxide region. The insulating layer is used to spatially isolate the gate region and the P-type well region.

[0007] In one embodiment, the gate region includes a substrate region extending from the upper surface of the LDMOS to the substrate of the LDMOS and being completely isolated from the substrate by a gate oxide region; the source region and the drain region are respectively disposed on both sides of the substrate region.

[0008] In one embodiment, the depth of the under-substrate region extending into the LDMOS substrate is less than the depth of the source region and the drain region extending into the LDMOS substrate.

[0009] In one embodiment, the underliner region is an inverted trapezoidal groove mechanism.

[0010] In one embodiment, the substrate region of the trench gate is disposed on the connection boundary between the P-type well region and the N-type drift region.

[0011] In one embodiment, the upper surface of the P-type well region is further provided with a P-body region, which is isolated from the source region on the upper surface of the P-type well region by a shallow trench.

[0012] In one embodiment, the insulating layer is made of silicon nitride.

[0013] In one embodiment, the gate region is made of polysilicon; the gate oxide region is made of silicon dioxide; and / or, the LDMOS substrate is a P-type substrate.

[0014] According to a second aspect, one embodiment provides an LDMOS device comprising a plurality of MOS cells, wherein at least one MOS cell is an LDMOS as described in any one of claims 1 to 9.

[0015] According to the LDMOS of the above embodiment, an insulating layer is added to spatially isolate the gate region and the N-type drift region, reduce the peak value of the local electric field on the dispersion surface, optimize the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the withstand voltage margin. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a cross-sectional structure of an LDMOS.

[0017] Figure 2 This is a schematic diagram of the electric field line distribution of a planar LDMOS.

[0018] Figure 3 This is a schematic cross-sectional view of an LDMOS structure in one embodiment;

[0019] Figure 4 This is a schematic cross-sectional view of the LDMOS in another embodiment;

[0020] Figure 5 This is a schematic cross-sectional view of an LDMOS with added trenches in one embodiment.

[0021] Figure 6 This is a schematic diagram comparing the breakdown voltage of different LDMOS structures in one embodiment;

[0022] Figure 7 This is a schematic diagram of the electric field line distribution of a planar LDMOS in one embodiment. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0024] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0025] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0026] Please refer to Figure 1This is a schematic diagram of a cross-sectional structure of an LDMOS. Planar LDMOS typically uses a gate-N-type drift region (N-drift) for lateral voltage withstand to achieve high-voltage turn-off support. The P-body region of the LDMOS is usually short-circuited to the source. Its core functions are to form a conductive channel, form a main withstand voltage PN junction with the N-drift, and suppress parasitic BJT effects and prevent latch-up by shorting to the source. Shallow Trench Isolation (STI) serves to provide electrical isolation (isolate adjacent devices to prevent leakage) and surface electric field modulation (located on the surface of the drift region between the gate and drain, its edges help disperse the electric field and optimize the breakdown voltage). The source, as the current input terminal of the LDMOS (for N-LDMOS), has a key structural feature where the internal N+ region (providing charge carriers) and the P+ contact region (connecting the body) are shorted in the metal layer, forming a "source-body short." Polysilicon serves as the gate electrode in LDMOS (located above the gate oxide, where a voltage is applied to control the opening and closing of the channel below) and extends as a field plate (often extending to cover part of the drift region, becoming a "gate field plate" to smooth the surface electric field). Silicon nitride (Si3N4), as a dielectric material, is used in the process for etching hard masks / stop layers (due to its higher etching selectivity compared to silicon dioxide), passivation protection layers, and stress layers (to improve CMOS performance). In LDMOS, it is usually part of the process, not the active region of the device. The drain is the current output / high voltage withstand terminal of the LDMOS, located at the end of the N-drift region, led out through a metal contact, and withstands a high voltage when the LDMOS is turned off. The P-well region and the body region are usually the same area. From a manufacturing perspective, "P-well" emphasizes that it is a P-type doped region formed by ion implantation, used to form the body region of the MOSFET and the necessary PN junction. The N-type drift region is the core area for achieving high-voltage capability in LDMOS. Its functions are voltage withstand (lightly doped, it can be fully depleted to withstand high voltage during turn-off) and conductivity (providing a path for current from the channel to the drain during turn-on). Its length and doping distribution are key considerations in the trade-off design of breakdown voltage (BV) and specific on-resistance (Ron, sp). The P-type substrate (P-sub) is the mechanical base and common electrical ground of the chip. Its functions are to support all devices, provide electrical isolation (forming a PN junction with the N-type region above), and be connected to the lowest potential (e.g., grounding, providing a path for parasitic currents).

[0027] LDMOS has two operating states: off and on. Specifically, it includes:

[0028] Off-state (withstand voltage): When the gate voltage (Vg) is 0 and a high voltage (Vd) is applied to the drain, the voltage drops mainly in two regions: the reverse-biased PN junction formed by the P-well / N-drift and the fully depleted N-drift region itself. The P-sub, through its connection with the PN junction at the bottom of the N-drift region, prevents the voltage from penetrating the entire substrate. The surface electric field is most likely to concentrate at the edges of the Poly gate and the STI, thus requiring techniques such as field plates (Poly extension) and RESURF doping for optimization.

[0029] On-state (conductivity): When the gate voltage (Vg) exceeds the threshold voltage, an N-type inversion layer channel forms on the surface of the Body region beneath the Poly gate. Electrons originate from the N+ region at the Source end, pass through the channel into the N-drift region, and finally reach the N+ region at the Drain end. The resistance of the N-drift region is the main factor determining the overall on-resistance of the device; therefore, it is necessary to minimize its resistance as much as possible while ensuring the withstand voltage.

[0030] Please refer to Figure 2 The diagram shows the electric field distribution of a planar LDMOS. Due to various geometric and dielectric abrupt changes on the device surface (such as gate edge, field oxygen / isolation boundary, curvature change of P-well / N-drift junction at the surface), the electric field lines are more likely to accumulate on the surface (purple area) in the off state, resulting in the surface electric field peak being significantly higher than the bulk electric field, making the device prone to surface breakdown.

[0031] In this embodiment, an insulating layer is added to spatially isolate the gate region and the N-type drift region, reducing the peak value of the local electric field on the dispersed surface, thereby optimizing the electric field distribution in the drift region, suppressing premature surface breakdown, and improving the breakdown voltage margin. In one embodiment, a vertical trench is introduced in the transition region (or adjacent region) between the P-well and the N-drift region, and a gate dielectric and a polysilicon gate are formed within the trench, so that the gate extends vertically into the silicon bulk (P-type substrate). The LDMOS with the trench gate region performs three-dimensional control of the drift region electric field and depletion layer shape in the off state, transferring the equipotential lines from the device surface to the bulk, dispersing the peak value of the local electric field on the surface, and optimizing the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin.

[0032] Example 1:

[0033] Please refer to Figure 3This is a schematic cross-sectional view of an LDMOS in one embodiment. The LDMOS disclosed in this application is based on a BCD process platform and includes a P-type well region 20 and an N-type drift region 30 fabricated in a substrate. The source region 21 of the LDMOS is disposed in the P-type well region 20, and the drain region 31 of the LDMOS is disposed in the N-type drift region 30. The gate region 2 of the LDMOS is disposed on the upper surface of the substrate 1 and is isolated between the P-type well region 20 and the N-type drift region 30 by a gate oxide region 11. The gate oxide region 11 covers the substrate 1, and the gate region 2 covers the gate oxide region 11. The extension length of the gate region 2 towards the N-type drift region 30 is less than the extension length of the gate oxide region 11 towards the N-type drift region 30. The area of ​​the gate oxide region 11 not covered by the gate region 2 is covered by an insulating layer 12, the thickness of which is greater than the thickness of the gate oxide region 11 covered by the gate region 2. The insulating layer 12 is used to spatially isolate the gate region 1 and the N-type drift region 30.

[0034] Please refer to Figure 4 The diagram shows a cross-sectional view of an LDMOS in another embodiment. In one embodiment, the extension length of the gate region 1 toward the P-type well region 20 is less than the extension length of the gate oxide region 11 toward the P-type well region 20. The area of ​​the gate oxide region 11 not covered by the gate region 2 is covered by an insulating layer 12, the thickness of which is greater than the thickness of the gate oxide region 2 covering the gate oxide region 11. The insulating layer 12 is used to spatially isolate the gate region 2 and the P-type well region 20.

[0035] Please refer to Figure 5 This is a cross-sectional schematic diagram of an LDMOS with added trenches in one embodiment. In one embodiment, the gate region 2 includes a substrate region 13, which extends from the upper surface of the LDMOS towards the substrate 1 of the LDMOS and is completely isolated from the substrate 1 by the gate oxide region 11. The source region 21 and the drain region 31 are respectively disposed on both sides of the substrate region 13. In one embodiment, the depth of the substrate region 13 extending into the substrate 1 of the LDMOS is less than the depth of the source region 21 and the drain region 31 extending into the substrate of the LDMOS. In one embodiment, the substrate region 13 is an inverted trapezoidal trench structure.

[0036] In one embodiment, the under-substrate region 13 of the trench gate is disposed on the connection boundary between the P-type well region 20 and the N-type drift region 30.

[0037] In one embodiment, a P-body region 22 is further disposed on the upper surface of the P-type well region 20, and is isolated from the source region 21 on the upper surface of the P-type well region 20 by a shallow trench isolation 23. In one embodiment, the insulating layer is made of silicon nitride. In one embodiment, the gate region is made of polysilicon. In one embodiment, the gate oxide region is made of silicon dioxide. In one embodiment, the substrate of the LDMOS is a P-type substrate. In one embodiment, the substrate of the LDMOS is an N-type substrate.

[0038] In one embodiment of this application, an LDMOS device is also disclosed, comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described above.

[0039] The LDMOS disclosed in the embodiments of this application (such as...) Figure 5 (as shown) and as Figure 1 Compared to conventional planar gate LDMOS, the three-dimensional electric field shaping introduced by the trench gate significantly reduces the peak electric field at the device surface, suppresses electric field concentration at the gate and junction edges, and shifts the breakdown point from the device surface to the device bulk, thereby improving breakdown voltage and breakdown consistency. Simultaneously, under the same breakdown target, it reduces the dependence on "lengthening / excessive dedoping" of the drift region, reduces the drift region resistance growth, improves the BV–Ron,sp tradeoff, and reduces conduction losses. Please refer to [reference needed]. Figure 6 and Figure 7 These are schematic diagrams comparing the breakdown voltage of different LDMOS structures and a schematic diagram of the electric field line distribution of a planar LDMOS in an embodiment of this application, respectively. Figure 6 The horizontal axis represents voltage, and the vertical axis represents current. The yellow curve represents... Figure 1 The breakdown voltage curves of the planar gate LDMOS are shown below; the purple curve represents... Figure 5 The breakdown voltage curve of the LDMOS is shown.

[0040] The LDMOS structure disclosed in this application embodiment can be used as a high-voltage switch integrated in BCD technology, and its core design lies in:

[0041] 1. Vertical isolation is achieved using P-sub / N-drift junctions;

[0042] 2. Laterally, the voltage is absorbed by the P-well / N-drift junction and the N-drift region itself;

[0043] 3. The surface uses a poly gate, STI, and special doping design (such as RESURF) to manage the electric field and prevent premature breakdown.

[0044] 4. During integration, all structures share process steps with low-voltage CMOS and BJT devices, achieving "intelligent power" integration on a single chip.

[0045] The LDMOS in the BCD process platform disclosed in this application includes a P-type well region and an N-type drift region fabricated in a substrate, with source and drain regions respectively provided. The gate region of the LDMOS is disposed on the upper surface of the substrate and isolated from the P-type well region and N-type drift region by a gate oxide region. The gate region and gate oxide region sequentially cover the substrate, with the gate region extending towards the N-type drift region less than the gate oxide region extending towards the N-type drift region, and the area of ​​the gate oxide region not covered by the gate region is covered by an insulating layer. Because the added insulating layer spatially isolates the gate region and the N-type drift region, it reduces the peak value of the local electric field on the dispersed surface, optimizes the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin.

[0046] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. An LDMOS in a BCD process platform, characterized in that, It includes a P-type well region and an N-type drift region fabricated in a substrate; the source region of the LDMOS is disposed in the P-type well region, and the drain region of the LDMOS is disposed in the N-type drift region; the gate region of the LDMOS is disposed on the upper surface of the substrate and is isolated between the P-type well region and the N-type drift region by a gate oxide region. The gate oxide region covers the substrate, the gate region covers the gate oxide region, the length of the gate region extending toward the N-type drift region is less than the length of the gate oxide region extending toward the N-type drift region, and the area of ​​the gate oxide region not covered by the gate region is covered by an insulating layer with a covering thickness greater than the thickness of the gate region covering the gate oxide region, and the insulating layer is used to spatially isolate the gate region and the N-type drift region.

2. The LDMOS as described in claim 1, characterized in that, The extension length of the gate region toward the P-type well region is less than the extension length of the gate oxide region toward the P-type well region, and the area of ​​the gate oxide region not covered by the gate region is covered by an insulating layer with a covering thickness greater than the thickness of the gate region covering the gate oxide region. The insulating layer is used to spatially isolate the gate region and the P-type well region.

3. The LDMOS as described in claim 1, characterized in that, The gate region includes a substrate region that extends from the upper surface of the LDMOS to the substrate of the LDMOS and is completely isolated from the substrate by a gate oxide region; the source region and the drain region are respectively disposed on both sides of the substrate region.

4. The LDMOS as described in claim 3, characterized in that, The depth to which the under-substrate region extends into the LDMOS substrate is less than the depth to which the source region and the drain region extend into the LDMOS substrate.

5. The LDMOS as described in claim 3, characterized in that, The lining area has an inverted trapezoidal groove structure.

6. The LDMOS as described in claim 3, characterized in that, The P-type well region and the N-type drift region are separated by the underlay region.

7. The LDMOS as described in claim 1, characterized in that, The upper surface of the P-type well region is further provided with a P-body region, which is isolated from the source region on the upper surface of the P-type well region by a shallow trench.

8. The LDMOS as described in claim 1, characterized in that, The insulating layer is made of silicon nitride.

9. The LDMOS as described in claim 1, characterized in that, The gate region is made of polysilicon; the gate oxide region is made of silicon dioxide; and the LDMOS substrate is a P-type substrate.

10. An LDMOS device, characterized in that, It includes multiple MOS units, wherein at least one MOS unit is an LDMOS as described in any one of claims 1 to 9.

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