A planar gate SiC MOSFET device with a P-type buried layer

Abstract

The application discloses a planar gate SiC MOSFET device with a P-type buried layer, which is sequentially provided with a substrate, a first epitaxial layer and a second epitaxial layer from bottom to top along the direction of Z axis; a Pwell region and a channel region are etched on the upper surface of the second N-type epitaxial layer, the channel region is located between the two Pwell regions, and the inner sides of the two Pwell regions and the channel region are JFET regions of the SiC MOSFET; a gate oxide layer is arranged above the JFET region, the gate oxide layer is connected between the adjacent Pwell region and the channel region (6), a polysilicon layer is arranged on the gate oxide layer, and the polysilicon layer is wrapped with a dielectric layer; a P-type buried layer is embedded in the first epitaxial layer, the P-type buried layer is located directly below the JFET region and is in contact with the bottom of the second N-type epitaxial layer. The application effectively protects the gate oxide dielectric and completely shields the electric field thereof.

Description

Technical Field

[0001] This invention belongs to the field of SiC MOSFET device technology, specifically relating to a planar gate SiC MOSFET device with a P-type buried layer. Background Technology

[0002] Due to their high breakdown field strength, high switching speed, and low specific on-resistance, SiC MOSFET devices are increasingly being used in various fields, enabling them to operate in more demanding environments and showing broad application prospects in photovoltaic power generation, motors, charging piles, and aerospace. However, gate oxide breakdown remains a critical issue in SiC MOSFET design. Gate oxide breakdown is a common failure mode for SiC MOSFETs, causing the device to lose its switching control capability or even burn out. The failure mechanism of gate oxide breakdown is mostly due to the gate oxide dielectric bearing too large a voltage, leading to time-dependent breakdown of the dielectric layer.

[0003] Based on the superior characteristics of silicon carbide (SiC) material, such as high breakdown field strength, high switching speed, and low specific on-resistance, SiC MOSFET devices exhibit significant technical advantages in power electronics systems, leading to their widespread adoption in an increasing number of application areas. These devices can operate stably in more demanding environments and have broad application prospects in fields with high power density and reliability requirements, such as photovoltaic power generation, motor drives, charging piles, and aerospace.

[0004] However, gate oxide breakdown has always been a key bottleneck restricting the reliability of SiC MOSFET devices in their design and application. Gate oxide breakdown is one of the common failure modes of SiC MOSFETs. Once it occurs, it will cause the device to lose its switching control capability, and in severe cases, it may even cause the device to burn out, resulting in system failure. From the perspective of failure mechanism, gate oxide breakdown mostly stems from the gate oxide dielectric layer being subjected to excessively high electric field stress, which breaks down under long-term operating conditions. The root causes mainly include two aspects: first, the quality of the oxide layer dielectric formed during the gate oxide process is poor, with quality problems such as interface defects and trapped charges; second, crystal defects in the SiC epitaxial layer migrate and expand under long-term electric and thermal stress, leading to an increase in the interface state density of the oxide layer, local electric field concentration, and ultimately causing breakdown failure.

[0005] Therefore, how to effectively reduce the gate oxide failure probability of SiC MOSFET devices has become a research focus and key technical challenge in the field of power semiconductors.

[0006] Currently, the technologies presented in the papers Chen X, Li X, Wang Y, et al. Different JFET designs on conduction and short-circuit capability for 3.3 kV planar-gate siliconcarbide MOSFETs[J]. IEEE Journal of the Electron Devices Society, 2020, 8:841-845. DOI:10.1109 / JEDS.2020.3010951 and CN118444122A (online monitoring circuit and method for SiC MOSFET gate oxide aging status) both aim to minimize the JFET size and reduce the electric field strength of the gate oxide dielectric through P-well pinch-off. However, this leads to a significant increase in the JFET region resistance. Other methods involve screening out devices with shorter lifespans through gate oxide aging, but these screening schemes are only effective for specific materials and process conditions and carry significant risks.

[0007] The commonly used protection schemes in the industry mainly include two technical paths: one is to optimize the device structure design to minimize the size of the JFET region and use the Pwell pinch-off effect to reduce the electric field strength of the gate oxide dielectric, thereby delaying the occurrence of gate oxide breakdown; the other is to screen the gate oxide dielectric by aging, and to conduct aging tests on the gate oxide quality before the device leaves the factory to eliminate devices with shorter lifespans, so as to improve the reliability level of the entire batch of products.

[0008] However, the above solutions still have certain limitations, and there is an urgent need to develop more efficient and reliable gate oxide protection technologies to meet the long-term reliability requirements of SiC MOSFETs in high-temperature, high-frequency, and high-power-density application scenarios. Summary of the Invention

[0009] To overcome the shortcomings of the existing technology, the present invention aims to provide a planar gate SiC MOSFET device with a P-type buried layer. By burying a P-type doped region under the JFET region of the SiC MOSFET, an electrical shielding is formed on the gate oxide dielectric of the JFET region, effectively protecting the gate oxide dielectric and completely shielding its electric field. At the same time, the process of realizing this structure is simple and convenient, and it can be achieved by performing double-layer epitaxy and ion implantation on the basis of the original process.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A planar gate SiC MOSFET device with a P-type buried layer, wherein a substrate, a first (N-type) epitaxial layer, and a second (N-type) epitaxial layer are sequentially disposed from bottom to top along the Z-axis direction; The upper surface of the second N-type epitaxial layer is etched with a Pwell region and a channel region. The channel region is located between the two Pwell regions, and the area between the inner side of the two Pwell regions and the channel region is the JFET region of the SiCMOSFET. Above the JFET region is a gate oxide layer, which spans between the adjacent Pwell region and the channel region. A polysilicon layer is disposed on the gate oxide layer and wrapped with a dielectric layer. A P-type buried layer is embedded in the first epitaxial layer. The P-type buried layer is located directly below the JFET region and is in contact with the bottom of the second N-type epitaxial layer.

[0011] A Pplus region is set on the outer side of the two Pwell regions. The lower part of the Pplus region is in contact with the top surface of the first epitaxial layer, and the inner side is in contact with the Pwell region and the second N-type epitaxial layer.

[0012] An Nplus region is etched in the area above the Pwell region and the channel region. An ohmic contact layer is formed on part of the top surface of the Nplus region, and another part of the top surface contacts the bottom surface of the gate oxide layer. The ohmic contact layer also covers the top surface of the Pplus region and contacts the gate oxide layer on the inside.

[0013] The Nplus region etched on the Pwell region has its outer side in contact with the inner side of the Pplus region.

[0014] A source front electrode metal layer is disposed on the top surface of the device, and a drain electrode is disposed on the bottom surface.

[0015] The JFET region is connected to the source front electrode metal layer in the main junction region outside the cell via P-plus.

[0016] The concentration of the P-type buried layer is 1e18cm. -3 up to 5e18cm -3 ; The thickness of the P-type buried layer is 0.3μm-1μm; The doping concentration of the JFET region is 1×10¹ 6 cm - ³ to 5×10¹ 6 cm - ³.

[0017] The concentration of the first SiC epitaxial layer is 8×10⁻⁶. 15 cm -3 Up to 1.2×10 16 cm -3 Thickness ranges from 8μm to 12μm.

[0018] An ohmic contact layer is provided at the bottom of the SiC substrate wafer, and good ohmic contact is formed by laser annealing; the laser wavelength of the laser annealing is usually 308–355nm, the number of pulses is usually 1–20 pulses, and the substrate temperature is room temperature to 400℃.

[0019] The beneficial effects of this invention are: 1. The process steps are relatively simple. P-type buried layers can be achieved through double-layer epitaxy and ion implantation. After epitaxy in the outer N-type doped region, P-type ion implantation doping is performed, and then a second epitaxial growth is carried out. Compared with the process engineering of conventional structures, the process is similar and the process is mature.

[0020] 2. The SiC MOSFET device with a buried P-type structure proposed in this invention forms an additional reverse-biased PN junction with the upper n-type JFET region. During blocking, a large number of high electric field lines are terminated within the depletion region of the P-type buried layer and the JFET region, preventing them from extending further upward to the gate oxide / SiC interface. This completely shields the electric field borne by the gate oxide dielectric from the device structure, effectively improving gate oxide lifetime, increasing gate oxide reliability, and reducing the likelihood of gate oxide breakdown.

[0021] 3. Because the device structure of the present invention shields the electric field of the gate oxide dielectric, defects in the SiC material will not extend to the gate oxide interface, thus effectively shielding defects in the SiC material.

[0022] 4. The improvements and ideas in this device structure are applicable not only to SiC MOSFETs, but also to other structures such as Si MOSFETs, demonstrating strong technical applicability.

[0023] 5. This invention reduces the difficulty of production and processing, and is highly feasible.

[0024] 6. While ensuring the gate oxide lifetime of the device, the local electric field in the defect region is significantly reduced. At the same time, the depletion region blocks the electromigration and propagation of defects upward to the gate oxide interface, suppressing interface state generation and threshold drift. Therefore, using this device structure can significantly reduce the requirements for the defect density of SiC material. Attached Figure Description

[0025] Figure 1 This is a cross-sectional view of the SiC MOSFET device of the present invention.

[0026] Figure 2 This is the first epitaxial growth process for SiC.

[0027] Figure 3 This is a P-type buried layer process for SiC.

[0028] Figure 4 This is a second epitaxial growth process for SiC.

[0029] Figure 5 For PWell lithography and implantation processes.

[0030] Figure 6 This is an NPlus self-aligned lithography process.

[0031] Figure 7 This is an NPlus self-aligned lithography process.

[0032] Figure 8 For PPlus lithography and implantation processes.

[0033] Figure 9 For PPlus lithography and implantation processes.

[0034] Figure 10 It uses the Poly lithography process.

[0035] Figure 11 For Source Contact lithography and ohmic contact processes.

[0036] Figure 12 It features a front-facing metal finish.

[0037] Figure 13 This is a flowchart illustrating the fabrication process of the cellular structure device of the present invention. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings.

[0039] like Figure 1 As shown, a planar gate SiC MOSFET device with a P-type buried layer is described. The process of growing the entire epitaxial layer 2 is divided into two layers: a P-type ion implantation process is performed in the middle, and after epitaxy in the outer N-type doped region, P-type ion implantation is performed to form a P-type buried layer 3. Then, subsequent epitaxial growth is performed to grow the second N-type epitaxial layer 4.

[0040] In subsequent process steps, the embedded P-type buried layer 3 is connected to the source front electrode metal layer 15 in the main junction region outside the cell via P-plus 8.

[0041] This invention establishes a device without introducing new processes, achieving the purpose of protecting the gate oxide layer 10 by growing a new P-type buried layer 3. The JFET resistance, as a component of the on-resistance, increases as the width of the JFET region 9 decreases. However, this invention does not alter the JFET region 9, so it has virtually no impact on Ron. While improving gate oxide lifetime, the device structure of this invention also prevents defects in the SiC material from extending into the gate oxide layer 10 due to the shielding of the electric field of the gate oxide dielectric 10. This means that this structure can effectively shield defects in the SiC material. Furthermore, this device structure can reduce the requirements for the defect density of the SiC material. In summary, this invention not only effectively improves the gate oxide reliability and gate oxide lifetime of the device, but also has universality and considerable application potential for other types of devices such as Si MOSFETs.

[0042] Take the planar gate N-channel enhancement-mode silicon carbide field-effect transistor as an example; Comparison of cell region cross-sections between device cell design and traditional SiC MOSFET device cell design, for example Figure 1 As shown. The device comprises an active region (the core working area of ​​the device), a gate control bus region (connecting the gates of all cells and providing a unified gate control signal), and a termination region (located at the outermost edge of the chip, used to alleviate electric field concentration, prevent edge breakdown, and protect the active region). The gate control bus region and the termination region are basically consistent with the traditional SiC MOSFET design and fabrication methods. The difference is that the buried P-type doped region is connected to the source front electrode metal layer 15 through the Pplus region 8 in the main junction region outside the cell. Other than that, this embodiment will not be described in detail.

[0043] In the active region of the device in this embodiment, the design optimization mainly focuses on the epitaxial layer of the device cell. The overall process flow diagram is as follows. Figure 13 As shown.

[0044] Device cross-sectional view as follows Figure 1 As shown, its active region includes a substrate 1, a first epitaxial layer 2, a P-type buried layer 3, a second epitaxial layer 4, a Pwell region 5, a channel region 6, an Nplus region 7, a Pplus region 8, a JFET region 9, a gate oxide layer 10, a Poly gate structure 11, an ILD dielectric layer 12, an ohmic contact layer 13, a back electrode metal layer 14, a source front electrode metal layer 15, and an ohmic contact layer 16 formed by the substrate and the back electrode metal.

[0045] From the flowchart Figure 2 As shown, the fabrication process of a planar gate SiC MOSFET device with a P-type buried layer includes the following steps: Step S1: Substrate 1 Preparation and Epitaxial Design. Based on the product design specifications, select a SiC substrate 1 (including but not limited to a 6-inch substrate) with suitable dimensions, thickness, and resistivity. Since the epitaxial layer parameters directly determine device performance, the doping concentration and thickness of the epitaxial layer must be precisely set through physical simulation calculations and design optimization. (Epitaxial concentration includes, but is not limited to, 8 × 10⁻⁶) 15 cm -3 Up to 1.2×10 16 cm -3 Epitaxial thickness including but not limited to 8μm to 12μm) Step S2: Initial Epitaxial Growth. The first epitaxial growth is performed on the prepared SiC substrate 1 wafer to form the first SiC epitaxial layer 2 (see...). Figure 2 ).

[0046] Step S3: P-type buried layer ion implantation. A hard mask layer 17 (optional materials include silicon dioxide, silicon nitride, or polysilicon) is deposited on the surface of the first epitaxial layer 2. To form the P-type buried layer, P-type buried layer implantation window 18 and P-type buried layer implantation window 29 are defined by photolithography and etching processes; after removing the photoresist, ion implantation is performed to form the implantation region of the P-type buried layer 3 (see...). Figure 3 The width of the P-type buried layer 3 depends on the width of the JFET, and the thickness includes, but is not limited to, 0.3μm-1μm.

[0047] Step S4: Secondary epitaxial growth. Remove all hard mask layers 17 from the wafer surface and perform a second epitaxial growth on the current structure to form the second N-type epitaxial layer 4 (see...). Figure 4 The thickness depends on the subsequent injection depth.

[0048] Step S5: Marking and etching process. Perform the marking and etching process to prepare high-precision alignment mark patterns on the wafer surface for subsequent photolithography processes.

[0049] Step S6: Pwell region ion implantation. A hard mask layer 20 is deposited on the surface of the second N-type epitaxial layer 4. To form the Pwell region 5, Pwell implantation windows 1 (21), 2 (22), and 3 (23) are created using photolithography and etching processes; after resist removal, ion implantation is performed to fabricate the Pwell region 5 (see...). Figure 5 ).

[0050] Step S7: Self-aligned process. After the Pwell window is opened, a hard mask layer 24 of a certain thickness is deposited again, and photoresist 25 at specific locations is retained by Nplus photolithography. This location depends on the position defined by the Pplus region 8. Subsequently, a self-aligned etching process is used: sidewall structures 26 are formed on the step sidewalls of the hard mask 20, while the portion protected by the photoresist 25 remains as the hard mask layer 27 (see...). Figure 6 ).

[0051] Step S8: Nplus Implantation. Perform high-temperature N or P ion implantation (including but not limited to 500°C to 650°C). Under the obstruction of hard masks 20 and 27, selective implantation is achieved within the Pwell region to form the Nplus doped region 7; at this time, the Pwell region located below the sidewall 26 is retained because it is not implanted and is defined as the channel region 6 (see...). Figure 7 ).

[0052] Step S9: PPlus region ion implantation. To avoid interference from residual masks, all hard masks on the surface are first removed, and a new hard mask layer 28 is deposited. Implantation window 1 29 and implantation window 2 30 are then created by PPlus photolithography etching (see...). Figure 8 After desizing, high-temperature B or Al ion implantation (including but not limited to 500°C to 650°C) is performed to form the Pplus region 8 (see...). Figure 9 ).

[0053] Step S10: JFET region implantation. Repeat process step S9: remove the old mask and deposit a new mask, and open the JFET implantation window by photolithography etching. Then perform high-temperature N or P ion implantation (including but not limited to 500°C to 650°C) to precisely adjust the doping concentration of JFET region 9 (including but not limited to 1×10¹). 6 cm - ³ to 5×10¹ 6 cm - ³), and then completely remove all hard masks.

[0054] Step S11: Carbon film deposition and high-temperature activation. A carbon film is deposited on the wafer surface as a protective layer, followed by high-temperature annealing to activate impurity ions in each implanted region (temperature typically 1600 to 1800°C, time typically 20–30 min). After activation, the carbon film on the surface is removed.

[0055] Step S12: Sacrificial oxidation. A high-temperature oxidation process is performed to remove the surface lattice damage caused by ion implantation, followed by chemical etching to remove the sacrificial oxide layer (temperature typically 1100–1400℃, usually 1150–1200℃, oxidation atmosphere typically dry oxygen O2, oxidation time typically 30 min–3 h, usually 1–2 h), thereby obtaining a low-defect SiC surface.

[0056] Step S13: Active region definition. A field oxide layer is deposited on the repaired wafer surface. The oxide layer in specific areas is selectively removed by photolithography and etching processes. The location depends on the design scheme, thereby defining the active region of the device.

[0057] Step S14: Polysilicon gate process. A gate oxide layer 10 of a specified thickness is grown on the surface of the active region, and a polysilicon layer 11 is deposited. After photolithography and etching, a polysilicon gate structure is formed (see...). Figure 10 ).

[0058] Step S15: ILD Ohmic Contact with Source. Deposit ILD dielectric layer 12 (typically USG+BPSG), and etch source contact holes. After resist removal, deposit ohmic contact metal and perform rapid thermal annealing (temperature typically 900–1100℃, usually 950–1000℃, time typically 30 s–5 min, usually 60 s–2 min, atmosphere typically Ar or N2 inert gas) to form ohmic contact layer 13. Finally, etch away excess metal (see [link to documentation]). Figure 11 ).

[0059] Step S16: Open the gate contact hole. Based on the above structure, perform photolithography and etching on the ILD dielectric layer 12 again to open the contact hole in the gate bus region and remove the resist. This region is usually located at the periphery or edge of the cell array.

[0060] Step S17: Front-side metallization. A source front-side electrode metal layer 15 (typically Ti / TiN / Al) is deposited on the wafer surface. The gate and source metal electrodes are defined and formed using photolithography and etching processes, followed by resist removal (see...). Figure 12 ).

[0061] Step S18: PA passivation layer fabrication. A PA passivation dielectric layer (such as SiO2 / SiN) is deposited on the wafer surface. Electrode lead-out windows are opened through photolithography and etching processes, followed by resist removal.

[0062] Step S19: PI and PAD. A PI passivation layer is coated on the surface, and the PI layer is opened by photolithography to expose the PAD electrode contact area. Finally, a curing process is performed.

[0063] Step S20: Backside thinning. The backside of the wafer is mechanically thinned to reduce the device's thermal resistance and drift region resistance.

[0064] Step S21: Backside drain electrode. An ohmic contact metal (typically Ni) is deposited on the backside of the wafer to form an ohmic contact layer 16, which is then laser-annealed to form a good ohmic contact. (The laser wavelength is typically 308–355 nm, the number of pulses is typically 1–20, and the substrate temperature is typically room temperature to 400 °C).

[0065] Subsequently, a back drain metal layer (such as Ti / Ni / Ag) is deposited to complete the fabrication of drain electrode 14 (see [link]). Figure 1 Finally, the finished product is inspected.

[0066] Photoresist type 25 is a positive photoresist with a thickness including but not limited to 1–2 μm, an exposure wavelength including but not limited to 365 nm i-line or 248 nm KrF, and an etching method that is usually dry.

[0067] This invention proposes a planar SiC MOSFET structure. A P-type buried layer 3 is embedded under the JFET region 9 of the SiC MOSFET to form an electrical shield for the gate oxide layer 10 of the JFET region 9. Through process design, the buried P-type buried layer 3 is connected to the source front electrode metal layer 15 in the main junction region around the cell via a Pplus region 8. The P-type buried layer 3 is achieved by ion implantation after a single-layer N-type epitaxy, followed by a second epitaxy to obtain a second N-type epitaxial layer 4. This SiC MOSFET device with a buried P-type structure can significantly improve gate oxide lifetime by shielding the gate oxide dielectric electric field through the buried layer structure.

[0068] Furthermore, while the device structure of the present invention shields the electric field of the gate oxide dielectric, the defects in the SiC material will not extend to the gate oxide interface. That is, the device structure of the present invention has the ability to shield the defects of the SiC material, which can significantly reduce the requirement for the defect density of the SiC material.

Claims

1. A planar gate SiC MOSFET device with a P-type buried layer, characterized in that, Along the Z-axis, from bottom to top, a substrate (1), a first epitaxial layer (2), and a second epitaxial layer (4) are arranged sequentially. The upper surface of the second N-type epitaxial layer (4) is etched with a Pwell region (5) and a channel region (6). The channel region (6) is located between the two Pwell regions (5). The area between the inner side of the two Pwell regions (5) and the channel region (6) is the JFET region (9) of the SiCMOSFET. The JFET region (9) is above a gate oxide layer (10), which spans between the adjacent Pwell region (5) and the channel region (6), and a polysilicon layer (11) is disposed thereon and wrapped with a dielectric layer (12). A P-type buried layer (3) is embedded in the first epitaxial layer (2). The P-type buried layer (3) is located directly below the JFET region (9) and is in contact with the bottom of the second N-type epitaxial layer (4).

2. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, A Pplus region (8) is set on the outer side of the two Pwell regions (5). The lower part of the Pplus region (8) is in contact with the top surface of the first epitaxial layer (2), and the inner side is in contact with the Pwell region (5) and the second N-type epitaxial layer (4).

3. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The Pwell region (5) and the channel region (6) are etched with an Nplus region (7). An ohmic contact layer (13) is provided on part of the top surface of the Nplus region (7), and another part of the top surface is in contact with the bottom surface of the gate oxide layer (10). The ohmic contact layer (13) also covers the top surface of the Pplus region (8) and is in contact with the gate oxide layer (10) on the inside.

4. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The Nplus region (7) etched on the Pwell region (5) has its outer side in contact with the inner side of the Pplus region (8).

5. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, A source front electrode metal layer (15) is provided on the top surface of the device, and a drain electrode (14) is provided on the bottom surface.

6. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The JFET region (9) is connected to the source front electrode metal layer (15) in the main junction region outside the cell via P-plus (8).

7. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The concentration of the P-type buried layer (3) is 1e18cm. -3 up to 5e18cm -3 ; The thickness of the P-type buried layer (3) is 0.3μm-1μm.

8. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The doping concentration of the JFET region (9) is 1×10¹ 6 cm - ³ to 5×10¹ 6 cm - ³.

9. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The concentration of the first SiC epitaxial layer (2) is 8×10⁻⁶. 15 cm -3 Up to 1.2×10 16 cm -3 Thickness ranges from 8μm to 12μm.

10. A planar gate SiC MOSFET device with a P-type buried layer according to claim 1, characterized in that, The SiC substrate (1) has an ohmic contact layer (16) at the bottom of the wafer, and good ohmic contact is formed by laser annealing; the laser wavelength of the laser annealing is usually 308–355 nm, the number of pulses is usually 1–20 pulses, and the substrate temperature is room temperature to 400 °C.

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