A single-gate reconfigurable feedback field effect transistor with charge storage layer

Abstract

The application discloses a single-gate reconfigurable feedback field effect transistor with a charge storage layer, which comprises a fin intrinsic channel wrapped by a gate oxide on three sides, a heavily doped drain end and a source end arranged at two ends of the fin intrinsic channel, a side wall for isolation symmetrically arranged on both sides of the channel, a gate oxide wrapping the channel, a nitride stack layer symmetrically arranged on both sides of the gate oxide outside the gate oxide, a gate wrapping the gate oxide, and a BOX layer substrate at the bottom of the device. The source end and the drain end of the device are doped with different types, the channel is intrinsic doped or lightly doped silicon, a p-i-n structure is formed, and the nitride stack layer is symmetrically arranged on both sides of the channel. The transistor disclosed by the application only needs one gate to complete the reconfigurable function, and the subsequent metal interconnection process is simplified. In addition, the single device integrates the functions of volatile storage, non-volatile storage and reconfigurable storage and calculation, and has a multi-functional storage paradigm.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a single-gate reconfigurable feedback field-effect transistor with a charge storage layer. Background Technology

[0002] The rapid development of artificial intelligence (AI) technology has led to an exponential increase in data volume, creating an urgent need for energy-efficient computing hardware. However, in von Neumann systems, the speed gap between the processor and memory—often referred to as the "memory wall"—has become a key bottleneck in high-performance computing systems. To address this bottleneck, researchers have proposed a three-dimensional integrated memory architecture, which alleviates the problem by reducing manufacturing costs and increasing packaging density (Reference: Das, Shamik, et al, Technology, performance, and computer-aided design of three-dimensional integrated circuits. Proceedings of the 2004 international symposium on Physical design, 2004).

[0003] Feedback field-effect transistors (FBFETs) have attracted widespread attention from researchers as an important means to overcome the Boltzmann bottleneck and reduce device power consumption. The FBFET was first proposed and verified by Padilla et al. in 2008. (Reference: Padilla A, Yeung CW, Shin C, et al, Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages. IEEE International Electron Devices Meeting, 2008: pp. 1-4). FBFETs regulate the channel barrier through a positive feedback mechanism, enabling extremely steep current switching (SS as low as ~0 mV / dec at room temperature) and a high switching current ratio (~10¹). 0 FBFETs offer advantages such as low operating voltage and a large memory window. Thanks to these characteristics, they demonstrate exceptional potential in logic and memory applications. Therefore, achieving three-dimensional integration of volatile and non-volatile memory on a single FBFET device is highly attractive.

[0004] Similarly, to further address the memory wall problem, the logic memory (LIM) architecture integrates processing and storage units, improving computational efficiency and system performance in von Neumann systems. Based on its switchable storage characteristics, FBFETs can perform both logic and storage operations within the LIM architecture. Simultaneously, device-level reconfigurability reduces the number of transistors required to implement logic in a logic memory (LIM) system. Recently, dual-gate and tri-gate reconfigurable LIMs based on reconfigurable FBFETs have attracted considerable attention (Reference: Shin, Yunwoo, et al, Logic‐In‐MemoryCharacteristics of Reconfigurable Feedback Field‐Effect Transistors with Double‐Gated Structure. Advanced Electronic Materials, 2023). However, reconfigurable transistors have been limited to dynamic programming, requiring additional constant programming signals to maintain the desired functionality. Therefore, single-gate FBFETs with reconfigurability demonstrate significant potential for future reconfigurable logic memory applications.

[0005] The application of feedback field-effect transistors in multifunctional memory integration and reconfigurable in-memory computing still needs further exploration and expansion. Summary of the Invention

[0006] The purpose of this invention is to address the difficulty of applying conventional feedback field-effect transistors (FETs) to multifunctional memory integration and reconfigurable in-memory computing. It proposes a single-gate reconfigurable feedback field-effect transistor (SGR-FBFET) with a charge storage layer. By introducing a charge-trapping stack layer above the channel, non-volatile memory functionality is achieved. Furthermore, by programming or erasing the gate, the charge-trapping layer can trap electrons or holes, thereby electrostatically modulating and doping the underlying intrinsic channel. + -in + The structure then becomes p + -ipn + Structure (n-type) or p + -nin + The p-type structure enables reconfigurable functionality. Furthermore, by utilizing the inherent hysteresis characteristics of feedback field-effect transistors, volatile memory and in-memory computing capabilities can be achieved.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A single-gate reconfigurable feedback field-effect transistor with a charge storage layer, characterized in that it includes:

[0009] Fin-type intrinsic channel surrounded by gate oxide on three sides;

[0010] Heavily doped p-type intrinsic channel located at one end of the fin channel + Drain end;

[0011] The heavily doped n-type fin intrinsic channel is located at the other end of the fin intrinsic channel. + Source end;

[0012] Electrical isolation sidewalls installed on both sides of the channel and in contact with the drain and source ends;

[0013] Gate oxide surrounding the intrinsic fin channel;

[0014] A charge trapping layer disposed on the outside of the gate oxide and symmetrically distributed along the left and right sides of the gate oxide;

[0015] A barrier layer disposed outside the charge trapping layer;

[0016] A metal gate with gate oxide encapsulated on three sides;

[0017] The insulator-on-silicon substrate is located at the bottom and consists of a silicon substrate and a buried oxide layer.

[0018] The finned channel is made of intrinsic silicon or lightly doped silicon, with a doping concentration of 0 cm⁻¹. -3 ~ 1×10 16 cm -3 ;

[0019] The drain terminal is heavily doped p + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ;

[0020] The source is heavily doped n + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ;

[0021] The sidewall is made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0022] The gate oxide is silicon dioxide, aluminum oxide, or hafnium dioxide;

[0023] The charge trapping layer is silicon nitride, aluminum oxide, hafnium dioxide, or ferroelectric hafnium oxide;

[0024] The barrier layer is made of silicon dioxide, aluminum oxide, hafnium dioxide, or ferroelectric hafnium oxide;

[0025] The metal gate is one or a combination of aluminum, copper, titanium, polycrystalline silicon, or titanium nitride.

[0026] The gate oxide and the metal gate are of equal length; the length of the charge trapping layer does not exceed half the length of the gate oxide layer; the heights of the electrical isolation sidewall, drain, source, and metal gate are equal.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] Using a single gate to achieve reconfigurability significantly reduces the complexity of metal interconnects, lowers wiring difficulty and parasitic effects compared to traditional dual-gate or multi-gate reconfigurable devices, which is beneficial to improving device density and reliability.

[0029] For the first time, the positive feedback mechanism of the feedback field-effect transistor is utilized to achieve a low operating voltage in both non-volatile memory and DRAM modes, which helps to significantly reduce power consumption and is suitable for high-performance computing and mobile devices with strict energy efficiency requirements.

[0030] In non-volatile memory mode, thanks to the positive feedback conduction mechanism, the read speed is only 0.4 ns, which is better than existing non-volatile memory.

[0031] It can be used as a reconfigurable logic storage unit to implement eight Boolean logic operations in a single device and can store logic outputs without external voltage supply.

[0032] In practical applications, this device integrates non-volatile memory, DRAM, and reconfigurable in-memory computing functions in the same structure without additional process steps. This simplifies system architecture, reduces manufacturing costs, and promotes the development of high-density, multi-functional three-dimensional integrated memory and reconfigurable in-memory computing systems. Attached Figure Description

[0033] Figure 1 This is a three-dimensional structural diagram of the present invention;

[0034] Figure 2 for Figure 1 Cross-sectional view at point A-A'-A'';

[0035] Figure 3 for Figure 1 Cross-sectional view at point B-B'-B'';

[0036] Figure 4 for Figure 1 Cross-sectional view at point C-C'-C'';

[0037] Figure 5The present invention presents the energy band diagrams in the off and on states when characterizing the N-type electrical properties.

[0038] Figure 6 The energy band diagrams for the off-state and on-state when characterizing the P-type electrical properties of this invention are shown.

[0039] Figure 7 This is a graph showing the transfer characteristics of the N-type in this invention.

[0040] Figure 8 This is a graph showing the transfer characteristics of the P-type in this invention.

[0041] Figure 9 This is a timing diagram illustrating the storage operation of an N-type DRAM cell in this invention.

[0042] Figure 10 This is a graph showing the migration characteristics of the present invention after programming and erasing in non-volatile memory mode;

[0043] Figure 11 This is a timing diagram of two consecutive read operations in non-volatile memory mode according to the present invention;

[0044] Figure 12 This is a schematic diagram of the XNOR memory cell circuit constructed according to the present invention;

[0045] Figure 13 This is a schematic diagram of the XOR memory cell circuit constructed according to the present invention;

[0046] Figure 14 This is a timing diagram of the XNOR / XOR gate circuit memory operation constructed according to the present invention;

[0047] Figure 15 This is a flowchart illustrating the preparation process of the present invention. Detailed Implementation

[0048] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] See Figure 1-4 The present invention proposes a single-gate reconfigurable feedback field-effect transistor (SGR-FBFET) with a charge storage layer, wherein the source and drain regions are heavily doped semiconductors with opposite doping types, and the channel is intrinsic silicon or lightly doped silicon. Figure 1 This is a three-dimensional structural diagram of the present invention, in which the metal gate electrode is made transparent to facilitate viewing the internal structure of the device.

[0050] The single-gate reconfigurable feedback field-effect transistor with a charge storage layer includes a fin intrinsic channel 1 encased on three sides by a gate oxide; a drain 2 at one end of the fin intrinsic channel and a source 3 at the other end; electrical isolation sidewalls 4 disposed on both sides of the channel and in contact with the drain and source; a gate oxide 5 encased on the outside of the fin intrinsic channel; a charge trapping layer 6 disposed on the outside of the gate oxide and symmetrically distributed along the left and right sides of the channel; a barrier layer 7 disposed on the outside of the charge trapping layer; a metal gate 8 encased on three sides by a gate oxide; and a silicon-on-insulator substrate composed of a silicon substrate 9 and a buried oxide layer 10 disposed at the bottom of the above structure.

[0051] The finned channel is made of intrinsic silicon or lightly doped silicon, with a doping concentration of 0 cm⁻¹. -3 ~ 1×10 16 cm -3 ;

[0052] The drain terminal is heavily doped p + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ;

[0053] The source is heavily doped n + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ;

[0054] The sidewall is made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0055] The gate oxide is silicon dioxide, aluminum oxide, or hafnium dioxide;

[0056] The charge trapping layer is silicon nitride, aluminum oxide, hafnium dioxide, or ferroelectric hafnium oxide;

[0057] The barrier layer is made of silicon dioxide, aluminum oxide, hafnium dioxide, or ferroelectric hafnium oxide;

[0058] The metal gate is one or a combination of aluminum, copper, titanium, polycrystalline silicon, or titanium nitride.

[0059] This invention proposes a single-gate reconfigurable feedback field-effect transistor (SGR-FBFET) with a charge storage layer, which integrates non-volatile memory, volatile memory, and reconfigurable in-memory computing functions. By implementing the device's polarity configuration using only a single gate, compared to traditional dual-gate or multi-gate structures, it simplifies metal interconnects and reduces wiring complexity and parasitic effects. Furthermore, it utilizes the positive feedback mechanism of the feedback field-effect transistor for the first time, achieving low-voltage operation in both non-volatile memory and DRAM modes, significantly reducing power consumption and making it suitable for high-energy-efficiency computing scenarios. Moreover, in non-volatile memory mode, the fast read mechanism based on positive feedback conduction achieves a read speed of only 0.4 ns, superior to existing non-volatile memories. This device can also serve as a reconfigurable in-memory computing unit, implementing eight Boolean logic operations within the same circuit architecture and maintaining its logic state even without external power supply.

[0060] Figure 5-6 The energy band diagrams for the off-state and on-state of this invention, representing the N-type and P-type electrical characteristics, are shown respectively. A represents the conduction band level in the off-state, B represents the valence band level in the off-state, C represents the conduction band level in the on-state, and D represents the valence band level in the on-state. When this invention undergoes an erase operation, the charge trapping layer traps holes, and the channel below the stacked layer is electrostatically induced to become n-type, lowering the channel energy band in this region. At this time, the device polarity is configured as n-type. Similarly, when this invention undergoes a programming operation, the charge trapping layer traps electrons, and the channel below the stacked layer is electrostatically induced to become p-type, raising the channel energy band in this region. At this time, the device polarity is configured as p-type.

[0061] Figure 7 and Figure 8 The transfer characteristic curves of this invention as an N-type and P-type device are given respectively, where the source-drain bias |Vds|=1V, and the charge density in the charge trapping layer after programming and erasing is approximately 5.0×10⁻⁶. 19 cm -3 The arrows indicate the scanning direction. As can be seen from the figure, regardless of whether it is an n-type or p-type, this invention exhibits an extremely high current switching ratio of ~10. 10 The subthreshold swing is almost zero. Furthermore, when this invention exhibits N-type characteristics, the on-state current is 28.6... A / When exhibiting P-type characteristics, the on-state current of this invention is 27.0 m. A / As can be seen from m, the proposed single-gate reconfigurable feedback field-effect transistor with charge storage layer has symmetrical n-type and p-type on-state characteristics, and the on-current ratio is only 1.06.

[0062] Figure 9This is a timing diagram illustrating the storage operation of a single-transistor DRAM cell constructed using the N-type architecture, as described in this invention. At the bit line voltage |V BL |=1V and word line voltage|V WL Under the read condition of |=0V, depending on whether the feedback loop is formed, the current of the DRAM cell constructed by this invention is 22 uA / um when the read logic state is "1" and 20 nA / um when the read logic state is "0". It can be seen that the sensing margin (SM) of the DRAM cell constructed by this invention is approximately 22 uA / um, enhancing the anti-interference capability of the DRAM cell.

[0063] Figure 10 This is a graph showing the displacement characteristics of the present invention after programming and erasing in non-volatile memory mode. A read operation was performed on the device after programming and erasing by applying 1 V to the drain and 0 V to the gate. Figure 10 As shown. The programmed device is P-type with a threshold voltage of 0.45 V, while the erased device is N-type with a threshold voltage of 0.34 V. Therefore, after a read operation is applied, the programmed device is in the ON state and the erased device is in the OFF state.

[0064] Figure 11 This is a timing diagram of two consecutive read operations in non-volatile memory mode according to the present invention. A represents the drain current in the read state after the programming operation, and B represents the drain current in the read state after the erasure operation. It can be seen that the drain current of the programmed device is 25.4 μA / μm, while the drain current of the erased device is 13 pA / μm. Furthermore, the sub-nanosecond (<1 ns) read time enables reliable state differentiation, which is superior to existing non-volatile memories.

[0065] Figure 12 and Figure 13 This is a schematic diagram of an XNOR and XOR memory cell circuit constructed according to the present invention. Utilizing the switching and storage characteristics of the proposed single-gate reconfigurable feedback field-effect transistor (SGR-FBFET) with a charge storage layer, logic storage operations can be performed in an SGR-FBFET-based memory cell. Due to the symmetrical reconfigurability of the SGR-FBFET, the reconfigurable logic memory cell can perform memory operations of eight Boolean logic gates (AND, OR, Buffer, NOT, NAND, NOR, XNOR, and XOR gates) in a single circuit. Here, XNOR and XOR gates are taken as examples, V... DD and V SS Corresponding to the power supply voltage V SUP , respectively set to 2.0 V and −2.0 V. Furthermore, V A and V BCorresponding to gate voltage V G -3V represents input logic "0", and 3V represents input logic "1".

[0066] Figure 14 This is a timing diagram for the stored operation of the XNOR / XOR gate circuit constructed according to the present invention. After the logic inputs "00", "01", "10" and "11" are executed in sequence, during the hold operation without external power supply, V OUT It can still maintain the initial output logic state.

[0067] See Figure 15 The manufacturing process of this invention is as follows:

[0068] (1) High dose of oxygen ions are injected into silicon substrate 9 by oxygen injection isolation technology and then annealed at high temperature to form an insulator-on-silicon substrate structure consisting of buried oxide layer 10 and top silicon layer 1.

[0069] (2) A fin-type channel structure is formed in the top silicon layer 1 by dry etching using self-aligned double patterning technology;

[0070] (3) A polycrystalline silicon virtual gate is deposited using chemical vapor deposition technology;

[0071] (4) Using chemical vapor deposition or atomic layer deposition, electrical isolation sidewalls 4 are deposited on both sides of the polycrystalline silicon virtual gate;

[0072] (5) An in-situ doped P⁺ silicon epitaxial layer 2 is grown in the drain window using a selective epitaxial process;

[0073] (6) An in-situ doped N⁺ silicon epitaxial layer 3 is grown within the source region window using a selective epitaxial process;

[0074] (7) The polysilicon virtual gate is removed by selective wet etching to expose the underlying fin channel;

[0075] (8) A gate oxide 5 is formed on the surface of the exposed channel 1 using atomic layer deposition technology;

[0076] (9) A charge trapping layer 6 is deposited on the surface of the gate dielectric layer using low-pressure chemical vapor deposition technology with dichlorosilane and ammonia as the reaction gas;

[0077] (10) An atomic layer deposition technique is used to form a barrier oxide layer 7 on the surface of the charge trapping layer 6;

[0078] (11) A common metal gate 8 is deposited using chemical vapor deposition technology, followed by rapid thermal annealing to form Figure 1 The structure shown.

[0079] Finally, the metal gate 8, drain 2, and source 3 are led out through interconnect metal, and all electrodes are planarized using chemical mechanical polishing technology. The device of this invention is connected together by metal interconnects using the CMOS VLSI back-end damascus process.

Claims

1. A single-gate reconfigurable feedback field-effect transistor with a charge storage layer, characterized in that it include: Fin-type intrinsic channel surrounded by gate oxide on three sides (1). The drain end (2) is located at one end of the intrinsic channel of the fin. The source end (3) is located at the other end of the fin-type intrinsic channel; Electrical isolation sidewalls (4) are installed on both sides of the channel and in contact with the drain end (2) and the source end (3). Gate oxide (5) wrapped around the outside of the fin intrinsic channel (1); A charge trapping layer (6) is disposed on the outside of the gate oxide (5) and symmetrically distributed along the left and right sides of the gate oxide (5); A barrier layer (7) is disposed outside the charge trapping layer (6); A metal gate (8) with gate oxide (5) on three sides. A silicon substrate on an insulator consisting of a silicon substrate (9) and a buried oxide layer (10) is disposed on the bottom.

2. The single-gate reconfigurable feedback field-effect transistor with a charge storage layer according to claim 1, characterized in that, The silicon nanosheet channel (1) is intrinsic silicon or lightly doped silicon, with a doping concentration of 0 cm⁻¹. -3 ~ 1×10 16 cm -3 ; The drain terminal (2) is a heavily doped p + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ; The source end (3) is a heavily doped n + Type region, doping concentration of 1×10 19 cm -3 ~ 1×10 20 cm -3 ; The sidewall (4) is made of silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass or borosilicate glass; The gate oxide (5) is silicon dioxide, aluminum oxide or hafnium dioxide; The charge trapping layer (6) is silicon nitride, aluminum oxide, hafnium dioxide, or ferroelectric hafnium oxide; The barrier layer (7) is silicon dioxide, aluminum oxide, hafnium dioxide or ferroelectric hafnium oxide; The metal gate (8) is one or a combination of aluminum, copper, titanium, polycrystalline silicon or titanium nitride.

3. The single-gate reconfigurable feedback field-effect transistor with a charge storage layer according to claim 1, characterized in that, The gate oxide (5) and the metal gate (8) are of equal length; the length of the charge trapping layer (6) is no more than half the length of the gate oxide layer (5); the heights of the electrical isolation sidewall (4), the drain (2), the source (3) and the metal gate (8) are equal.

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