A semiconductor device, a manufacturing method thereof, and an electronic apparatus

Abstract

The application provides a semiconductor device, a manufacturing method thereof and an electronic device. The semiconductor device comprises a substrate, an epitaxial layer and an electrode layer. The epitaxial layer is provided with an isolation structure. The semiconductor device further comprises: an active region, a passive region and a scribe lane region which are sequentially arranged from inside to outside; a gate, a source and a drain are all arranged in the active region; a gate pad and a drain pad are both arranged in the passive region; and the isolation structure is arranged in the passive region and at least partially surrounds the active region. The isolation structure is prone to corrosion and cracking in a complex environment generated in a cutting process. Arranging the isolation structure in the passive region instead of the scribe lane region can avoid corrosion and cracking of the isolation structure in the complex environment. In a use process, even in a humid and hot environment, the isolation structure can avoid the epitaxial layer in the active region from being eroded by moisture, thereby improving the corrosion resistance of the semiconductor device and improving the manufacturing yield and reliability of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0002] Chips are typically fabricated on wafers, and there are usually many chips on a wafer. Each chip is separated by scribe lines, and a dicing process is used to cut along these scribe lines to separate the individual chips. During use, moisture in the humid and hot environment can corrode the epitaxial layer within the chip, resulting in low corrosion resistance. Summary of the Invention

[0003] This application provides a semiconductor device, a method for manufacturing the same, and an electronic device for improving the corrosion resistance of the semiconductor device.

[0004] In a first aspect, embodiments of this application provide a semiconductor device comprising: a substrate, and an epitaxial layer and an electrode layer sequentially stacked on the substrate. The epitaxial layer contains an isolation structure, and the electrode layer contains a gate, a source, a drain, a gate pad, and a drain pad. The semiconductor device further comprises: an active region, a passive region, and a dicing region sequentially arranged from the inside out. The gate, source, and drain are all located in the active region, while the gate pad and drain pad are all located in the passive region. The isolation structure is located in the passive region and at least partially surrounds the active region. This isolation structure can shield electrical interference generated by other structures, achieving electrical isolation of the active region and improving the performance of the device within the active region. Furthermore, during the use of the semiconductor device, even in a humid and hot environment, the isolation structure can prevent moisture from penetrating into the epitaxial layer of the active region, avoiding moisture erosion of the epitaxial layer within the active region, thereby improving the corrosion resistance of the semiconductor device. In addition, the isolation structure is relatively fragile and is prone to corrosion and cracking in the complex environment generated during the dicing process. Placing the isolation structure in the passive area rather than the dicing area can prevent the isolation structure from being corroded and cracked in the complex environment. This can prevent cracks caused by the isolation structure from extending to the active area and causing adverse effects on the active area, thereby improving the corrosion resistance of semiconductor devices and improving the manufacturing yield and reliability of semiconductor devices.

[0005] Optionally, the epitaxial layer includes a buffer layer, a channel layer, and a barrier layer sequentially stacked along a first direction from the substrate to the electrode layer, wherein the isolation structure penetrates at least the channel layer and the barrier layer along the first direction. For example, the isolation structure penetrates the channel layer and the barrier layer along the first direction but does not penetrate the buffer layer. Since the channel layer and the barrier layer generally contain structures for signal transmission, which are susceptible to surrounding electrical interference, the isolation structure penetrating the channel layer and the barrier layer can effectively shield the surrounding electrical interference and improve the performance of the semiconductor device. Furthermore, cracks generated during dicing are more likely to extend in the channel layer and the barrier layer, so the isolation structure penetrating the channel layer and the barrier layer can prevent cracks from extending into the active region. The degree of corrosion of the channel layer and the barrier layer in a humid and hot environment has a significant impact on the performance of the semiconductor device, so the isolation structure penetrating the channel layer and the barrier layer can prevent the channel layer and the barrier layer from being corroded. In addition, when the isolation structure is formed by ion implantation, the fabrication process of the semiconductor device can be simplified and the manufacturing cost reduced. Alternatively, the isolation structure can penetrate the buffer layer, channel layer, and barrier layer along the first direction. If cracks appear in the epitaxial layer during the dicing process, these cracks will not only extend along the channel layer and barrier layer, but may also extend along the buffer layer. Therefore, when the isolation structure penetrates each film layer in the epitaxial layer, it can effectively block the extension of cracks, thereby improving the manufacturing yield, reliability, and corrosion resistance of semiconductor devices.

[0006] Optionally, the active region includes a first edge and a second edge positioned opposite each other, and the passive region includes a third edge and a fourth edge. The third edge is located between the scribe line region and the first edge, and the fourth edge is located between the scribe line region and the second edge. The gate pad is located between the first edge and the third edge, and the drain pad is located between the second edge and the fourth edge. The length of the isolation structure located between the first edge and the third edge along the second direction is a first length, and the length of the isolation structure located between the second edge and the fourth edge along the second direction is a second length. The first length is less than the second length. The second direction is the arrangement direction of the first edge and the second edge and is parallel to the substrate surface. Since the voltage applied to the gate pad is generally less than the voltage applied to the drain pad, the second length of the isolation structure near the drain pad is larger, which can increase the electrical isolation capability of this part of the isolation structure, thereby achieving effective electrical isolation. Setting the first length of the isolation structure near the gate pad smaller can reduce the process complexity.

[0007] Optionally, the isolation structure has a perforated structure. Thus, if a crack exists in the isolation structure, the perforated structure can prevent the crack from extending further towards the center of the semiconductor device, thereby further improving the manufacturing yield, reliability, and corrosion resistance of the semiconductor device.

[0008] Optionally, the semiconductor device further includes a seal, which at least partially surrounds the isolation structure, with both the gate pad and drain pad located on the side of the seal facing the active region; at least a portion of the seal is located within the electrode layer. In this way, the seal can prevent impurities from splashing into the active region during the dicing process, avoiding adverse effects on the circuitry within the active region, thereby further improving the manufacturing yield and reliability of the semiconductor device.

[0009] Furthermore, one end of the seal is located in the electrode layer, and the other end of the seal extends through the epitaxial layer towards the substrate. In this way, the seal can prevent cracks generated during the cutting process from extending into the active region, and can also prevent moisture from entering the active region in the humid and hot environment during use, thereby further improving the manufacturing yield, reliability, and corrosion resistance of semiconductor devices.

[0010] Furthermore, a groove is provided on the surface of the substrate facing the epitaxial layer, at least a portion of which is located on the passive region near the scribe line area; the other end of the seal is located within the groove. Since the penetration of cracks may cause cracking between the epitaxial layer and the substrate, the extension of the epitaxial layer into the substrate can prevent cracks from penetrating to the interface between the epitaxial layer and the substrate, thereby further improving the fabrication yield, reliability, and corrosion resistance of the semiconductor device.

[0011] Optionally, the epitaxial layer located in the dicing zone includes oxygen, and the mass percentage of oxygen in the epitaxial layer is not less than 3% of all elements included in the epitaxial layer. This indicates that the epitaxial layer located in the dicing zone contains a large amount of oxygen. Since oxidation occurs during corrosion, injecting oxygen in advance can prevent oxidation from occurring, thereby preventing further corrosion and further improving corrosion resistance.

[0012] Furthermore, the epitaxial layer comprises: a buffer layer, a channel layer, and a barrier layer sequentially stacked along a first direction from the substrate to the electrode layer; the mass percentage of oxygen in the barrier layer and the mass percentage of oxygen in the channel layer are both not less than 3%. Since the barrier layer and channel layer are more susceptible to interference during the dicing process, increasing the oxygen content in these two layers can mitigate the impact of the dicing process. Furthermore, when oxygen is introduced through ion implantation or elemental diffusion, it can simplify the fabrication process and reduce costs. It should be understood that the oxygen content in different layers is not limited to the ranges listed above and can be adjusted according to actual needs to meet the requirements of different scenarios.

[0013] Optionally, the epitaxial layer is disposed in the active region and the passive region; the semiconductor device also includes a passivation layer that covers the side of the epitaxial layer facing the dicing area. Thus, the passivation layer protects the epitaxial layer and the interface between the epitaxial layer and the substrate, preventing scratches and corrosion of the epitaxial layer during dicing. Furthermore, since there is no epitaxial layer in the dicing area, cracks in the epitaxial layer can be effectively prevented during dicing, thereby further improving the fabrication yield, reliability, and corrosion resistance of the semiconductor device.

[0014] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device. This method is used to fabricate the semiconductor device described in the first aspect and any embodiment thereof. The method may include: forming an epitaxial layer on a substrate; forming an isolation structure in the epitaxial layer; forming an electrode layer on the epitaxial layer, wherein the electrode layer is provided with a gate, a source, a drain, a gate pad, and a drain pad; the semiconductor device further includes, when an active region, a passive region, and a dicing region are sequentially arranged from the inside out, the gate, source, and drain are all located in the active region, and the gate pad and drain pad are all located in the passive region; the isolation structure is located in the passive region, and the isolation structure at least partially surrounds the active region. This can improve the fabrication yield, reliability, and corrosion resistance of the semiconductor device.

[0015] It should be understood that since the principle of the semiconductor device manufactured by this method is similar to that of the aforementioned semiconductor device, the implementation and technical effects of this method can be found in the implementation and technical effects of the aforementioned semiconductor device, and the repetition will not be repeated.

[0016] Thirdly, embodiments of this application also provide an electronic device, which may include: a housing, and a semiconductor device as described in the first aspect and any embodiment thereof, wherein the semiconductor device is disposed within the housing. Thus, by improving the performance of the semiconductor device, the performance of the electronic device is also improved.

[0017] It should be understood that since the principle by which this electronic device solves the problem is similar to that of the aforementioned semiconductor device, the implementation and technical effects of this electronic device can be found in the implementation and technical effects of the aforementioned semiconductor device, and the repetition will not be repeated. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0019] Figure 2 A top view of a wafer provided in an embodiment of this application;

[0020] Figure 3 A top view of a chip provided in an embodiment of this application;

[0021] Figure 4 For along Figure 3 The cross-sectional view shown in the x1-x2 direction;

[0022] Figure 5 A top view of an isolation structure provided in an embodiment of this application;

[0023] Figure 6 A top view of another isolation structure provided in an embodiment of this application;

[0024] Figure 7 A top view of another chip provided in an embodiment of this application;

[0025] Figure 8 For along Figure 7 A cross-sectional view shown in the x1-x2 direction;

[0026] Figure 9 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0027] Figure 10 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0028] Figure 11 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0029] Figure 12 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0030] Figure 13 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0031] Figure 14 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0032] Figure 15 For along Figure 7 Another sectional view shown in the x1-x2 direction;

[0033] Figure 16 For along Figure 7 Another sectional view shown in the x1-x2 direction.

[0034] Figure label:

[0035] m0 - Wafer, m1 - Die-Dish, m2 - Chip, m21 - Die-Dish area, m22 - Passive area, m23 - Active area, y1 - First edge, y2 - Second edge, y3 - Third edge, y4 - Fourth edge, d1 - First length, d2 - Second length, 10 - Substrate, 11 - Groove, 20 - Epitaxial layer, 21 - Buffer layer, 22 - Channel layer, 23 - Barrier layer, 30 - Electrode layer, 40 - Isolation structure, 40a - Hollow structure, 51 - Source, 52 - Gate, 53 - Drain, 54 - Field plate, 55 - Gate pad, 56 - Drain pad, 60 - Seal, 70 - Passivation layer. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0037] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0038] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0039] In the embodiments of this application, the words "first" and "second" do not limit the quantity or order.

[0040] To facilitate understanding of the technical solutions provided in the embodiments of this application, their application scenarios are first described below. The semiconductor devices provided in the embodiments of this application can be widely used in various electronic devices, which may include various terminal devices and electronic components. Terminal devices may include, but are not limited to, smartphones, smart TVs, smart TV set-top boxes, smartwatches, personal computers (PCs), wearable devices, smart broadband, etc. Electronic components may include, but are not limited to, wireless networks, fixed networks, servers, and other telecommunications equipment, as well as chip modules, memory, and other devices; these will not be listed exhaustively here. For example, semiconductor devices can be chips or devices of various power levels in electronic devices, such as, but not limited to, radio frequency amplifiers, switching devices, or terminal driver devices; these will not be listed exhaustively here.

[0041] Figure 1 An exemplary schematic diagram of a semiconductor device applied within an electronic device is shown. (Refer to...) Figure 1 As shown, the electronic device includes a housing 100 and a circuit board 200 disposed within the housing 100, with a semiconductor device 300 disposed on the circuit board 200. The semiconductor device 300 is the core of the electronic device. With continuous technological development, higher requirements are placed on the energy consumption, power, efficiency, and miniaturization of the semiconductor device 300. Materials such as GaN, GaAs, SiC, Ga2O3, AlN, and diamond have wide band gaps, offering significant advantages in high-power and high-frequency applications. Using these materials to fabricate the semiconductor device 300 ensures that it meets performance requirements.

[0042] like Figure 2 As shown, chip m2 is typically fabricated on wafer m0, and there are usually many chips m2 on wafer m0. Each chip m2 is separated by a dicing track m1. A dicing process is used to separate the individual chips m2 along the dicing track m1, resulting in individual chips m2. During use, moisture in the humid and hot environment can corrode the epitaxial layer within the chip m2, leading to low corrosion resistance.

[0043] Based on this, embodiments of this application provide a semiconductor device for improving its corrosion resistance. Exemplarily, the semiconductor device provided in this application includes: a substrate, and an epitaxial layer and an electrode layer sequentially stacked on the substrate. An isolation structure is provided within the epitaxial layer, and a gate, source, drain, gate pad, and drain pad are provided within the electrode layer. The semiconductor device further includes: an active region, a passive region, and a dicing region sequentially arranged from the inside out. The gate, source, and drain are all located in the active region, while the gate pad and drain pad are all located in the passive region. The isolation structure is located in the passive region and at least partially surrounds the active region. This isolation structure can shield electrical interference generated by other structures, achieving electrical isolation of the active region and improving the performance of the device within the active region. Furthermore, during the use of the semiconductor device, even in a humid and hot environment, the isolation structure can prevent moisture from penetrating into the epitaxial layer of the active region, avoiding moisture erosion of the epitaxial layer within the active region, thereby improving the corrosion resistance of the semiconductor device. In addition, the isolation structure is relatively fragile and is prone to corrosion and cracking in the complex environment generated during the dicing process. Placing the isolation structure in the passive area rather than the dicing area can prevent the isolation structure from being corroded and cracked in the complex environment. This can prevent cracks caused by the isolation structure from extending to the active area and causing adverse effects on the active area, thereby improving the corrosion resistance of semiconductor devices and improving the manufacturing yield and reliability of semiconductor devices.

[0044] It should be understood that the specific implementation of a semiconductor device can be a diced chip or device, or a wafer before dicing; no specific limitation is made here. The following description uses specific embodiments as examples.

[0045] Figure 3 An exemplary schematic diagram of a semiconductor device provided in an embodiment of this application is shown, with reference to... Figure 3 As shown, taking a semiconductor device as chip m2 as an example, the semiconductor device may include an active region m23, a passive region m22, and a dicing region m21 arranged sequentially from the inside out. Therefore, the active region m23 can be regarded as the region located in the center of the semiconductor device, that is, the center point A of the semiconductor device is located in the active region m23. The passive region m22 is arranged around the active region m23, so the passive region m22 is located on the side of the active region m23 away from the center point A of the semiconductor device. The dicing region m21 is arranged around the passive region m22, so the dicing region m21 is located on the side of the passive region m22 away from the active region m23. Therefore, from the inside out, the passive region m22 surrounds the active region m23, and the dicing region m21 surrounds the passive region m22.

[0046] When a semiconductor device includes a circuit composed of at least one of other active or passive devices such as transistors, resistors, capacitors, and inductors, the circuit is generally located within the active region m23. Therefore, the active region m23 can also be called the circuit region. The function of the semiconductor device can be realized through the circuit within this circuit region. When the semiconductor device includes a transistor, the gate, source, and drain of the transistor are generally located within the active region m23. It should be understood that, to avoid making the attached diagrams overly complex, Figure 3 The circuit is not shown in the diagram.

[0047] When the semiconductor device also includes a gate pad 55 and a drain pad 56, the gate pad 55 and the drain pad 56 are connected to the circuitry within the active region m23. For example, the gate pad 55 is typically connected to the gate 52 of the transistor, and the drain pad 56 is typically connected to the drain 53 of the transistor. Figures 3 to 6 These connections are not shown in the diagram. Signal transmission between the circuit and the outside world can be achieved through the gate pad 55 and drain pad 56, thereby enabling the normal operation of the semiconductor device. At this time, the gate pad 55 and drain pad 56 are generally located within the passive region m22.

[0048] The area between the dicing channel m1 and the passive region m22 is the dicing channel region m21. When dicing the wafer, the dicing is usually performed along the dicing channel m1. Therefore, the setting of the dicing channel region m21 can avoid adverse effects on the structure in the active region m23 and the passive region m22 during dicing, thereby improving the manufacturing yield and performance of the chip m2.

[0049] See Figure 4 As shown, Figure 4 For along Figure 3 The cross-sectional view shown along the x1-x2 direction in the figure shows that the semiconductor device may further include: a substrate 10, and an epitaxial layer 20 and an electrode layer 30 sequentially stacked on the substrate 10; a gate 52, a source 51, a drain 53, a gate pad 55, and a drain pad 56 are all disposed within the electrode layer 30. Of course, when the semiconductor device also includes other conductive structures such as a field plate 54, the field plate 54 and other conductive structures may also be disposed within the electrode layer 30; furthermore, the electrode layer 30 also includes a dielectric material used to insulate the conductive structures. Along the first direction from the substrate 10 to the electrode layer 30, i.e. Figure 4 In the z-direction, the epitaxial layer 20 may include a buffer layer 21, a channel layer 22, and a barrier layer 23 stacked sequentially. Therefore, the buffer layer 21 is the layer closest to the substrate 10 in the epitaxial layer 20, and the barrier layer 23 is the layer farthest from the substrate 10 in the epitaxial layer 20. Each layer in the epitaxial layer 20 can be formed using epitaxial technology and can be made using other ultra-wide bandgap semiconductor materials such as Si, GaAs, SiC, GaN, Ga2O3, or AlN. It should be understood that different layers in the epitaxial layer 20 are all formed using semiconductor materials through epitaxial technology. The specific materials used to fabricate each layer in the epitaxial layer 20 can be set according to actual needs and are not specifically limited here.

[0050] The semiconductor device may further include an isolation structure 40, which is disposed within the epitaxial layer 20 and located within the passive region m22. The isolation structure 40 may at least partially surround the active region m23. This isolation structure 40 can shield electrical interference generated by other structures, achieving electrical isolation of the active region m23 and improving the performance of the device within the active region m23. Furthermore, the isolation structure 40 is relatively fragile and prone to corrosion and cracking under the complex environment generated during the dicing process. By placing the isolation structure 40 in the passive region m22 rather than the dicing area m21, corrosion and cracking of the isolation structure 40 under complex conditions can be avoided. This prevents cracks in the isolation structure 40 from extending to the active region m23 and adversely affecting it, thereby improving the corrosion resistance of the semiconductor device and increasing its manufacturing yield and reliability. Furthermore, during the use of semiconductor devices, even in humid and hot environments, the isolation structure 40 can prevent moisture from penetrating into the epitaxial layer 20 of the active region m23, thus preventing the epitaxial layer 20 in the active region m23 from being corroded by moisture, thereby improving the corrosion resistance of semiconductor devices.

[0051] It should be understood that the isolation structure 40 at least partially surrounds the active region m23, which can be understood as: the isolation structure 40 is a closed structure, and this closure completely surrounds the active region m23, such as... Figure 3As shown in the diagram; alternatively, the isolation structure 40 is a non-closed structure with two ends and a certain gap between them. In this case, the isolation structure 40 partially surrounds the active region m23, but is not shown in the diagram. Furthermore, since the material used to fabricate the isolation structure 40 differs from the materials used to fabricate the layers in the epitaxial layer 20, the resistivity of the isolation structure 40 is generally higher than that of the layers in the epitaxial layer 20, thus achieving a barrier function. In addition, the layers in the epitaxial layer 20 are easily corroded in the complex environment generated during the cutting process or in humid and hot environments. The isolation structure 40 can prevent the epitaxial layer 20 within the active region m23 from being corroded, improving the corrosion resistance of the semiconductor device.

[0052] For example, the isolation structure 40 may extend at least through the channel layer 22 and the barrier layer 23 along the first direction. For example, the isolation structure 40 penetrates the channel layer 22 and the barrier layer 23 along the first direction but does not penetrate the buffer layer 21. Since the channel layer 22 and the barrier layer 23 generally contain some structures for signal transmission, these structures are easily affected by surrounding electrical interference. Therefore, the isolation structure 40 penetrating the channel layer 22 and the barrier layer 23 can effectively shield the surrounding electrical interference and improve the performance of the semiconductor device. Furthermore, cracks generated during dicing are more likely to extend in the channel layer 22 and the barrier layer 23. Therefore, the isolation structure 40 penetrating the channel layer 22 and the barrier layer 23 can prevent cracks from extending into the active region m23. The degree of corrosion of the channel layer 22 and the barrier layer 23 in a humid and hot environment has a significant impact on the performance of the semiconductor device. Therefore, the isolation structure 40 penetrating the channel layer 22 and the barrier layer 23 can prevent the channel layer 22 and the barrier layer 23 from being corroded. In addition, when the isolation structure 40 is formed by ion implantation, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost reduced. Alternatively, the isolation structure 40 can penetrate the buffer layer 21, the channel layer 22, and the barrier layer 23 along the first direction. If a crack appears in the epitaxial layer 20 during the dicing process, the crack will not only extend along the channel layer 22 and the barrier layer 23, but may also extend along the buffer layer 21. Therefore, when the isolation structure 40 penetrates each film layer in the epitaxial layer 20, it can effectively block the extension of cracks, thereby improving the manufacturing yield, reliability, and corrosion resistance of semiconductor devices.

[0053] Combination Figure 4 As shown, the active region m23 includes a first edge y1 and a second edge y2 positioned opposite each other. The first edge y1 and the second edge y2 can be arranged along a second direction, which can be... Figure 4The x-direction is shown in the diagram; the passive region m22 includes a third edge y3 and a fourth edge y4. The third edge y3 and the fourth edge y4 can also be arranged along the second direction. The third edge y3 is located between the slicing channel region m21 and the first edge y1, and the fourth edge y4 is located between the slicing channel region m21 and the second edge y2. Therefore, the first edge y1 and the second edge y2 can be considered as two edges at the boundary between the active region m23 and the passive region m22, and the third edge y3 and the fourth edge y4 can be considered as two edges at the boundary between the passive region m22 and the slicing channel region m21. When the isolation structure 40 at least partially surrounds the active region m23, the first edge y1 and the second edge y2 can overlap with the edges of the isolation structure 40 facing the active region m23. That is, the area surrounded by the isolation structure 40 is the active region m23, as shown in the diagram. Figure 3 and Figure 4 As shown; or, the portion of the isolation structure 40 facing the edge of the active region m23 is located between the first edge y1 and the third edge y3, and between the second edge y2 and the fourth edge y4. That is, the boundary between the active region m23 and the passive region m22 does not overlap with the edge of the isolation structure 40 facing the active region m23. Therefore, the area surrounded by the passive region m22 is the active region m23, which is not shown in the diagram. In summary, regardless of the location of the isolation structure 40 within the passive region m22, electrical isolation of the active region m23 can be achieved, as well as improvements in the manufacturing yield, reliability, and corrosion resistance of semiconductor devices.

[0054] When the gate pad 55 is located between the first edge y1 and the third edge y3, and the drain pad 56 is located between the second edge y2 and the fourth edge y4, the length of the isolation structure 40 located between the first edge y1 and the third edge y3 along the second direction is the first length d1, and the length of the isolation structure 40 located between the second edge y2 and the fourth edge y4 along the second direction is the second length d2. The relationship between the first length d1 and the second length d2 can be as follows:

[0055] Method 1 The first length d1 is equal to the second length d2, such as... Figure 4 As shown.

[0056] Method 2 The first length d1 is less than the second length d2, such as... Figure 5 As shown, since the voltage applied to the gate pad 55 is generally less than the voltage applied to the drain pad 56, the portion of the isolation structure 40 near the drain pad 56 (such as...) Figure 5 The second length d2 of the area indicated by 42 in the diagram is relatively large, which can increase the electrical isolation capability of this part of the isolation structure 40, thereby achieving effective electrical isolation; the part of the isolation structure 40 near the gate pad 55 (such as...) Figure 5Setting the first length d1 of the area indicated by 41 in the diagram to a smaller value can reduce process complexity.

[0057] Method 3 The first length d1 is greater than the second length d2, which is not shown in the figure. When the voltage applied to the gate pad 55 is less than the voltage applied to the drain pad 56, the electrical isolation capability will be weaker compared with the above method 2, but electrical isolation can still be achieved to a certain extent. If the voltage applied to the gate pad 55 is greater than the voltage applied to the drain pad 56, then this method can also achieve an effective electrical isolation effect.

[0058] In summary, the relationship between the first length d1 and the second length d2 can be determined by choosing from methods 1, 2, or 3 as described above, and is not specifically limited here. Similarly, the dimensions of other positions within the isolation structure 40 can be set according to actual needs, and are not specifically limited here.

[0059] Furthermore, the isolation structure 40 may have a cutout structure 40a, wherein the cutout structure 40a may be located in the portion of the isolation structure 40 near the drain pad 56 (e.g., Figure 6 In the 42 indicated areas, such as Figure 6 As shown in the diagram; or, the cutout structure 40a may be located in this portion of the isolation structure 40 near the gate pad 55 (as shown in the diagram). Figure 6 In the area indicated by 41 in the diagram, no illustration is provided; or, the hollow structure 40a can be located in other positions of the isolation structure 40, etc. The specific configuration can be determined according to actual needs, and is not specifically limited here. It should be understood that the hollow structure 40a can be implemented based on any of the structures described in Method 1, Method 2, and Method 3 above. Figure 6 The illustration only demonstrates implementation based on Method 2, but is not limited to Method 2; it can also be implemented based on Method 1 or Method 3, only without illustration. Furthermore, the number and shape of the cutout structures 40a can be set according to actual needs and are not specifically limited here. Thus, if the isolation structure 40 has cracks, the presence of the cutout structures 40a can prevent the cracks from continuing to extend towards the center of the semiconductor device, thereby further improving the manufacturing yield, reliability, and corrosion resistance of the semiconductor device.

[0060] Figures 7 to 10 An exemplary schematic diagram of another semiconductor device provided in an embodiment of this application is shown, with reference to... Figures 7 to 10 As shown, the structure of the semiconductor device in this embodiment is the same as that described above. Figures 4 to 6The semiconductor devices in any of the described embodiments have a generally similar structure, with the difference being that the semiconductor device also includes a seal 60. Exemplarily, the seal 60 at least partially surrounds the isolation structure 40, with the gate pad 55 and drain pad 56 both disposed on the side of the seal 60 facing the active region m23, and at least a portion of the seal 60 located within the electrode layer 30. Thus, the seal 60 can prevent impurities from splashing into the active region m23 during the dicing process, avoiding adverse effects of impurities on the circuitry within the active region m23, thereby further improving the fabrication yield and reliability of the semiconductor device.

[0061] It should be understood that the seal 60 can be disposed on the side of the passive region m22 near the dicing region m21. When the seal 60 at least partially surrounds the isolation structure 40, the seal 60 can be a closed structure (not shown), which completely surrounds the isolation structure 40 and encloses the gate pad 55, drain pad 56, and the circuitry within the active region m23. Alternatively, the seal 60 can be a non-closed structure that partially surrounds the isolation structure 40 and similarly encloses the gate pad 55, drain pad 56, and the circuitry within the active region m23, thereby protecting the active region m23.

[0062] The layout of the seal 60 can include the following:

[0063] The first type The sealing element 60 is disposed above the epitaxial layer 20 and located on the electrode layer 30, such as... Figure 8 As shown, the seal 60 can prevent impurities from splashing into the active area m23 during the cutting process, thus avoiding the impurities from having an adverse effect on the circuit in the active area m23.

[0064] The second type A portion of the seal 60 is located in the electrode layer 30, and another portion is located in the epitaxial layer 20, such as... Figure 9 and Figure 10 As shown, that is, one end of the seal 60 (such as...) Figure 9 The top end of the seal 60 shown is located on the electrode layer 30, and the other end of the seal 60 (as shown) Figure 9 The bottom end of the seal 60 shown penetrates the epitaxial layer 20 towards the substrate 10. In this way, the seal 60 can prevent cracks generated during the cutting process from extending into the active region m23, and can also prevent moisture from entering the active region m23 in the humid and hot environment during use, thereby further improving the manufacturing yield, reliability and corrosion resistance of the semiconductor device.

[0065] In this second approach, the other end of the seal 60 can be located at the interface between the substrate 10 and the epitaxial layer 20; in other words, the end face of the other end of the seal 60 stops on the surface of the substrate 10, such as... Figure 9As shown; or, when a groove 11 is provided on the surface of the substrate 10 facing the epitaxial layer 20, and at least a portion of the groove 11 is located on the side of the passive region m22 near the scribe line region m21, the other end of the seal 60 is located within the groove 11, as shown. Figure 10 As shown. Since the penetration of cracks may cause cracks to appear between the epitaxial layer 20 and the substrate 10, the extension of the epitaxial layer 20 into the substrate 10 can prevent cracks from penetrating to the interface between the epitaxial layer 20 and the substrate 10, thereby further improving the manufacturing yield, reliability and corrosion resistance of semiconductor devices.

[0066] For example, the seal 60 may be made of materials such as metal or metal oxide, and any material that can achieve the function of the seal 60 is applicable to the embodiments of this application.

[0067] It should be understood that the structure of the semiconductor device in this embodiment is the same as that described above. Figures 4 to 6 For similarities in the structure of the semiconductor devices in any of the described embodiments, please refer to the relevant descriptions in the foregoing embodiments; repeated details will not be repeated.

[0068] Figures 11 to 16 An exemplary schematic diagram of another semiconductor device provided in an embodiment of this application is shown, with reference to... Figures 11 to 16 As shown, the structure of the semiconductor device in this embodiment is the same as that described above. Figures 4 to 10 The semiconductor devices in any of the described embodiments have a generally similar structure, with the difference being that the epitaxial layer 20 within the scribe line region m21 is etched.

[0069] For example, the epitaxial layer 20 within the scribe line region m21 is completely etched away, while the epitaxial layer 20 within the passive region m22 remains unetched. In this case, the sides of the epitaxial layer 20 and the exposed surface of the substrate 10 within the scribe line region m21 can be covered by a dielectric material. This dielectric material protects the epitaxial layer 20 and the interface between the epitaxial layer 20 and the substrate 10, preventing scratches and corrosion of the epitaxial layer 20 during dicing. Furthermore, since there is no epitaxial layer 20 within the scribe line region m21, cracks in the epitaxial layer 20 can be effectively prevented during dicing, thereby further improving the manufacturing yield, reliability, and corrosion resistance of the semiconductor device. The dielectric material can be directly deposited on the surface of the substrate 10, such as... Figure 11 As shown, this simplifies the manufacturing process and improves manufacturing efficiency; alternatively, a groove is formed on the surface of the substrate 10 facing the epitaxial layer 20, and the dielectric material is deposited in the groove, such as... Figure 12 As shown, the dielectric material can effectively protect the interface between the epitaxial layer 20 and the substrate 10, preventing cracking between the epitaxial layer 20 and the substrate 10.

[0070] Alternatively, not only is the entire epitaxial layer 20 within the scribe line region m21 etched away, but a portion of the epitaxial layer 20 within the passive region m22 can also be etched away. In this case, if a seal 60 is provided, and the seal 60 extends to the surface of the substrate 10 or into a groove within the substrate 10, the seal 60 can cover the sides of the inner and outer epitaxial layers 20 within the passive region m22. The side of the seal 60 facing the scribe line region m21 is covered by a dielectric material, such as... Figure 13 As shown; if the side of the epitaxial layer 20 is not covered by the seal 60, then the side of the epitaxial layer 20 can be covered by the medium material, which is not shown in the figure, thereby achieving protection of the epitaxial layer 20.

[0071] Alternatively, a portion of the epitaxial layer 20 within the diced region m21 may be etched away, and the etched portion can be filled or covered by a dielectric material. For example, such as... Figure 14 As shown, the epitaxial layer 20 within the scribe line region m21 shown on the left side of the figure is not etched, while the epitaxial layer 20 within the scribe line region m21 shown on the right side of the figure is etched. Furthermore, a portion of the epitaxial layer 20 within the scribe line region m21 shown on the right side of the figure is etched. For example, a trench is provided in the region between the scribe line and the passive region m22, and this trench passes through all the layers in the epitaxial layer 20 along the z-direction (e.g., ...). Figure 15 (As shown) or a portion of the film (not shown); for example, the different sizes of the different films in the epitaxial layer 20 inside and outside the scribe line region m21 are etched, so that the side surface of the epitaxial layer 20 is not a vertical surface, but a slope (as shown). Figure 16 Examples include curved surfaces (not shown) or surfaces with special shapes (not shown). Of course, when part of the epitaxial layer 20 within the dicing region m21 is etched away, the specific implementation method is not limited to... Figures 14 to 16 The methods shown here can also be other than these; they are just examples. Figures 14 to 16 The structure shown is merely an example for illustration; the specific configuration can be adjusted according to actual needs to improve design flexibility and meet the requirements of different scenarios.

[0072] It should be understood that, regardless of the structure described above, the film layer formed by the covering or filling dielectric material can be regarded as the passivation layer 70, and the material used to make the passivation layer 70 can be the same as or different from the dielectric material in the electrode layer 30.

[0073] In summary, the etching morphology, etching range, and etching area can be flexibly adjusted according to factors such as process, application scenario, and structural complexity of semiconductor devices, thereby improving corrosion resistance in different scenarios.

[0074] It should be understood that the structure of the semiconductor device in this embodiment is the same as that described above. Figures 4 to 10For similarities in the structure of the semiconductor devices in any of the described embodiments, please refer to the relevant descriptions in the foregoing embodiments; repeated details will not be repeated.

[0075] This application provides another semiconductor device, the structure of which is the same as that described above. Figures 4 to 16 The semiconductor devices in any of the described embodiments have a generally similar structure, with the following differences: when an epitaxial layer is provided within the scribe line region, the epitaxial layer located in the scribe line region may include oxygen. For example, the mass percentage of oxygen in the epitaxial layer is not less than 3% of all elements included in the epitaxial layer. This indicates that the epitaxial layer located in the scribe line region contains a large amount of oxygen. Since oxidation occurs alongside corrosion, pre-implantation of oxygen can prevent oxidation, thereby preventing further corrosion and further improving corrosion resistance.

[0076] The oxygen content in each epitaxial layer can be the same or different. For example, but not limited to, when the epitaxial layer includes a buffer layer, a channel layer, and a barrier layer, the mass percentage of oxygen in the barrier layer should be no less than 3%, the mass percentage of oxygen in the channel layer should be no less than 3%, and the mass percentage of oxygen in the buffer layer should be no less than 3%. Since the barrier layer and channel layer are more easily affected during the dicing process, increasing the oxygen content of these two layers can avoid the impact of the dicing process. When oxygen is obtained through ion implantation or element diffusion, it can also simplify the fabrication process and reduce costs. It should be understood that the oxygen content in different layers is not limited to the ranges listed above and can be set according to actual needs to meet the requirements of different scenarios.

[0077] It should be understood that the structure of the semiconductor device in this embodiment is the same as that described above. Figures 4 to 16 For similarities in the structure of the semiconductor devices in any of the described embodiments, please refer to the relevant descriptions in the foregoing embodiments; repeated details will not be repeated.

[0078] This application provides a method for fabricating a semiconductor device, which can be used to fabricate the aforementioned... Figures 4 to 16 In any of the described embodiments, the semiconductor device and the method of fabrication may include:

[0079] Step 1: Form an epitaxial layer on the substrate. For example, epitaxial technology can be used, and semiconductor materials such as GaN can be used, to sequentially form a buffer layer, a channel layer and a barrier layer on the substrate, so that the buffer layer, the channel layer and the barrier layer constitute an epitaxial layer, and the buffer layer, the channel layer and the barrier layer are all three film layers formed by different doping methods based on GaN material.

[0080] Step 2: Form an isolation structure in the epitaxial layer; for example, ion implantation technology can be used to form the isolation structure in the epitaxial layer.

[0081] Step 3: Form an electrode layer on the epitaxial layer. For example, the gate, source, and drain can be fabricated simultaneously using the same process, so they can be located in the same film layer, which is temporarily referred to as the first film layer. The area of ​​the first film layer other than the gate, source, and drain can be filled with a dielectric material to achieve insulation between the gate, source, and drain. When the semiconductor device also includes a field plate, the field plate can be fabricated on the first film layer and then filled with a dielectric material. When the film layer containing the field plate is referred to as the second film layer, the first and second film layers together constitute the electrode layer. The gate pad and drain pad can be disposed in the same layer as the field plate, or, if a third film layer is also present, the gate pad and drain pad are located in the third film layer. In this case, the first, second, and third film layers together constitute the electrode layer. Furthermore, the gate, source, and drain are all located in the active region, and the gate pad and drain pad are all located in the passive region. The isolation structure is located in the passive region, and the isolation structure at least partially surrounds the active region.

[0082] Thus, the isolation structure can shield electrical interference from other structures, achieving electrical isolation of the active region and improving the performance of devices within it. Furthermore, isolation structures are relatively fragile and prone to corrosion and cracking in the complex environments created during the dicing process. Placing the isolation structure in the passive region rather than the dicing area prevents corrosion and cracking under these conditions, thus preventing cracks from extending to the active region and adversely affecting it. This improves the corrosion resistance of semiconductor devices, increasing their manufacturing yield and reliability. In addition, even in humid and hot environments, the isolation structure prevents moisture from penetrating into the epitaxial layer of the active region, avoiding moisture erosion and further enhancing the corrosion resistance of the semiconductor device.

[0083] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: The substrate, and an epitaxial layer and an electrode layer stacked sequentially on the substrate, wherein the epitaxial layer has an isolation structure and the electrode layer has a gate, a source, a drain, a gate pad and a drain pad. The semiconductor device further includes: an active region, a passive region, and a dicing region arranged sequentially from the inside out; the gate, the source, and the drain are all disposed in the active region; the gate pad and the drain pad are all disposed in the passive region; and the isolation structure is disposed in the passive region, with the isolation structure at least partially surrounding the active region.

2. The semiconductor device as claimed in claim 1, characterized in that, The epitaxial layer includes a buffer layer, a channel layer, and a barrier layer stacked sequentially along a first direction from the substrate to the electrode layer, wherein the isolation structure extends at least through the channel layer and the barrier layer along the first direction.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The active region includes a first edge and a second edge that are opposite to each other, and the passive region includes a third edge and a fourth edge. The third edge is located between the slicing area and the first edge, and the fourth edge is located between the slicing area and the second edge. The gate pad is disposed between the first edge and the third edge, and the drain pad is disposed between the second edge and the fourth edge; The length of the isolation structure between the first edge and the third edge along the second direction is a first length, and the length of the isolation structure between the second edge and the fourth edge along the second direction is a second length, wherein the first length is less than the second length; the second direction is the arrangement direction of the first edge and the second edge and is parallel to the substrate surface.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The isolation structure has a hollow structure.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The semiconductor device further includes a seal that at least partially surrounds the isolation structure, wherein the gate pad and the drain pad are both disposed on the side of the seal facing the active region; at least a portion of the seal is located within the electrode layer.

6. The semiconductor device as claimed in claim 5, characterized in that, One end of the seal is located in the electrode layer, and the other end of the seal extends through the epitaxial layer toward the substrate.

7. The semiconductor device as claimed in claim 6, characterized in that, The substrate has a groove on one side of its surface facing the epitaxial layer, at least a portion of which is located on the side of the passive region near the dicing area; the other end of the seal is located within the groove.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The epitaxial layer located in the dicing zone includes oxygen, and the mass percentage of oxygen in the epitaxial layer is not less than 3% of all elements included in the epitaxial layer.

9. The semiconductor device as claimed in claim 8, characterized in that, The epitaxial layer includes a buffer layer, a channel layer, and a barrier layer sequentially stacked along a first direction from the substrate to the electrode layer. The oxygen element has a mass percentage of not less than 3% in the barrier layer and a mass percentage of not less than 3% in the channel layer.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The epitaxial layer is disposed in the active region and the passive region; The semiconductor device further includes a passivation layer that covers the side of the epitaxial layer facing the scribe line region.

11. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial layer is formed on the substrate; An isolation structure is formed in the epitaxial layer; An electrode layer is formed on the epitaxial layer, and the electrode layer contains a gate, a source, a drain, a gate pad, and a drain pad; the semiconductor device further includes an active region, a passive region, and a diced region arranged sequentially from the inside out, wherein the gate, the source, and the drain are all located in the active region, and the gate pad and the drain pad are all located in the passive region; the isolation structure is located in the passive region, and the isolation structure at least partially surrounds the active region.

12. An electronic device, characterized in that, It includes: a housing, and a semiconductor device as described in any one of claims 1-10, wherein the semiconductor device is disposed within the housing.

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