Method of manufacturing an integrated device and integrated device
By employing plasma doping and structural optimization in CS SOI integrated devices, core and shell layers with different doping characteristics are formed, solving the problem of performance improvement in CS SOI integrated devices and achieving device performance optimization and suppression of short-channel effects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOI MICRO CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-05
AI Technical Summary
How to improve the performance of CS SOI integrated devices, especially through doping characteristics and structural optimization.
Alternating sacrificial layers and pre-formed nanosheets are formed on a substrate, and nanosheets in different regions are plasma-doped to form core and shell layers with different doping characteristics. Subsequently, a ring gate device is patterned and sidewalls are formed on the sidewalls. After removing the sacrificial layers, an epitaxial shell layer is formed to form a gate stack around the core layer.
By employing flexible doping characteristics and structural design, the performance of the gate-to-ring device was optimized, the short-channel effect was suppressed, and the overall performance of the device was improved.
Smart Images
Figure CN122161152A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more specifically to a method for manufacturing an integrated device and an integrated device. Background Technology
[0002] With the development of silicon-on-insulator (SOI) technology and core-and-shell (CS) devices, the advantages of CS devices have gradually become apparent. However, how to improve the performance of CS SOI integrated devices remains an urgent problem to be solved. Summary of the Invention
[0003] In view of the above problems, this disclosure provides a method for manufacturing an integrated device and an integrated device.
[0004] According to one aspect of this disclosure, a method for manufacturing an integrated device is provided, comprising: forming a plurality of alternately stacked sacrificial layers and pre-prepared nanosheets in a vertical direction on a substrate, wherein, after each formation of the pre-prepared nanosheets, the pre-prepared nanosheets are doped with plasma in a first region of the substrate to have a first doping characteristic and in a second region of the substrate, different from the first region, the pre-prepared nanosheets are doped with a second doping characteristic different from the first doping characteristic; patterning the sacrificial layers and pre-prepared nanosheets together into a first fin and a second fin extending along a first direction in the first region and the second region, respectively; forming in the first region and the second region of the substrate a second fin extending along a second direction intersecting the first direction, thereby connecting with the first fin and the second fin. A first sacrificial gate and a second sacrificial gate with intersecting fins are formed, and a first sidewall and a second sidewall are formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively. A first source / drain layer is formed on both sides of the first sidewall in a first direction to connect with the prepared nanosheet on the first region, and a second source / drain layer is formed on both sides of the second sidewall in a first direction to connect with the prepared nanosheet on the second region. The sacrificial layer is removed from the inner sides of the first sidewall and the second sidewall to expose the prepared nanosheet. The exposed portion of the prepared nanosheet is etched to form a core layer, and a shell layer is further epitaxially formed on the surface of the core layer. The core layer and the shell layer form a nanosheet. A first gate stack and a second gate stack are formed around the periphery of the nanosheet in the first sidewall and the second sidewall, respectively.
[0005] According to another aspect of this disclosure, an integrated device is provided, comprising: a substrate; a first channel portion and a second channel portion respectively on a first region of the substrate and a second region different from the first region, the first channel portion including a plurality of first nanosheets extending along a first direction and spaced apart from each other in a vertical direction, the second channel portion including a plurality of second nanosheets extending along the first direction and spaced apart from each other in a vertical direction, wherein each nanosheet includes a core layer and a shell layer surrounding the core layer, wherein the core layer and the shell layer are respectively doped with different doping characteristics, the core layer of the first nanosheet is doped with a first doping characteristic and the core layer of the second nanosheet is doped with a second doping characteristic different from the first doping characteristic; a first gate stack and a second gate stack respectively extending along a second direction intersecting the first direction and surrounding the outer periphery of the first nanosheet and the second nanosheet in the first region and the second region of the substrate; a first sidewall on the sidewall of the first gate stack and a second sidewall on the sidewall of the second gate stack; and a first source / drain layer on both sides of the first sidewall in the first direction and respectively connected to the first channel portion and the second source / drain layer on both sides of the second sidewall in the first direction and respectively connected to the second channel portion.
[0006] According to embodiments of this disclosure, an integrated device is provided. In this integrated device, core layers in different regions and / or at different heights can be doped with different doping characteristics, such as different conductivity types and / or different doping concentrations. A shell layer can surround the core layer to form a nanosheet. Thus, the device performance of a gate-to-ring device implemented based on such a nanosheet can be optimized separately through different doping characteristics. Attached Figure Description
[0007] The above-mentioned contents, other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings, which will be described in conjunction with the drawings.
[0008] Figure 1A The schematic diagram shows a cross-sectional view of the integrated device according to an embodiment of the present disclosure in a second direction.
[0009] Figure 1B A schematic cross-sectional view of an integrated device according to an embodiment of the present disclosure is shown in a first direction.
[0010] Figure 2 A flowchart illustrating a method for manufacturing an integrated device according to an embodiment of the present disclosure is shown schematically.
[0011] Figures 3-8 The illustration schematically depicts some processes for doping prepared nanosheets according to embodiments of the present disclosure.
[0012] Figures 9-16 The illustration schematically depicts some processes for manufacturing integrated devices according to embodiments of the present disclosure. Detailed Implementation
[0013] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0015] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0016] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).
[0017] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0018] With the development of silicon-on-insulator (SOI) technology and core-shell (CS) devices, the advantages of CS devices (such as improved channel mobility) have gradually become apparent.
[0019] Furthermore, CS devices are characterized by their dual-channel structure. Taking the core-shell junctionless (CSJL) SOI nanosheet (NS) structure as an example, the CSJL SOI NS structure has a core (2-8 nm thick) at its center, surrounded by a shell (2-8 nm thick). The core and shell together form the nanosheet. The core is heavily doped (approximately 1e18-5e19 cm⁻¹). -3 The structure of ).
[0020] Based on this, embodiments of this disclosure provide an integrated device. The integrated device may include two or more gate-ring devices integrated together. Further, at least a portion of the two or more gate-ring devices may be implemented based on a CSJL SOI NS structure doped with different doping characteristics. The following description is in conjunction with the accompanying drawings.
[0021] Figure 1A The schematic diagram shows a cross-sectional view of the integrated device according to an embodiment of the present disclosure in a second direction. Figure 1B A schematic cross-sectional view of an integrated device according to an embodiment of the present disclosure is shown in a first direction.
[0022] like Figure 1A and Figure 1B As shown, the integrated device in this embodiment may include a substrate and two gate-around devices integrated together on the substrate. Although two gate-around devices are described here as an example, the specific number of gate-around devices is not limited thereto.
[0023] The substrate can be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator substrate. Based on this, the gate-around device according to this embodiment can be a fully depleted silicon-on-insulator (FDSOI) device. However, this disclosure is not limited thereto; in other embodiments, the substrate can also be a bulk silicon substrate, etc., which will not be elaborated here. The following description uses an SOI substrate as an example.
[0024] The SOI substrate may include a base substrate 101 and a buried oxide layer 102, and a gate ring device on the buried oxide layer 102, which are sequentially disposed in the vertical direction Z. For example, the base substrate 101 may include silicon, etc. The buried oxide layer 102 may include silicon dioxide, etc. The gate ring device (specifically, the channel portion of the gate ring device) may be adjacent to the buried oxide layer 102. Furthermore, in the SOI substrate, an active region may be defined by an isolation portion 10S, such as shallow trench isolation (STI). And, the gate ring device may be formed on the active region. It should be understood that the two gate ring devices described above may also be isolated from each other by a dielectric layer.
[0025] For example, the gate-ring device may include a gate-ring field-effect transistor (GAAFET). Furthermore, the two gate-ring devices on the substrate may have different doping characteristics relative to each other. For example, the doping characteristics of the two gate-ring devices may differ in terms of conductivity type and / or doping concentration.
[0026] In terms of conductivity type, one of these two ring gate devices can be a p-type device and the other can be an n-type device.
[0027] For example, the substrate may include a first region (which may serve as an nFET region) and a second region (which may serve as a pFET region) that are distinct from each other. The first and second regions may extend along a first direction X (e.g., a first horizontal direction) and be adjacent in a second direction Y (e.g., a second horizontal direction) that intersects (e.g., is perpendicular to) the first direction X. Based on this, the two ring gate devices described above may include a first ring gate device in the first region and a second ring gate device in the second region. Figure 1B The image shows a cross-sectional view of the first ring gate device in the first region along the first direction X. The second ring gate device in the second region may have substantially the same structure, except for different doping characteristics.
[0028] Furthermore, the two gate ring devices can be the CSJL SOI NS structure described above. Thus, in this embodiment, the p-type and n-type can be implemented based on the doping type of the core layer of each of the two gate ring devices.
[0029] For example, a first ring gate device may include a first channel portion, a first gate stack, a first sidewall, and a first source / drain layer. A second ring gate device may include a second channel portion, a second gate stack, a second sidewall, and a second source / drain layer. The first channel portion and the second channel portion may each include a corresponding shell layer and a core layer.
[0030] Specifically, the first channel portion includes a plurality of first nanosheets extending along a first direction X and spaced apart from each other in a vertical direction Z. The second channel portion includes a plurality of second nanosheets extending along the first direction X and spaced apart from each other in a vertical direction Z. For example, the materials of the first and second nanosheets may be silicon, etc. Furthermore, each of the plurality of first nanosheets and each of the plurality of second nanosheets each includes a core layer and a shell layer surrounding the core layer.
[0031] For each nanosheet, the core and shell are doped with different conductivity types. For example, if the core is doped with a first conductivity type, the outer shell can be doped with the opposite second conductivity type, and vice versa. Furthermore, the core can be heavily doped while the shell can be lightly doped.
[0032] In one embodiment, with respect to the first nanosheet and the second nanosheet, the core layer 1031 of the first nanosheet is doped with a first conductivity type (e.g., either n-type or p-type), and the core layer 1032 of the second nanosheet is doped with a second conductivity type different from the first conductivity type (e.g., either p-type or n-type). For example, the doping concentration of the core layer is 1e18~5e19 cm⁻¹. -3 The core layer has a doping thickness of 5~20 nm. Furthermore, for example, the shell 1033 of the first nanosheet can be of the second conductivity type, and the shell 1034 of the second nanosheet can be of the first conductivity type.
[0033] In another embodiment, the core layer 1031 of the first nanosheet and the core layer 1032 of the second nanosheet can be doped with the same conductivity type but with different doping concentrations. Alternatively, the core layer 1031 of the first nanosheet and the core layer 1032 of the second nanosheet can be doped with different conductivity types and with different doping concentrations.
[0034] The first gate stack and the second gate stack extend along the second direction Y and surround the outer periphery of the first nanosheet and the second nanosheet, respectively.
[0035] For example, each of the first and second gate stacks may include a gate dielectric layer 1071, a work function layer 1072, and a gate electrode layer 1073. For example, the gate dielectric layer 1071 may include a high-k gate dielectric such as hafnium oxide (HfO2). An interface oxide layer (not shown in the figure) may exist between the gate dielectric layer 1071 and the nanosheet. The work function layer 1072 may include a metal nitride such as TiN and has a suitable work function, for example, an n-type work function for n-type devices and a p-type work function for p-type devices. Therefore, for ease of distinction, in... Figure 1ADifferent colors are used to indicate different work function layers. The gate electrode layer 1073 may include a conductive material, such as a metal like tungsten (W).
[0036] Furthermore, a first sidewall is formed on the sidewall of the first grid stack in the first direction X. A second sidewall is formed on the sidewall of the second grid stack in the first direction X. Furthermore, in Figure 1B The diagram schematically illustrates the gate sidewall 104 and inner sidewall 105 included in the first sidewall. It should be understood that the second sidewall also includes corresponding gate sidewalls and inner sidewalls, which will not be described in detail here. The first and second sidewalls may extend along a second direction Y, and at least one of them may include, for example, a nitride (e.g., silicon nitride).
[0037] Continue to refer to Figure 1B The first source / drain layer 106 is located on both sides of the first sidewall in the first direction X and is in contact with the first channel portion. Similarly, the second source / drain layer is located on both sides of the second sidewall in the first direction X and is in contact with the second channel portion. For example, the first source / drain layer 106 and the second source / drain layer may comprise semiconductor materials such as silicon of the same system as the first and second channel portions, and may be doped to a conductivity type suitable for the first and second gate ring devices, such as n-type or p-type.
[0038] Furthermore, in one embodiment of this disclosure, at least two, or even all, of the plurality of first nanosheets have the same doping concentration relative to each other. At least two, or even all, of the plurality of second nanosheets have the same doping concentration relative to each other. However, the embodiments of this disclosure are not limited thereto. In another embodiment, at least two, or even all, of the plurality of first nanosheets have different doping concentrations relative to each other. At least two, or even all, of the plurality of second nanosheets have different doping concentrations relative to each other. Furthermore, in yet another embodiment of this disclosure, the doping concentrations of first and second nanosheets located at the same height relative to the substrate in the vertical direction may be the same or different.
[0039] Based on this, in the embodiments of this disclosure, through flexible doping, the core layers in different regions and / or at different heights of the integrated device can be doped with different doping characteristics, such as different conductivity types and / or different doping concentrations. A shell layer can surround the core layer to form a nanosheet. Thus, the device performance of the gate-to-ring device implemented based on such nanosheets can be optimized separately through different doping characteristics.
[0040] Further reference Figure 1A and Figure 1BThe first nanosheet and the second nanosheet at the same height can have the same thickness in the vertical direction Z. However, the embodiments of this disclosure are not limited thereto. In another embodiment of this disclosure, the thickness of the first nanosheet and the second nanosheet in the vertical direction Z can be different from each other.
[0041] Furthermore, the thickness of the core layer at its middle portion in the first direction X in the vertical direction Z is thinner than the thickness of its ends in the first direction X in the vertical direction Z. Thus, a space for forming a shell is created around the outer periphery of the core layer. For example, see reference... Figure 1A The shell is located between the gate stack and the core layer, and surrounds the outer periphery of the core layer in the second direction Y.
[0042] Further reference Figure 1B The shell layer does not extend through the core layer in the first direction X to contact the source / drain layer. Therefore, in this embodiment of the present disclosure, the first channel portion is connected to the first source / drain layer 106 only through the core layer 1031 of the first nanosheet, and the second channel portion is connected to the second source / drain layer only through the core layer 1032 of the second nanosheet.
[0043] Furthermore, the bottom surface of the lowest nanosheet among the plurality of first nanosheets and the plurality of second nanosheets is in contact with the top surface of the buried oxide layer 102. In embodiments of this disclosure, the lowest nanosheet among the plurality of first nanosheets and the plurality of second nanosheets may be obtained by doping the same nanosheet with different doping characteristics. Further, this same nanosheet may be fabricated based on the top silicon layer of an SOI substrate. In this way, short-channel effects can be suppressed, and device performance can be improved.
[0044] The method for manufacturing the integrated device described above, in conjunction with the accompanying drawings, is described below with reference to the accompanying drawings. It should be understood that this disclosure may be presented in various forms, and some examples will be described below. In the following description, the selection of various materials is involved. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following mentions etching a certain material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation. Figure 2 A flowchart illustrating a method for manufacturing an integrated device according to an embodiment of the present disclosure is shown schematically.
[0045] like Figure 2 As shown, the method of this embodiment may include operations S210 to S270.
[0046] In operation S210, a plurality of sacrificial layers and preparatory nanosheets are formed on a substrate in a vertical direction, wherein, after each formation of the preparatory nanosheet, the preparatory nanosheet is doped with plasma in a first region of the substrate to have a first doping characteristic and in a second region of the substrate, different from the first region, the preparatory nanosheet is doped with plasma to have a second doping characteristic different from the first doping characteristic.
[0047] In operation S220, the sacrificial layer and the prepared nanosheet are patterned together into a first fin and a second fin extending along a first direction in a first region and a second region, respectively.
[0048] In operation S230, a first sacrificial gate and a second sacrificial gate are formed on a first region and a second region of the substrate, respectively, extending along a second direction intersecting the first direction and thus intersecting the first fin and the second fin, and a first sidewall and a second sidewall are formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively.
[0049] In operation S240, a first source / drain layer is formed on both sides of the first sidewall in the first direction, in contact with the prepared nanosheet on the first region, and a second source / drain layer is formed on both sides of the second sidewall in the first direction, in contact with the prepared nanosheet on the second region.
[0050] In operation S250, the sacrificial layer is removed from the inner sides of the first and second sidewalls to expose the prepared nanosheets.
[0051] In operation S260, the exposed portion of the prepared nanosheet is etched to form a core layer, and a shell layer is further epitaxially formed on the surface of the core layer, with the core layer and shell layer forming the nanosheet.
[0052] In operation S270, a first gate stack and a second gate stack are formed around the periphery of the nanosheet within the first sidewall and the second sidewall, respectively.
[0053] The following combination Figures 3-16 The above-described method for manufacturing integrated devices will be further explained. Figures 3-8 The schematic illustration shows some processes for doping prepared nanosheets according to embodiments of the present disclosure, with the processes shown in a cross-section of the device in a second direction. Figures 9-16 The schematic illustration shows some processes for manufacturing an integrated device according to embodiments of the present disclosure, with the processes shown in a cross-section of the device in a first direction.
[0054] like Figure 3As shown, an SOI substrate can be provided, which may include a base substrate 101, a buried oxide layer 102, and a top silicon layer 103 as described above. For example, before forming a plurality of alternately stacked sacrificial layers 231 and pre-formed nanosheets, the top silicon layer 103 may be thinned (e.g., by oxidation processes and wet etching processes) so that the thinned top silicon layer 103 serves as the bottommost pre-formed nanosheet among the plurality of pre-formed nanosheets. For example, the thickness of the bottommost pre-formed nanosheet may be 5-11 nm.
[0055] like Figure 4 and Figure 5 As shown, a first mask pattern 211 can be formed on a prepared nanosheet in a second region of the substrate using a photolithography process. The portion of the prepared nanosheet exposed in the first region of the substrate due to the absence of the first mask pattern 211 is then subjected to plasma doping of a first conductivity type. For example, a first plasma 221 suitable for n-type doping can be used for doping. After doping, the first mask pattern 211 is removed. Thus, this prepared nanosheet in the first region can be used in subsequent processes to fabricate the bottommost first nanosheet. For example, the first nanosheet can be Si:P (phosphorus-doped silicon) to serve as the first channel portion of the n-type layer.
[0056] It should be further explained that plasma doping can be achieved by applying a pulse (e.g., tens to hundreds of volts) to introduce a plasma of dopant gas into the exposed portion. Using this doping method, ultra-shallow junctions (<10 nm) can be achieved by doping the prepared nanosheets. Furthermore, this doping method offers advantages such as minimal lattice damage, good doping uniformity, low leakage current in the first and second nanosheets formed by doping, and the elimination of pre-amorphization implantation (PAI) processes, making it suitable for advanced structures such as SOI and FinFET. In addition, this doping method allows for individual control of the doping concentration in different regions of each layer of prepared nanosheets (e.g., portions of the same prepared nanosheet in the first and second regions, and / or portions of different nanosheets in the first and second regions, etc.), providing process flexibility. Thus, different layers of prepared nanosheets can be doped with different concentrations, resulting in different doping concentrations and / or thicknesses between at least two first nanosheets fabricated in subsequent processes, and also different doping concentrations and / or thicknesses between at least two second nanosheets.
[0057] like Figure 6As shown, similarly to the above, a second mask pattern 212 can be formed on the prepared nanosheet in the first region of the substrate using a photolithography process. The portion of the prepared nanosheet exposed in the second region of the substrate due to the absence of the second mask pattern 212 is then subjected to plasma doping of a second conductivity type. For example, a second plasma 222 suitable for p-type doping can be used for doping. After doping, the second mask pattern 212 is removed. Thus, this prepared nanosheet in the second region can be used in subsequent processes to fabricate the bottommost second nanosheet. For example, the second nanosheet can be Si:B (boron-doped silicon) to serve as the second channel portion of the p-type layer.
[0058] like Figure 7 and Figure 8 As shown, a sacrificial layer 231 (e.g., SiGe) can be epitaxially grown on the bottommost pre-prepared nanosheet, and a semiconductor layer 232 (e.g., a silicon layer) can be epitaxially grown on the sacrificial layer 231, so that the semiconductor layer 232 serves as the undoped pre-prepared nanosheet. For example, the epitaxial temperature can be 500~800°C. Further, the above operation is repeated, and plasma doping can be performed after each formation of the pre-prepared nanosheet, thereby forming alternately stacked sacrificial layers 231 and doped pre-prepared nanosheets. Compared to epitaxially growing multiple layers of sacrificial layers 231 and pre-prepared nanosheets and then uniformly doping them, the above method causes less damage to the pre-prepared nanosheets, resulting in less reduction in the uniformity of the pre-prepared nanosheets after doping, and the sacrificial layer 231 is less affected by doping. Thus, the quality of the first and second channels constructed based on the pre-prepared nanosheets can be improved, thereby improving the performance of the integrated device.
[0059] Next, a sacrificial gate can be formed and replaced with a gate stack. The following description uses the back-gate process as an example, but it should be understood that the method of this disclosure embodiment is also applicable to the front-gate process, and will not be elaborated upon here. The following example uses the fabrication process of the first region. Figures 10-16 As shown in the image, it should be understood that the second area was produced in a similar manner, which will not be elaborated upon below.
[0060] like Figure 9 and Figure 10 As shown, an etching mask such as photoresist (not shown) can be formed, and the photoresist can be patterned by photolithography into a form corresponding to the trench to be formed. For example, the photoresist can be in the form of a strip extending along a first direction X. For convenience, hard mask structures that may be used in the patterning process, such as hard masks in the form of stacked oxide / nitride layers, are not shown here. In addition, besides the example using photoresist, a spacer image transfer (SIT) process can also be used. For example, a sidewall of, for example, nitride (e.g., silicon nitride) extending along the first direction X can be formed by a sidewall formation process, and this sidewall can be used as an etching mask.
[0061] The etching mask thus formed can be used to sequentially etch each layer by anisotropic etching, such as reactive ion etching (RIE) in the vertical Z direction. According to an embodiment, the etching can penetrate into the substrate 101. This forms a protruding structure (which may be referred to as a "fin") extending along the first direction X on the substrate. The etching mask can then be removed. And, referring to… Figure 9 As can be seen, after etching, a first fin located in the first region and a second fin located in the second region are formed. These two fins are used to fabricate the first ring gate device and the second ring gate device in subsequent processes, respectively.
[0062] For electrical isolation purposes, isolation portions 10S can be formed on both sides of each fin in the second direction Y, such as shallow trench isolation (STI). For example, the isolation portions 10S can be formed by depositing an oxide on a substrate, planarizing the deposited oxide (e.g., chemical mechanical polishing (CMP), and etching back the planarized oxide). The isolation portions 10S fill the bottom of each trench, and more specifically, their top surface can be no higher than the top surface of the bottommost prepared nanosheet (so that at least the top surface of the bottommost prepared nanosheet can be used as a channel portion) and no lower than the bottom surface of the buried oxide layer 102 (which can extend continuously with the buried oxide layer 102). For example, the top surface of the isolation portion 10S can be slightly lower than the top surface of the buried oxide layer 102. The bottom of the fin can be surrounded by the isolation portion 10S, but the upper part, in particular the aforementioned prepared nanosheet and sacrificial layer 231, still protrudes outward relative to the top surface of the isolation portion 10S. In this way, the two fins can be electrically isolated from each other by the isolation portion 10S.
[0063] Subsequently, a sacrificial gate can be formed. The sacrificial gate can extend along the second direction Y to intersect with the fin. The sacrificial gate may include a gate oxide layer 301, a polysilicon layer 302, and a hard mask layer 303. The material of the hard mask layer 303 may include, for example, a stack of oxides and nitrides. Based on this, a gate sidewall 104 can be formed on the sidewall of the sacrificial gate by a sidewall forming process. The material of the gate sidewall 104 may include nitrides, and the thickness may be, for example, 6 nm ± 3 nm.
[0064] Next, as Figure 11 As shown, using the sacrificial gate and gate sidewall 104 as an etching mask, the fin is etched to expose the sidewalls of the prepared nanosheet in the first direction X. For example, the sacrificial gate and gate sidewall 104 can be used as an etching mask to perform anisotropic etching, such as reactive ion etching (RIE) in the vertical direction Z, on the sacrificial layer 231 and the prepared nanosheet. The RIE can stop at the buried oxide layer 102. Thus, the prepared nanosheet can be self-aligned to the sacrificial gate. Over-etching of the buried oxide layer 102 is possible, see reference. Figure 12 .
[0065] According to embodiments of this disclosure, an inner sidewall 105 may be formed at the end of the sacrificial layer 231 in the first direction X. For example, as Figure 12 As shown, the sacrificial layer 231 can be selectively etched relative to the prepared nanosheet, such that its sidewalls are recessed inward to a certain depth relative to the sidewall of the gate sidewall 104 or the sidewall of the prepared nanosheet. Preferably, the recess depths of the sacrificial layers 231 are substantially the same and can be substantially equal to the thickness of the gate sidewall 104 (in the first direction X), so that the subsequently formed inner sidewall 105 can have substantially the same thickness as the gate sidewall 104.
[0066] In the recess thus formed, an inner sidewall 105 can be formed. A dielectric material layer of a certain thickness can be formed on the substrate, for example, by deposition. The thickness of the deposited dielectric material layer is sufficient to fill the recess. For example, the dielectric material layer may include SiC, etc. Subsequently, the deposited dielectric material layer can be etched back by, for example, a vertical Z-axis RIE, thereby forming the inner sidewall 105. The inner sidewall 105 may also include the same material as the gate sidewall 104, with a thickness of, for example, 5 nm ± 3 nm. At the same time, a second sidewall can be formed in the same manner, which will not be described in detail here.
[0067] Subsequently, a source / drain layer can be epitaxially grown on the sidewalls exposed in the first direction X of the prepared nanosheet. For example, as Figure 12 As shown, the exposed sidewalls of a prepared nanosheet can be used as seeds to form an epitaxial layer through selective epitaxial growth, for example, and then doped to form a source / drain layer. The source / drain layer can be formed in contact with the exposed sidewalls of the prepared nanosheet. Specifically, the exposed sidewalls of the prepared nanosheet in a first region can be used as seeds to obtain an epitaxial layer through selective epitaxial growth, and then the epitaxial layer can be doped to form a first source / drain layer. The exposed sidewalls of the prepared nanosheet in a second region can be used as seeds to obtain an epitaxial layer through selective epitaxial growth, and then the epitaxial layer can be doped to form a second source / drain layer. For example, the material of the first source / drain layer can be silicon. The material of the second source / drain layer can be germanium-silicon. The source / drain layer can be doped to n-type or p-type by, for example, in-situ doping or ion implantation. Subsequently, the source / drain layer and the prepared nanosheet can be activated by a rapid thermal annealing process.
[0068] Next, an alternative gate process can be performed to replace the sacrificial gate and sacrificial layer 231 with a gate stack.
[0069] like Figure 13 As shown, a liner 108 and an interlayer dielectric layer 109 can be formed on a substrate. For example, the liner 108 and the interlayer dielectric layer 109 can be formed by depositing a nitride in a generally conformal manner and depositing an oxide on the nitride, and then planarizing the nitride and oxide deposited as in CMP. CMP can be performed to expose the sacrificial gate inside the gate sidewall 104.
[0070] The sacrificial gate can be selectively etched away to expose the pre-existing nanosheets and the sacrificial layer 231 within the space between the gate sidewalls 104. The sacrificial layer 231 can also be selectively etched away. However, it should be understood that since the pre-existing nanosheets in the first region and the second region of the same height may have etch selectivity relative to each other (e.g., due to different doping characteristics), the pre-existing nanosheets in the first region and the second region of the same height may have different thicknesses after such removal of the sacrificial layer 231.
[0071] like Figure 14 and Figure 15 As shown, a core trimming process, such as dry etching, can then be used to etch the exposed portion of the prepared nanosheet, causing the center of the prepared nanosheet in the first direction X to be recessed relative to the end in the vertical direction Z, thus serving as the core layer. In this way, the recessed area can serve as the space for the epitaxial shell. It should be understood that, through the core trimming process, the core layers of the first region and the second region at the same height can also be trimmed, making their thicknesses substantially the same.
[0072] Subsequently, shells are further epitaxially grown on the surfaces (e.g., recesses) of the core layers in the first and second regions, respectively, to form the first and second nanosheets. Similar to the preceding description, the thicknesses of the first and second nanosheets at the same height may differ relative to each other. However, in another embodiment of this disclosure, the thicknesses of the first and second nanosheets at the same height can also be substantially modified to be the same by a core trimming process.
[0073] Next, a grid stack can be formed within the space between the grid sidewalls 104. For example, as Figure 16 As shown, a gate dielectric layer 1071, a work function layer 1072, and a gate electrode layer 1073 can be formed sequentially to obtain the final gate stack. The stack surrounding the first nanosheet is the first gate stack. The stack surrounding the second nanosheet is the second gate stack.
[0074] The integrated device according to embodiments of this disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such an integrated device, and an electronic device can be constructed therefrom. Such an electronic device may also include components such as a display screen that works with the integrated circuit and a wireless transceiver that works with the integrated circuit. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks. Furthermore, the manufacturing method of embodiments of this disclosure can be extended to the manufacturing of other CS device structures.
[0075] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0076] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for manufacturing an integrated device, characterized in that, include: Multiple sacrificial layers and pre-prepared nanosheets are formed on a substrate in a vertical direction, wherein, after each formation of a pre-prepared nanosheet, the pre-prepared nanosheet is doped with plasma in a first region of the substrate to have a first doping characteristic, and in a second region of the substrate different from the first region to have a second doping characteristic different from the first doping characteristic. The sacrificial layer and the prepared nanosheet are patterned together as a first fin and a second fin extending along a first direction in the first region and the second region, respectively. A first sacrificial gate and a second sacrificial gate are formed on the first region and the second region of the substrate, respectively, extending along a second direction intersecting the first direction and thus intersecting the first fin and the second fin, and a first sidewall and a second sidewall are formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively. A first source / drain layer is formed on both sides of the first sidewall in the first direction, which is in contact with the prepared nanosheet on the first region, and a second source / drain layer is formed on both sides of the second sidewall in the first direction, which is in contact with the prepared nanosheet on the second region. The sacrificial layer was removed from the inner sides of the first and second sidewalls respectively to expose the prepared nanosheets; The exposed portion of the prepared nanosheet is etched to form a core layer, and a shell layer is further epitaxially formed on the surface of the core layer, wherein the core layer and the shell layer form a nanosheet; A first gate stack and a second gate stack are formed within the first sidewall and the second sidewall, respectively, surrounding the outer periphery of the nanosheet.
2. The method according to claim 1, characterized in that, The first doping characteristic differs from the second doping characteristic in terms of conductivity type and / or doping concentration.
3. The method according to claim 1 or 2, characterized in that, Using the plasma to dope the prepared nanosheets in a first region of the substrate to have a first doping characteristic and to dope the prepared nanosheets in a second region of the substrate to have a second doping characteristic includes: A first mask pattern is formed on the prepared nanosheet in a second region of the substrate, and plasma doping is performed on the portion of the prepared nanosheet exposed in the first region of the substrate due to the absence of the first mask pattern, resulting in the first doping characteristic. A second mask pattern is formed on the prepared nanosheet in a first region of the substrate, and plasma doping is performed on the portion of the prepared nanosheet exposed in a second region of the substrate due to the absence of the second mask pattern, resulting in the second doping characteristic.
4. The method according to claim 1 or 2, characterized in that, The substrate is an SOI substrate, and the SOI substrate includes a buried oxide layer and a top silicon layer on the buried oxide layer; Before forming the plurality of alternately stacked sacrificial layers and preparatory nanosheets, the top silicon layer is further thinned so that the thinned top silicon layer serves as the bottommost preparatory nanosheet among the plurality of preparatory nanosheets.
5. The method according to claim 1 or 2, characterized in that, It also includes doping and activating the prepared nanosheets.
6. An integrated device, characterized in that, include: Substrate; A first channel portion and a second channel portion are respectively located in a first region of the substrate and in a second region different from the first region. The first channel portion includes a plurality of first nanosheets extending along a first direction and spaced apart from each other in a vertical direction. The second channel portion includes a plurality of second nanosheets extending along the first direction and spaced apart from each other in a vertical direction. Each nanosheet includes a core layer and a shell layer surrounding the core layer. The core layer and the shell layer are doped with different conductivity types. The core layer of the first nanosheet is doped with a first doping characteristic and the core layer of the second nanosheet is doped with a second doping characteristic different from the first doping characteristic. A first gate stack and a second gate stack, respectively, extend along a second direction intersecting the first direction on the first region and the second region of the substrate and respectively surround the outer periphery of the first nanosheet and the second nanosheet; The first sidewall on the sidewall of the first grid stack and the second sidewall on the sidewall of the second grid stack; and The first source / drain layer is located on both sides of the first sidewall in the first direction and is respectively connected to the first channel portion, and the second source / drain layer is located on both sides of the second sidewall in the first direction and is respectively connected to the second channel portion.
7. The integrated device according to claim 6, characterized in that, The first doping characteristic differs from the second doping characteristic in terms of conductivity type and / or doping concentration.
8. The integrated device according to claim 7, characterized in that, At least two of the plurality of first nanosheets have different doping concentrations relative to each other; and / or At least two of the plurality of second nanosheets have different doping concentrations relative to each other.
9. The integrated device according to any one of claims 6 to 8, characterized in that, The doping concentration of the core layer is 1e18~5e19 cm⁻¹ -3 The doping thickness of the core layer is 5~20 nm.
10. The integrated device according to any one of claims 6 to 8, characterized in that, The first and second nanosheets, which are at the same height relative to the substrate in the vertical direction, have substantially the same or different thicknesses in the vertical direction.
11. The integrated device according to any one of claims 6 to 8, characterized in that, The core layer is thinner in the vertical direction at its middle portion in the first direction than it is at its end portion in the vertical direction.
12. The integrated device according to claim 10, characterized in that, The first channel portion is connected to the first source / drain layer only through the core layer of the first nanosheet, and the second channel portion is connected to the second source / drain layer only through the core layer of the second nanosheet.