A field effect transistor

Abstract

The application discloses a field effect transistor, comprising: MOS cells and Schottky body diode cells, the MOS cells having: first shield gate structures, first mesa regions between adjacent first shield gate structures, the first mesa regions comprising first n-type drift layers, p-type body region layers, n+ type source regions, source electrode contact holes, p+ regions, and first source electrodes; the Schottky body diode cells having: second shield gate structures, second mesa regions between adjacent second shield gate structures, the second mesa regions comprising second n-type drift layers, and second source electrodes in contact with the second n-type drift layers to form Schottky contacts, the surface layer doping concentration of the second n-type drift layers in contact with the second source electrodes to form the Schottky contacts being less than or equal to 3 x 10 16 cm ‑3 -2; the ratio of the Schottky body diode cells to the MOS cells is between 1:2 and 1:10, and the width of the second mesa regions is less than the width of the first mesa regions. The application has low off-state leakage current, low on-resistance and large Schottky body diode freewheeling capability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a field-effect transistor. Background Technology

[0002] In field-effect transistors with shielded gate structures, the introduction of the shielded gate structure introduces a lateral electric field into the n-type drift layer, which can further reduce the on-resistance R of the field-effect transistor. DS（on） and Miller capacitance C GD This results in the advantages of low conduction loss and low switching loss.

[0003] However, a challenge faced by conventional shielded-gate field-effect transistors (SFETs) is that when used in synchronous rectifier circuits, they operate in the third quadrant (where both voltage and current are negative). In this state, high demands are placed on the reverse recovery performance and on-state voltage drop of the body diode. This is because the body diode of a conventional SFET is a self-integrated pn junction body diode, a bipolar device with a long reverse recovery time and large reverse recovery current, resulting in relatively high reverse recovery losses. Secondly, the pn junction body diode also has an on-state voltage drop of approximately 0.8V to 1.3V, which also contributes to some body diode conduction losses.

[0004] It is known that integrating a Schottky diode into a shielded gate field-effect transistor (SFET) can improve the reverse recovery capability of the device. Since the turn-on voltage of the self-integrated Schottky diode (approximately 0.3~0.4V) is lower than the built-in potential of the pn junction diode (approximately 0.7V), the self-integrated Schottky diode will conduct first due to its lower turn-on voltage when operating in the third quadrant. As the Schottky diode is a unipolar device, its reverse recovery time is very short, thus reducing reverse recovery losses. Secondly, the Schottky diode has a lower forward voltage drop, thus reducing conduction losses.

[0005] However, there are two common problems in known shielded gate field-effect transistors with integrated Schottky diodes: (1) After integrating the Schottky diode, the off-state leakage current of the shielded gate field-effect transistor will increase; (2) After integrating the Schottky diode, if the ratio of Schottky diode cells to MOS cells in the shielded gate field-effect transistor is too small, the area ratio of the Schottky diode will be small and the current carrying capacity will be weak. The reverse recovery performance is significantly improved when the current is small, but when the current is large, the self-integrated pn junction diode in the MOS cell will inevitably be turned on, which will result in very little improvement in the reverse recovery performance; if the ratio of Schottky diode cells to MOS cells in the shielded gate field-effect transistor is too large, since the Schottky diode cells do not contribute to the on-resistance, the on-resistance will increase under the same chip area, thereby increasing the conduction loss of the device.

[0006] Therefore, there is a need for semiconductor devices with low off-state leakage current, low on-resistance, and large Schottky diode freewheeling capability. Summary of the Invention

[0007] In view of this, the technical problem to be solved by the present invention is to provide a field-effect transistor that at least partially solves the technical problems existing in the prior art. To address the above problems, the present invention provides the following technical solution for a field-effect transistor: Including MOS cells and Schottky diode cells, among which, The MOS cell has: a first shielding gate structure, and a first mesa region between adjacent first shielding gate structures. The first mesa region includes, from bottom to top, a first n-type drift layer, a p-type body layer formed in the surface layer of the first n-type drift layer, an n+ type source region stacked on the p-type body layer, a source electrode contact hole extending inward from the surface of the first mesa region into the p-type body layer, a p+ region located at the bottom of the source electrode contact hole and surrounding the bottom of the source electrode contact hole, and a first source electrode located in the source electrode contact hole and forming an ohmic contact with the n+ type source region. The Schottky diode cell has: a second shielding gate structure, and a second mesa region between adjacent second shielding gate structures. The second mesa region includes a second n-type drift layer and a second source electrode that forms a Schottky contact with the second n-type drift layer. The surface doping concentration of the second n-type drift layer forming the Schottky contact with the second source electrode is ≤3 x 10⁻⁶. 16 cm -3 ; The ratio of the Schottky diode cell to the MOS cell is between 1:2 and 1:10; The width of the second countertop area does not exceed the width of the first countertop area.

[0008] Preferably, the second source electrode is located on the surface of the second n-type drift layer.

[0009] Preferably, the second source electrode is one of Ti, Ni, Pd, Au, and Pt.

[0010] Preferably, the second source electrode and the first source electrode are made of the same electrode material.

[0011] Preferably, the second n-type drift layer has at least two layers from bottom to top, and the two layers have different doping concentrations.

[0012] Preferably, a p-type well region is further provided in the n-type drift layer located in the bottom region of the first shielding gate structure and / or the second shielding gate structure to alleviate the electric field concentration in the bottom region of the shielding gate.

[0013] Preferably, a p-type carrier region is also provided on the surface region of the n-type drift layer in the second mesa region of the Schottky diode cell to optimize the electric field distribution on one side of the Schottky diode cell and reduce the off-state leakage current.

[0014] Preferably, the ratio of the Schottky diode cell to the MOS cell is between 1:3 and 1:7.

[0015] This invention enables the fabrication of semiconductor devices with low off-state leakage current, low on-resistance, and high Schottky diode freewheeling capability. The advantages over existing technologies are as follows: The field-effect transistor of this invention has a surface doping concentration ≤3 x 10⁻⁶ by setting the n-type drift layer to form a Schottky contact with the second source electrode. 16 cm -3 By setting the width of the second mesa region to be smaller than that of the first mesa region, the off-state leakage current is effectively reduced. At the same time, by setting the ratio of Schottky diode cells to MOS cells between 1:2 and 1:10, a trade-off between reverse recovery performance and on-resistance is achieved, and the device has a large freewheeling capability of Schottky diodes, thereby reducing the total device loss. Attached Figure Description

[0016] Figure 1 This is a vertical cross-sectional view of the first specific embodiment of the field-effect transistor of the present invention; Figure 2 The pressure resistance curves are simulated using TCAD software with different n-type drift layer concentrations. Figure 3 It is a pressure resistance curve diagram of different widths of the second platform area simulated using TCAD software; Figure 4 This is a vertical cross-sectional view of a second specific embodiment of the field-effect transistor of the present invention; Figure 5 This is a vertical cross-sectional view of the third specific embodiment of the field-effect transistor of the present invention; Figure 6 This is a vertical cross-sectional view of the fourth specific embodiment of the field-effect transistor of the present invention; The technical features corresponding to the markings in the figure are: 11 Drain electrode; 21 n+ type semiconductor layer; 31 n type drift layer; 32 n-type drift layers; 33n+ type source pole region; 41 insulating film 41a grid insulating film; 41b Shielding grid insulating film; 51 Shielded gate electrode; 61 Gate electrode; 71 p-type body region; 72p type well region; 73p type carrier region; 81 p+ area; 91. Source electrode; 91a First source electrode; 91b Second source electrode. Detailed Implementation

[0017] To more clearly illustrate the technical solution of the present invention, a brief description will be provided below through embodiments or prior art. Obviously, the following drawings are merely illustrative of some embodiments of the present invention, and the scope of protection claimed by the present invention is not limited to the embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, and methods have been omitted so as not to obscure the description of the invention with unnecessary detail.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] Unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0021] In this invention, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are used. "Etc" usually refers to the direction shown in the accompanying drawings, or to the direction of the component itself in terms of verticality, perpendicularity, or gravity; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit the invention.

[0022] Figure 1 This is a vertical cross-sectional view of the first specific embodiment of the field-effect transistor of the present invention, in which a silicon-based shielding gate integrating a Schottky diode is integrated. This field-effect transistor has two regions: a MOS cell and a Schottky diode cell.

[0023] The MOS cell includes: a drain electrode 11 located at the bottom layer of the field-effect transistor; an n+ type semiconductor layer 21 located above the drain electrode 11; and an n-type drift layer 31 located above the n+ type semiconductor layer 21. The n-type drift layer 31 includes a shielding gate structure and a first mesa region between adjacent shielding gate structures. The gate trench in the shielding gate structure extends downward from the upper surface of the n-type drift layer 31. Further, the gate trench includes a gate electrode 61, a shielding gate electrode 51, and an insulating film 41. The insulating film 41 includes a gate insulating film 41a and a shielding gate insulating film 41b. The gate insulating film 41a... The shielding gate insulating film 41b is wrapped around the outer surface of the gate electrode 61. The first mesa region includes, from bottom to top, an n-type drift layer 31, a p-type body region 71 formed in the surface of the n-type drift layer 31, an n+ type source region 33 stacked on the p-type body region 71, a source electrode contact hole extending inward from the surface of the first mesa region into the p-type body region 71, a p+ region 81 located at the bottom of the source electrode contact hole and surrounding the bottom of the source electrode contact hole, and a first source electrode 91a located in the source electrode contact hole and forming an ohmic contact with the n+ type source region 33. The Schottky diode cell comprises: a drain electrode 11 located at the bottom layer of the field-effect transistor; an n+ type semiconductor layer 21 located above the drain electrode 11; and an n-type drift layer 31 located above the n+ type semiconductor layer 21. The n-type drift layer 31 includes a shielding gate structure and a second mesa region between adjacent shielding gate structures. In the shielding gate structure, the gate trench extends downward from the upper surface of the n-type drift layer 31. Further, the gate trench includes a gate electrode 61, a shielding gate electrode 51, and an insulating film 41. The insulating film 41 includes a gate insulating film 41a and a shielding gate insulating film 41b. The gate insulating film 41a wraps around the outer surface of the gate electrode 61, and the shielding gate insulating film 41b wraps around the outer surface of the shielding gate electrode 51. The second mesa region includes the n-type drift layer 31 and an n-type drift layer 32 located above the n-type drift layer 31. The doping concentration of the n-type drift layer 32 is ≤3 x 10⁻⁶. 16 cm -3 It forms a Schottky contact with the second source electrode 91b, which is one of the metals such as Ti, Ni, Pd, Au, and Pt. The second source electrode 91b and the first source electrode 91a are the same metal.

[0024] Figure 1 The silicon-based shielded gate field-effect transistor with integrated Schottky diode shown exhibits a high-concentration electron inversion layer when the voltage VGS applied between the gate electrode 61 and the source electrode 91 is greater than the threshold voltage VGS(th). In the p-type body region 71, near the gate insulating film 41a, electron carriers accumulate. When a positive voltage is applied between the drain electrode 11 and the source electrode 91, a complete and high-concentration electron channel is formed in the MOS cell region between the drain electrode 11 and the first source electrode 91a, allowing current to flow between them. However, a high-concentration electron inversion layer also forms in the Schottky diode cell region near the gate insulating film 41a. Due to the Schottky barrier, the current between the drain electrode 11 and the second source electrode 91b is much smaller than the current flowing between the drain electrode 11 and the first source electrode 91a when a positive voltage is applied between them. In the on-state, there is basically no conduction current in the cell region of a Schottky diode. Therefore, it is necessary to reasonably set the ratio of Schottky diode cells to MOS cells to reduce the influence of the Schottky diode cell region on the on-resistance.

[0025] Figure 1The silicon-based shielded gate field-effect transistor with integrated Schottky diode shown exhibits the following behavior: When the voltage VGS=0 is applied between the gate electrode 61 and the source electrode 91, and a forward voltage is then applied between the drain electrode 11 and the source electrode 91, the PN junction barrier formed by the p-type body region and the n-type drift region 31 in the MOS cell region will cause longitudinal depletion of electron carriers. In addition, the shielded gate electrode 51 has the same potential as the source electrode 91, and the shielded gate electrode 51 will cause lateral auxiliary depletion of electron carriers. Both deplete together to achieve breakdown voltage. Similarly, in the Schottky diode cell region, the Schottky junction barrier formed by the second source electrode 91b and the n-type drift region 32 will cause longitudinal depletion of electron carriers. In addition, the shielded gate electrode 51 has the same potential as the source electrode 91, and the shielded gate electrode 51 will cause lateral auxiliary depletion of electron carriers. Both deplete together to achieve breakdown voltage. Since the n-type drift region 31 and the n-type drift region 32 form a double epitaxial layer, and the doping concentration of the n-type drift layer 32 is ≤3 x10⁻⁶, 16 cm -3 The presence of the n-type drift region 32 can reduce device leakage current and reduce device loss in the off-state by balancing BV (breakdown voltage) and Rsp (specific on-resistance) with low doping concentration.

[0026] Figure 1 Compared to known shielded gate field-effect transistors (SFETs) with integrated Schottky diodes, the inventors of this application, through in-depth research, discovered that the off-state leakage current of a Schottky diode increases with increasing contact semiconductor concentration. This is due to the dramatic enhancement of the quantum tunneling effect. When the semiconductor doping concentration increases, the depletion region formed by the metal-semiconductor Schottky contact becomes significantly thinner. When a reverse voltage is applied, an extremely strong built-in electric field is formed in this thinned region. This enhanced electric field dramatically increases the probability of quantum tunneling, making it easier for electrons to directly penetrate the potential barrier, rather than relying solely on thermal energy to cross it. Therefore, with a relative increase in concentration, the current component dominated by the tunneling effect rapidly increases, becoming the main reason for the increase in reverse leakage current. This effect also directly limits the reverse breakdown voltage capability of highly doped Schottky diodes. Therefore, the inventors of this application have achieved a surface doping concentration ≤3 x 10⁻⁶ for the Schottky contact formed between the n-type drift layer 32 and the second source electrode 91b. 16 cm -3 To reduce off-state leakage current, such as Figure 2To simulate the withstand voltage curves of different n-type drift layer concentrations using TCAD software, the horizontal axis represents drain voltage in V, and the vertical axis represents drain current in A. Three different concentrations of n-type drift layer 32 were used: 1.15e15, 1.72e16, and 3.91e16. The withstand voltage curves show that the off-state leakage current decreases with decreasing n-type drift layer 32 concentration. When the off-state leakage current is set to 250... When using uA to determine whether a device has broken down, the n-type drift layer 32 concentrations are 1.15e15, 1.72e16, and 3.91e16, corresponding to breakdown voltages of 67.3V, 66V, and 10V, respectively. When the n-type drift layer 32 concentration is 3.91e16, the breakdown voltage is only 10V. If we use 100mA of off-state leakage current to determine breakdown, the breakdown voltage can still reach 67V when the n-type drift layer 32 concentration is 3.91e16. However, due to the larger off-state leakage current, the device will experience significant off-state losses during application. Figure 2 The embodiments of the present invention have verified that the surface doping concentration of the Schottky contact formed between the n-type drift layer 32 and the second source electrode 91b is ≤3 x 10⁻⁶. 16 cm -3 This can reduce the off-state leakage current of the device, thereby reducing the total device loss.

[0027] The inventors of this application reduced the off-state leakage current through the above-mentioned means. At the same time, by reasonably setting the ratio of Schottky diode cells and MOS cells, it was found through research that setting the ratio of Schottky diode cells to MOS cells to be between 1:2 and 1:10 can form a trade-off between reverse recovery performance and on-resistance, and has a large freewheeling capability of Schottky diodes, thereby reducing the total device loss. More preferably, in the embodiments of the present invention, the ratio of Schottky diode cells to MOS cells is between 1:3 and 1:7.

[0028] Simply relying on the surface doping concentration of the aforementioned setting to form a Schottky contact between the n-type drift layer 32 and the second source electrode 91b to improve the problem of large off-state leakage current cannot achieve the expected goal. The inventors of this application, through further research, discovered that... Figure 1The silicon-based shielded gate field-effect transistor (SFET) with integrated Schottky diodes is shown. It features second mesa regions of varying widths. During reverse breakdown, the gate region and the Schottky diode work together to deplete electrons. As the width of the second mesa region increases, the number of electrons depleted by the gate region remains constant; excess electrons are depleted by the Schottky diode, enhancing the built-in electric field. This enhanced field dramatically increases the probability of quantum tunneling, making it easier for electrons to directly penetrate the potential barrier, rather than relying solely on thermal energy to cross it. Therefore, it can be concluded that as the width of the second mesa region increases, the reverse leakage current of the device increases. Thus, the inventors of this application further reduced the off-state leakage current by setting the width of the second mesa region to be no greater than the width of the first mesa region. Figure 3 To simulate the withstand voltage curves for different widths of the second mesa region using TCAD software, the horizontal axis represents drain voltage in V, and the vertical axis represents drain current in A. The graph shows three different widths of the second mesa region: 1.4µm, 1.5µm, and 1.6µm. The width of the first mesa region is 1.6µm. The withstand voltage curves show that the off-state leakage current increases with the increase of the width of the second mesa region. Setting the width of the second mesa region to be no greater than the width of the first mesa region can reduce the off-state leakage current of the device. When using an off-state leakage current of 250µA to determine whether the device has broken down, the withstand voltages for the second mesa region widths of 1.4µm, 1.5µm, and 1.6µm are 65.8V, 68V, and 20V, respectively. When the width of the second mesa region is the same as the width of the first mesa region, the withstand voltage can only reach 20V at a 250µA off-state leakage current. Therefore... Figure 3 It was verified that the off-state leakage current can be reduced by reasonably controlling the width of the second mesa region.

[0029] Figure 4 This is a vertical cross-sectional view of a second specific embodiment of the field-effect transistor of the present invention, in which a silicon-based shielding gate integrating a Schottky diode is also incorporated. This field-effect transistor has two regions: a MOS cell and a Schottky diode cell. Figure 1 The difference lies in that: the shielded gate electrode 51 is located in the middle of the gate trench, and the gate electrode 61 is formed around the upper sides of the shielded gate electrode 51 and separated by the insulating film 41. Figure 2 Working principle and Figure 1 The same applies, so I won't go into details here.

[0030] Compared to Figure 1 , Figure 4 The structural gate electrode 61 is located on both sides of the shielding gate electrode 51. Figure 4 In terms of structural performance and Figure 1Both have the same structure and can form a Schottky contact between the n-type drift layer 32 and the second source electrode 91b with a surface doping concentration ≤ 3 x 10⁻⁶. 16 cm -3 The width of the second mesa region should not exceed the width of the first mesa region, and the ratio of Schottky diode cells to MOS cells should be set reasonably to reduce the total device loss.

[0031] Figure 5 This is a vertical cross-sectional view of the third specific embodiment of the field-effect transistor of the present invention, which also integrates the silicon-based shielding gate of a Schottky diode, and... Figure 1 The difference lies in that a p-type well region 72 is set in the n-type drift layer at the bottom of the shielding grid structure.

[0032] Compared to Figure 1 , Figure 5 The silicon-based shielded gate field-effect transistor with integrated Schottky diode shown, when forward-biased, operates on the same principle as... Figure 1 The principle is the same. During reverse blocking, when the voltage VGS applied between the gate electrode 61 and the source electrode 91 is 0, and a forward voltage is then applied between the drain electrode 11 and the source electrode 91, the PN junction barrier formed by the p-type body region 71 and the n-type drift region 31 in the MOS cell region will exert a longitudinal depletion effect on the electron carriers. In addition, the shielding gate electrode 51 has the same potential as the source electrode 91, and the shielding gate electrode 51 will exert a lateral auxiliary depletion effect on the electron carriers. At the same time, the p-type well region 72 will exert a lateral auxiliary depletion effect on the electron carriers. All three factors work together to deplete the electron carriers and achieve breakdown voltage. Figure 5 The presence of a p-type well region 72 at the bottom of the trench can alleviate the electric field concentration at the bottom of the trench, thereby improving the device's breakdown voltage. This is especially beneficial when the concentration of the n-type drift region 31 is the same. Figure 5 Compared to Figure 1 The structure allows for higher voltage resistance. If you require the development of a device with the same voltage resistance, Figure 5 Structure compared to Figure 1 , Figure 5 The withstand voltage can be reduced to a level comparable to that of the n-type drift region 31 by increasing the concentration of 31 and decreasing the trench depth. Figure 1 At the same level, increasing the concentration of the n-type drift region 31 can reduce Rsp, and reducing the trench depth can reduce the output capacitance Coss. Lower Rsp reduces conduction losses, and lower output capacitance Coss helps reduce switching losses, thereby reducing total losses.

[0033] Figure 5 In the Schottky diode cell region, the Schottky junction barrier formed by the second source electrode 91b and the n-type drift region 32 will have a longitudinal depletion effect on electron carriers. The rest of the principle is the same as that in the MOS cell region mentioned above, and will not be repeated here.

[0034] Figure 6This is a vertical cross-sectional view of the fourth specific embodiment of the field-effect transistor of the present invention, which also integrates a silicon-based shielding gate of a Schottky diode, and... Figure 1 The difference lies in the fact that the surface region of the n-type drift layer 32 in the second mesa region of the Schottky diode cell is provided with a p-type carrier region 73.

[0035] Compared to Figure 1 , Figure 6 The silicon-based shielded gate field-effect transistor with integrated Schottky diode shown exhibits forward conduction and reverse breakdown voltage mechanisms similar to those of... Figure 1 The mechanism is the same, but the difference lies in the fact that, according to the theory of MOSFETs and Schottky diodes, the leakage current of a PN junction is smaller than that of a Schottky junction under the same voltage rating. Excessive leakage current in the off-state will affect the device's voltage rating (the device's voltage rating is extracted through leakage current) and increase the turn-off loss, thus affecting the total device loss. Since the silicon-based shielded gate field-effect transistor with integrated Schottky diode has integrated Schottky diode, the leakage current under the voltage rating is determined by the magnitude of the Schottky leakage current, which is larger than that of a conventional MOSFET. In order to minimize leakage current, a p-type carrier region 73 is set on the surface region of the n-type drift layer 32 in the second mesa region of the Schottky diode cell. The p-type carrier region 73 generates a lateral depletion effect on electron carriers, thereby reducing the off-state leakage current during the voltage rating process.

[0036] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A field-effect transistor, characterized in that, include: MOS cells and Schottky diode cells, among which, The MOS cell has: a first shielding gate structure, and a first mesa region between adjacent first shielding gate structures. The first mesa region includes, from bottom to top, a first n-type drift layer, a p-type body layer formed in the surface layer of the first n-type drift layer, an n+ type source region stacked on the p-type body layer, a source electrode contact hole extending inward from the surface of the first mesa region into the p-type body layer, a p+ region located at the bottom of the source electrode contact hole and surrounding the bottom of the source electrode contact hole, and a first source electrode located in the source electrode contact hole and forming an ohmic contact with the n+ type source region. The Schottky diode cell has: a second shielding gate structure, and a second mesa region between adjacent second shielding gate structures. The second mesa region includes a second n-type drift layer and a second source electrode that forms a Schottky contact with the second n-type drift layer. The surface doping concentration of the second n-type drift layer forming the Schottky contact with the second source electrode is ≤3 x 10⁻⁶. 16 cm -3 ; The ratio of the Schottky diode cell to the MOS cell is between 1:2 and 1:10; The width of the second countertop area is smaller than the width of the first countertop area.

2. The field-effect transistor according to claim 1, characterized in that: The second source electrode is located on the surface of the second n-type drift layer.

3. The field-effect transistor according to claim 1, characterized in that: The second source electrode is one of Ti, Ni, Pd, Au, and Pt.

4. The field-effect transistor according to claim 1, characterized in that: The second source electrode and the first source electrode are made of the same electrode material.

5. The field-effect transistor according to claim 1, characterized in that: The second n-type drift layer has at least two layers from bottom to top, and the two layers have different doping concentrations.

6. The field-effect transistor according to claim 1, characterized in that: A p-type well region is also provided in the n-type drift layer located in the bottom region of the first shielding grid structure and / or the second shielding grid structure to alleviate the electric field concentration in the bottom region of the shielding grid.

7. The field-effect transistor according to claim 1, characterized in that: In the surface region of the n-type drift layer located in the second mesa region of the Schottky diode cell, a p-type carrier region is also provided to optimize the electric field distribution on one side of the Schottky diode cell and reduce the off-state leakage current.

8. The field-effect transistor according to claim 1, characterized in that: The ratio of the Schottky diode cell to the MOS cell is between 1:3 and 1:7.

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