Semiconductor device and integrated circuit device including the same

Abstract

Semiconductor devices and integrated circuit devices are provided. A semiconductor device includes a substrate having a first trench and a second trench, a device isolation pattern disposed in the first trench to define an active region in the substrate, a gate insulation pattern disposed on the active region, a gate electrode disposed on the gate insulation pattern, and a recess pattern filling at least a portion of the second trench and having a recessed upper surface. In a plan view, at least a portion of the recess pattern can overlap the gate electrode, and a depth of the second trench can be in a range of 80% to 100% of a depth of the first trench.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0177681, filed with the Korean Intellectual Property Office on December 3, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiments relate to semiconductor devices and integrated circuit devices including the semiconductor devices. Background Technology

[0003] With the increasing demand for miniaturization, multifunctionality, and high performance in electronic products, high-capacity integrated circuit devices are frequently required. This typically necessitates increased integration density to provide high-capacity integrated circuits. As the size of memory devices such as DRAM decreases, the gate length of the transistors configured to drive the memory device (e.g., transistors constituting a sense amplifier) ​​can also decrease, and / or threshold voltage variations can occur / threshold voltage variations can increase. Summary of the Invention

[0004] The example embodiments provide semiconductor devices and / or integrated circuit devices that exhibit improved electrical characteristics while having reduced feature sizes.

[0005] According to an example embodiment, a semiconductor device includes: a substrate having a first trench and a second trench; a device isolation pattern disposed in the first trench to define an active region in the substrate; a gate insulating pattern disposed on the active region; a gate electrode disposed on the gate insulating pattern; and a recessed pattern filling at least a portion of the second trench and having a concave upper surface. In a plan view, at least a portion of the recessed pattern may overlap with the gate electrode, and the depth of the second trench may be in the range of 80% to 100% of the depth of the first trench.

[0006] According to an example embodiment, a semiconductor device includes: a substrate having an active region defined by a device isolation pattern; a recessed pattern defined by the active region; a gate electrode disposed on the active region and including a portion vertically overlapping the recessed pattern and a portion vertically overlapping the device isolation pattern; and a gate insulating pattern between the gate electrode and the active region. In the portion vertically overlapping the gate electrode, the upper surface of the recessed pattern may be configured to be further from the upper surface of the substrate in the vertical direction than the upper surface of the device isolation pattern in the vertical direction.

[0007] According to an example embodiment, an integrated circuit device includes: a sense amplifier configured to detect a voltage on a bit line, and includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. At least one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor may include: a substrate having a first trench and a second trench; a device isolation pattern disposed in the first trench to define an active region in the substrate; a gate insulating pattern disposed on the active region; a gate electrode disposed on the gate insulating pattern; and at least one recessed pattern filling at least a portion of the second trench and having a concave upper surface. In a plan view, at least a portion of the recessed pattern may overlap with the gate electrode, and the depth of the second trench may be in the range of 80% to 100% of the depth of the first trench.

[0008] According to an example embodiment, a method of manufacturing a semiconductor device includes: forming a first trench and a second trench on a substrate; forming a first insulating layer to fill the first trench and the second trench; performing a planarization process such that the first insulating layer is removed downwards to an upper surface of the substrate to form a device isolation pattern and a recessed pattern; forming a gate insulating layer and a conductive layer on the substrate; and patterning the gate insulating layer and the conductive layer to form a gate insulating pattern and a gate electrode. The recessed pattern may have a concave upper surface, and the gate electrode may have a protrusion corresponding to and / or projecting toward the concave upper surface of the recessed pattern.

[0009] According to an example embodiment, the width of the first groove may be greater than the width of the second groove.

[0010] According to an example embodiment, a device isolation pattern can be formed in a first trench, and a recessed pattern can be formed in a second trench.

[0011] According to an example embodiment, the upper surface of the recessed pattern can be formed at a lower level than the upper surface of the device isolation pattern.

[0012] According to an example embodiment, the upper surface of the device isolation pattern may be formed at the same or substantially the same level as the upper surface of the substrate.

[0013] According to an example embodiment, the second trench may include a bottom surface, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface of the substrate and having a tilt angle different from that of the first side surface. The edge of the upper surface of the recessed pattern may contact the second side surface.

[0014] According to an example embodiment, the depth of the second trench can be 80% to 100% of the depth of the first trench.

[0015] According to the example embodiment, the same patterning process can be used to form the first trench and the second trench.

[0016] According to example embodiments, a planarization process can be performed using an etch-back process and / or a chemical mechanical polishing (CMP) process.

[0017] According to the example embodiment, the formation of device isolation patterns and the formation of recessed patterns can be performed in the same operation. Attached Figure Description

[0018] Figure 1 This is a plan view of a semiconductor device according to an example embodiment.

[0019] Figure 2A It is the edge of the semiconductor device according to the example embodiment. Figure 1 A cross-sectional view of line A1-A1'.

[0020] Figure 2B It is the edge of the semiconductor device according to the example embodiment. Figure 1 A cross-sectional view of line B1-B1'.

[0021] Figure 3 yes Figure 2B A magnified view of part X1.

[0022] Figures 4A to 4E These are diagrams sequentially illustrating methods for manufacturing semiconductor devices according to exemplary embodiments, and corresponding to... Figure 2B Cross-sectional view.

[0023] Figure 5 This is a block diagram of an integrated circuit device according to an example embodiment.

[0024] Figure 6 This is a layout diagram of a semiconductor device according to an example embodiment.

[0025] Figure 7 This is an equivalent circuit diagram of the readout amplifier according to the example embodiment.

[0026] Figure 8 This is a plan view of an integrated circuit device including semiconductor devices according to an example embodiment.

[0027] Figures 9A to 9C The respective edges of the integrated circuit device according to the example embodiment Figure 8 The cross-sectional views taken by lines A2-A2', B2-B2', and C-C'. Detailed Implementation

[0028] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it will be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context clearly and / or explicitly describes the opposite. On the other hand, the term “composed of” indicates that a component is formed solely by the listed element(s).

[0029] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “top,” “bottom,” “front,” and “back” are used in this document to describe positional relationships such as those shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms also cover different orientations of the devices.

[0030] As used herein, components described as “electrical connections” are configured such that electrical signals can be transmitted from one component to another (although such electrical signals may be attenuated in strength and may be selectively transmitted during transmission).

[0031] Terms such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular” as used herein encompass similarity or near-identity, including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements otherwise indicate otherwise, the term “substantially” may be used herein to emphasize this meaning.

[0032] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0033] Figure 1 This is a plan view of a semiconductor device according to an example embodiment. Figure 2A It is the edge of the semiconductor device according to the example embodiment. Figure 1 The cross-sectional view taken from line A1-A1'. Figure 2B It is the edge of the semiconductor device according to the example embodiment. Figure 1 The cross-sectional view taken from line B1-B1'.

[0034] Reference Figure 1 , Figure 2A and Figure 2BThe semiconductor device may include a substrate 110 and a gate electrode GE. The substrate 110 may include an active region AR, a device isolation pattern 120, a recessed pattern 121, and a first source / drain region SD1 and a second source / drain region SD2. For example, the recessed pattern 121 may be a pattern having a recess on a top surface / upper surface 121s. For example, the recessed pattern 121 may have a recessed portion in the top surface / upper surface 121s. For example, the recess on the top surface / upper surface 121s of the recessed pattern 121 may be a recess formed in the center or another portion of the top surface / upper surface 121s of the recessed pattern 121. The recessed portion of the top surface / upper surface 121s may be at a lower level than other portions of the top surface / upper surface 121s of the recessed pattern 121.

[0035] For clarity, the direction parallel to the upper surface 110s of the substrate 110 will be referred to as the first direction DR1, the direction parallel to the upper surface 110s of the substrate 110 and perpendicular to the first direction DR1 will be referred to as the second direction DR2, and the direction perpendicular to the upper surface 110s of the substrate 110 will be referred to as the third direction DR3. For example, the first direction DR1 and the second direction DR2 can be horizontal, and the third direction DR3 can be vertical.

[0036] Substrate 110 may include, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 110 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer. Device isolation pattern 120 may be disposed within substrate 110 to define an active region AR.

[0037] The active region AR can be a region within the substrate 110 implanted with impurities. For example, when the semiconductor device is an NMOS transistor, the active region AR can be formed by ion implantation of P-type impurities. When the semiconductor device is a PMOS transistor, the active region AR can be formed by ion implantation of N-type impurities. Multiple active regions AR can be formed in the substrate 110, and the active region AR can be a portion of the substrate 110 surrounded by the device isolation pattern 120.

[0038] Device isolation pattern 120 may surround at least a portion of active region AR, thereby separating that portion from other active regions AR. Device isolation pattern 120 may be disposed within a first trench TCH1 recessed from the upper surface 110s of substrate 110. Device isolation pattern 120 may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may comprise a single layer or multiple layers.

[0039] A portion of the device isolation pattern 120 may be disposed below the gate electrode. For example, a portion of the device isolation pattern may vertically overlap with the gate electrode. In the overlapping region of the device isolation pattern and the gate electrode, the upper surface of the device isolation pattern 120 may be coplanar or substantially coplanar with the upper surface 110s of the substrate 110. However, the inventive concept is not limited thereto, and the upper surface of the device isolation pattern 120 may not be a flat surface.

[0040] The recessed pattern 121 may be disposed within the substrate 110 and below the gate electrode GE. For example, the recessed pattern 121 may be defined by an active region AR, and the side and bottom surfaces of the recessed pattern 121 may be surrounded by the active region AR.

[0041] The recessed pattern 121 may vertically overlap with the gate electrode GE. For example, in a cross-sectional view, the entire recessed pattern 121 may overlap with the gate electrode GE on the third direction DR3. Although not shown, in an example embodiment, a portion of the recessed pattern 121 may not vertically overlap with the gate electrode GE.

[0042] In the plan view, at least a portion of the recessed pattern 121 may be disposed within the gate electrode GE. In an example embodiment, the entire recessed pattern 121 may be disposed within the gate electrode GE.

[0043] One or more recessed patterns 121 may be disposed in the active region AR and / or below the gate electrode GE. In this embodiment, two recessed patterns 121 are disposed in the active region AR and below the gate electrode GE. When multiple recessed patterns 121 are disposed, at least a portion of the recessed pattern 121 may, for example, vertically overlap with the gate electrode GE in a plan view. For example, all of the multiple recessed patterns 121 may vertically overlap with the gate electrode GE. Alternatively, a portion of the multiple recessed patterns 121 may completely overlap with the gate electrode GE in the vertical direction, wherein a portion of the recessed pattern 121 may partially overlap with the gate electrode GE in the vertical direction, while another portion of the recessed pattern 121 may not overlap with the gate electrode GE in the vertical direction. For example, some of the multiple recessed patterns 121 may completely overlap with the gate electrode GE in the vertical direction, some other recessed patterns 121 may partially overlap with the gate electrode GE in the vertical direction, and other recessed patterns 121 may not overlap with the gate electrode GE in the vertical direction.

[0044] The recessed pattern 121 can be disposed within the second trench TCH2 recessed from the upper surface 110s of the substrate 110. The upper surface 121s of the recessed pattern 121 can be concave.

[0045] In an example embodiment, the depth d2 of the second trench TCH2 may be less than or equal to the depth d1 of the first trench TCH1. In an example embodiment, the depth d2 of the second trench TCH2 may be at least about 80%, for example, at least about 90% or at least about 95%, of the depth d1 of the first trench TCH1. In an example embodiment, the depth d2 of the second trench TCH2 may be equal to the depth d1 of the first trench TCH1. The active region AR can then be defined by the device isolation pattern 120 and the recessed pattern 121. For example, the bottom boundary of the active region AR may be at the same level as the bottom surface of the device isolation pattern 120.

[0046] The recessed pattern 121 may include the same material as the device isolation pattern 120, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may include a single layer or multiple layers.

[0047] The gate electrode GE can be disposed on the substrate 110 across the active region AR. For example, when the active region AR extends longitudinally, for example, in the second direction DR2, the gate electrode can extend longitudinally, for example, in the first direction DR1. The gate electrode GE can cover at least a portion of the recessed pattern 121. In an example embodiment, the gate electrode GE can completely cover the recessed pattern 121, and the recessed pattern 121 can be disposed inside the gate electrode GE in a plan view.

[0048] The gate electrode GE may have a protrusion PRT corresponding to and / or projecting toward the recessed portion of the upper surface 121s of each of the recessed patterns 121. This will be referred to later. Figure 3 Describe it.

[0049] The gate electrode GE can be formed of a conductive material. In an example embodiment, the gate electrode GE may include a conductive pattern and a blocking pattern (not shown) surrounding the conductive pattern. For example, the conductive pattern may be formed of a material having a lower resistivity than the blocking pattern. For example, the conductive pattern may be formed of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, conductive metal nitrides, or combinations thereof. The blocking pattern may cover the side and bottom surfaces of the conductive pattern. The blocking pattern may be formed of a conductive material having a predetermined work function (e.g., a higher work function than the conductive pattern). For example, the blocking pattern may include a metal layer / metal nitride layer. The metal layer may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride, cobalt nitride (CoN), and platinum nitride (PtN).

[0050] The gate insulating pattern GI can be inserted between the gate electrode GE and the substrate 110.

[0051] The gate insulating pattern GI can cover the substrate 110 and the upper surface 121s of the recessed pattern 121 below the gate electrode GE. The gate insulating pattern GI can have a downward concave shape corresponding to the recessed pattern 121.

[0052] The gate insulating pattern GI may comprise a high-k dielectric material having a higher dielectric constant than silicon oxide. For example, the gate insulating pattern GI may comprise at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but the inventive concept is not limited thereto. Alternatively, the gate insulating pattern GI may be formed by thermally oxidizing the upper surface of the substrate 110.

[0053] The gate spacer SP can be disposed on the source / drain region SD to cover the opposite sidewalls of the gate electrode GE. The gate spacer SP can be formed of an insulating material such as silicon oxide or silicon nitride.

[0054] The source / drain region SD can be located on opposite sides of the gate electrode GE. The source / drain region SD can include a first source / drain region SD1 located on one side of the gate electrode GE and a second source / drain region SD2 located on the other side of the gate electrode GE. The first source / drain region SD1 and the second source / drain region SD2 can be located within the active region AR.

[0055] The first source / drain region SD1 and the second source / drain region SD2 can together with the gate electrode GE to form a transistor, and can be the source region and drain region of the transistor, respectively. For example, the first source / drain region SD1 can correspond to the drain region, and the second source / drain region SD2 can correspond to the source region.

[0056] The first source / drain region SD1 and the second source / drain region SD2 may be disposed on opposite sides of the gate electrode GE and may be disposed below the gate spacer SP. The first source / drain region SD1 and the second source / drain region SD2 may be formed by implanting impurity ions into the active region AR using the gate electrode GE as an ion implantation mask. The first source / drain region SD1 and the second source / drain region SD2 may include impurities having a conductivity type opposite to that of the substrate 110.

[0057] The first source / drain region SD1 and the second source / drain region SD2 can be formed by doping or ion implantation with substantially the same impurities. For example, the first source / drain region SD1 and the second source / drain region SD2 may, for example, include the same impurities per unit volume. The first source / drain region SD1 and the second source / drain region SD2 can be interchangeably labeled according to the final transistor circuit configuration. For example, the active region AR may include P-type impurities, and the first source / drain region SD1 and the second source / drain region SD2 may include N-type impurities.

[0058] In an example embodiment, the recessed pattern 121 may be disposed below the gate electrode GE.

[0059] Figure 3 yes Figure 2B An enlarged cross-sectional view of part X1 shows the portion in which the recessed pattern 121 is formed.

[0060] Reference Figures 1 to 3 One or more second trenches TCH2 can be formed in the substrate 110, and a recessed pattern 121 can be formed in each second trench TCH2.

[0061] The second trench TCH2 may include a bottom surface and side surfaces. The side surfaces of the second trench TCH2 may include a first side surface 123a and a second side surface 123b with different angles relative to the upper surface 110s of the substrate 110. The first side surface 123a may be connected to the bottom surface, and the second side surface 123b may be disposed above the first side surface 123a and may correspond to or be in contact with the upper surface 110s of the substrate 110. The second side surface 123b may be an inclined surface having a smaller tilt angle than the first side surface 123a. For example, the first side surface 123a may have a tilt angle of about 70 degrees to about 90 degrees relative to the upper surface 110s of the substrate 110. The second side surface 123b may have a tilt angle of about 45 degrees to about 80 degrees relative to the upper surface 110s of the substrate 110. For example, in a cross-sectional view, the tilt angle of the side surfaces of the second trench may be an acute angle between a line parallel to the sidewall of the second trench and a line parallel to the upper surface 110s of the substrate. Each of the first side surface 123a and the second side surface 123b can be a substantially flat surface or can be configured as a curved surface. When each of the first side surface 123a and the second side surface 123b is configured as a curved surface, the inclination angle can be the average inclination angle of the tangents of the first side surface 123a and the second side surface 123b, respectively. The first side surface 123a can be a side surface of the second trench TCH2 as described below. Figure 4A The trench forming process described herein forms the portion, and the second side surface 123b may be the side surface of the second trench TCH2 as described below. Figure 4C The process of forming the recessed pattern 121 in the second trench TCH2 is described. For example, the first side surface 123a of the second trench TCH2 may be the portion of the side surface of the second trench TCH2 that contacts the recessed pattern 121, and the second side surface 123b of the second trench TCH2 may be the portion of the side surface of the second trench TCH2 that contacts the gate insulating pattern GI.

[0062] The recessed pattern 121 may fill at least a portion of the second trench TCH2. In an example embodiment, the recessed pattern 121 may fill the interior of the second trench TCH2 from the bottom surface of the second trench TCH2 to the point where the first side surface 123a and the second side surface 123b contact each other. For example, the recessed pattern 121 may have a concave upper surface 121s. In an example embodiment, the edge of the upper surface 121s of the recessed pattern 121 may abut or contact the edge of the second side surface 123b.

[0063] When viewed in cross-section, if the height of the lowest point of the upper surface 121s of the recessed pattern 121 is defined as a first level LV1, and the height of the highest point of the upper surface 121s of the recessed pattern 121 is defined as a second level LV2, then the first level LV1 can be lower than the second level LV2. For example, the central portion of the recessed pattern 121 can be further away from the upper surface 110s of the substrate 110 in the vertical direction than the edge of the recessed pattern 121.

[0064] In the example embodiment, the upper surface of the device isolation pattern 120 that vertically overlaps with the gate electrode GE can be a flat surface or a substantially flat surface. The upper surface of the device isolation pattern 120 can be at the same level or substantially at the same level (e.g., substantially coplanar) as the upper surface 110s of the substrate 110. For example, if the height of the upper surface of the device isolation pattern 120 that vertically overlaps with the gate electrode GE is defined as a third level LV3, then the third level LV3 can be the same as or substantially the same as the height of the upper surface 110s of the substrate 110. Therefore, the third level LV3 can be higher than the second level LV2 and the first level LV1. For example, the highest point of the upper surface 121s of the recessed pattern 121 can be at a lower level than the upper surface of the device isolation pattern 120 and the upper surface 110s of the substrate 110.

[0065] In an example embodiment, when a portion of the upper surface of the device isolation pattern 120 is a concave curved surface, the lowest point of the upper surface of the device isolation pattern 120 may be at a level lower than the upper surface 110s of the substrate 110. Even in this case, the upper surface of the device isolation pattern 120 may be configured to be closer to the upper surface 110s of the substrate 110 in the vertical direction than the upper surface 121s of the recessed pattern 121.

[0066] A gate electrode GE can be disposed on a recessed pattern 121, and a gate insulating pattern GI is inserted between the gate electrode GE and the recessed pattern 121. The gate electrode GE can have a lower surface corresponding to the shape of the upper surface 121s of the recessed pattern 121 and the shape of the second side surface 123b of the second trench TCH2. For example, the gate electrode GE can have a protrusion PRT corresponding to the upper surface 121s of the recessed pattern 121 and the second side surface 123b of the second trench TCH2. For example, the protrusion PRT of the gate electrode GE can protrude toward the upper surface 121s of the recessed pattern 121. Therefore, in the gate electrode GE, the lower surface of the portion vertically overlapping with the recessed pattern 121 can be at a lower level than the lower surface of the portion vertically overlapping with the device isolation pattern 120.

[0067] Due to transistor operation (e.g., when a voltage is applied to the gate electrode GE), a channel region CHN can be formed in the active region AR below the gate electrode GE. The channel region CHN can be formed below the gate electrode GE, for example, in a sloping region adjacent to the upper surface 110s of the substrate 110 and the second side surface 123b of the second trench TCH2. The protrusion PRT of the gate electrode GE can be surrounded from the side surface of the gate electrode GE by the channel region CHN below the gate electrode GE. For example, the channel region CHN can be formed along the side surface of the protrusion PRT of the gate electrode GE, thereby expanding the area of ​​the channel region CHN. Therefore, the channel region CHN can be disposed between the source / drain regions in a finned channel shape, and the transistor can operate similarly to a finned transistor. For example, a finned channel and a finned transistor can be a channel and a transistor respectively formed with the aforementioned recessed pattern.

[0068] The vertical distance t from the upper surface 110s of the substrate 110 to the lowest point of the upper surface 121s of the recessed pattern 121 can be proportional to the size of the channel region CHN. The larger the distance t from the upper surface 110s of the substrate 110 to the lowest point of the upper surface 121s of the recessed pattern 121, the larger the size of the channel region CHN. In an example embodiment, the width (e.g., horizontal width) w of the uppermost part of the second trench TCH2 can be less than or equal to twice the distance (e.g., vertical distance) t from the upper surface 110s of the substrate 110 to the lowest point of the upper surface 121s of the recessed pattern 121 (w ≤ 2t).

[0069] In the example embodiment, the recessed pattern 121 may be set as a rectangular shape in the plan view, but the inventive concept is not limited thereto. For example, in the plan view, the recessed pattern 121 may be set as a circular, elliptical, or polygonal shape. Furthermore, for example in the plan view, the recessed pattern 121 may be elongated in one direction.

[0070] In the example embodiment, the length or width of the channel region CHN formed between the source / drain regions SD can be controlled by varying the shape and number of the recessed pattern 121. For example, the effective channel length can be increased by varying the shape or number of the recessed pattern 121. As a result, higher current density can be achieved while reducing the switching time of the transistor.

[0071] Figures 4A to 4E It corresponds to Figure 2B The cross-sectional view sequentially illustrates a method for manufacturing a semiconductor device according to an example embodiment.

[0072] Reference Figure 4A A mask pattern (not shown) can be formed on the substrate 110, and the mask pattern can be used as an etching mask to perform a patterning / etching process to form the first trench TCH1, the second trench TCH2, and the active region AR. Taking into account the location where the gate electrode GE will be formed, the second trench TCH2 can be formed in the region overlapping with the gate electrode GE. Each of the second trenches TCH2 may have a first side surface 123a (see...). Figure 3 ).

[0073] In an example embodiment, the first trench TCH1 and the second trench TCH2 can be formed using the same patterning process. Therefore, the depths of the first trench TCH1 and the second trench TCH2 can be the same. In an example embodiment, the second trench TCH2 can be formed to have a narrower width than the first trench TCH1. For example, when the trench width is formed below a certain range, the etching rate can be lower. Therefore, the etching degree of the second trench TCH2 can be less than that of the first trench TCH1. For example, the depth of the second trench TCH2 can be less than the depth of the first trench TCH1. The depth difference between the first trench TCH1 and the second trench TCH2 can fall within a process margin.

[0074] Reference Figure 4B A first insulating layer INS1 can be formed to fill the first trench TCH1 and the second trench TCH2.

[0075] The first insulating layer INS1 can be formed by forming a device isolation pattern 120 (see...). Figure 3 ) and recessed pattern 121 (see Figure 3 The insulating material is formed. For example, the first insulating layer INS1 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), low-k dielectric, or a combination thereof.

[0076] When the first insulating layer INS1 fills the first trench TCH1 and the second trench TCH2, the insulating material can be deposited to different degrees depending on the widths of the first trench TCH1 and the second trench TCH2. For example, the region forming the first trench TCH1 may have a relatively large width, and the region forming the second trench TCH2 may have a relatively small width, making it easier for the insulating material to be deposited in the first trench TCH1 than in the second trench TCH2. As a result, the first trench TCH1 may be completely filled or overfilled, and the second trench TCH2 may be left unfilled.

[0077] Reference Figure 4C The first insulating layer INS1 can be planarized until the upper surface 110s of the substrate 110, such as the upper surface of the active region AR, is exposed. Planarization of the first insulating layer INS1 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The planarized substrate 110 can then be cleaned.

[0078] A portion of the first insulating layer INS1 can be removed to form a device isolation pattern 120 in the first trench TCH1 and a recessed pattern 121 in the second trench TCH2.

[0079] During the planarization process of the upper surface 110s of substrate 110 and the first insulating layer INS1, the substrate 110 and the first insulating layer INS1 can be etched to different degrees depending on the stacking degree, etching rate, and exposed area of ​​each of the substrate 110 and the first insulating layer INS1. For example, the insulating material forming the first insulating layer INS1 may have a higher etching rate than the material of the substrate 110. Furthermore, the first trench TCH1 has a wider width than the second trench TCH2, such that the first insulating layer INS1 in the region where the first trench TCH1 is formed can have a larger exposed area than the first insulating layer INS1 in the region where the second trench TCH2 is formed. Additionally, the first insulating layer INS1 can be deposited to different degrees in the first trench TCH1 and the second trench TCH2. Therefore, the first insulating layer INS1 in the second trench TCH2 can be etched more than the first insulating layer INS1 in the first trench TCH1.

[0080] As a result, the substrate 110, the device isolation pattern 120, and the recessed pattern 121 can be formed with different shapes and depths depending on their respective etching degrees. For example, a concave recess can be formed on the upper surface 121s of the recessed pattern 121. Therefore, the upper surface 121s of the recessed pattern 121 can be at a lower level than the upper surface of the device isolation pattern 120.

[0081] After etching the first insulating layer INS1 and the upper surface 110s of the substrate 110, the upper surface of the device isolation pattern 120 and the upper surface 110s of the substrate 110 may be substantially flat or coplanar. However, in some examples, the upper surface of the device isolation pattern 120 and the upper surface 110s of the substrate 110 may not be completely flat surfaces. At least a portion of the upper surface of the device isolation pattern 120 and the upper surface 110s of the substrate 110 adjacent to the device isolation pattern 120 and the recessed pattern 121 may be curved surfaces. In the figures, the device isolation pattern 120 is shown as a flat surface, but in some embodiments, at least a portion of the upper surface of the device isolation pattern 120 may also be a curved surface.

[0082] During the etching of the portion of the first insulating layer INS1 corresponding to the recessed pattern 121, the adjacent upper surface 110s of the substrate 110 may also be additionally etched to form a sloping surface. For example, when a portion of the first insulating layer INS1 in the second trench TCH2 is etched and removed, the edge region where the side surface of the second trench TCH2 adjoins the upper surface 110s of the substrate 110 may be exposed to the outside. The exposed edge region is readily etchable and may be additionally etched similarly to the chamfers observed during the etch-back process and / or planarization process. The additionally etched sloping surface of the substrate 110 may form the second side surface 123b of the second trench TCH2 (see...). Figure 3 ).

[0083] Reference Figure 4D A second insulating layer INS2 and a conductive layer CL can be sequentially formed on the substrate 110.

[0084] The second insulating layer INS2 may be conformally formed on the substrate 110 and may be formed of a material that forms the gate insulating pattern GI. For example, the second insulating layer INS2 may be formed of a high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, the gate insulating pattern GI may be formed of at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but the inventive concept is not limited thereto.

[0085] A conductive layer CL may be formed on the second insulating layer INS2. The conductive layer CL may be formed of the material forming the gate electrode GE. For example, the conductive layer CL may be formed of various conductive materials (e.g., tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, conductive metal nitrides, or combinations thereof). Although not shown, the conductive layer CL may include multiple layers, and the conductive layer CL may include a first conductive layer (not shown) for a blocking pattern and a second conductive layer (not shown) for a conductive pattern. The first and second conductive layers may be formed of the materials forming the blocking pattern and the conductive pattern, respectively.

[0086] Reference Figure 4E The conductive layer CL and the second insulating layer INS2 can be patterned to form the gate electrode GE and the gate insulating pattern GI. Gate spacers SP can be additionally formed on opposite sides of the gate electrode GE and the gate insulating pattern GI.

[0087] Patterning of the conductive layer CL and the second insulating layer INS2 can be achieved by forming a mask pattern on the conductive layer CL and using the mask pattern as an etching mask to perform a patterning / etching process.

[0088] As described above, according to the example embodiment, the recessed pattern 121 can be formed simultaneously in the same process as forming the device isolation pattern 120.

[0089] For example, when manufacturing semiconductor devices, a recessed pattern 121 can be formed without an additional mask to facilitate the implementation of fin channels within the transistor.

[0090] The semiconductor device according to the example embodiment can be used in various integrated circuit devices. For example, the semiconductor device can be used in a semiconductor-based memory device. The memory device can be volatile memory (such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), dual data rate synchronous dynamic random access memory (DDR SDRAM), low power dual data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics dual data rate synchronous dynamic random access memory (GDDR SDRAM), dual data rate type 2 synchronous dynamic random access memory (DDR2 SDRAM), dual data rate type 3 synchronous dynamic random access memory (DDR3 SDRAM), dual data rate type 4 synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.) or non-volatile memory (such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), etc.).

[0091] Figure 5This is a block diagram of an integrated circuit device according to an example embodiment.

[0092] Reference Figure 5 The integrated circuit device includes a memory cell area A1 and a peripheral circuit area A2.

[0093] Memory cell area A1 may include memory cell array 101. Peripheral circuit area A2 may include command decoder 108, control logic 107, address buffer 104, row decoder 103, column decoder 102, sense amplifier 105, and data input / output circuitry 106. Peripheral circuit area A2 may output data via data line DQ in response to commands CMD, address ADDR, and control signals received from an external device such as a memory controller.

[0094] The memory cell array 101 includes a plurality of memory cells (not shown) arranged in a two-dimensional or three-dimensional manner. For example, the memory cell array 101 may include a plurality of memory cells arranged in a matrix of multiple rows and columns. The memory cells may be electrically connected between bit lines BL and word lines (not shown) that intersect each other.

[0095] Each memory cell may include a data storage element and a selection element, and the selection element and the data storage element may be connected in series.

[0096] The data storage element can be electrically connected between the bit line BL and the select element, and the select element can be electrically connected between the data storage element and the word line.

[0097] The selected element can be a field-effect transistor (FET). For example, the data storage element can be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device according to the example embodiment can be dynamic random access memory (DRAM). For example, the data storage element can include a magnetic tunnel junction pattern. In this case, the semiconductor memory device according to the example embodiment can be magnetic random access memory (MRAM). For example, the data storage element can include a phase change material or a variable resistance material. In this case, the semiconductor memory device according to the example embodiment can be phase change random access memory (PRAM) or resistive random access memory (ReRAM). However, these are merely examples, and the inventive concept is not limited thereto. The data storage element can include various structures and / or materials capable of storing data.

[0098] Command decoder 108 can decode commands (CMDs) received from external devices such as memory controllers to generate control signals corresponding to the commands (CMDs) in control logic 107, such as write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc. Commands (CMDs) may include activation commands, read commands, write commands, precharge commands, etc.

[0099] Address buffer 104 may receive address ADDR from memory controller (i.e., external device). Address ADDR may include row address RA for addressing rows of memory cell array 101 and column address CA for addressing columns of memory cell array. Address buffer 104 may send row address RA to row decoder 103 and column address CA to column decoder 102.

[0100] The row decoder 103 can select one of multiple word lines electrically connected to the memory cell array 101. The row decoder 103 can decode the row address RA received from the address buffer 104, select the single word line corresponding to the row address RA, and activate the selected word line.

[0101] The column decoder 102 can select one of the multiple bit lines BL of the memory cell array 101. The column decoder 102 can decode the column address CA received from the address buffer 104 to select the predefined bit line BL corresponding to the column address CA.

[0102] The sense amplifier 105 can be electrically connected to the bit lines BL of the memory cell array 101. The sense amplifier 105 can read the voltage or voltage change in a selected bit line BL from multiple bit lines BL, amplify the read voltage, and output the amplified voltage. The data input / output circuit 106 can output data based on the read and amplified voltage output from the sense amplifier 105 to the outside via the data line DQ.

[0103] Figure 6 This is a layout diagram of a semiconductor device according to an example embodiment.

[0104] Reference Figure 6 An integrated circuit device may include multiple memory cell regions A1. Each of the multiple memory cell regions A1 may be surrounded by a peripheral circuit region A2. The peripheral circuit region A2 may refer to all areas surrounding the memory cell regions A1, excluding the memory cell regions A1.

[0105] In some embodiments, each of the plurality of memory cell regions A1 may be a memory cell region MCA of a DRAM device, and the peripheral circuit region A2 may be the region in which the peripheral circuit of the DRAM device is formed, as well as the core region / area (hereinafter referred to as "peripheral circuit region A2").

[0106] In the peripheral circuit area A2, circuits for reading data from or writing data to the memory cell area A1, circuits for signal processing, and circuits for power supply can be configured. Peripheral circuit area A2 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a connection block CJT. Multiple sense amplifiers (see...) Figure 5 The sense amplifier block (S / A) can be located within the sense amplifier block (S / A). The connection block (CJT) can be located at the intersection of the sub-word line driver block (SWD) and the sense amplifier block (S / A). Within the connection block (CJT), the power supply driver and ground driver for driving the sense amplifier can be alternately configured. Peripheral circuitry such as inverter chains and input / output circuits can also be formed in the peripheral circuitry area (A2).

[0107] In the integrated circuit device according to the example embodiment, a plurality of transistors may be disposed in the peripheral circuit region A2. For example, the transistors of the sense amplifier may be disposed in the sense amplifier block S / A.

[0108] Figure 7 This is an equivalent circuit diagram of the readout amplifier according to the example embodiment.

[0109] Reference Figure 7 The sense amplifier may include a first driver DRV1 and a second driver DRV2 electrically connected between a pair of bit lines BL and / BL. The pair of bit lines includes a first bit line BL and a second bit line / BL, and the second bit line / BL may be a complementary bit line.

[0110] The first driver DRV1 may include a first PMOS transistor P1 and a second PMOS transistor P2 connected in series between the alignment lines BL and / BL, and the second driver DRV2 may include a first NMOS transistor N1 and a second NMOS transistor N2 connected in series between the alignment lines.

[0111] When the voltage level of the first bit line BL is higher than the voltage level of the second bit line / BL, the first PMOS transistor P1 and the second NMOS transistor N2 can be turned on, and the second PMOS transistor P2 and the first NMOS transistor N1 can be turned off simultaneously. The voltage of the first bit line BL can be amplified to the first power supply voltage V. DD The voltage level, and the voltage of the second bit line / BL can be amplified to the second power supply voltage V. SS The level.

[0112] Conversely, when the voltage level of the second bit line / BL is higher than the voltage level of the first bit line BL, the first PMOS transistor P1 and the second NMOS transistor N2 can be turned off, and the second PMOS transistor P2 and the first NMOS transistor N1 can be turned on simultaneously. The voltage of the second bit line / BL can be amplified to the first power supply voltage V. DD The voltage level, and the voltage of the first line BL can be amplified to the second power supply voltage V. SS The level.

[0113] In the example embodiment, refer to Figures 1 to 3The described semiconductor device can be applied to a pair of NMOS transistors and / or PMOS transistors that constitute a sense amplifier.

[0114] Figure 8 This is a plan view of an integrated circuit device including semiconductor devices according to an example embodiment. Figures 9A to 9C The respective edges of the integrated circuit device according to the example embodiment Figure 8 The cross-sectional views taken by lines A2-A2', B2-B2', and C-C'.

[0115] Reference Figure 8 and Figures 9A to 9C The substrate 110 may include a memory cell region A1 and a peripheral circuit region A2. For ease of description, the memory cell region A1 will be described first, followed by the peripheral circuit region A2.

[0116] In memory cell region A1, the integrated circuit device may include substrate 110, source / drain region SD, word line structure 150, bit line structure 140, bit line contact BTC, memory node contact SC, landing pad 170, and data storage pattern DSP.

[0117] Substrate 110 may include, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 110 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0118] The substrate 110 may include an active region AR and a device isolation pattern 120.

[0119] Device isolation pattern 120 may be disposed within substrate 110 and define active region AR. Active region AR may be spaced apart from each other in a first direction DR1 and a second direction DR2 that intersect each other (e.g., orthogonally). The first direction DR1 and the second direction DR2 may be parallel to the lower surface of substrate 110.

[0120] Device isolation pattern 120 can separate active regions AR from each other while surrounding the active regions AR. Device isolation pattern 120 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), low-k dielectric, or combinations thereof. Device isolation pattern 120 may include a single layer or multiple layers. In an example embodiment, device isolation pattern 120 may include a silicon oxide layer.

[0121] Each active region AR may have an isolated island shape and may be in the form of a strip extending in a fourth direction DR4. The fourth direction DR4 may be parallel to the lower surface of the substrate 110 and intersect the first direction DR1 and the second direction DR2. The fourth direction DR4 may intersect the first direction DR1 at an angle other than 90 degrees (e.g., an acute angle). In a plan view, the active region AR may be a portion of the substrate 110 surrounded by device isolation patterns 120. The active region AR may protrude from other portions of the substrate 110 in a third direction DR3 perpendicular to the lower surface of the substrate 110. For example, the active region AR may extend upward in the third direction DR3, for example, between device isolation patterns 120. The device isolation pattern 120 may include an insulating material and may include at least one of, for example, silicon oxide, silicon nitride, and combinations thereof.

[0122] Source / drain regions SD may be disposed within substrate 110, for example, within active region AR. Each of the source / drain regions SD may be configured as either a source or drain region of a transistor. For example, with respect to a single active region AR, two word line structures 150 may span the single active region AR. A drain region may be formed between the two word line structures 150, while a source region may be formed on the opposite side of the drain region relative to the two word line structures 150. The source and drain regions are formed by doping or ion implantation of the same or substantially the same impurities, and the source and drain regions may be interchangeably named according to the circuit configuration of the ultimately formed transistor. The source / drain regions SD may include impurities having a conductivity type opposite to that of substrate 110. For example, active region AR may include P-type impurities, while source / drain regions SD may include N-type impurities.

[0123] Multiple word line structures 150 can be arranged in memory cell area A1. The word line structures 150 can extend longitudinally in the second direction DR2 and be spaced apart from each other in the first direction DR1. The word line structures 150 can span the active area AR.

[0124] The word line structure 150 and the source / drain region SD can form a buried channel array transistor (BCAT).

[0125] The word line structure 150 may be buried within the substrate 110. Each word line structure 150 may include a gate electrode 151, a gate insulating pattern 153, and a gate capping pattern 157.

[0126] Gate electrode 151 may span the active region AR and device isolation pattern 120 in the second direction DR2. Gate insulating pattern 153 may be inserted between gate electrode 151 and active region AR, and between gate electrode 151 and device isolation pattern 120. Gate capping pattern 157 may cover gate electrode 151.

[0127] A buffer pattern 130 may be disposed on the substrate 110. The buffer pattern 130 may cover the active region AR, the device isolation pattern 120, and the word line structure 150. In an example embodiment, the buffer pattern 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0128] Bit line structures 140 may extend longitudinally in a first direction DR1 and may be spaced apart from each other in a second direction DR2. Bit line structures 140 may have stripes extending in the first direction DR1. Each bit line structure 140 may include a bit line 141 and a bit line capping pattern 143 on the bit line 141.

[0129] Bit line contacts BTC can be provided on each active region AR, and multiple bit line contacts BTC can be provided on the active region AR. The bit line contacts BTC can be electrically connected to and / or contact a portion of the source / drain region SD within the active region AR, respectively. The bit line contacts BTC can be spaced apart from each other in a first direction DR1 and a second direction DR2. The bit line contacts BTC can be inserted between the active region AR and the bit line 141, respectively. Each of the bit line contacts BTC can electrically connect a corresponding bit line 141 in the bit line 141 to the corresponding source / drain region SD.

[0130] A bit line capping pattern 143 may be provided on the upper surface of the bit line 141. Multiple bit line capping patterns 143 may be provided on the upper surface of the bit line 141. Each bit line capping pattern 143 may extend longitudinally along the corresponding bit line 141 in a first direction DR1 and may be spaced apart from each other in a second direction DR2. The bit line capping pattern 143 may vertically overlap with the bit line 141.

[0131] A bit line spacer 145 may be provided on the side surface of the bit line 141 and the side surface of the bit line cover pattern 143. Multiple bit line spacers 145 may be provided on the side surface of the bit line and the side surface of the bit line cover pattern 143. The bit line spacers 145 may cover the side surface of the bit line 141 and the side surface of the bit line cover pattern 143.

[0132] Storage node contacts SC can be provided between adjacent bit lines 141. Multiple storage node contacts SC can be provided in the memory cell area A1, and the storage node contacts SC can be spaced apart from each other in the first direction DR1 and the second direction DR2.

[0133] The memory node contact SC may extend within the substrate 110 to contact a portion of the source / drain region SD of the active region AR, and may be electrically connected to the respective source / drain region SD. The memory node contact SC may be formed of a conductive material and may include at least one of, for example, polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an example embodiment, the memory node contact SC may include doped polysilicon and may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb).

[0134] The storage node contacts SC can be spaced apart from each other in the first direction DR1 by the fence pattern 160 on the word line structure 150.

[0135] A fence pattern 160 may be disposed between bit line structures 140 and may vertically overlap with word line structures 150. The fence pattern 160 may be alternately disposed with memory node contacts SC in a first direction DR1. The fence pattern 160 may spatially separate the memory node contacts SC from each other and may electrically insulate the memory node contacts SC from each other. The lower surface of the fence pattern 160 may contact the gate cap pattern 157 of the word line structure 150.

[0136] The fence pattern 160 may include an insulating material, and may include, for example, silicon nitride.

[0137] Landing pads 170 can be provided on the storage node contact SC. Multiple landing pads 170 can be provided on the storage node contact SC, and the landing pads 170 can be spaced apart from each other in the first direction DR1 and the second direction DR2. The landing pads 170 can be electrically connected to and / or contact the corresponding storage node contact SC. The landing pads 170 can cover the upper surface of the bit line capping pattern 143.

[0138] At least a portion of each landing pad 170 may vertically overlap with the corresponding storage node contact SC. The landing pad 170 may include a metallic material (e.g., tungsten, titanium, tantalum, etc.).

[0139] A fill pattern 180 may surround the landing pad 170. The fill pattern 180 may be interposed between adjacent landing pads 170. In a plan view, the fill pattern 180 may be in the form of a mesh with holes through which the landing pads 170 penetrate. For example, the fill pattern 180 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof. For example, the fill pattern 180 may include empty spaces (e.g., air gaps) comprising an air layer.

[0140] Data storage pattern DSPs can be set on landing pad 170. Multiple data storage pattern DSPs can be set on landing pad 170, and the data storage pattern DSPs can be spaced apart from each other in the first direction DR1 and the second direction DR2. Each data storage pattern DSP can be electrically connected to the corresponding second source / drain region SD2 through the corresponding landing pad 170 and the corresponding memory node contact SC.

[0141] For example, a data storage pattern DSP can be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device according to the example embodiment can be dynamic random access memory (DRAM). For example, a data storage pattern DSP can include a magnetic tunnel junction pattern. In this case, the semiconductor memory device according to the example embodiment can be magnetic random access memory (MRAM). For example, a data storage pattern DSP can include a phase change material or a variable resistance material. In this case, the semiconductor memory device according to the example embodiment can be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). However, these are merely examples, and the inventive concept is not limited thereto. A data storage pattern DSP can include various structures and / or materials capable of storing data.

[0142] In the peripheral circuit area A2, a row decoder and a column decoder (see...) can be disposed on the substrate 110. Figure 5 ), Readout amplifier (see Figure 5 The peripheral circuitry includes a memory cell array and a controller (not shown). According to an example embodiment, the peripheral circuitry may include transistors, resistors, and capacitors electrically connected to the memory cell array. In an example embodiment, transistors in memory cell region A1 may be provided in a buried form, and transistors in peripheral circuitry region A2 may be provided in a flat / planar form.

[0143] In the example embodiment, at least a portion of the transistors in the peripheral circuit region A2 may be provided in a flat / planar form, but may also be provided as... Figures 1 to 3 The finned transistor described in [the text].

[0144] For example, the peripheral circuit region A2 may include a sense amplifier, and the transistors in the sense amplifier may be provided as fin transistors.

[0145] The sense amplifier may include a first PMOS transistor P1 and a second PMOS transistor P2 constituting the first driver DRV1, and a first NMOS transistor N1 and a second NMOS transistor N2 constituting the second driver DRV2.

[0146] The first PMOS transistor P1 and the second PMOS transistor P2 can be disposed in the first active region AR1, and the first NMOS transistor N1 and the second NMOS transistor N2 can be disposed in the second active region AR2. The first active region AR1 can be formed by ion implantation of N-type impurities, while the second active region AR2 can be formed by ion implantation of P-type impurities.

[0147] In the first driver DRV1, the gate electrode GE of the first PMOS transistor P1 and the gate electrode GE of the second PMOS transistor P2 can be disposed on the substrate 110. The source / drain region SD can be disposed on opposite sides of the first PMOS transistor P1 and the second PMOS transistor P2, and between the first PMOS transistor P1 and the second PMOS transistor P2. In the second driver DRV2, the gate electrode GE of the first NMOS transistor N1 and the gate electrode GE of the second NMOS transistor N2 can be disposed on the substrate 110. The source / drain region SD can be disposed on opposite sides of the first NMOS transistor N1 and the second NMOS transistor N2, and between the first NMOS transistor N1 and the second NMOS transistor N2. Each gate electrode GE and the source / drain region SD disposed on opposite sides of each gate electrode GE can constitute a corresponding transistor.

[0148] In each transistor of the first driver DRV1 and the second driver DRV2, at least one second trench TCH2 may be formed in the substrate 110, and a recessed pattern 121 may be formed in the second trench TCH2. Each gate electrode GE may include a protrusion PRT corresponding to the recessed pattern 121.

[0149] In an example embodiment, a portion of the transistor in each of the first driver DRV1 and the second driver DRV2 may be disposed in the same layer as a portion of the components of the memory cell region A1. Furthermore, in an example embodiment, a portion of the transistor in each of the first driver DRV1 and the second driver DRV2 may be formed of the same material as a portion of the components of the memory cell region A1, and a portion of the transistor in each of the first driver DRV1 and the second driver DRV2 may be manufactured using the same process as a portion of the components of the memory cell region A1. For example, the gate electrode GE of the peripheral circuit region A2 may be disposed in the same layer as the bit line 141 of the memory cell region A1. Furthermore, in each transistor of the first driver DRV1 and the second driver DRV2, the gate electrode GE may be manufactured using the same manufacturing process as that used to manufacture the bit line 141.

[0150] In the example embodiment, the shape and number of the recessed patterns 121 in at least a portion of the transistors of the first driver DRV1 and the second driver DRV2 can be varied in different ways to control the channel length and width between the source / drain regions. For example, the shape or number of the recessed patterns 121 can be changed in different ways to increase the effective channel length. As a result, the switching time of the transistors can be reduced, and higher current densities can be achieved.

[0151] In an integrated circuit device having the above structure, mismatch between transistors in the peripheral circuit region (e.g., between transistors in the sense amplifier) ​​can be reduced. This will be described below.

[0152] When the sense amplifier is in operation, the small potential difference between a pair of bit lines BL and / BL should be accurately read out and amplified. For this purpose, the first PMOS transistor P1 and the second PMOS transistor P2 should have the same electrical characteristics (e.g., threshold voltage), and the first NMOS transistor N1 and the second NMOS transistor N2 should have the same electrical characteristics (e.g., threshold voltage).

[0153] However, mismatch can occur between the transistors constituting the sense amplifier due to random dopant fluctuations (RDF) during the formation of the channel region (CHN). For example, the location and density of impurities may fluctuate randomly when impurities are implanted into the channel region (CHN), leading to mismatch between transistors. RDF can be a major cause of threshold voltage variation in each transistor. Mismatch between transistors can be reduced by increasing the channel area of ​​the transistors. However, increasing the channel area of ​​the transistors in the sense amplifier may lead to an increase in the area occupied by the sense amplifier in the peripheral circuitry region.

[0154] In an example embodiment, a recessed pattern can be formed beneath the gate electrode to effectively control channel dimensions, such as channel length and width. The gate electrode may include protrusions corresponding to the recessed pattern. The gate electrode including protrusions may be configured to surround or extend the channel. Therefore, the transistor can be driven in the same or similar manner as a FinFET.

[0155] As described above, the transistors of the semiconductor device according to the example embodiment can be provided in a small area in a planar view, while achieving a substantially large effective channel area in three dimensions. As a result, mismatch between transistors in the sense amplifier can be reduced.

[0156] As described above, according to the example embodiments, a semiconductor device can be provided that includes transistors with increased effective channel length while maintaining a compact overall size.

[0157] Furthermore, according to example embodiments, integrated circuit devices can be provided that have improved electrical characteristics while maintaining reduced feature sizes. For example, integrated circuit devices with reduced mismatch between transistors constituting a sense amplifier can be provided.

[0158] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the inventive concept. For example, in the exemplary embodiment, a transistor used in a sense amplifier in the peripheral circuit region is described as an example, but the inventive concept is not limited thereto. Embodiments of this disclosure can be applied to various transistors included in other integrated circuits. As other examples, different figures illustrate different exemplary embodiments, and different embodiments disclose features that differ from each other; these figures and embodiments are not necessarily intended to be mutually exclusive. Rather, features depicted in different figures and / or described above in different embodiments may be combined with other features from other figures / embodiments when the related descriptions of the figures and embodiments are considered as a whole to produce additional variations of the embodiments. For example, unless the context clearly indicates otherwise, components and / or features of the different embodiments described above may be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and this disclosure includes additional embodiments.

[0159] Therefore, the exemplary embodiments are for illustrative purposes only and are not intended to limit the inventive concept. The invention should be defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate having a first trench and a second trench; Device isolation pattern, which is in the first trench to define an active region in the substrate; A gate insulating pattern on the active region; Gate electrode, which is located on the gate insulating pattern; as well as A recessed pattern that fills at least a portion of the second groove and has a concave upper surface. in: In the plan view, at least a portion of the recessed pattern overlaps with the gate electrode; and The depth of the second trench is in the range of 80% to 100% of the depth of the first trench.

2. The semiconductor device according to claim 1, wherein: The gate electrode has a protrusion that projects toward the upper surface of the recess in the recessed pattern.

3. The semiconductor device according to claim 1, wherein: The second trench includes a bottom surface and a side surface; The side surface includes a first side surface connected to the bottom surface and a second side surface connected to the first side surface and the upper surface of the substrate; as well as The first side and the second side have different tilt angles relative to the upper surface of the substrate.

4. The semiconductor device according to claim 3, wherein: The second side surface has a tilt angle of 45 to 80 degrees relative to the upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein: The horizontal width of the uppermost part of the second trench is less than or equal to twice the vertical distance from the upper surface of the substrate to the lowest point of the upper surface of the recessed pattern.

6. The semiconductor device according to claim 1, wherein: The substrate includes a plurality of second trenches; Multiple recessed patterns are provided in the plurality of second grooves; and In the plan view, at least a portion of each of the plurality of recessed patterns overlaps with the gate electrode.

7. A semiconductor device, comprising: A substrate having an active region defined by a device isolation pattern; A recessed pattern defined by the active region; A gate electrode is located on the active region and includes a portion that vertically overlaps with the recessed pattern and a portion that vertically overlaps with the device isolation pattern. as well as A gate insulating pattern is formed between the gate electrode and the active region. in: In the portion that vertically overlaps with the gate electrode, the upper surface of the recessed pattern is configured to be farther from the upper surface of the substrate in the vertical direction than the upper surface of the device isolation pattern in the vertical direction.

8. The semiconductor device according to claim 7, wherein: The upper surface of the device isolation pattern in the portion that vertically overlaps with the gate electrode is at the same level as the upper surface of the substrate.

9. The semiconductor device according to claim 8, wherein: The upper surface of the recessed pattern has a concave shape; and The highest point of the upper surface of the recessed pattern that vertically overlaps with the gate electrode is at a level lower than the upper surface of the substrate.

10. The semiconductor device according to claim 7, wherein: The lower surface of the portion of the gate electrode that vertically overlaps with the recessed pattern is positioned at a lower level than the lower surface of the portion of the gate electrode that vertically overlaps with the device isolation pattern.

11. An integrated circuit device, comprising: A sense amplifier, configured to detect the voltage of a bit line, includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. in: At least one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor includes: A substrate having a first trench and a second trench; Device isolation pattern, which is in the first trench to define an active region in the substrate; The gate insulation pattern on the active region; The gate electrode on the gate insulating pattern; and At least one recessed pattern that fills at least a portion of the second groove and has a concave upper surface; In the plan view, at least a portion of the recessed pattern overlaps with the gate electrode; and The depth of the second trench is in the range of 80% to 100% of the depth of the first trench.

12. The integrated circuit device of claim 11, comprising: The memory cell area includes multiple memory cells and the peripheral circuit area includes the sense amplifier.

13. The integrated circuit device according to claim 12, wherein: At least a portion of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are disposed in the same layer as at least a portion of the plurality of memory cells.

14. The integrated circuit device according to claim 13, wherein: The memory cell region further includes a word line structure and a bit line structure, both of which are electrically connected to the plurality of memory cells; and The gate electrodes of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are disposed in the same layer as at least a portion of the bit line structure.

15. The integrated circuit device of claim 11, further comprising a plurality of active regions defined by the device isolation pattern. in: The plurality of active regions include a first active region and a second active region containing impurities of different conductivity types; and The first PMOS transistor and the second PMOS transistor are disposed in the first active region, and the first NMOS transistor and the second NMOS transistor are disposed in the second active region.

16. The integrated circuit device according to claim 11, wherein: The gate electrode has a protrusion that projects toward the upper surface of the recess in the recessed pattern.

17. The integrated circuit device according to claim 11, wherein: The second trench includes a bottom surface and a side surface; The side surface includes a first side surface connected to the bottom surface and a second side surface connected to the first side surface and the upper surface of the substrate; and The first side and the second side have different tilt angles relative to the upper surface of the substrate.

18. The integrated circuit device according to claim 17, wherein: The second side surface has a tilt angle of 45 to 80 degrees relative to the upper surface of the substrate.

19. The integrated circuit device according to claim 11, wherein: The horizontal width of the uppermost part of the second trench is less than or equal to twice the vertical distance from the upper surface of the substrate to the lowest point of the upper surface of the recessed pattern.

20. The integrated circuit device according to claim 11, wherein: The at least one recessed pattern is a plurality of recessed patterns; and In the plan view, at least a portion of each of the plurality of recessed patterns overlaps with the gate electrode.

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