Display device

Abstract

A display device includes a substrate, a first transistor over the substrate and connected to a first power supply line, a second transistor over the substrate and connected to a second power supply line, a light-emitting element connected to the first transistor and the second transistor, and a connection element connected to the first power supply line and the light-emitting element, wherein the connection element overlaps at least a part of the first transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0177401, filed in Korea on December 3, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more particularly, to a display device including a light-emitting element. Background Technology

[0004] With the development of the information society, the demand for different types of display devices is increasing. Flat panel display devices (FPDs), such as liquid crystal displays and light-emitting diode displays, have been developed and applied in various fields.

[0005] In flat panel display devices, light-emitting diode (LED) displays emit light due to the radiative recombination of excitons. Excitons are formed by electrons and holes by injecting charge into the light-emitting layer between the cathode (for injecting electrons) and the anode (for injecting holes) in the LED.

[0006] Light-emitting diode (LED) displays offer a variety of advantages and improved performance. For example, compared to liquid crystal displays (LCDs), LED displays are self-emissive, resulting in wider viewing angles, and they are ultra-thin and lightweight because they do not require a backlight unit. Furthermore, LED displays are also advantageous in terms of power consumption.

[0007] Light-emitting diode (LED) display devices can include inorganic-based and organic-based light-emitting elements. Inorganic-based light-emitting elements have relatively superior stability, fast response characteristics, and high contrast, and micro-LEDs (micro-LEDs or μLEDs) are widely used as inorganic-based light-emitting elements for high resolution.

[0008] However, inorganic light-emitting elements may have a lower threshold voltage than organic light-emitting elements, which could lead to light emission in the black state, resulting in reduced image quality. Summary of the Invention

[0009] Therefore, embodiments of this disclosure relate to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One aspect of this disclosure is to provide a display device capable of improving image quality.

[0011] Additional features and aspects will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept provided herein. Other features and aspects of the present disclosure may be realized and obtained, or may be derived from, the structures particularly pointed out in the written description, as well as the claims of this disclosure and the accompanying drawings.

[0012] To achieve these and other aspects of the present disclosure, as embodied and broadly described herein, a display device includes: a substrate; a first transistor located above the substrate and connected to a first power line; a second transistor located above the substrate and connected to a second power line; a light-emitting element connected to the first transistor and the second transistor; and a connecting element connected to the first power line and the light-emitting element, wherein the connecting element overlaps with at least a portion of the first transistor.

[0013] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the various principles of this disclosure. In the drawings:

[0015] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure;

[0016] Figure 2 This is an equivalent circuit diagram of a sub-pixel of a display device according to a first embodiment of the present disclosure;

[0017] Figure 3 This is a timing diagram of multiple signals and multiple node voltages for driving a display device according to a first embodiment of the present disclosure;

[0018] Figure 4 This is a schematic plan view of a display device according to a first embodiment of the present disclosure;

[0019] Figure 5 This is a schematic cross-sectional view of a display device according to a first embodiment of the present disclosure;

[0020] Figure 6 This is an equivalent circuit diagram of a sub-pixel of a display device according to a second embodiment of the present disclosure;

[0021] Figure 7 A schematic plan view of a display device according to a second embodiment of the present disclosure; and

[0022] Figure 8 This is a schematic cross-sectional view of a display device according to a second embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which it pertains.

[0024] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. shown in the accompanying drawings used to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0025] For ease of description, dimensions including the size and thickness of each component shown in the figures are shown, and this disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions of the relative size, position and thickness of the components shown in the various figures submitted herein are part of this disclosure.

[0026] Throughout this disclosure, the same reference numerals refer to the same parts.

[0027] Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies will be omitted or may be briefly discussed when it is determined that such detailed descriptions unnecessarily obscure the essential points of this disclosure.

[0028] When using terms such as “including,” “having,” or “comprising” as used in this disclosure, additional parts may be added, unless the term “only” is used herein.

[0029] Furthermore, when a component is represented in the singular, it includes the plural unless otherwise stated.

[0030] When analyzing components, even if there is no explicit description, it is interpreted as including the error range.

[0031] When describing positional relationships, for example, when the positional relationship between two parts / layers is described as "above", "on top", "above", "below", "under", etc., one or more other parts / layers may be provided between the two parts / layers, unless the terms "immediately adjacent" or "directly" are used with them.

[0032] When describing temporal relationships, such as when temporal precedence is described as "after", "following", "next", "before", etc., discontinuous or sequential cases may also be included unless "immediately" or "directly" is used.

[0033] As used herein, the terms “connection” and “coupling” are intended to have the broadest possible meaning. Specifically, the phrase “A connects to B (A is connected to B)” includes both direct connection (where there are no intermediate parts or elements) and indirect connection (where there are one or more intermediate parts or elements between A and B). In other words, “A connects to B (A is connected to B)” includes both direct physical or electrical coupling and indirect coupling through one or more intermediate parts. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The terms “coupling” and “contact” should be interpreted in the same way. For example, the term “in contact with” as used herein includes both “indirect contact” and “direct contact.” Therefore, when the phrase “A is in contact with B” is used, it means that there may be other parts between A and B unless explicitly specified as “A is in direct contact with B.”

[0034] Although the terms first, second, etc., are used to describe various components, these components are not substantially limited by these terms. These terms are only used to distinguish one component from another and may not define any order or sequence. Therefore, within the technical spirit of this disclosure, the first component described below can be substantially the second component.

[0035] Features of the various embodiments of this disclosure may be partially or completely combined or integrated with each other, various interlocks and drives are technically possible, and each embodiment may be implemented independently of each other or together in a related relationship.

[0036] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure, and shows a pixel.

[0038] like Figure 1 As shown, in a display device according to an embodiment of the present disclosure, gate line GL and emitter line EL can extend in a first direction X. Data line DL, first power line PL1, second power line PL2, and reference line RL can extend in a second direction Y and can intersect with gate line GL and emitter line EL, thereby defining a plurality of sub-pixels SP. Each sub-pixel SP can be provided with a light-emitting element, a plurality of transistors, and a storage capacitor, which will be described in detail later.

[0039] The gate line GL can transmit the gate signal SCAN, and the emitter line EL can transmit the emit signal EM. The data line DL can transmit the data voltage Vdata, and the reference line RL can transmit the reference voltage Vref. Furthermore, the first power line PL1 can be a high-potential power line transmitting the high-potential voltage VDD, and the second power line PL2 can be a low-potential power line transmitting the low-potential voltage VSS.

[0040] Each sub-pixel SP can be disposed between a gate line GL and an emitter line EL in the second direction Y. For example, the gate line GL can be disposed at the lower part of each sub-pixel SP, and the emitter line EL can be disposed at the upper part of each sub-pixel SP. However, the embodiments of this disclosure are not limited thereto, and the arrangement of the gate line GL and the emitter line EL can be varied.

[0041] In the first direction X, a reference line RL can be positioned between two first power lines PL1, and a second power line PL2 can be positioned between the first power line PL1 and the reference line RL. A data line DL can be positioned between the first power line PL1 and the second power line PL2, and also between the second power line PL2 and the reference line RL. That is, one of the first power line PL1, the second power line PL2, and the reference line RL can be positioned between two adjacent data lines DL.

[0042] Here, the distance between the data line DL and the second power line PL2 can be greater than the distance between the data line DL and the first power line PL1 or the distance between the data line DL and the reference line RL. Each sub-pixel SP can be set between the data line DL and the second power line PL2.

[0043] The data line DL may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. The first data line DL1 may be positioned between a first power line PL1 and a second power line PL2. The second data line DL2 may be positioned between the second power line PL2 and a reference line RL. The third data line DL3 may be positioned between the reference line RL and another second power line PL2. The fourth data line DL4 may be positioned between another second power line PL2 and another first power line PL1.

[0044] Furthermore, the auxiliary power line PLA and the auxiliary reference line RLa can extend in the first direction X. The gate line GL and the emitter line EL can be disposed between the auxiliary power line PLA and the auxiliary reference line RLa. In this case, the auxiliary power line PLA can be disposed adjacent to the emitter line EL, and the auxiliary reference line RLa can be disposed adjacent to the gate line GL. However, the embodiments of this disclosure are not limited thereto, and the arrangement of the auxiliary power line PLA and the auxiliary reference line RLa can be varied.

[0045] The auxiliary power line PLA can cross and overlap with the first data line DL1, the second data line DL2, the third data line DL3 and the fourth data line DL4, the first power line PL1, the second power line PL2 and the reference line RL, and can be connected to the first power line PL1 to supply a high potential voltage VDD to each sub-pixel SP.

[0046] The auxiliary reference line RLa can intersect and overlap with the second data line DL2 and the third data line DL3, the second power line PL2, and the reference line RL, and can be connected to the reference line RL to supply a reference voltage Vref to each sub-pixel SP. The auxiliary reference line RLa can be spaced apart from the first data line DL1 and the fourth data line DL4, as well as the first power line PL1.

[0047] Each subpixel SP can have a substantially rectangular shape. However, embodiments of this disclosure are not limited thereto, and the shape of each subpixel SP can vary.

[0048] Multiple subpixels SP can constitute a pixel. For example, a pixel may include a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4. The first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4 may be arranged sequentially in a first direction X. Here, the first subpixel SP1 and the second subpixel SP2 may be red subpixels, the third subpixel SP3 may be a green subpixel, and the fourth subpixel SP4 may be a blue subpixel. However, embodiments of this disclosure are not limited thereto, and the number and arrangement of subpixels SP in a pixel may vary.

[0049] Two adjacent sub-pixels SP in the first direction X can be symmetrical. For example, the first sub-pixel SP1 and the second sub-pixel SP2 can be symmetrical with respect to the reference line RL with respect to the third sub-pixel SP3 and the fourth sub-pixel SP4. The first sub-pixel SP1 can be symmetrical with respect to the second power line PL2 with respect to the second sub-pixel SP2, and the third sub-pixel SP3 can be symmetrical with respect to the other second power line PL2 with respect to the fourth sub-pixel SP4.

[0050] The structure of the sub-pixels of the display device according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0051] Figure 2 This is an equivalent circuit diagram of a sub-pixel of a display device according to a first embodiment of the present disclosure, and will be referred to together with it. Figure 1 Describe it.

[0052] exist Figure 2In the first embodiment of the display device according to this disclosure, a sub-pixel SP may include a switching transistor ST, a driving transistor DT, a sensing transistor NT, a storage capacitor Cst, and a light-emitting diode LD. The sub-pixel SP may have a basic configuration of a 3T1C structure including three transistors and one storage capacitor, but embodiments of this disclosure are not limited thereto. The number of transistors and capacitors can vary. Furthermore, the sub-pixel SP may also include an emitting transistor ET and a connecting transistor CT.

[0053] For example, the switching transistor ST, driving transistor DT, sensing transistor NT, emitter transistor ET, and connection transistor CT can be n-type transistors. However, embodiments of this disclosure are not limited thereto. In other embodiments, the switching transistor ST, driving transistor DT, sensing transistor NT, emitter transistor ET, and connection transistor CT can be p-type transistors.

[0054] The switching transistor ST can be switched according to the gate signal SCAN and can transmit the data voltage Vdata to the first node N1. Specifically, the gate of the switching transistor ST can be connected to the gate line GL and can be supplied with the gate signal SCAN. The source of the switching transistor ST can be connected to the data line DL and can be supplied with the data voltage Vdata. The drain of the switching transistor ST can be connected to the first node N1.

[0055] The driving transistor DT can be switched according to the voltage of the first node N1, and can transfer a high-potential voltage VDD to the second node N2. Specifically, the gate of the driving transistor DT can be connected to the first node N1. The drain of the driving transistor DT can be connected to the first power supply line PL1 and can be supplied with a high-potential voltage VDD. The source of the driving transistor DT can be connected to the second node N2.

[0056] The sensing transistor NT can be switched according to the gate signal SCAN, and can transfer the reference voltage Vref to the second node N2, or transfer the voltage of the second node N2 to the reference line RL. Specifically, the gate of the sensing transistor NT can be connected to the gate line GL and can be supplied with the gate signal SCAN. The source of the sensing transistor NT can be connected to the reference line RL and can be supplied with the reference voltage Vref, or transfer the voltage of the second node N2 to the reference line RL. The drain of the sensing transistor NT can be connected to the second node N2.

[0057] The storage capacitor Cst can hold the data voltage Vdata supplied to the first node N1 for one frame and can store the threshold voltage Vth of the driving transistor DT. The first and second capacitor electrodes of the storage capacitor Cst can be connected to the first node N1 and the second node N2, respectively.

[0058] A light-emitting diode (LD) can emit light with a brightness proportional to the current driving the transistor DT. Specifically, the anode of the LD can be connected to the second node N2, and the cathode of the LD can be connected to the third node N3.

[0059] Furthermore, the emitter transistor ET can be switched according to the emitter signal EM and can transmit a low-potential voltage VSS to the third node N3. Specifically, the gate of the emitter transistor ET can be connected to the emitter line EL and can be supplied with the emitter signal EM. The source of the emitter transistor ET can be connected to the second power line PL2 and can be supplied with a low-potential voltage VSS. The drain of the emitter transistor ET can be connected to the third node N3.

[0060] The connecting transistor CT can be a connecting element used to connect the third node N3 and the first power supply line PL1, and can be a diode-type transistor in which the gate and drain are connected. The connecting transistor CT can be switched according to a high-potential voltage VDD, and can transmit the high-potential voltage VDD to the third node N3. Specifically, the gate and drain of the connecting transistor CT can be connected to the first power supply line PL1, and can be supplied with a high-potential voltage VDD. The source of the connecting transistor CT can be connected to the third node N3.

[0061] The gate of the driving transistor DT, the drain of the switching transistor ST, and the first capacitor electrode of the storage capacitor Cst can form the first node N1. The source of the driving transistor DT, the drain of the sensing transistor NT, the second capacitor electrode of the storage capacitor Cst, and the anode of the light-emitting diode LD can form the second node N2. The cathode of the light-emitting element LD, the drain of the emitting transistor ET, and the source of the connecting transistor CT can form the third node N3.

[0062] Therefore, in the display device according to the first embodiment of this disclosure, by providing a connecting transistor CT as a connecting element and forming a voltage path, the cathode voltage of the light-emitting diode LD, i.e., the voltage of the third node N3, can be controlled. Thus, it is possible to prevent the light-emitting diode LD from emitting light in a black state.

[0063] Reference Figure 3 The driving operation of the display device according to the first embodiment of the present disclosure is described.

[0064] Figure 3 This is a timing diagram for driving a plurality of signals and a plurality of node voltages of a display device according to a first embodiment of the present disclosure, and will be referred to together with the above. Figure 2 Describe it.

[0065] like Figure 3As shown, in a display device according to a first embodiment of the present disclosure, a frame may include a first segment TP1, a second segment TP2, a third segment TP3, and a fourth segment TP4.

[0066] The first segment TP1 can be a write segment. In the first segment TP1, the gate signal SCAN can be high and the transmit signal EM can be low.

[0067] Therefore, the switching transistor ST and the sensing transistor NT can be turned on, and the emitting transistor ET can be turned off, so that the data voltage Vdata and the reference voltage Vref can be stored in the storage capacitor Cst.

[0068] Here, the first node N1 can be charged with the data voltage Vdata, the second node N2 can be charged with the reference voltage Vref, and the third node N3 can be charged with the high potential voltage VDD.

[0069] In this configuration, the voltage Vn2 at the second node N2 can be lower than the voltage Vn3 at the third node N3, and a reverse bias voltage can be applied to the LED LD. Therefore, no current Ioff can flow through the LED LD, and the LED LD can remain off.

[0070] Next, the second section TP2 can be a stabilization section. In the second section TP2, the gate signal SCAN and the transmit signal EM can be at a low level.

[0071] Therefore, the switching transistor ST, the sensing transistor NT, and the emitter transistor ET can be turned off, allowing the first node N1 and the second node N2 to float. Charge can accumulate in the second node N2 through the current flowing through the driving transistor DT, thus increasing the voltage Vn2 of the second node N2.

[0072] In this scenario, the increased voltage Vn2 of the second node N2 can be lower than the voltage Vn3 of the third node N3, which is charged with a high potential voltage VDD, and a reverse bias voltage can be applied to the LED LD. Therefore, no current Ioff can flow through the LED LD, and the LED LD may not emit light.

[0073] Next, the third segment TP3 can be the transmit segment. In the third segment TP3, the gate signal SCAN can be low, and the transmit signal EM can be high.

[0074] Therefore, the switching transistor ST and the sensing transistor NT can be turned off, and the emitting transistor ET can be turned on, so that the third node N3 can be charged with a low potential voltage VSS.

[0075] In this case, the voltage Vn3 of the third node N3, charged with a low potential voltage VSS, can be lower than the voltage Vn2 of the second node N2, and a forward bias voltage can be applied to the LED LD. Therefore, current Ion can flow through the LED LD, and the LED LD can emit light.

[0076] Next, the fourth segment TP4 can be a non-emitting segment. In the fourth segment TP4, the gate signal SCAN and the emit signal EM can be at a low level.

[0077] Therefore, the switching transistor ST, the sensing transistor NT, and the emitter transistor ET can be turned off, allowing the first node N1 and the second node N2 to float. Charge can accumulate in the second node N2 through the current flowing through the driving transistor DT, thus increasing the voltage Vn2 of the second node N2. This increase in voltage Vn2 can continue until the driving transistor DT is turned off.

[0078] In this configuration, the third node N3 can be charged with a high potential voltage VDD. The increased voltage Vn2 of the second node N2 can be lower than or equal to the voltage Vn3 of the third node N3. Therefore, a reverse bias voltage or no bias voltage can be applied to the LED LD, so that no current Ioff can flow through the LED LD, and the LED LD can not emit light.

[0079] Therefore, in the display device according to the first embodiment of this disclosure, by making the voltage Vn3 of the third node N3, which is the voltage of the cathode of the light-emitting diode LD, higher than or equal to the voltage Vn2 of the second node N2, it is possible to prevent the light-emitting diode LD from emitting light in the first segment TP1, the second segment TP2, and the fourth segment TP4, other than the third segment TP3, which is the emitting segment. Therefore, by preventing light emission in a black state, the contrast of the display device can be improved, and the image quality of the display device can be improved.

[0080] Reference Figure 4 The planar configuration of a display device according to a first embodiment of the present disclosure is described.

[0081] Figure 4 This is a schematic plan view of a display device according to a first embodiment of the present disclosure, and shows a sub-pixel corresponding to Figure 1 Area A1.

[0082] exist Figure 4In the first direction X, the gate line GL and the emitter line EL can intersect with the first power line PL1, the second power line PL2, and the data line DL in the second direction Y to define the sub-pixel SP. A switching transistor ST, a driving transistor DT, a sensing transistor NT, an emitter transistor ET, a connecting transistor CT, a storage capacitor Cst, and a light-emitting diode LD can be disposed in the sub-pixel SP.

[0083] In the first direction X, the driving transistor DT and the emitting transistor ET can be arranged adjacent to each other, and the switching transistor ST and the sensing transistor NT can be arranged adjacent to each other.

[0084] In the second direction Y, the storage capacitor Cst can be disposed between the driving transistor DT and the emitter transistor ET and the switching transistor ST and the sensing transistor NT, and the connecting transistor CT can be disposed between the driving transistor DT and the emitter transistor ET and the emitter line EL.

[0085] Meanwhile, the light-emitting diode (LD) can be stacked with the driving transistor (DT).

[0086] Reference Figure 5 A detailed description of the cross-sectional configuration of the display device according to a first embodiment of the present disclosure.

[0087] Figure 5 This is a schematic cross-sectional view of a display device according to a first embodiment of the present disclosure, and shows a sub-pixel.

[0088] exist Figure 5 According to a first embodiment of the present disclosure, the display device may include a first transistor 121, a second transistor 122, a third transistor 123, and a fourth transistor 124, a capacitor 125, and a light-emitting element 140 on a substrate 110. The light-emitting element 140 may be electrically connected to the first transistor 121 and the second transistor 122. The first transistor 121 may be electrically connected to the capacitor 125 and the third transistor 123, and also electrically connected to the fourth transistor 124. The second transistor 122 may be electrically connected to the fourth transistor 124.

[0089] Specifically, a buffer layer 111 may be provided on the substrate 110. The substrate 110 may be a glass substrate or a plastic substrate. For example, polyimide may be used for plastic substrates, but the embodiments of this disclosure are not limited thereto.

[0090] The buffer layer 111 can be disposed substantially over the entire substrate 110. The buffer layer 111 can be formed as a single layer or multiple layers of inorganic insulating material. For example, the inorganic insulating material of the buffer layer 111 may include silicon nitride (SiNxx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0091] Meanwhile, although not shown in the figure, a light-shielding layer can be provided between the substrate 110 and the buffer layer 111. The light-shielding layer can overlap with the first transistor 121.

[0092] The first, second, third, and fourth active layers 121a, 122a, 123a, and 124a may be disposed on the buffer layer 111. Each of the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a may include a channel region at its central portion and source and drain regions on both sides of the channel region. The first, second, third, and fourth active layers 121a, 122a, 123a, and 124a may be formed of an oxide semiconductor material. Alternatively, the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a may be formed of polysilicon, and in this case, the ends of each of the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a may be doped with impurities.

[0093] A gate insulating layer 112 may be disposed on the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a and the buffer layer 111. The gate insulating layer 112 may be disposed substantially over the entire substrate 110. The gate insulating layer 112 may be formed as a single layer or multiple layers of inorganic insulating material. For example, the inorganic insulating material of the gate insulating layer 112 may include silicon nitride (SiNxx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0094] First, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g, as well as a first capacitor electrode 125a, can be formed on the gate insulating layer 112. The first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g can overlap with the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a, respectively. The first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g can be configured to correspond to the central portions of the first, second, third, and fourth active layers 121a, 122a, 123a, and 124a, respectively.

[0095] The first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g, and the first capacitor electrode 125a, can be formed of a conductive material such as a metal. For example, the first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g, and the first capacitor electrode 125a, can be formed of one or more of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and their alloys. The first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g, and the first capacitor electrode 125a, can have a single-layer structure or a multi-layer structure.

[0096] An interlayer insulating layer 113 may be disposed on the first, second, third, and fourth gate electrodes 121g, 122g, 123g, and 124g, and the first capacitor electrode 125a. The interlayer insulating layer 113 may be disposed substantially over the entire substrate 110. The interlayer insulating layer 113 may be formed as a single layer or multiple layers of inorganic insulating material. For example, the inorganic insulating material of the interlayer insulating layer 113 may include silicon nitride (SiNxx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0097] First, second, third and fourth source electrodes 121s, 122s, 123s and 124s, first, second, third and fourth drain electrodes 121d, 122d, 123d and 124d, second capacitor electrode 125b, first line 127, second line 128 and third line 129 can be provided on the interlayer insulating layer 113.

[0098] The first, second, third, and fourth source electrodes 121s, 122s, 123s, and 124s, the first, second, third, and fourth drain electrodes 121d, 122d, 123d, and 124d, the second capacitor electrode 125b, the first line 127, the second line 128, and the third line 129 can be formed of a conductive material such as a metal. For example, the first, second, third, and fourth source electrodes 121s, 122s, 123s, and 124s, the first, second, third, and fourth drain electrodes 121d, 122d, 123d, and 124d, the second capacitor electrode 125b, the first line 127, the second line 128, and the third line 129 can be formed of one or more of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and their alloys. The first, second, third and fourth source electrodes 121s, 122s, 123s and 124s, the first, second, third and fourth drain electrodes 121d, 122d, 123d and 124d, the second capacitor electrode 125b, the first line 127, the second line 128 and the third line 129 may have a single-layer structure or a multi-layer structure.

[0099] The first source electrode 121s and the first drain electrode 121d can contact the two ends of the first active layer 121a through contact holes respectively provided in the gate insulating layer 112 and the interlayer insulating layer 113. The second source electrode 122s and the second drain electrode 122d can contact the two ends of the second active layer 122a through contact holes respectively provided in the gate insulating layer 112 and the interlayer insulating layer 113. The third source electrode 123s and the third drain electrode 123d can contact the two ends of the third active layer 123a through contact holes respectively provided in the gate insulating layer 112 and the interlayer insulating layer 113. Furthermore, the fourth source electrode 124s and the fourth drain electrode 124d can contact the two ends of the fourth active layer 124a through contact holes respectively provided in the gate insulating layer 112 and the interlayer insulating layer 113, and the fourth drain electrode 124d can contact the fourth gate electrode 124g through a contact hole provided in the interlayer insulating layer 113. The second capacitor electrode 125b can overlap with the first capacitor electrode 125a.

[0100] The first source electrode 121s can be connected to the second capacitor electrode 125b, and the first drain electrode 121d can be connected to the second line 128. The second source electrode 122s can be connected to the third line 129, and the second drain electrode 122d can be connected to the fourth source electrode 124s. The third source electrode 123s can be connected to the first line 127, and the third drain electrode 123d can be connected to the first capacitor electrode 125a through a contact hole provided in the gate insulating layer 112. The fourth source electrode 124s can be connected to the second drain electrode 122d, and the fourth drain electrode 124d can be connected to the second line 128.

[0101] A first active layer 121a, a first gate electrode 121g, a first source electrode 121s, and a first drain electrode 121d can constitute a first transistor 121. A second active layer 122a, a second gate electrode 122g, a second source electrode 122s, and a second drain electrode 122d can constitute a second transistor 122. A third active layer 123a, a third gate electrode 123g, a third source electrode 123s, and a third drain electrode 123d can constitute a third transistor 123. A fourth active layer 124a, a fourth gate electrode 124g, a fourth source electrode 124s, and a fourth drain electrode 124d can constitute a fourth transistor 124.

[0102] The first capacitor electrode 125a and the second capacitor electrode 125b can form a capacitor 125, wherein an interlayer insulating layer 113 is inserted therebetween as a dielectric.

[0103] The first transistor 121 can be Figure 2 The driving transistor DT, the second transistor 122 can be Figure 2 The emitter transistor ET, and the third transistor 123 can be Figure 2 The switching transistor ST, the fourth transistor 124 can be the connecting transistor CT, and the capacitor 125 can be the storage capacitor Cst.

[0104] Additionally, the first line 127 could be Figure 4 The data cable DL, the second cable 128 can be Figure 4 The first power supply line PL1 supplies the high potential voltage VDD, and the third line 129 can be... Figure 4 The second power line PL2 supplies a low-potential voltage VSS. However, embodiments of this disclosure are not limited thereto. In other embodiments, the second line 128 may be a first power line PL1 supplying a low-potential voltage VSS, and the third line 129 may be a second power line PL2 supplying a high-potential voltage VDD.

[0105] at the same time, Figure 2 The sensing transistor NT can also be disposed on the substrate 110, and can have a transistor that is substantially the same as the first transistor 121, the second transistor 122 and the third transistor 123.

[0106] Next, a first passivation layer 114 may be provided on the first, second, third, and fourth source electrodes 121s, 122s, 123s, and 124s, the first, second, third, and fourth drain electrodes 121d, 122d, 123d, and 124d, the second capacitor electrode 125b, the first line 127, the second line 128, and the third line 129. The first passivation layer 114 may be substantially disposed over the entire substrate 110. The first passivation layer 114 may be formed as a single layer or multiple layers of inorganic insulating material. For example, the inorganic insulating material of the first passivation layer 114 may include silicon nitride (SiNxx), silicon oxide (SiOx), or silicon oxynitride (SiON). The first passivation layer 114 may be omitted.

[0107] An outer coating 115 may be disposed on the first passivation layer 114. The outer coating 115 may be disposed substantially over the entire substrate 110. The outer coating 115 may eliminate step differences caused by the underlying layer and may have a substantially flat top surface. The outer coating 115 may be formed of an organic insulating material such as photopolymer (photoacryl).

[0108] The reflective electrode 132 and the connecting electrode 134 can be disposed on the outer coating 115. The reflective electrode 132 and the connecting electrode 134 can be formed of a metal with relatively high reflectivity. For example, the reflective electrode 132 and the connecting electrode 134 can be formed of aluminum (Al), silver (Ag) or chromium (Cr).

[0109] The reflective electrode 132 may partially overlap with the first transistor 121 and the capacitor 125. The reflective electrode 132 may be electrically connected to the first transistor 121 and the capacitor 125 through contact holes disposed in the first passivation layer 114 and the outer coating layer 115. In this case, the reflective electrode 132 may contact the second capacitor electrode 125b through the contact holes, but embodiments of this disclosure are not limited thereto. Alternatively, the reflective electrode 132 may contact the first source electrode 121s.

[0110] The connection electrode 134 may partially overlap with the second transistor 122 and the fourth transistor 124. The connection electrode 134 may be electrically connected to the second transistor 122 and the fourth transistor 124 through contact holes disposed in the first passivation layer 114 and the outer coating layer 115. In this case, the connection electrode 134 may contact the second drain electrode 122d through the contact holes, but embodiments of this disclosure are not limited thereto. Alternatively, the connection electrode 134 may contact the fourth source electrode 124s.

[0111] The second passivation layer 116 can be disposed on the reflective electrode 132 and the connecting electrode 134. The second passivation layer 116 can be disposed substantially over the entire substrate 110. The second passivation layer 116 can be formed as a single layer or multiple layers of inorganic insulating material. For example, the inorganic insulating material of the second passivation layer 116 may include silicon nitride (SiNxx), silicon oxide (SiOx), or silicon oxynitride (SiON). The second passivation layer 116 can be omitted.

[0112] The adhesive layer 117 can be disposed on the second passivation layer 116. The adhesive layer 117 can be disposed substantially on the entire substrate 110 and can fix the light-emitting element 140 transferred thereon.

[0113] The adhesive layer 117 may have a substantially flat top surface. The adhesive layer 117 may be formed of an organic insulating material, such as a photocurable adhesive that is photocurable and can have adhesive properties. For example, the adhesive layer 117 may be formed of a photosensitive propylene polymer (photopolymer). However, the embodiments of this disclosure are not limited thereto. Alternatively, the adhesive layer 117 may be formed of one of a polyimide (PI) resin, an epoxy resin, a polyurethane resin, and a polydimethylsiloxane (PDMS) resin.

[0114] The light-emitting element 140 may be disposed on the adhesive layer 117. The light-emitting element 140 may overlap with the reflective electrode 132. In addition, the light-emitting element 140 may partially overlap with the first transistor 121 and the capacitor 125.

[0115] The light-emitting element 140 may be provided in the form of a micro LED chip (or μLED chip) comprising an n-electrode, an n-type layer, an active layer, a p-type layer, and a p-electrode. The light-emitting element 140 may have a lateral structure in which the n-electrode and the p-electrode are disposed on the same side (e.g., the side opposite to the side facing the substrate 110), and light is emitted through the same side where the n-electrode and the p-electrode are disposed.

[0116] However, the embodiments disclosed herein are not limited thereto. In other embodiments, the light-emitting element 140 may have a flip-chip structure, wherein the n-electrode and the p-electrode are disposed on the same side (e.g., the side facing the substrate 110), and light is emitted via the opposite side to the side where the n-electrode and the p-electrode are disposed, or the light-emitting element 140 may have a vertical structure, wherein the n-electrode and the p-electrode are disposed on opposite sides.

[0117] The light-emitting element 140 can be Figure 2 The light-emitting diode (LD) may include a first element electrode 141, a second element electrode 142, light-emitting structures 143, 144 and 145, and a protective layer 146.

[0118] The first element electrode 141 and the second element electrode 142 can be disposed on the light-emitting structures 143, 144, and 145, and can be spaced apart from each other. The first element electrode 141 and the second element electrode 142 can be disposed at different heights. For example, the second element electrode 142 can be disposed higher than the first element electrode 141.

[0119] The first element electrode 141 may be disposed on the opposite side of the second element electrode 142. That is, the second element electrode 142 may be disposed between the two portions of the first element electrode 141. In this case, the first element electrode 141 may surround the second element electrode 142. However, the embodiments of this disclosure are not limited thereto. In other embodiments, the first element electrode 141 may be disposed on one side of the second element electrode 142.

[0120] Here, the first element electrode 141 can be an n-electrode, and the second element electrode 142 can be a p-electrode. The first element electrode 141 can be a cathode, and the second element electrode 142 can be an anode.

[0121] However, the embodiments disclosed herein are not limited thereto. Alternatively, in other embodiments, the first element electrode 141 may be a p electrode, and the second element electrode 142 may be an n electrode.

[0122] The first element electrode 141 and the second element electrode 142 may be formed of a conductive material. For example, the first element electrode 141 and the second element electrode 142 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, the embodiments of this disclosure are not limited thereto.

[0123] The light-emitting structures 143, 144, and 145 may include a first element layer 143, a light-emitting layer 144, and a second element layer 145. The light-emitting layer 144 may be disposed between the first element layer 143 and the second element layer 145.

[0124] The light-emitting layer 144 and the second element layer 145 may be disposed on the first element layer 143 and may correspond to the central portion of the first element layer 143. The light-emitting layer 144 and the second element layer 145 may have a width and area smaller than that of the first element layer 143 to partially expose the top surface of the first element layer 143. The first element electrode 141 may be disposed on the exposed top surface of the first element layer 143, and the second element electrode 142 may be disposed on the second element layer 145.

[0125] The first element layer 143 and the second element layer 145 can be formed by doping an n-type or p-type impurity into a semiconductor material. For example, the first element layer 143 and the second element layer 145 can be formed by doping an n-type or p-type impurity into gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). Furthermore, for example, the n-type impurity can be silicon (Si), germanium (Ge), or indium (Sn), and the p-type impurity can be magnesium (Mg), zinc (Zn), or beryllium (Be). However, the embodiments of this disclosure are not limited thereto.

[0126] The light-emitting layer 144 can receive electrons and holes from the first element layer 143 and the second element layer 145, respectively, and emit light. The light-emitting layer 144 can be formed of a single quantum well (SQW) structure or a multi-quantum well (MQW) structure. For example, the light-emitting layer 144 can be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0127] The protective layer 146 may be provided with a first element electrode 141, a second element electrode 142, and light-emitting structures 143, 144, and 145. The protective layer 146 may cover and protect the first element electrode 141, the second element electrode 142, and the light-emitting structures 143, 144, and 145, and may partially expose the top surfaces of the first element electrode 141 and the second element electrode 142.

[0128] The protective layer 146 can be formed as a single layer or multiple layers of inorganic insulating material. The inorganic insulating material of the protective layer 146 may include silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0129] Next, a planarization layer 118 can be disposed on the light-emitting element 140 and the adhesive layer 117. The planarization layer 118 can be disposed substantially over the entire substrate 110.

[0130] The planarization layer 118 may surround a portion of the side surface of the light-emitting element 140 and may fix and protect the light-emitting element 140. The thickness of the planarization layer 118 may be less than the thickness of the light-emitting element 140 and may also be less than the thickness of the first element layer 143. The top surface of the planarization layer 118 may be configured to be lower than the first element electrode 141 and the second element electrode 142, thereby exposing the first element electrode 141 and the second element electrode 142.

[0131] For example, the planarization layer 118 can be formed of an organic insulating material such as a photosensitive propylene polymer (photopropylene) and can have a substantially flat top surface.

[0132] The first contact electrode 152 and the second contact electrode 154 can be disposed on the planarization layer 118 and the light-emitting element 140.

[0133] The first contact electrode 152 can overlap with and contact the second element electrode 142 of the light-emitting element 140. In addition, the first contact electrode 152 can overlap with the reflective electrode 132, and can contact and be electrically connected to the reflective electrode 132 through contact holes provided in the second passivation layer 116, adhesive layer 117 and planarization layer 118.

[0134] Therefore, the first contact electrode 152 can be electrically connected to the first source electrode 121s of the first transistor 121 and the second capacitor electrode 125b of the capacitor 125 via the reflective electrode 132. The second element electrode 142 of the light-emitting element 140 can be electrically connected to the first source electrode 121s of the first transistor 121 and the second capacitor electrode 125b of the capacitor 125 via the first contact electrode 152 and the reflective electrode 132.

[0135] The second contact electrode 154 can overlap with and contact the first element electrode 141 of the light-emitting element 140. In addition, the second contact electrode 154 can overlap with the connecting electrode 134, and can contact and be electrically connected to the connecting electrode 134 through contact holes provided in the second passivation layer 116, adhesive layer 117 and planarization layer 118.

[0136] Therefore, the second contact electrode 154 can be electrically connected to the second drain electrode 122d of the second transistor 122 and the fourth source electrode 124s of the fourth transistor 124 via the connection electrode 134. The first element electrode 141 of the light-emitting element 140 can be electrically connected to the second drain electrode 122d of the second transistor 122 and the fourth source electrode 124s of the fourth transistor 124 via the second contact electrode 154 and the connection electrode 134.

[0137] The first contact electrode 152 and the second contact electrode 154 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first contact electrode 152 and the second contact electrode 154 may be formed of a metal, and may be formed of one or more of, for example, aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and their alloys.

[0138] Thus, the display device according to the first embodiment of this disclosure may include a fourth transistor 124 as a connecting element. Since the fourth transistor 124 has a substantially the same structure as the first transistor 121, the second transistor 122 and the third transistor 123 and is substantially on the same plane as the first transistor 121, the second transistor 122 and the third transistor 123, the connecting element can be easily formed without additional processes.

[0139] By placing the connecting elements on a different plane than the first transistor 121, the second transistor 122, and the third transistor 123, the design area of ​​the pixel circuit can be ensured.

[0140] Reference Figures 6 to 8 A display device according to a second embodiment of the present disclosure is described. Except for the connecting elements, the display device according to the second embodiment of the present disclosure has a construction that is substantially the same as or similar to that of the first embodiment. Components identical to those in the first embodiment are indicated by the same or similar reference numerals, and explanations of identical components may be shortened or omitted.

[0141] Figure 6 This is an equivalent circuit diagram of a sub-pixel of a display device according to a second embodiment of the present disclosure, and will be referred to together with it. Figure 1 Describe it.

[0142] exist Figure 6 In the second embodiment of the display device according to this disclosure, a sub-pixel SP may include a switching transistor ST, a driving transistor DT, a sensing transistor NT, a storage capacitor Cst, and a light-emitting diode LD. Furthermore, the sub-pixel SP may also include an emitting transistor ET and a connecting diode CD.

[0143] The switching transistor ST can be switched according to the gate signal SCAN and can transmit the data voltage Vdata to the first node N1. The driving transistor DT is connected to the first node N1 and the second node N2. The driving transistor DT can be switched according to the voltage of the first node N1 and can transmit the high potential voltage VDD to the second node N2. The sensing transistor NT can be switched according to the gate signal SCAN and can transmit the reference voltage Vref to the second node N2, or transmit the voltage of the second node N2 to the reference line RL. The first and second capacitor electrodes of the storage capacitor Cst can be connected to the first node N1 and the second node N2, respectively. The anode of the light-emitting diode LD can be connected to the second node N2, and the cathode of the light-emitting diode LD can be connected to the third node N3.

[0144] The connecting diode CD can be a connecting element used to connect the third node N3 and the first power line PL1, and can transmit the high-potential voltage VDD to the third node N3. Specifically, the anode of the connecting diode CD can be connected to the first power line PL1 and can be supplied with a high-potential voltage VDD. The cathode of the connecting diode CD can be connected to the third node N3.

[0145] Connecting diode CD can be with Figure 2 The connection transistor CT is the same. The connection diode CD can be an organic diode based on organic materials, which will be described in detail later.

[0146] Therefore, in the display device according to the second embodiment of this disclosure, by providing a connecting diode CD as a connecting element and forming a voltage path, the cathode voltage of the light-emitting diode LD, i.e., the voltage of the third node N3, can be controlled. Thus, it is possible to prevent the light-emitting diode LD from emitting light in a black state.

[0147] Reference Figure 7 The planar configuration of a display device according to a second embodiment of the present disclosure is described.

[0148] Figure 7 This is a schematic plan view of a display device according to a second embodiment of the present disclosure, and shows a sub-pixel corresponding to Figure 1 Area A1.

[0149] exist Figure 7 In the first direction X, the gate line GL and the emitter line EL can intersect with the first power line PL1, the second power line PL2, and the data line DL in the second direction Y to define the sub-pixel SP. A switching transistor ST, a driving transistor DT, a sensing transistor NT, an emitter transistor ET, a connecting diode CD, a storage capacitor Cst, and a light-emitting diode LD can be disposed in the sub-pixel SP.

[0150] In the first direction X, the driving transistor DT and the connecting diode CD can be arranged to be adjacent to the emitting transistor ET, and the switching transistor ST and the sensing transistor NT can be arranged to be adjacent to each other.

[0151] In the second direction Y, the storage capacitor Cst can be positioned between the driving transistor DT and the emitter transistor ET, and between the switching transistor ST and the sensing transistor NT, and the connecting diode CD can be positioned substantially between the driving transistor DT and the emitter line EL. In this case, the connecting diode CD can partially overlap with the driving transistor DT.

[0152] Meanwhile, the light-emitting diode (LD) can be configured to overlap with the driving transistor (DT).

[0153] The display device including a connected diode CD according to the second embodiment of the present disclosure can be used with the display device including a connected transistor CT according to the first embodiment of the present disclosure. Figure 4 The display device operates in the same manner as the display device according to the first embodiment, and the width and area of ​​the driving transistor DT and the emitting transistor ET can be increased compared to the display device according to the first embodiment.

[0154] Reference Figure 8 The cross-sectional configuration of the display device according to the second embodiment of the present disclosure is described in detail.

[0155] Figure 8 This is a schematic cross-sectional view of a display device according to a second embodiment of the present disclosure, showing a sub-pixel.

[0156] exist Figure 8 According to a second embodiment of this disclosure, the display device may include a first transistor 121, a second transistor 122, and a third transistor 123, a capacitor 125, an organic diode 260, and a light-emitting element 140 on a substrate 110. The light-emitting element 140 may be electrically connected to the first transistor 121 and the second transistor 122. The first transistor 121 may be electrically connected to the capacitor 125 and the third transistor 123, and also electrically connected to the organic diode 260. The second transistor 122 may be electrically connected to the organic diode 260.

[0157] In other words, in the display device according to the second embodiment of this disclosure, the following can be omitted. Figure 5 The fourth transistor 124.

[0158] Specifically, the first transistor 121, the second transistor 122, the third transistor 123, and the capacitor 125 can be disposed on the substrate 110. The first passivation layer 114 and the outer coating layer 115 can be sequentially disposed on the first transistor 121, the second transistor 122, the third transistor 123, and the capacitor 125.

[0159] Next, a reflective electrode 132 and a connecting electrode 134 can be disposed on the outer coating 115. The reflective electrode 132 and the connecting electrode 134 can be formed of a metal with relatively high reflectivity. For example, the reflective electrode 132 and the connecting electrode 134 can be formed of aluminum (Al), silver (Ag), or chromium (Cr).

[0160] The reflective electrode 132 can be electrically connected to the first transistor 121 and the capacitor 125, and the connecting electrode 134 can be electrically connected to the second transistor 122. In addition, the reflective electrode 132 is disposed between the first transistor 121 and the light-emitting element 140.

[0161] Furthermore, the first electrode 262 may be disposed on the outer coating 115. The first electrode 262 may include the same material as the reflective electrode 132 and the connecting electrode 134 and be disposed on the same layer as the reflective electrode 132 and the connecting electrode 134.

[0162] The first electrode 262 may partially overlap with the first transistor 121 and may be electrically connected to the first transistor 121 through contact holes provided in the first passivation layer 114 and the outer coating layer 115. In this case, the first electrode 262 may contact the first drain electrode 121d of the first transistor 121 through the contact holes.

[0163] The second passivation layer 116 can be disposed on the reflective electrode 132, the connecting electrode 134, and the first electrode 262. An adhesive layer 117 can be disposed on the second passivation layer 116. A light-emitting element 140 can be disposed on the adhesive layer 117. The light-emitting element 140 can be spaced apart from the first electrode 262.

[0164] Next, the planarization layer 118 can be disposed on the light-emitting element 140 and the adhesive layer 117.

[0165] The planarization layer 118 may have an opening that exposes a first electrode 262 having a second passivation layer 116 and an adhesive layer 117. A first semiconductor layer 264 and a second semiconductor layer 266 may be sequentially disposed on the first electrode 262 exposed through the opening.

[0166] At least one of the first semiconductor layer 264 and the second semiconductor layer 266 may comprise an organic material and may be formed by a solvent-based process. That is, at least one of the first semiconductor layer 264 and the second semiconductor layer 266 may be an organic layer. The height of the first semiconductor layer 264 and the second semiconductor layer 266 may increase from the center to the edge.

[0167] However, the embodiments disclosed herein are not limited thereto. In other embodiments, at least one of the first semiconductor layer 264 and the second semiconductor layer 266 may comprise an inorganic material and may be formed by inkjet or vacuum deposition processes.

[0168] The first semiconductor layer 264 may be a p-type semiconductor layer, and the second semiconductor layer 266 may be an n-type semiconductor layer. The first semiconductor layer 264 may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). The second semiconductor layer 266 may include at least one of an electron injection layer (EIL) and an electron transport layer (ETL).

[0169] However, the embodiments disclosed herein are not limited thereto. In other embodiments, the first semiconductor layer 264 may be an n-type semiconductor layer, and the second semiconductor layer 266 may be a p-type semiconductor layer.

[0170] The first contact electrode 152 and the second contact electrode 154 can be disposed on the planarization layer 118 and the light-emitting element 140. The first contact electrode 152 can be connected to the second element electrode 142 of the light-emitting element 140. The second contact electrode 154 can be connected to the first element electrode 141 of the light-emitting element 140. However, the embodiments of this disclosure are not limited thereto. In other embodiments, the first contact electrode 152 can be connected to the first element electrode 141 of the light-emitting element 140, and the second contact electrode 154 can be connected to the second element electrode 142 of the light-emitting element 140.

[0171] Meanwhile, the second electrode 268 can be disposed on the second semiconductor layer 266. The second electrode 268 may include the same material as the first contact electrode 152 and the second contact electrode 154 and be disposed on the same layer as the first contact electrode 152 and the second contact electrode 154. In this case, the second electrode 268 can be connected to the second contact electrode 154 and can be integrally formed with the second contact electrode 154.

[0172] The second electrode 268 can be electrically connected to the connection electrode 134 via the second contact electrode 154, and is also electrically connected to the second drain electrode 122d of the second transistor 122 via the second contact electrode 154 and the connection electrode 134. Furthermore, the second electrode 268 can be electrically connected to the first element electrode 141 of the light-emitting element 140.

[0173] The first electrode 262, the first semiconductor layer 264, the second semiconductor layer 266, and the second electrode 268 can constitute an organic diode 260, and the organic diode 260 can be... Figure 6The diode CD is connected. In this case, the first electrode 262 can be the anode, and the second electrode 268 can be the cathode. However, embodiments of this disclosure are not limited thereto. In other embodiments, the first electrode 262 can be the cathode, and the second electrode 268 can be the anode.

[0174] The first transistor 121 can be Figure 6 The driving transistor DT, the second transistor 122 can be Figure 6 The emitter transistor ET, and the third transistor 123 can be Figure 6 The switching transistor ST, and the capacitor 125 can be the storage capacitor Cst.

[0175] Therefore, the display device according to the second embodiment of this disclosure may include an organic diode 260 as a connection element. Since the organic diode 260 can be disposed on a different plane from the first transistor 121, the second transistor 122 and the third transistor 123, the area of ​​the first transistor 121 and the second transistor 122 (i.e., the driving transistor DT and the emitting transistor ET) can be increased, and it can be applied to a high-resolution display device.

[0176] Furthermore, by increasing the channel width of the drive transistor DT and the emitter transistor ET, the drive current can be increased at lower voltages, thereby reducing power consumption and shortening the on-off time of the drive and emitter transistors.

[0177] By providing connecting electrodes and forming a voltage path, the display device of this disclosure can adjust the cathode voltage of the light-emitting element. This prevents the light-emitting element from emitting light in a black state, thereby improving the image quality of the display device.

[0178] Furthermore, by providing organic diodes as connecting elements on a different plane than the transistor, the width and area of ​​the transistor can be increased, allowing the display device of this disclosure to be applied to high-resolution display devices. The drive current can be increased at lower voltages, thereby reducing power consumption and achieving low power consumption.

[0179] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device of this disclosure without departing from the technical concept or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: substrate; A first transistor located above the substrate and connected to a first power line; A second transistor located above the substrate and connected to a second power line; A light-emitting element connected to the first transistor and the second transistor; as well as A connecting element that connects to the first power line and the light-emitting element. The connecting element overlaps with at least a portion of the first transistor.

2. The display device according to claim 1, wherein, The connecting element includes a first electrode and a second electrode, and The first electrode of the connecting element is connected to the first power line, and the second electrode of the connecting element is connected to the cathode of the light-emitting element.

3. The display device according to claim 2, wherein, The drain of the first transistor is connected to the first power supply line, and the source of the first transistor is connected to the anode of the light-emitting element. The drain of the second transistor is connected to the cathode of the light-emitting element, and the source of the second transistor is connected to the second power supply line.

4. The display device according to claim 2, wherein, The first electrode is electrically connected to the drain of the first transistor, and the second electrode is electrically connected to the drain of the second transistor.

5. The display device according to claim 2, wherein, The connecting element further includes a first semiconductor layer and a second semiconductor layer between the first electrode and the second electrode, and Wherein, one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer.

6. The display device according to claim 5, wherein, The connecting element is an organic diode comprising an organic material, wherein at least one of the first semiconductor layer and the second semiconductor layer is an organic diode.

7. The display device according to claim 6, wherein, The height of the first semiconductor layer and the second semiconductor layer increases from the center to the edge.

8. The display device according to claim 2, further comprising a reflective electrode between the first transistor and the light-emitting element. in, The first electrode comprises the same material as the reflective electrode and is disposed on the same layer as the reflective electrode.

9. The display device according to claim 8, further comprising: The first contact electrode is connected to the first element electrode of the light-emitting element; as well as The second contact electrode is connected to the second element electrode of the light-emitting element. The second electrode comprises the same material as the first contact electrode and the second contact electrode and is disposed on the same layer as the first contact electrode and the second contact electrode.

10. The display device of claim 1, further comprising an outer coating between the first transistor and the second transistor and the connecting element.

11. The display device according to claim 1, further comprising: Switching is performed based on the gate signal, and the data voltage is transmitted to the third transistor of the first node; Switching is performed according to the gate signal and the reference voltage is transmitted to the second node or the voltage of the second node is transmitted to the fourth transistor of the reference line; as well as The capacitors connected to the first node and the second node, The first transistor is connected to the first node and the second node, and the light-emitting element is connected to the second node.

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