Display device and electronic device

Abstract

A display device and an electronic device are disclosed. The display device includes a back plate including a first back plate layer including a first base and a switching transistor disposed on the first base, and a second back plate layer including a second base and a driving transistor disposed on the second base, and a light emitting element layer disposed on the back plate and including a light emitting element electrically connected to the driving transistor.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0177737, filed on December 3, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to a display device and an electronic device. Background Technology

[0003] With the development of the information society, the demand for display devices used to display images has increased and diversified. Therefore, various types of display devices, including light-emitting display devices, have been developed. A light-emitting display device may include a backplane containing pixel circuitry and a light-emitting element layer containing light-emitting elements. Summary of the Invention

[0004] The disclosed aspect provides a display device and electronic device that can reduce power consumption.

[0005] However, the disclosure is not limited to those described herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art by referring to the detailed description of the disclosure given below.

[0006] According to the disclosed aspects, a display device is provided, the display device comprising: a backplane including a first backplane layer and a second backplane layer, the first backplane layer including a first substrate and a switching transistor disposed on the first substrate, the second backplane layer including a second substrate and a driving transistor disposed on the second substrate; and a light-emitting element layer disposed on the backplane and including a light-emitting element electrically connected to the driving transistor.

[0007] In an embodiment, the switching transistor may be a thin-film transistor formed on a first substrate, and the driving transistor may be a metal-oxide-semiconductor field-effect transistor formed on a second substrate.

[0008] In an embodiment, the first substrate and the second substrate may be made of different materials.

[0009] In an embodiment, the first substrate may be an insulating substrate, and the second substrate may be a semiconductor substrate.

[0010] In an embodiment, the first backsheet layer may further include a capacitor disposed on the first substrate.

[0011] In an embodiment, the first backplane layer may further include a connection electrode disposed on the first substrate and electrically connected to the switching transistor, and the connection electrode may be exposed on the upper surface of the first backplane layer.

[0012] In an embodiment, the second backplane layer may further include a first contact terminal and a second contact terminal disposed on the second substrate and electrically connected to the source region and drain region of the driving transistor, respectively.

[0013] In one embodiment, the second backsheet layer may be disposed on the first backsheet layer, and the light-emitting element layer may be disposed on the second backsheet layer.

[0014] In an embodiment, one of the first contact terminal and the second contact terminal may be electrically connected to the connecting electrode, and the other of the first contact terminal and the second contact terminal may be electrically connected to the light-emitting element.

[0015] In an embodiment, the backplane may further include a line layer disposed between the second backplane layer and the light-emitting element layer, and the line layer may include a conductive pattern that electrically connects the driving transistor to the light-emitting element and the switching transistor.

[0016] In an embodiment, the light-emitting element layer may further include a pixel electrode disposed on a backplane and electrically connected to a driving transistor, and the light-emitting element may be disposed on the pixel electrode.

[0017] In one embodiment, the light-emitting element may be connected to the pixel electrode.

[0018] In an embodiment, the light-emitting element may be a micro-light-emitting diode comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed on a pixel electrode.

[0019] In an embodiment, the display device may further include pixels comprising a switching transistor, a driving transistor, and a light-emitting element, wherein the light-emitting element layer may further include a common electrode disposed on the light-emitting element.

[0020] According to the disclosed aspects, a display device is provided, the display device comprising: a first backplane layer including an insulating substrate and a thin-film transistor formed on the insulating substrate; a second backplane layer disposed on the first backplane layer and including a semiconductor substrate and a metal-oxide-semiconductor field-effect transistor formed on the semiconductor substrate; and a light-emitting element layer disposed on the second backplane layer and including a light-emitting element.

[0021] In an embodiment, the first backplane layer may further include a connection electrode electrically connected between the thin-film transistor and the metal-oxide-semiconductor field-effect transistor.

[0022] In an embodiment, the display device may further include a line layer disposed between the second backplane layer and the light-emitting element layer, and the line layer may include a conductive pattern electrically connected between the metal-oxide-semiconductor field-effect transistor and the light-emitting element.

[0023] In an embodiment, the light-emitting element layer may further include pixel electrodes disposed on the line layer, and the light-emitting element may be disposed on the pixel electrode.

[0024] In an embodiment, the display device may further include a pixel comprising a thin-film transistor, a metal-oxide-semiconductor field-effect transistor, and a light-emitting element. The thin-film transistor may be a switching transistor of the pixel, and the metal-oxide-semiconductor field-effect transistor may be a driving transistor of the pixel.

[0025] According to the disclosed aspects, an electronic device is provided, comprising: a display module including a display panel; and a processor for transmitting image data signals to the display module. The display panel may include: a backplane including a first backplane layer and a second backplane layer, the first backplane layer including a first substrate and a switching transistor disposed on the first substrate, the second backplane layer including a second substrate and a driving transistor disposed on the second substrate; and a light-emitting element layer disposed on the backplane and including a light-emitting element electrically connected to the driving transistor.

[0026] The display device according to an embodiment may include a backplane comprising a first backplane layer and a second backplane layer, the first backplane layer including a switching transistor and the second backplane layer including a driving transistor. In some embodiments, the switching transistor may be a thin-film transistor and the driving transistor may be a metal-oxide-semiconductor field-effect transistor.

[0027] According to an embodiment, by forming the switching transistor and the driving transistor separately in the first backplane layer and the second backplane layer, the integration density of the backplane can be reduced and a high-resolution display device can be easily manufactured. Furthermore, by forming the driving transistor as a metal-oxide-semiconductor field-effect transistor, the power consumption of the display device can be reduced.

[0028] However, the effects of the disclosed embodiments are not limited to those illustrated above, and various other effects are included herein. Attached Figure Description

[0029] The above and other aspects and features of the disclosure will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 This is a schematic perspective view showing a display device according to an embodiment; Figure 2 This is a schematic diagram illustrating the pixels of a display device according to an embodiment; Figure 3 This is a schematic plan view showing the display area of ​​a display device according to an embodiment; Figure 4 This is a schematic cross-sectional view showing the display panel of the display device according to an embodiment; Figure 5This is a schematic cross-sectional view showing the display area of ​​a display device according to an embodiment; Figure 6 This is a schematic cross-sectional view showing the pixels of a display device according to an embodiment; Figure 7 This is a schematic diagram illustrating a smartwatch including a display device according to an embodiment; Figure 8 and Figure 9 This is a schematic diagram illustrating a head-mounted display device including a display device according to an embodiment; Figure 10 This is a schematic diagram illustrating a head-mounted display device including a display device according to an embodiment; Figure 11 This is a schematic diagram illustrating a vehicle dashboard and a central dashboard including a display device according to an embodiment; Figure 12 This is a schematic diagram illustrating a transparent display device including a display apparatus according to an embodiment; and Figure 13 This is a block diagram of an electronic device according to a disclosed embodiment. Detailed Implementation

[0030] The invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0031] It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on said other element or layer, or an intervening layer may also be present. Throughout the specification, the same reference numerals denote the same components.

[0032] It will be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0033] Features of each of the various disclosed embodiments may be combined with each other in part or in whole, and may interact with each other technically differently, and the corresponding embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0034] Specific embodiments will now be described with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic perspective view showing a display device according to an embodiment.

[0036] Reference Figure 1 The display device 10 can be a device for displaying moving or still images and can be used as a display screen for various electronic devices. For example, the display device 10 can be included in various electronic products (such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices) and portable electronic devices (such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) and used as a display screen for electronic devices. For example, the display device 10 can also be included in other electronic devices such as virtual reality (VR) devices or augmented reality (AR) devices.

[0037] In an embodiment, the display device 10 may be a light-emitting display device that includes a light-emitting element. For example, the display device 10 may be an organic light-emitting display device that includes an organic light-emitting diode, a quantum dot light-emitting display device that includes a quantum dot light-emitting layer, an inorganic light-emitting display device that includes an inorganic semiconductor, or a micro light-emitting display device that includes a micro light-emitting diode such as a micro LED or a nano LED.

[0038] In the following description, an embodiment of the display device 10, comprising micro-light-emitting diodes (micro-LEDs) or nano-light-emitting diodes (nano-LEDs), will be described. However, the display device 10 according to the embodiment is not limited to a light-emitting display device, and the technical features of the embodiment described below can be applied to other types of display devices.

[0039] The display device 10 may include a display panel 100 comprising a display area DA and a non-display area NDA. In an embodiment, the display panel 100 may have a quadrilateral shape in a plan view, but the embodiment is not limited to this. For example, the display panel 100 may also have other polygonal shapes, circular shapes, elliptical shapes, or irregular shapes in a plan view besides quadrilateral shapes.

[0040] exist Figure 1 In the diagram, a first direction DR1, a second direction DR2, and a third direction DR3 are represented. In an embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can be the horizontal direction, the vertical direction, and the thickness direction of the display panel 100, respectively.

[0041] The display area DA can be an area where pixels PX are set, and can be an area where images are displayed by pixels PX. For example, pixels PX and lines (or portions of lines) connected to pixels PX can be set in the display area DA. In describing embodiments, the term "connection" can include the meaning of electrical connection and / or physical connection. Figure 1 The illustration shows an embodiment in which the display area DA has a quadrilateral shape in a plan view, but the shape of the display area DA is not limited to this.

[0042] Each pixel PX can emit light of a specific color. For example, each pixel PX can emit red, green, blue, white, or another color of light.

[0043] In an embodiment, each of the pixels PX may include a light-emitting element. For example, each pixel PX may include a light-emitting element that emits red, green, blue, white, or another color of light.

[0044] In one embodiment, each of the pixels PX may include a light-emitting element that emits light of the same color as the emission color of the corresponding pixel PX. In another embodiment, at least one pixel PX may include a light-emitting element that emits light of a different color than the emission color of the corresponding pixel PX, and a color filter or light conversion layer corresponding to the emission color of the corresponding pixel PX may be disposed on the light-emitting element.

[0045] In this embodiment, the light-emitting element of each pixel PX can be a light-emitting diode (LED). As an example, each pixel PX may include a microLED or nanoLED having dimensions in the range of micrometers to nanometers. As an example, the light-emitting element may be a microLED having a lateral length, longitudinal length, diameter, or height of several hundred micrometers (e.g., about 100 μm or less), but the embodiment is not limited thereto. The light-emitting element may emit light with a peak wavelength in a specific band. As an example, the light-emitting element may emit light with a peak wavelength in the red, green, or blue bands.

[0046] In an embodiment, each pixel PX may further include a pixel circuit electrically connected to a light-emitting element. Each pixel circuit may supply a drive current to the light-emitting element in response to a drive signal supplied to the corresponding pixel PX. The pixel circuit may include circuit elements containing transistors.

[0047] The non-display area NDA can be an area other than the display area DA, and the non-display area NDA can be an area where no image is displayed. The non-display area NDA can be set around the display area DA. As an example, the non-display area NDA can be set at the edge of the display panel 100 to surround the display area DA.

[0048] In an embodiment, the non-display area NDA may include a first pad (or "solder pad") area PDA1, a second pad area PDA2, and a peripheral area PHA. Lines connected to pixels PX (e.g., portions of lines extending from the display area DA to the non-display area NDA) and pads PD may be disposed in the non-display area NDA.

[0049] Already Figure 1 The illustration shows an embodiment of a display device 10 including a first pad region PDA1 and a second pad region PDA2 respectively disposed on different sides (e.g., the upper side and the lower side) of the display area DA, but the number or position of the pad regions PDA1 and PDA2 is not limited thereto. As an example, the display device 10 may also include only one of the first pad region PDA1 and the second pad region PDA2, or include three or more pad regions.

[0050] Each of the first pad region PDA1 and the second pad region PDA2 may include a pad PD connected to an external circuit board. The drive signal and drive voltage for driving the pixel PX can be supplied from the external circuit board to the display device 10 through the pad PD.

[0051] The peripheral area PHA can be the remaining area of ​​the non-display area NDA, excluding the first pad area PDA1 and the second pad area PDA2. The peripheral area PHA can surround the display area DA. Lines connecting the display driver and / or pads PD and pixels PX (e.g., signal lines and power lines that transmit corresponding drive signals and drive voltages to pixels PX) can pass through the peripheral area PHA.

[0052] In an embodiment, the peripheral region PHA may include a common voltage supply region. As an example, a common electrode disposed in the display region DA may extend to the peripheral region PHA and may be connected to a power line that transmits a common voltage (e.g., a second driving voltage supplied to the pixel PX) in the peripheral region PHA.

[0053] The peripheral region PHA may or may not include a driving circuit region. For example, the peripheral region PHA may also include a driving circuit region having at least a portion of a display driver electrically connected to the pixel PX, but the embodiments are not limited thereto. As an example, each of the gate driver and the data driver including the scan driver may be disposed in the peripheral region PHA of the display panel 100 and electrically connected to the pixel PX via the line of the display panel 100, or may be disposed on a circuit board or the like outside the display panel 100 and electrically connected to the pixel PX via the pad PD and the line of the display panel 100.

[0054] Figure 2 This is a schematic diagram illustrating pixels of a display device according to an embodiment. For example, in Figure 2The diagram schematically shows the inclusion of Figure 1 The structure of the pixel PX in the display device 10.

[0055] exist Figure 2 The illustration shows an embodiment where the display device 10 is a light-emitting display device and therefore the pixel PX includes a light-emitting element LE. However, the embodiment is not limited to this, and the type and structure of the display device 10 and the pixel PX included in the display device 10 can be varied according to the embodiment.

[0056] Reference Figure 2 A pixel (PX) can include pixel circuitry (PXC) and a light-emitting element (LE). This is already... Figure 2 The diagram illustrates a structure where the pixel circuit PXC is connected between the first power line VDL and the light-emitting element LE, but the embodiment is not limited to this. For example, the pixel circuit PXC can also be connected between the light-emitting element LE and the second power line VSL.

[0057] Pixels PX can include pixel circuits PXC with various structures or shapes. Therefore, already... Figure 2 The pixel circuit PXC is briefly shown in block shape. Figure 2 The diagram shows a scan line SL for transmitting scan signals, a data line DL for transmitting data signals, a first power line VDL for transmitting a first drive voltage VDD (e.g., a high-potential pixel voltage or anode voltage), and a second power line VSL for transmitting a second drive voltage VSS (e.g., a low-potential common voltage or cathode voltage) connected to... Figure 2 Examples of signal lines and power lines for a pixel PX are provided, but the embodiment is not limited thereto. For example, the type, number, etc., of the signal lines and / or power lines connected to each pixel PX can be varied depending on the construction of the pixel circuit PXC, etc.

[0058] The pixel circuit PXC can supply a drive current Id to the light-emitting element LE in response to a drive signal (e.g., a scan signal and a data signal) supplied to the pixel PX via corresponding signal lines (e.g., scan line SL and data line DL). The pixel circuit PXC may include circuit elements comprising a drive transistor. For example, the pixel circuit PXC may include a drive transistor, at least one capacitor, and at least one switching transistor. The drive transistor is electrically connected between a first power line VDL and the light-emitting element LE and supplies the drive current Id to the light-emitting element LE. The at least one capacitor includes a storage capacitor storing a voltage corresponding to the data signal. The at least one switching transistor is electrically connected to the drive transistor and the storage capacitor. In embodiments, the pixel circuit PXC may include compensation circuitry for compensating for characteristic deviations between pixels PX; therefore, the pixel circuit PXC may include a switching transistor.

[0059] A light-emitting element (LE) can be connected between the pixel circuit PXC and the second power line VSL. The LE can emit light in response to a drive current Id supplied from the pixel circuit PXC. For example, during the period when the drive current Id is supplied from the pixel circuit PXC, the LE can emit light with a brightness corresponding to the magnitude of the drive current Id.

[0060] Figure 3 This is a schematic plan view showing the display area of ​​a display device according to an embodiment. For example, Figure 3 The setting is shown Figure 1 A schematic shape of pixel PX in a portion of the display area DA.

[0061] Reference Figures 1 to 3 The display panel 100 of the display device 10 may include pixels PX disposed in the display area DA. The pixels PX may be arranged in a stripe shape or other shapes in the display area DA. The arrangement shape, position, size, etc. of the pixels PX may be varied according to the embodiments.

[0062] Each pixel PX can have a quadrilateral shape such as a rectangle, square, or rhombus in the planar view, but the embodiment is not limited to this. For example, each pixel PX can have other polygonal shapes, circular shapes, elliptical shapes, or other shapes in the planar view besides quadrilateral shapes.

[0063] In an embodiment, a pixel PX may include a first pixel PX1 (e.g., a red sub-pixel) emitting light of a first color (e.g., red light), a second pixel PX2 (e.g., a green sub-pixel) emitting light of a second color (e.g., green light), and a third pixel PX3 (e.g., a blue sub-pixel) emitting light of a third color (e.g., blue light). At least one first pixel PX1, at least one second pixel PX2, and at least one third pixel PX3 adjacent to each other can form each unit pixel UPX. As an example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 arranged sequentially along a first direction DR1 can form a unit pixel UPX. The number, type, arrangement, etc., of pixels PX forming each unit pixel UPX can also be varied according to the embodiment.

[0064] Each pixel PX may include a light-emitting element LE. For example, a first pixel PX1 may include a first light-emitting element LE1, a second pixel PX2 may include a second light-emitting element LE2, and a third pixel PX3 may include a third light-emitting element LE3. In an embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of a first color, a second color, and a third color, respectively. As an example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit red light, green light, and blue light, respectively. In another embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may emit light of the same color (e.g., blue light or white light), and a light conversion pattern (e.g., a wavelength conversion pattern including quantum dots) and / or a color filter for converting or controlling the color or wavelength of the light emitted from each light-emitting element LE may be disposed above at least one of the first light-emitting elements LE1, the second light-emitting element LE2, and the third light-emitting element LE3.

[0065] Each light-emitting element LE can have a circular shape in a planar view, but the embodiments are not limited to this. For example, each light-emitting element LE can have a quadrilateral shape (e.g., a rectangular shape, a square shape, or a rhombus shape), an elliptical shape, or other shapes in a planar view.

[0066] Already Figure 3 The illustration shows an embodiment where each pixel PX includes one light-emitting element LE, but the embodiment is not limited thereto. For example, at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may also include multiple light-emitting elements LE.

[0067] For example, it has only been in Figure 3 The diagram shows a light-emitting element LE within the components of a pixel PX, but the pixel PX may also include additional components. For example, the pixel PX may also include... Figure 2 The pixel circuit PXC shown is shown.

[0068] Figure 4 This is a schematic cross-sectional view showing the display panel of a display device according to an embodiment. For example, Figure 4 The illustration schematically shows the display panel 100 in relation to the construction of the display panel 100 according to the embodiment. Figure 1 The cross-section of a portion corresponding to the display area DA.

[0069] Reference Figures 1 to 4 The display panel 100 may include a backplane BPL and a light-emitting element layer EDL disposed on the backplane BPL. The backplane BPL and the light-emitting element layer EDL may be bonded to each other, so that the pixel circuit PXC and the light-emitting element LE of each pixel PX can be electrically connected to each other.

[0070] The backplane BPL may include pixel circuits PXC for each of the pixels PX. For example, the backplane BPL may be disposed in each pixel region of the display area DA and may include circuit elements (e.g., driving transistors, switching transistors, and capacitors) that form the pixel circuits PXC of the corresponding pixel PX.

[0071] The backplane BPL can be disposed over the entire area of ​​the display panel 100, including the display area DA and the non-display area NDA. The backplane BPL may also include lines electrically connected to the pixels PX and / or the pads PD.

[0072] In an embodiment, the backplane BPL may include a first backplane layer GBP and a second backplane layer SBP comprising transistors with different structures and / or different types. For example, the first backplane layer GBP may include a first substrate and a first type of transistor disposed on the first substrate, and the second backplane layer SBP may include a second substrate and a second type of transistor disposed on the second substrate.

[0073] In an embodiment, the backplane BPL may further include a line layer CNL disposed on the second backplane layer SBP. For example, the line layer CNL may be disposed between the second backplane layer SBP and the light-emitting element layer EDL. The line layer CNL may include conductive patterns (or lines) for connecting the second backplane layer SBP and the light-emitting element layer EDL to each other.

[0074] Already Figure 4 The second backplane layer (SBP) and the line layer (CNL) are shown separately, but the embodiments are not limited thereto. For example, the line layer (CNL) may also be included in the second backplane layer (SBP).

[0075] The light-emitting element layer (EDL) may include a light-emitting element (LE) for each of the pixels (PX). For example, the EDL may include a light-emitting element (LE) disposed in each pixel region of the display area (DA) and electrically connected to the pixel circuit PXC of the corresponding pixel (PX).

[0076] In an embodiment, the display panel 100 may further include an optical layer MLA disposed on the light-emitting element layer EDL. The optical layer MLA may include optical elements for improving the optical performance of the display panel 100. For example, the optical layer MLA may include a microlens array comprising microlenses disposed on the light-emitting elements LE of each pixel PX. By disposing the microlens array on the light-emitting element layer EDL, the light emitted from the pixel PX can be effectively controlled and / or dispersed, thereby improving the optical performance of the display panel 100.

[0077] Figure 5 This is a schematic cross-sectional view showing the display area of ​​a display device according to an embodiment. For example, Figure 5 It shows Figure 3and Figure 4 An embodiment of a cross-section of a portion of the display area DA. Figure 5 The cross-section of the first pixel PX1, the second pixel PX2, and the third pixel PX3 located in the unit pixel region UPA is shown as a view of the display panel 100. Figure 3 The cross section corresponding to line X1-X1'.

[0078] Figure 6 This is a schematic cross-sectional view showing the pixels of a display device according to an embodiment. For example, Figure 6 It shows Figure 5 An enlarged cross-section of the first pixel PX1. In an embodiment, the cross-sectional structures of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be substantially the same or similar to each other.

[0079] Apart from Figures 1 to 4 In addition, refer to Figure 5 and Figure 6 A pixel PX may include circuit elements of a pixel circuit PXC disposed in a backplane BPL and light-emitting elements LE disposed in a light-emitting element layer EDL. For example, a pixel PX may include at least one switching transistor SWT, a driving transistor DRT, and a capacitor C disposed in each pixel region of the backplane BPL, and a light-emitting element LE disposed in each pixel region of the light-emitting element layer EDL.

[0080] Already Figure 5 and Figure 6 The illustration shows that each pixel PX includes two switching transistors SWT, comprising a first switching transistor SWT1 and a second switching transistor SWT2, but the embodiment is not limited to this. For example, the number or connection structure of the switching transistors SWT in each pixel PX can be varied depending on the construction of the pixel circuit PXC.

[0081] The pixel region where each pixel PX is set may include the emission region of the light-emitting element LE of the corresponding pixel PX. For example, the first pixel region where the first pixel PX1 is set may include the first emission region EA1 of the light-emitting element LE of the first pixel PX1 (hereinafter referred to as "first light-emitting element LE1"). The second pixel region where the second pixel PX2 is set may include the second emission region EA2 of the light-emitting element LE of the second pixel PX2 (hereinafter referred to as "second light-emitting element LE2"). The third pixel region where the third pixel PX3 is set may include the third emission region EA3 of the light-emitting element LE of the third pixel PX3 (hereinafter referred to as "third light-emitting element LE3").

[0082] For example, each pixel region may also include a pixel circuit region having circuit elements disposed on a pixel circuit PXC connected to a light-emitting element LE of the corresponding pixel PX. The emission region and pixel circuit region of each pixel PX may be stacked on top of each other, but the embodiments are not limited thereto.

[0083] In this embodiment, the switching transistor SWT and driving transistor DRT of pixel PX can be disposed on different substrates. For example, the switching transistor SWT of pixel PX can be disposed on a first substrate GSUB and formed as a first backplane layer GBP, and the driving transistor DRT of pixel PX can be disposed on a second substrate SSUB and formed as a second backplane layer SBP.

[0084] The switching transistors (SWTs) and driving transistors (DRTs) of a pixel PX can be different types of transistors. For example, each of the switching transistors (SWTs) of a pixel PX can be a thin-film transistor (TFT) formed on a first substrate GSUB. For example, each of the driving transistors (DRTs) of a pixel PX can be a metal-oxide-semiconductor field-effect transistor (MOSFET) formed on a second substrate SSUB using semiconductor processes. As an example, MOSFET-type driving transistors (DRTs) can be formed using silicon semiconductor processes. For example, the backplane BPL according to an embodiment can be a hybrid backplane combining TFT-type switching transistors (SWTs) formed on the first substrate GSUB and MOSFET-type driving transistors (DRTs) formed on the second substrate SSUB.

[0085] In embodiments, the first substrate GSUB and the second substrate SSUB can be made of different materials. For example, the first substrate GSUB can be a substrate made of a material suitable for forming TFTs (e.g., a rigid insulating substrate such as a glass substrate), or it can be a flexible insulating substrate comprising a polymer resin such as polyimide. There are no particular limitations on the material or properties of the first substrate GSUB, as long as it is suitable as a substrate component for forming TFTs.

[0086] The second substrate (SSUB) can be a substrate made of a material suitable for forming a MOSFET, such as a semiconductor substrate like a silicon wafer. There are no particular limitations on the material or properties of the second substrate (SSUB), as long as it is suitable as a substrate component for forming a MOS TFT.

[0087] The first backplane layer GBP may include a first substrate GSUB and switching transistors SWT disposed on the first substrate GSUB. In an embodiment, each of the switching transistors SWT may be a TFT, and the first backplane layer GBP may be a thin-film transistor circuit board.

[0088] In an embodiment, the first backplane layer GBP may include circuit elements other than the driving transistor DRT among the circuit elements forming the pixel circuit PXC of each pixel PX. For example, the first backplane layer GBP may include at least one switching transistor SWT included in each pixel PX, such as a first switching transistor SWT1 and a second switching transistor SWT2 for each pixel PX. In an embodiment, at least one of the switching transistors SWT of each pixel PX may be electrically connected to the driving transistor DRT of each pixel PX. For example, the first backplane layer GBP may include a capacitor C (e.g., a storage capacitor) included in each pixel PX. In an embodiment, the capacitor C may be electrically connected to the driving transistor DRT of the corresponding pixel PX. As an example, the capacitor C may be electrically connected to the gate electrode GE of the driving transistor DRT.

[0089] In an embodiment, the first backplane layer GBP may further include connection electrodes (or contact terminals) for electrically connecting the circuit elements in the first backplane layer GBP and the circuit elements in the second backplane layer SBP to each other. As an example, the first backplane layer GBP may further include a first connection electrode CNE1 electrically connected to a first switching transistor SWT1 of each pixel PX and a second connection electrode CNE2 electrically connected to a capacitor C of each pixel PX.

[0090] For example, the first backplane layer GBP may also include an insulating layer. As an example, the first backplane layer GBP may also include a first insulating layer GINS1, a second insulating layer GINS2, a third insulating layer GINS3, and a fourth insulating layer GINS4 sequentially disposed or stacked on the first substrate GSUB.

[0091] Each switching transistor SWT may include an active layer ACT and a gate electrode G. In one embodiment, each switching transistor SWT may further include at least one of a source electrode SE and a drain electrode DE. In another embodiment, at least one switching transistor SWT may not include separate source electrodes SE and drain electrodes DE, and the source region S and drain region D may be connected (e.g., directly connected) to other circuit elements, connection patterns, lines, etc., to serve as source and drain electrodes, respectively. Figure 5 and Figure 6 The illustration shows an embodiment where each of the switching transistors SWT has a top-gate structure, but the embodiment is not limited thereto. For example, at least one switching transistor SWT may also have a bottom-gate structure. Each of the switching transistors SWT may be a P-type transistor or an N-type transistor, and the connection orientation may vary depending on the conductivity type of each of the switching transistors SWT.

[0092] An active layer ACT can be disposed on a first substrate GSUB. As an example, the active layer ACT can be formed (e.g., directly) on the first substrate GSUB, or formed on a buffer layer disposed on the first substrate GSUB. The active layer ACT can include a semiconductor material. For example, the active layer ACT can include amorphous silicon, polycrystalline silicon, or oxide semiconductor. The active layer ACT can include a channel region CHA, a source region S, and a drain region D. The source region S and drain region D can be located on opposite sides of the channel region CHA, respectively. The source region S and drain region D can have a higher conductivity than the channel region CHA.

[0093] The first insulating layer GINS1 can be disposed on the active layer ACT. For example, the first insulating layer GINS1 can cover the first substrate GSUB and the active layer ACT. The first insulating layer GINS1 can include at least one insulating material (e.g., silicon oxide (SiO2)). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), hafnium oxide (HfO) x (or other inorganic insulating materials), and can be formed in single or multiple layers.

[0094] The gate electrode G can be disposed on the first insulating layer GINS1. The gate electrode G may include at least one conductive material and may be formed as a single layer or multiple layers.

[0095] In this embodiment, the first capacitor electrode CE1 may also be disposed on the first insulating layer GINS1. The first capacitor electrode CE1 may form a capacitor C together with the second capacitor electrode CE2. The gate electrode G and the first capacitor electrode CE1 may be formed simultaneously and may have the same conductive material and / or cross-sectional structure.

[0096] The second insulating layer GINS2 can be disposed on the gate electrode G and the first capacitor electrode CE1. For example, the second insulating layer GINS2 can cover the first insulating layer GINS1, the gate electrode G, and the first capacitor electrode CE1. The second insulating layer GINS2 can include at least one insulating material (e.g., an inorganic insulating material) and can be formed as a single layer or multiple layers.

[0097] The source electrode SE and drain electrode DE can be disposed on the second insulating layer GINS2. The source electrode SE can penetrate the first insulating layer GINS1 and the second insulating layer GINS2 and be electrically connected to the source region S. The drain electrode DE can penetrate the first insulating layer GINS1 and the second insulating layer GINS2 and be electrically connected to the drain region D. Each of the source electrode SE and the drain electrode DE can include at least one conductive material and can be formed as a single layer or multiple layers.

[0098] In this embodiment, the second capacitor electrode CE2 may also be disposed on the second insulating layer GINS2. The second capacitor electrode CE2 may be stacked on the third-direction DR3 with the first capacitor electrode CE1. The source electrode SE, the drain electrode DE, and the second capacitor electrode CE2 may be formed simultaneously and may have the same conductive material and / or cross-sectional structure.

[0099] The third insulating layer GINS3 can be disposed on the source electrode SE, the drain electrode DE, and the second capacitor electrode CE2. For example, the third insulating layer GINS3 can cover the second insulating layer GINS2, the source electrode SE, the drain electrode DE, and the second capacitor electrode CE2. The third insulating layer GINS3 can include at least one insulating material (e.g., inorganic insulating material and / or organic insulating material) and can be formed as a single layer or multiple layers.

[0100] The first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed on the third insulating layer GINS3. The first connecting electrode CNE1 may penetrate the third insulating layer GINS3 and be electrically connected to the electrode (e.g., the drain electrode DE) of the first switching transistor SWT1. The second connecting electrode CNE2 may penetrate the third insulating layer GINS3 and be electrically connected to the electrode (e.g., the second capacitor electrode CE2) of the first capacitor C. Each of the first connecting electrode CNE1 and the second connecting electrode CNE2 may include at least one conductive material and may be formed as a single layer or multiple layers.

[0101] A portion of each of the first connecting electrode CNE1 and the second connecting electrode CNE2 may be exposed on the surface of the first backplane layer GBP. As an example, all or a portion of the upper surface of each of the first connecting electrode CNE1 and the second connecting electrode CNE2 may be exposed on the upper surface of the first backplane layer GBP.

[0102] A fourth insulating layer GINS4 may be disposed around the first connecting electrode CNE1 and the second connecting electrode CNE2. For example, the fourth insulating layer GINS4 may be disposed on the third insulating layer GINS3 and may include openings that expose the first connecting electrode CNE1 and the second connecting electrode CNE2. Figure 5 and Figure 6The illustration shows an embodiment in which the first connecting electrode CNE1, the second connecting electrode CNE2, and the fourth insulating layer GINS4 are formed at the same height, but the embodiment is not limited thereto. The fourth insulating layer GINS4 may include at least one insulating material (e.g., an inorganic insulating material and / or an organic insulating material) and may be formed as a single layer or multiple layers.

[0103] In an embodiment, the surface of the first backplane layer GBP can be substantially flat. For example, the upper surface of the first backplane layer GBP, which exposes at least a portion of the first connection electrode CNE1 and the second connection electrode CNE2, as well as the fourth insulating layer GINS4, can be substantially flat. Therefore, the bonding strength between the first backplane layer GBP and the second backplane layer SBP can be increased.

[0104] The second backplane layer (SBP) can be disposed on the first backplane layer (GBP). The second backplane layer (SBP) may include a second substrate (SSUB) and driving transistors (DRTs) disposed on the second substrate (SSUB). Each driving transistor (DRT) can be disposed in each pixel region of the display area (DA). Each driving transistor (DRT) can be electrically connected to the light-emitting element (LE) of the corresponding pixel (PX). In an embodiment, the driving transistor (DRT) may be a MOSFET, and the second backplane layer (SBP) may be a semiconductor circuit board formed using a semiconductor substrate such as a silicon wafer through semiconductor processes.

[0105] In an embodiment, the second backplane layer SBP may further include contact terminals (or lines) electrically connected to circuit elements in the second backplane layer SBP. As an example, the second backplane layer SBP may also include a first contact terminal CT1, a second contact terminal CT2, and a third contact terminal CT3 electrically connected to the driving transistor DRT of each pixel PX.

[0106] The second backsheet layer (SBP) may also include insulating layers. As an example, the second backsheet layer (SBP) may also include a fifth insulating layer (SINS1), a sixth insulating layer (SINS2), and a seventh insulating layer (SINS3) sequentially disposed or stacked on the second substrate (SSUB).

[0107] The second substrate SSUB can be disposed on the first backplane layer GBP. For example, the second substrate SSUB can be disposed on the first connecting electrode CNE1, the second connecting electrode CNE2, and the fourth insulating layer GINS4.

[0108] The second substrate SSUB can be a semiconductor substrate, such as a silicon substrate (e.g., a silicon wafer), a germanium substrate, or a silicon-germanium substrate. The second substrate SSUB can be a substrate doped with a first type of impurity. A well region WA can be disposed in the upper surface of the second substrate SSUB. The well region WA can be a region doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. As an example, if the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. In another example, if the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity. Each of the well regions WA can include a source region SRA corresponding to the source electrode of the driving transistor DRT, a drain region DRA corresponding to the drain electrode of the driving transistor DRT, and a channel region CH disposed between the source region SRA and the drain region DRA.

[0109] The driving transistor DRT may include a source region SRA, a drain region DRA, and a channel region CH disposed in each well region WA, and a gate electrode GE superimposed on the channel region CH. The driving transistor DRT may be a MOSFET-type transistor formed using semiconductor processes and may have the advantage of low power consumption. For example, a driving transistor DRT formed as a MOSFET can have a very small subthreshold swing. Therefore, the voltage applied to the driving transistor DRT can be reduced, and the voltage difference between the first driving voltage VDD and the second driving voltage VSS used to ensure the operating region margin of the driving transistor DRT can be reduced. Therefore, the power consumption of the driving transistor DRT and the display device 10 including the driving transistor DRT can be reduced.

[0110] The bottom insulating film BINS can be disposed between the gate electrode GE and the well region WA. The first side surface insulating film SIL1 can be disposed on the side surface of the gate electrode GE. The first side surface insulating film SIL1 can be disposed on the bottom insulating film BINS.

[0111] Each of the source region SRA and drain region DRA can be a region doped with type I impurities. The gate electrode GE can be stacked on the third-direction DR3 with the well region WA. The channel region CH can be stacked on the third-direction DR3 with the gate electrode GE. The source region SRA can be located on one side of the gate electrode GE, and the drain region DRA can be located on the other side of the gate electrode GE.

[0112] Each of the well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SRA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DRA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SRA due to the bottom insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DRA due to the bottom insulating film BINS. The distance between the source region SRA and the drain region DRA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the driving transistors DRT can be increased, thereby preventing punch-through and hot carrier phenomena caused by short channels.

[0113] The fifth insulating layer, SINS1, can be disposed on the second substrate, SSUB. The fifth insulating layer, SINS1, can be formed as silicon carbonitride (SiCN) or silicon oxide (SiO). x ( ) type inorganic membrane, but the embodiments are not limited to this.

[0114] The sixth insulating layer, SINS2, can be disposed on the fifth insulating layer, SINS1. The sixth insulating layer, SINS2, can be formed as silicon oxide (SiO2). x ( ) type inorganic membrane, but the embodiments are not limited to this.

[0115] The first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3 may be disposed on the sixth insulating layer SINS2. Each of the first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3 may penetrate the fifth insulating layer SINS1 and the sixth insulating layer SINS2, and be electrically connected to any one of the source region SRA, the drain region DRA, and the gate electrode GE of the driving transistor DRT. As an example, the first contact terminal CT1 may be electrically connected to the source region SRA of the driving transistor DRT, the second contact terminal CT2 may be electrically connected to the drain region DRA of the driving transistor DRT, and the third contact terminal CT3 may be electrically connected to the gate electrode GE of the driving transistor DRT.

[0116] Each of the first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3 can be electrically connected to a circuit element (e.g., a first switching transistor SWT1 or a capacitor C) or a light-emitting element LE in the first backplane layer GBP via at least one conductive pattern (or line) disposed in the line layer CNL. For example, one of the first contact terminal CT1 and the second contact terminal CT2 can be electrically connected to the first switching transistor SWT1, and the other of the first contact terminal CT1 and the second contact terminal CT2 can be electrically connected to the light-emitting element LE. The driving transistor DRT can be a P-type transistor or an N-type transistor, and the connection direction of the driving transistor DRT can be changed according to the conductivity type of the driving transistor DRT.

[0117] The driving transistor DRT can be electrically connected between the first switching transistor SWT1 and the light-emitting element LE via conductive patterns. As an example, the first contact terminal CT1 can be electrically connected to the first connection electrode CNE1 via the first conductive pattern ML1, and can be electrically connected to the electrode of the first switching transistor SWT1 (e.g., the drain electrode DE or the source electrode SE) via the first connection electrode CNE1. For example, the second contact terminal CT2 can be electrically connected to the pixel electrode of each pixel PX (e.g., the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3) via the second conductive pattern ML2 and the fourth conductive pattern ML4, and can be electrically connected to the light-emitting element LE via the pixel electrode. In an embodiment, the gate electrode GE of the driving transistor DRT can be electrically connected to the capacitor C. For example, the third contact terminal CT3 can be electrically connected to the second connection electrode CNE2 via the third conductive pattern ML3, and can be electrically connected to the electrode of the capacitor C (e.g., the second capacitor electrode CE2) via the second connection electrode CNE2. Figure 5 and Figure 6 In this context, the third conductive pattern ML3 is positioned on the opposite side of the first conductive pattern ML1. The two patterns ML3A and ML3B can be patterns connected to each other in a planar diagram (e.g., a single pattern).

[0118] Each of the first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3 may include at least one conductive material (e.g., any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd)), and may be formed as a single layer or multiple layers.

[0119] A seventh insulating layer, SINS3, may be disposed on the side surface of each of the first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3. The upper surface (or a portion thereof) of each of the first contact terminal CT1, the second contact terminal CT2, and the third contact terminal CT3 may not be covered by the seventh insulating layer SINS3 and may be exposed on the upper surface of the second backplane layer SBP. The seventh insulating layer SINS3 may be formed as silicon oxide (SiO2). x ( ) type inorganic membrane, but the embodiments are not limited to this.

[0120] A line layer (CNL) (or backplane for light-emitting elements) may include conductive patterns, through electrodes, and insulating layers. As an example, the line layer (CNL) may include a first conductive pattern ML1, a second conductive pattern ML2, a third conductive pattern ML3, a fourth conductive pattern ML4, a first through electrode VA1, a second through electrode VA2, a third through electrode VA3, a fourth through electrode VA4, a fifth through electrode VA5, a sixth through electrode VA6, a seventh through electrode VA7, an eighth insulating layer CINS1, a ninth insulating layer CINS2, and a tenth insulating layer CINS3. Some of the through electrodes may extend through the second backplane layer (SBP).

[0121] The eighth insulating layer CINS1 can be disposed on the second backplane layer SBP. The first conductive pattern ML1, the second conductive pattern ML2, and the third conductive pattern ML3 can be disposed on the eighth insulating layer CINS1.

[0122] The first conductive pattern ML1 can be electrically connected to the first contact terminal CT1 via the first through electrode VA1 that penetrates the eighth insulating layer CINS1. The first conductive pattern ML1 can be electrically connected to the first connecting electrode CNE1 via the second through electrode VA2 that penetrates the second substrate SSUB, the fifth insulating layer SINS1, the sixth insulating layer SINS2, the seventh insulating layer SINS3, and the eighth insulating layer CINS1.

[0123] The second conductive pattern ML2 can be electrically connected to the second contact terminal CT2 through the third through electrode VA3 that penetrates the eighth insulating layer CINS1.

[0124] The third conductive pattern ML3 can be electrically connected to the third contact terminal CT3 via the fourth through electrode VA4, which penetrates the eighth insulating layer CINS1. The third conductive pattern ML3 can also be electrically connected to the second connecting electrode CNE2 via the fifth through electrode VA5, which penetrates the second substrate SSUB, the fifth insulating layer SINS1, the sixth insulating layer SINS2, the seventh insulating layer SINS3, and the eighth insulating layer CINS1. In an embodiment, the second side insulating film SIL2 can be disposed on the side surface of each of the second through electrode VA2 and the fifth through electrode VA5.

[0125] The ninth insulating layer CINS2 can be disposed on the eighth insulating layer CINS1, the first conductive pattern ML1, the second conductive pattern ML2, and the third conductive pattern ML3. The fourth conductive pattern ML4 can be disposed on the ninth insulating layer CINS2.

[0126] The fourth conductive pattern ML4 can be disposed on the ninth insulating layer CINS2. The fourth conductive pattern ML4 can be electrically connected to the second conductive pattern ML2 through the sixth through electrode VA6 that penetrates the ninth insulating layer CINS2. The fourth conductive pattern ML4 can be electrically connected to the light-emitting element LE (or electrically connected to the pixel electrode of the light-emitting element LE) through the seventh through electrode VA7 that penetrates the tenth insulating layer CINS3.

[0127] The tenth insulating layer CINS3 can be disposed on the ninth insulating layer CINS2 and the fourth conductive pattern ML4. The light-emitting element layer EDL can be disposed on the tenth insulating layer CINS3.

[0128] Already Figure 5 and Figure 6 The structure of a line layer CNL is shown in a relatively simple manner, but the embodiments are not limited thereto. As an example, a line layer CNL may also include a greater number of conductive layers and insulating layers. Each of the conductive layers in the line layer CNL may include at least one conductive pattern disposed in each pixel region.

[0129] Each of the conductive patterns (e.g., first conductive pattern ML1, second conductive pattern ML2, third conductive pattern ML3, and fourth conductive pattern ML4) and through electrodes (e.g., first through electrode VA1, second through electrode VA2, third through electrode VA3, fourth through electrode VA4, fifth through electrode VA5, sixth through electrode VA6, and seventh through electrode VA7) of the line layer CNL may include at least one conductive material. As an example, each of the conductive patterns and through electrodes of the line layer CNL may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof. In embodiments, the conductive patterns and through electrodes of the line layer CNL may include the same conductive material, but embodiments are not limited thereto.

[0130] Each of the insulating layers of the line layer CNL (e.g., the eighth insulating layer CINS1, the ninth insulating layer CINS2, and the tenth insulating layer CINS3) may comprise at least one insulating material (e.g., an inorganic or organic insulating material) and may be formed as a single layer or multiple layers. As an example, each of the eighth insulating layer CINS1, the ninth insulating layer CINS2, and the tenth insulating layer CINS3 may be formed as silicon oxide (SiO2). x( ) type inorganic membrane, but the embodiments are not limited to this.

[0131] The light-emitting element layer (EDL) can be disposed on the backplane layer (BPL). As an example, the light-emitting element layer (EDL) can be disposed on the line layer (CNL) (or the second backplane layer (SBP)) of the backplane layer (BPL).

[0132] The light-emitting element layer (EDL) may include pixel electrodes ET1, ET2, and ET3, a light-emitting element (LE), a common electrode (CME), and a passivation layer (PSV). In an embodiment, the light-emitting element layer (EDL) may further include at least one of contact electrodes CTE1 and CTE2 disposed on at least one surface of the light-emitting element (LE), a protective film PRL surrounding the side surface of the light-emitting element (LE), a reflective film RF disposed around the light-emitting element (LE), and an eleventh insulating layer (EINS).

[0133] Pixel electrodes ET1, ET2, and ET3 can be disposed on the backplane BPL. As an example, pixel electrodes ET1, ET2, and ET3 can be disposed on the tenth insulating layer CINS3.

[0134] Pixel electrodes ET1, ET2, and ET3 can be disposed in the corresponding pixel regions where pixels PX are disposed, and can be separate from each other. For example, the pixel electrode of the first pixel PX1 (hereinafter referred to as "first pixel electrode ET1") can be disposed separately in the first pixel region where the first pixel PX1 is disposed, the pixel electrode of the second pixel PX2 (hereinafter referred to as "second pixel electrode ET2") can be disposed separately in the second pixel region where the second pixel PX2 is disposed, and the pixel electrode of the third pixel PX3 (hereinafter referred to as "third pixel electrode ET3") can be disposed separately in the third pixel region where the third pixel PX3 is disposed.

[0135] Each of the pixel electrodes ET1, ET2, and ET3 can be electrically connected to the fourth conductive pattern ML4 via the seventh through electrode VA7, and can be electrically connected to the driving transistor DRT via at least one conductive pattern including the fourth conductive pattern ML4. For example, each of the pixel electrodes ET1, ET2, and ET3 can be electrically connected to the first semiconductor layer SEM1 of the light-emitting element LE via the first contact electrode CTE1.

[0136] For example, the first pixel electrode ET1 can be electrically connected between the fourth conductive pattern ML4 and the first light-emitting element LE1 of the first pixel PX1. The second pixel electrode ET2 can be electrically connected between the fourth conductive pattern ML4 and the second light-emitting element LE2 of the second pixel PX2. The third pixel electrode ET3 can be electrically connected between the fourth conductive pattern ML4 and the third light-emitting element LE3 of the third pixel PX3.

[0137] Pixel electrodes ET1, ET2, and ET3 can physically and / or electrically bond the backplane BPL and the light-emitting element LE to each other. In embodiments, pixel electrodes ET1, ET2, and ET3 can be bonding electrodes (or bonding pads) for stably mounting or bonding the light-emitting element LE to or onto the backplane BPL. As an example, the first pixel electrode ET1 can be a first bonding electrode corresponding to the bonding electrode of the first pixel PX1, the second pixel electrode ET2 can be a second bonding electrode corresponding to the bonding electrode of the second pixel PX2, and the third pixel electrode ET3 can be a third bonding electrode corresponding to the bonding electrode of the third pixel PX3.

[0138] However, the types of pixel electrodes ET1, ET2, and ET3 are not limited to this, and the type, structure, and / or material of pixel electrodes ET1, ET2, and ET3 can be varied depending on the bonding structure, bonding method, etc., between the backplane BPL and the light-emitting element LE. In the following, embodiments of pixel electrodes ET1, ET2, and ET3 as bonding electrodes will be described.

[0139] Each of the pixel electrodes ET1, ET2, and ET3 can be formed as a single layer or multiple layers including a bonding layer BDL (also referred to as a "bonding metal layer"). As an example, each of the pixel electrodes ET1, ET2, and ET3 may include a bonding layer BDL and a reflective layer RFL disposed on the bonding layer BDL.

[0140] The bonding layer (BDL) may include a conductive material suitable for bonding processes. For example, the bonding layer (BDL) may include a metal or metal alloy with excellent electrical and thermal conductivity, or a transparent conductive material capable of undergoing bonding processes. Examples of metals or metal alloys included in the bonding layer (BDL) may include eutectic metals such as gold (Au)-tin (Sn) alloys, titanium (Ti), zirconium (Zr), nickel (Ni), or chromium (Cr). Examples of transparent conductive materials included in the bonding layer (BDL) may include indium tin oxide (ITO), zinc oxide (ZnO), etc. The bonding layer (BDL) may also be made of other conductive materials.

[0141] In embodiments, the bonding layer BDL may have a thickness sufficient to facilitate or readily perform the bonding process. As an example, the bonding layer BDL may have a thickness of several hundred nanometers (nm) (e.g., a thickness in the range of about 200 nm to about 500 nm), but embodiments are not limited thereto.

[0142] The reflective layer RFL can be disposed on the bonding layer BDL. In embodiments, the reflective layer RFL may include a conductive material (e.g., a metal) with high light reflectivity. For example, the reflective layer RFL may include aluminum (Al) or other metals with high light reflectivity (e.g., molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), etc.). In another embodiment, the reflective layer RFL may include a transparent conductive layer used as a distributed Bragg reflector (DBR).

[0143] In an embodiment, the reflective layer RFL can cover (e.g., completely cover) the lower surface of each of the light-emitting elements LE. Therefore, light that has traveled in the downward direction from each of the light-emitting elements LE can be effectively reflected, thereby improving the light efficiency of the light-emitting elements LE and the pixel PX including the light-emitting elements LE.

[0144] In an embodiment, each of the pixel electrodes ET1, ET2, and ET3 may further include a barrier layer covering at least one surface of the bonding layer BDL and the reflective layer RFL. As an example, each of the pixel electrodes ET1, ET2, and ET3 may further include at least one of a first barrier layer covering the lower surface of the bonding layer BDL, a second barrier layer covering the upper surface of the bonding layer BDL and the lower surface of the reflective layer RFL, and a third barrier layer covering the upper surface of the reflective layer RFL.

[0145] The barrier layer may include a material suitable for preventing diffusion (e.g., preventing intermetallic diffusion). For example, the barrier layer may be made of a material capable of ensuring the conductivity of each of the pixel electrodes ET1, ET2, and ET3 and / or formed at a thickness capable of ensuring the conductivity of each of the pixel electrodes ET1, ET2, and ET3. In embodiments, the barrier layer may include a material with a high intermetallic diffusion prevention effect (such as titanium (Ti), titanium nitride (TiN), nickel (Ni), or other diffusion-preventing materials) and may be formed at a thickness less than or equal to the thickness of each of the reflective layer RFL and the bonding layer BDL. For example, the barrier layer may be formed as a thin film comprising a material suitable for preventing metal diffusion included in the bonding layer BDL and / or the reflective layer RFL.

[0146] The light-emitting element LE can be disposed on the pixel electrodes ET1, ET2, and ET3. For example, the light-emitting element LE of each pixel PX can be coupled to (or connected to) the pixel electrode of the corresponding pixel PX.

[0147] In this embodiment, the light-emitting elements (LEs) of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be disposed in the same layer (or at the same level) of the light-emitting element layer EDL. When the light-emitting elements (LEs) of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are disposed in the same layer, the structure of the display panel 100 can be simplified, and the thickness of the display panel 100 can be reduced. However, the embodiment is not limited to this. For example, the light-emitting elements (LEs) of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can also be disposed in different layers of the light-emitting element layer EDL.

[0148] In an embodiment, the first contact electrode CTE1 can be disposed above each of the pixel electrodes ET1, ET2, and ET3, and the light-emitting element LE of each pixel PX can be disposed on the first contact electrode CTE1. The first contact electrode CTE1 has already been... Figure 6 The component is shown as separate from the light-emitting element LE, but the embodiment is not limited thereto. For example, the first contact electrode CTE1 can also be considered as a component included in the light-emitting element LE. The first contact electrode CTE1 can be formed or etched together with the light-emitting element LE, or it can be formed or etched separately from the light-emitting element LE.

[0149] In another embodiment, the light-emitting element LE or pixel PX may not include the first contact electrode CTE1. For example, the light-emitting element LE may be disposed (e.g., directly disposed) on the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3 of each pixel PX.

[0150] Already Figure 5 and Figure 6 The illustration shows a display panel 100 having a structure in which pixel electrodes ET1, ET2, and ET3 are disposed on a backplane BPL and a light-emitting element LE is bonded (or connected) to the backplane BPL via the pixel electrodes ET1, ET2, and ET3. However, the structure of the display panel 100 according to the embodiment is not limited to this. For example, the light-emitting element LE may also be appropriately disposed on the backplane BPL using an adhesive layer, connecting electrodes, wires, etc., without using a bonding method.

[0151] The first contact electrode CTE1 can be disposed on the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3 of each pixel PX. The first contact electrode CTE1 can be disposed on the surface (e.g., the lower surface) of the first semiconductor layer SEM1 included in the light-emitting element LE. The first contact electrode CTE1 can protect the first semiconductor layer SEM1 and smoothly connect the light-emitting element LE to the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3 of each pixel PX.

[0152] The first contact electrode CTE1 may include a metal, a metal oxide, or other conductive material. In an embodiment, the first contact electrode CTE1 may include a transparent conductive material (e.g., ITO, indium zinc oxide (IZO), or other transparent conductive materials), but the embodiment is not limited thereto.

[0153] Each of the light-emitting elements (LEs) can be disposed on the first contact electrode CTE1 (or the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3) of the corresponding pixel PX. Each of the light-emitting elements (LEs) can be electrically connected to the driving transistor DRT of the corresponding pixel PX via the first contact electrode CTE1, the pixel electrode of the corresponding pixel PX (e.g., the first pixel electrode ET1, the second pixel electrode ET2, or the third pixel electrode ET3), etc.

[0154] Each of the light-emitting elements (LEs) may include a first semiconductor layer SEM1, a light-emitting layer EML, and a second semiconductor layer SEM2 sequentially disposed on a first contact electrode CTE1. For example, the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 may be sequentially disposed or stacked on the first contact electrode CTE1 along a third direction DR3. In embodiments, the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 may be formed from a semiconductor epitaxial stack or epitaxial layer formed by epitaxial growth on a growth substrate comprising semiconductor material. As an example, each of the light-emitting elements (LEs) may be a microlight-emitting diode including a first semiconductor layer SEM1, a light-emitting layer EML, and a second semiconductor layer SEM2.

[0155] In one embodiment, the light-emitting element LE can be formed by etching a semiconductor epitaxial stack or epitaxial layer grown on a growth substrate, and can be disposed on or bonded to (or connected to) pixel electrodes ET1, ET2, and ET3 using at least one transfer substrate. In another embodiment, the light-emitting element LE can be formed by disposing or bonding a semiconductor epitaxial stack or epitaxial layer grown on a growth substrate onto a backplane BPL using a wafer-to-wafer bonding process, etc., and then etching the semiconductor epitaxial stack or epitaxial layer. Pixel electrodes ET1, ET2, and ET3 can be etched and separated into individual patterns after the light-emitting element LE is formed or disposed on the backplane BPL, or separated into individual patterns before the light-emitting element LE is formed or disposed on the backplane BPL.

[0156] The first semiconductor layer SEM1 may include a semiconductor material doped with a first type of impurity. For example, the first semiconductor layer SEM1 may include a nitride-based semiconductor material, a phosphide-based semiconductor material, or other semiconductor materials, and may be doped with a first type of impurity. In an embodiment, the first semiconductor layer SEM1 may be a p-type semiconductor layer (e.g., p-GaN) doped with p-type impurities such as Mg, Zn, Ca, or Ba, but the embodiments are not limited thereto.

[0157] The light-emitting layer (EML) can be disposed on the first semiconductor layer (SEM1). For example, the EML can be disposed between the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). The EML can emit light by recombination of electron-hole pairs generated according to the electrical signals applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0158] The light-emitting layer (EML) may include nitride-based semiconductor materials, phosphide-based semiconductor materials, or other semiconductor materials, and may have a single quantum well structure or a multiple quantum well structure. In embodiments, the EML may have a multiple quantum well structure including a quantum well layer containing InGaN and a blocking layer containing GaN, AlGaN, or GaAlN, but the embodiments are not limited thereto. In embodiments where the EML includes InGaN, the color of the light emitted from the EML can be controlled or changed by adjusting the indium (In) content.

[0159] The emissive layer EML can emit light in the visible light band, such as light in the band from about 400 nm to about 900 nm. For example, the emissive layer EML can emit blue light with a peak wavelength in the range of about 440 nm to about 480 nm, green light with a peak wavelength in the range of about 510 nm to about 550 nm, or red light with a peak wavelength in the range of about 610 nm to about 650 nm. As an example, the emissive layer EML of the first emissive element LE1 can emit red light, the emissive layer EML of the second emissive element LE2 can emit green light, and the emissive layer EML of the third emissive element LE3 can emit blue light. However, the embodiments are not limited to this, and the emissive layer EML can also emit light of colors or wavelengths other than those exemplified above.

[0160] The second semiconductor layer SEM2 may include a semiconductor material doped with a second type of impurity. For example, the second semiconductor layer SEM2 may include a nitride-based semiconductor material, a phosphide-based semiconductor material, or other semiconductor materials, and may be doped with a second type of impurity. In an embodiment, the second semiconductor layer SEM2 may be an n-type semiconductor layer doped with an n-type impurity such as Si, Ge, Se, or Sn (e.g., n-GaN), but the embodiments are not limited thereto.

[0161] In this embodiment, the second contact electrode CTE2 can be disposed on each light-emitting element LE, and the common electrode CME can be disposed on the second contact electrode CTE2. For example, the second semiconductor layer SEM2 of the light-emitting element LE can be electrically connected to the common electrode CME through the second contact electrode CTE2.

[0162] The second contact electrode CTE2 is already in place. Figure 6 The component shown is separate from the light-emitting element LE, but the embodiment is not limited thereto. For example, the second contact electrode CTE2 can also be considered as a component included in the light-emitting element LE. The second contact electrode CTE2 can be formed or etched together with the light-emitting element LE, or it can be formed or etched separately from the light-emitting element LE.

[0163] In another embodiment, the light-emitting element LE or pixel PX may not include the second contact electrode CTE2. For example, the common electrode CME may be connected (e.g., directly connected) to or in contact with the light-emitting element LE.

[0164] The second contact electrode CTE2 can be disposed on the surface (e.g., the upper surface) of the second semiconductor layer SEM2. The second contact electrode CTE2 can protect the second semiconductor layer SEM2 and smoothly connect the light-emitting element LE to the common electrode CME.

[0165] The second contact electrode CTE2 may include a metal, a metal oxide, or other conductive material. In an embodiment, the second contact electrode CTE2 may be formed as a transparent electrode layer comprising a transparent conductive material (e.g., ITO, IZO, or other transparent conductive materials). Therefore, light generated from the light-emitting element LE can be transmitted through the second contact electrode CTE2 and emitted onto the upper part of the light-emitting element LE.

[0166] The light-emitting element (LE) can be surrounded by a protective film (PRL), etc. For example, the side surface of each of the light-emitting elements (LE) can be surrounded by a protective film (PRL) and a reflective film (RF).

[0167] The protective film PRL may surround the side surface of the light-emitting element LE. In an embodiment, the protective film PRL may also surround the side surface of at least one of the pixel electrodes ET1, ET2 and ET3, the first contact electrode CTE1 and the second contact electrode CTE2. As an example, the protective film PRL may be disposed (e.g., disposed entirely) in the display area DA to surround the side surfaces of the light-emitting element LE, the pixel electrodes ET1, ET2 and ET3, the first contact electrode CTE1 and the second contact electrode CTE2.

[0168] The protective film PRL may include openings that expose a portion (e.g., the upper surface) of the light-emitting element LE or the second contact electrode CTE2. For example, the protective film PRL may include openings that expose a portion (e.g., a portion of the upper surface) of the light-emitting element LE or the second contact electrode CTE2. In the open portion of the protective film PRL, the light-emitting element LE or the second contact electrode CTE2 may be connected to the common electrode CME.

[0169] The protective film PRL may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ) and hafnium oxide (HfO) x At least one of the insulating materials or other insulating materials. The protective film PRL can protect the light-emitting element LE and increase the electrical stability of the light-emitting element LE.

[0170] The reflective film RF can be disposed on at least a portion of the protective film PRL. For example, the reflective film RF can be disposed on a portion of the side surface of the protective film PRL surrounding each of the light-emitting elements LE.

[0171] The reflective film RF can surround the side surface of each of the light-emitting elements LE. For example, in a plan view, the reflective film RF can surround the light-emitting element LE.

[0172] The reflective film RF can reflect and recycle light generated from each of the light-emitting elements LE and guided in the lateral direction, etc. The luminous efficiency of each of the light-emitting elements LE (e.g., the proportion of light emitted to the upper part of the light-emitting element LE) can be increased by the reflective film RF.

[0173] In one embodiment, the reflective film RF may include a metal with high reflectivity, such as aluminum (Al). In another embodiment, the reflective film RF may include a distributed Bragg reflector. As an example, the reflective film RF may include at least one pair (e.g., two or more pairs) of first and second layers with different refractive indices, arranged alternately or sequentially. One of the first and second layers may be a low-refractive-index layer, and the other of the first and second layers may be a high-refractive-index layer with a higher refractive index than the low-refractive-index layer. Each of the first and second layers may be formed of silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x ), titanium dioxide (Ti x O y ), aluminum oxide (Al) x Oy Inorganic membranes made from materials such as inorganic membranes.

[0174] The eleventh insulating layer (EINS) can be disposed on the protective film (PRL) and the reflective film (RF). The eleventh insulating layer (EINS) can also be disposed around each of the light-emitting elements (LEs). As an example, the eleventh insulating layer (EINS) can also be disposed between the light-emitting elements (LEs).

[0175] In an embodiment, the eleventh insulating layer EINS may be formed at a height greater than or equal to the height of the light-emitting element LE, and may be open above each of the light-emitting elements LE. For example, the eleventh insulating layer EINS may include an opening that exposes a portion of the upper surface of the light-emitting element LE or the second contact electrode CTE2.

[0176] The eleventh insulating layer (EINS) can be formed as a single layer or multiple layers comprising at least one insulating material. As an example, the eleventh insulating layer (EINS) can be composed of silicon oxide (SiO₂). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), hafnium oxide (HfO) x (or other inorganic insulating materials, such as single-layer or multi-layer inorganic films. In another example, the eleventh insulating layer EINS can be an organic film comprising organic insulating materials.)

[0177] The common electrode CME can be disposed on the light-emitting element LE, the second contact electrode CTE2, and the eleventh insulating layer EINS.

[0178] In an embodiment, the common electrode CME may be disposed (e.g., disposed entirely) in the display area DA. For example, the common electrode CME may be a common layer shared by the light-emitting elements LE of the display area DA and the pixels PX including the light-emitting elements LE.

[0179] The common electrode CME can be electrically connected to the light-emitting element LE. For example, an opening can be formed in the protective film PRL and the eleventh insulating layer EINS above each of the light-emitting elements LE, and the common electrode CME can be connected to the second contact electrode CTE2 (or the light-emitting element LE) in the opening.

[0180] In one embodiment, the common electrode CME can be electrically connected to the second contact electrode CTE2, and can be electrically connected to the second semiconductor layer SEM2 of the light-emitting element LE through the second contact electrode CTE2. In another embodiment, the pixel PX may not include the second contact electrode CTE2, and the common electrode CME can contact (e.g., directly contact) the upper surface of the light-emitting element LE and be electrically connected to the second semiconductor layer SEM2 of the light-emitting element LE.

[0181] In an embodiment, the common electrode CME can be electrically connected to power lines formed on the backplane BPL inside and / or outside the display area DA. As an example, the common electrode CME can be electrically connected to power lines formed on the backplane BPL in the peripheral area PHA adjacent to (e.g., immediately adjacent / directly adjacent to) the display area DA. Figure 2 The common electrode CME can receive a second driving voltage VSS from the second electric field line VSL. In one embodiment, the common electrode CME can be used as the cathode electrode for each of the light-emitting elements LE and pixels PX. In another embodiment, the display panel 100 can have a common anode structure, and the common electrode CME can be connected to a first electric field line VDL to which a first driving voltage VDD is applied, and can be used as the anode electrode for each of the light-emitting elements LE and pixels PX. When the display panel 100 has a common anode structure, the conductivity type or position of the first semiconductor layer SEM1 and the second semiconductor layer SEM2 included in the light-emitting element LE can be changed or modified in reverse.

[0182] The common electrode CME can include a conductive material that can transmit light. For example, the common electrode CME can be made of ITO, IZO, or other transparent conductive materials.

[0183] A passivation layer PSV can be disposed on the common electrode CME. In an embodiment, the passivation layer PSV can be disposed (e.g., disposed entirely) in the display area DA to cover the common electrode CME.

[0184] In an embodiment, the upper surface of the passivation layer PSV may be substantially flat. For example, the passivation layer PSV may be made of a material suitable for having a substantially flat upper surface and / or formed at a thickness suitable for having a substantially flat upper surface, or planarized by a planarization process performed after film formation.

[0185] The passivation layer PSV may include at least one insulating material and may have a single-layer or multi-layer structure. In embodiments, the passivation layer PSV may include an inorganic insulating material (e.g., silicon oxide (SiO2)). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), hafnium oxide (HfO) x (or other inorganic insulating materials), but the embodiments are not limited thereto.

[0186] The optical layer MLA can be disposed on the light-emitting element layer EDL. As an example, the optical layer MLA can be disposed on the passivation layer PSV of the light-emitting element layer EDL.

[0187] The optical layer MLA may include lenses LS stacked with each of the light-emitting elements LE. For example, the optical layer MLA may be formed as a microlens array disposed in the emitting regions EA1, EA2, and EA3 of the display region DA.

[0188] In an embodiment, the lens LS may have a size corresponding to the emission area of ​​each pixel PX and may be superimposed (e.g., completely superimposed) with the light-emitting elements LE disposed in each pixel PX. As an example, the lens LS may be a microlens having a size corresponding to the size of each of the light-emitting elements LE. In an embodiment, the lens LS may cover the light-emitting elements LE and their periphery, and may have a size larger than each light-emitting element LE in a planar view. In an embodiment, the lens LS may be a microlens having a convex lens shape disposed above the light-emitting elements LE, but the type, shape, and / or size of the lens LS are not limited thereto.

[0189] The lens LS can be made of a transparent material, allowing light incident from the light-emitting element LE to pass through. The lens LS can be made of a material suitable for appropriately controlling or improving the characteristics of the light emitted from the pixel PX and / or shaped to appropriately control or improve the characteristics of the light emitted from the pixel PX.

[0190] In embodiments, the display panel 100 or the display device 10 including the display panel 100 may further include additional components. As an example, the display panel 100 or the display device 10 including the display panel 100 may further include a light conversion layer, a color filter, etc. disposed above the pixel PX (or light-emitting element LE).

[0191] As described above, the display device 10 according to the embodiment may include a backplane BPL comprising a first backplane layer GBP and a second backplane layer SBP. The first backplane layer GBP includes a first substrate GSUB and a switching transistor SWT, and the second backplane layer SBP includes a second substrate SSUB and a driving transistor DRT. In the embodiment, the switching transistor SWT and the driving transistor DRT may be transistors of different types or structures. For example, the switching transistor SWT may be a TFT formed on an insulating substrate such as a glass substrate or a flexible substrate, and the driving transistor DRT may be a MOSFET formed on a semiconductor substrate such as a silicon wafer (e.g., a MOSFET formed by silicon semiconductor processes).

[0192] According to an embodiment, by separately forming the switching transistor SWT and the driving transistor DRT in the first backplane layer GBP and the second backplane layer SBP respectively, the integration density of the backplane BPL can be reduced and the high-resolution display device 10 can be easily manufactured.

[0193] In some embodiments, the power consumption of the display device 10 can be reduced by forming the driving transistor DRT as a MOSFET. For example, the power consumption of the display device 10 can be significantly reduced by forming the driving transistor DRT of the pixel PX, which accounts for about 20% to about 30% of the total power consumption of the display device 10, as a MOSFET.

[0194] In some embodiments, various types of pixel circuits PXC can be easily formed by forming the switching transistor SWT of the pixel PX as a TFT. For example, the switching transistor SWT included in the pixel circuit PXC can be easily disposed or formed on the first substrate GSUB without incurring additional costs due to structural changes in the pixel circuit PXC.

[0195] The display device 10 according to one disclosed embodiment can be applied to various electronic devices. The electronic device according to the disclosed embodiment includes the above-described display device 10, and may also include modules or devices with additional functions in addition to the display device 10.

[0196] Figure 7 This is a schematic diagram illustrating a smartwatch including a display device according to an embodiment.

[0197] Reference Figure 7 The display device 10_1 according to the embodiment can be applied to a smartwatch 1000_1, which is one of the smart devices. In the embodiment, the display device 10_1 can be a reference... Figures 1 to 6 The described display device 10.

[0198] Figure 8 and Figure 9This is a schematic diagram illustrating a head-mounted display device including a display device according to an embodiment.

[0199] Reference Figure 8 and Figure 9 According to the embodiment, the head-mounted display device 1000_2 can be a virtual reality device. The head-mounted display device 1000_2 may include a first display device 10_2, a second display device 10_3, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0200] The first display device 10_2 can display an image to the user's left eye, and the second display device 10_3 can display an image to the user's right eye. In an embodiment, each of the first display device 10_2 and the second display device 10_3 can be a reference. Figures 1 to 6 The described display device 10.

[0201] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0202] The intermediate frame 1400 can be disposed between the first display device 10_2 and the control circuit board 1600, and between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 can support and fix the first display device 10_2, the second display device 10_3 and the control circuit board 1600.

[0203] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert externally input image sources into video data and transmit the video data to the first display device 10_2 and the second display device 10_3 via connectors.

[0204] The control circuit board 1600 can transmit video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_2, and transmit video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_3. In another example, the control circuit board 1600 can transmit the same video data to both the first display device 10_2 and the second display device 10_3.

[0205] The display device housing 1100 can accommodate a first display device 10_2, a second display device 10_3, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 can cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 have been shown to be configured separately, but the embodiments are not limited to this. The first eyepiece 1210 and the second eyepiece 1220 can be combined into a single eyepiece.

[0206] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical component 1520. Therefore, the user can view the magnified virtual image of the first display device 10_2 through the first optical component 1510 and the first eyepiece 1210, and can view the magnified image of the second display device 10_3 through the second optical component 1520 and the second eyepiece 1220.

[0207] The headband 1300 can secure the display device housing 1100 to the user's head, allowing the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 to remain positioned on the user's left and right eyes, respectively. When the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display device 1000_2 can include, for example... Figure 10 The eyeglasses frame shown is not the headband 1300.

[0208] For example, the head-mounted display device 1000_2 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0209] Figure 10 This is a schematic diagram illustrating a head-mounted display device including a display device according to an embodiment.

[0210] Reference Figure 10The head-mounted display device 1000_3 according to the embodiment can be an eyeglass-type device. The head-mounted display device 1000_3 according to the embodiment may include a display device 10_4, a left eye lens 10a, a right eye lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflective member 40, and a display device housing portion 50.

[0211] exist Figure 10 The head-mounted display device 1000_3 has been shown as an eyeglass-type display device including temples 30a and 30b, but the embodiments are not limited thereto. For example, the head-mounted display device 1000_3 can be used in various forms in other electronic devices.

[0212] The display device housing 50 can accommodate the display device 10_4 and the reflective member 40 (or optical path conversion member). The image displayed on the display device 10_4 can be reflected by the reflective member 40 and provided to the user's right eye through the right eye lens 10b. For example, the user can view an augmented reality image combining a virtual image displayed on the display device 10_4 through his / her right eye and a real image seen through the right eye lens 10b. In an embodiment, the display device housing 50 may include an optical member disposed between the display device 10_4 and the reflective member 40. The image displayed on the display device 10_4 can be magnified by the optical member, converted in the optical path by the reflective member 40, and provided to the user's right eye through the right eye lens 10b.

[0213] exist Figure 10 The display device housing 50 has been shown to be located at the right end of the support frame 20, but the embodiment is not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. For example, the image displayed on the display device 10_4 may be reflected by the reflective member 40 and provided to the user's left eye through the left eye lens 10a. For example, the user may view the image displayed on the display device 10_4 through his / her left eye. In another example, the display device housing 50 may be located at both the left and right ends of the support frame 20. For example, the user may view the image displayed on the display device 10_4 through both his / her left and right eyes. In the embodiment, the display device 10_4 may be a reference Figures 1 to 6 The described display device 10.

[0214] Figure 11 This is a schematic diagram illustrating the dashboard and central dashboard of a vehicle including a display device according to an embodiment. Figure 11 The image shows a vehicle equipped with display devices 10_a, 10_b, 10_c, 10_d and 10_e according to an embodiment.

[0215] Reference Figure 11The display devices 10_a, 10_b, and 10_c according to the embodiments can be applied to a vehicle's dashboard, a vehicle's central dashboard, or a central information display (CID) mounted on a vehicle's instrument panel. For example, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a vehicle. In the embodiments, at least one of the display devices 10_a, 10_b, 10_c, 10_d, and 10_e can be a reference... Figures 1 to 6 The described display device 10.

[0216] Figure 12 This is a schematic diagram illustrating a transparent display device including a display apparatus according to an embodiment.

[0217] Reference Figure 12 The display device 10_5 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user positioned on the front surface of the transparent display device can not only view the image IM displayed on the display device 10_5, but also see the object RS or background positioned on the rear surface of the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion, or may be made of a light-transmitting material. In the embodiment, the display device 10_5 may be a reference... Figures 1 to 6 The described display device 10.

[0218] Figure 13 This is a block diagram of an electronic device according to a disclosed embodiment.

[0219] Reference Figure 13 According to one embodiment of the disclosed electronic device 1, it may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0220] Display module 11 may include a display panel for displaying images. For example, display module 11 may include a display panel 100 according to at least one of the above embodiments.

[0221] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0222] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. The processor 12 can transmit image data signals and / or input control signals stored in the memory 13 to the display module 11. For example, the processor 12 executes an application stored in the memory 13, the image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0223] The power module 14 may include a power supply module (such as a power adapter or battery) and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0224] At least one of the components of the electronic device 1 according to one disclosed embodiment may be included in the display device 10 according to one disclosed embodiment. Some of the modules that are functionally included in a single module may be included in the display device 10, and other modules may be disposed separately from the display device 10. For example, the display device 10 may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed in the electronic device 1 as other devices besides the display device 10.

[0225] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of the invention. Therefore, the disclosed embodiments of the invention are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, the display device comprising: A backplane includes: a first backplane layer including a first substrate and a switching transistor disposed on the first substrate; and a second backplane layer including a second substrate and a driving transistor disposed on the second substrate; and A light-emitting element layer is disposed on the backplate and includes light-emitting elements electrically connected to the driving transistor.

2. The display device according to claim 1, wherein, The switching transistor is a thin-film transistor formed on the first substrate, and The driving transistor is a metal-oxide-semiconductor field-effect transistor formed on the second substrate.

3. The display device according to claim 1, wherein, The first substrate and the second substrate are made of different materials.

4. The display device according to claim 3, wherein, The first substrate is an insulating substrate, and The second substrate is a semiconductor substrate.

5. The display device according to claim 1, wherein, The first backsheet layer also includes a capacitor disposed on the first substrate.

6. The display device according to claim 1, wherein, The first backplane layer further includes a connection electrode disposed on the first substrate and electrically connected to the switching transistor, and The connection electrode is exposed on the upper surface of the first backsheet layer.

7. The display device according to claim 6, wherein, The second backplane layer further includes a first contact terminal and a second contact terminal disposed on the second substrate and electrically connected to the source region and drain region of the driving transistor, respectively.

8. The display device according to claim 7, wherein, The second backsheet layer is disposed on the first backsheet layer, and The light-emitting element layer is disposed on the second backplate layer.

9. The display device according to claim 8, wherein, One of the first contact terminal and the second contact terminal is electrically connected to the connection electrode, and The other of the first contact terminal and the second contact terminal is electrically connected to the light-emitting element.

10. The display device according to claim 1, wherein, The backplate also includes a line layer disposed between the second backplate layer and the light-emitting element layer, and The line layer includes a conductive pattern that electrically connects the driving transistor to the light-emitting element and the switching transistor.

11. The display device according to claim 1, wherein, The light-emitting element layer also includes pixel electrodes disposed on the backplate and electrically connected to the driving transistor, and The light-emitting element is disposed on the pixel electrode.

12. The display device according to claim 11, wherein, The light-emitting element is connected to the pixel electrode.

13. The display device according to claim 11, wherein, The light-emitting element is a micro-light-emitting diode comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed on the pixel electrode.

14. The display device according to claim 11, further comprising: A pixel includes the switching transistor, the driving transistor, and the light-emitting element. The light-emitting element layer further includes a common electrode disposed on the light-emitting element.

15. A display device, the display device comprising: The first backplane layer includes an insulating substrate and a thin-film transistor formed on the insulating substrate; A second backplane layer is disposed on the first backplane layer and includes a semiconductor substrate and a metal-oxide-semiconductor field-effect transistor formed on the semiconductor substrate; as well as A light-emitting element layer is disposed on the second backsheet layer and includes light-emitting elements.

16. The display device according to claim 15, wherein, The first backplane layer also includes a connection electrode electrically connected between the thin-film transistor and the metal-oxide-semiconductor field-effect transistor.

17. The display device according to claim 15, further comprising: A line layer is disposed between the second backplate layer and the light-emitting element layer. The line layer includes a conductive pattern electrically connected between the metal-oxide-semiconductor field-effect transistor and the light-emitting element.

18. The display device according to claim 17, wherein, The light-emitting element layer further includes pixel electrodes disposed on the line layer, and The light-emitting element is disposed on the pixel electrode.

19. The display device according to claim 15, further comprising: A pixel includes the thin-film transistor, the metal-oxide-semiconductor field-effect transistor, and the light-emitting element. Wherein, the thin-film transistor is the switching transistor of the pixel, and The metal-oxide-semiconductor field-effect transistor is the driving transistor of the pixel.

20. An electronic device, the electronic device comprising: Display module, including display panel; as well as The processor transmits image data signals to the display module. The display panel includes: a back panel, comprising a first back panel layer and a second back panel layer, the first back panel layer comprising a first substrate and a switching transistor disposed on the first substrate, the second back panel layer comprising a second substrate and a driving transistor disposed on the second substrate; and a light-emitting element layer disposed on the back panel and comprising a light-emitting element electrically connected to the driving transistor.

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