N-type single crystal silicon wafer and method for diffusion gettering treatment thereof

Abstract

The application provides an N-type monocrystalline silicon wafer and a diffusion gettering treatment method thereof, and belongs to the technical field of solar cells, and comprises the following steps: performing texturing cleaning on the N-type monocrystalline silicon wafer, performing passivation on the N-type monocrystalline silicon wafer after the texturing cleaning, and performing diffusion gettering on the N-type monocrystalline silicon wafer after the passivation. The application can accurately control a thermal field and an air field in a crystal growth process, reduces defects caused by in-situ growth by adopting a passivation technology, realizes high-quality N-type monocrystalline silicon growth, simultaneously develops an N-type monocrystalline silicon wafer diffusion gettering post-treatment technology, optimizes an impurity diffusion heat process, and eliminates problems such as local impurity defects in in-situ growth, impurity pollution and stress defects in a cutting process and the like.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to an N-type monocrystalline silicon wafer and its diffusion gettering process. Background Technology

[0002] In the production process of HJT (Heterojunction with Intrinsic Thin-layer) solar cells, silicon wafers are the core component, and their quality directly determines the performance and efficiency of the final cell. However, current technologies still face multiple challenges and problems in improving silicon wafer quality, especially in the crystal growth stage, where these problems are particularly prominent.

[0003] First, the temperature gradient and temperature stability during crystal growth are key factors in controlling the growth of high-quality single-crystal silicon. Ideally, a highly uniform and stable temperature field needs to be maintained to ensure that the crystal grows uniformly at a stable rate, reducing inconsistencies in growth rate caused by temperature fluctuations, and thus avoiding defects such as dislocations and voids. However, in actual production, achieving ideal thermal field control is particularly difficult due to limitations in the precision of heating elements, imperfections in equipment design, and unavoidable minor fluctuations in the operating process. This requires not only a high-precision temperature sensing and control system, but also precise layout and optimization of heating elements, as well as strict monitoring and adjustment of the entire growth process.

[0004] Secondly, the complexity of the crystal growth mechanism during the in-situ growth of single-crystal silicon makes it extremely difficult to completely avoid the formation of defects such as dangling bonds and trapped states. These defects not only reduce the minority carrier lifetime of the silicon wafer but also negatively impact the photoelectric conversion efficiency of HJT solar cells. The formation of dangling bonds and trapped states is often closely related to factors such as atomic arrangement, chemical bonding, and impurity introduction during crystal growth. To reduce the generation of these defects, researchers need to conduct in-depth research on the crystal growth mechanism and optimize growth conditions, such as adjusting the growth rate, improving the gas environment, and increasing the purity of raw materials. Simultaneously, advanced characterization techniques need to be developed to monitor defect formation in real time during growth and make timely adjustments and corrections accordingly.

[0005] Furthermore, the handling and protection of silicon wafers during subsequent processing are also crucial factors affecting their quality. During cutting, polishing, and cleaning, even the slightest damage or contamination can have irreversible effects on the quality of the silicon wafer; therefore, high-precision processing equipment, high-quality auxiliary materials, and strict process control are necessary to ensure the integrity and cleanliness of the silicon wafers during processing.

[0006] In summary, improving the quality of silicon wafers during the production of HJT solar cells is a complex process involving multiple stages and factors. To overcome the challenges and problems in existing technologies, it is necessary to continuously innovate and optimize crystal growth technology, processing technology, and testing equipment to promote the continuous improvement of HJT solar cell performance and efficiency. Summary of the Invention

[0007] The purpose of this invention is to provide an N-type single-crystal silicon wafer and its diffusion gettering process to overcome the problems existing in the prior art. This invention can precisely control the thermal field and gas field during crystal growth, and uses passivation technology to reduce defects caused by the in-situ growth process, thereby achieving high-quality N-type single-crystal silicon growth. At the same time, it develops a diffusion gettering post-processing technology for n-type single-crystal silicon wafers, which optimizes the impurity diffusion thermal process to eliminate local impurity defects in in-situ growth, as well as impurity contamination and stress defects during the cutting process.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A diffusion gettering process for N-type single-crystal silicon wafers includes the following steps: (1) Texturing and cleaning of N-type monocrystalline silicon wafers; (2) Passivate the N-type monocrystalline silicon wafer after texturing and cleaning; (3) Diffusion gettering is performed on the passivated N-type single crystal silicon wafer; Further, step one specifically involves: performing preliminary cleaning on the N-type monocrystalline silicon wafer, using potassium hydroxide solution to perform anisotropic etching on the N-type monocrystalline silicon wafer to form a pyramid-shaped textured surface, washing with deionized water, performing RCA cleaning, then washing again with deionized water, and then drying. Furthermore, the preliminary cleaning uses SC1 solution; the concentration of the potassium hydroxide solution is 0.1-0.5 wt%. Further, step two specifically involves depositing a silicon nitride thin film on the surface of an N-type single-crystal silicon wafer; Furthermore, the method for depositing a silicon nitride thin film in step two is: plasma-enhanced chemical vapor deposition, thermal oxidation, or atomic layer deposition. Further, step three specifically involves: forming a phosphorus source layer on the surface of an N-type single-crystal silicon wafer using a phosphorus source, followed by diffusion; Furthermore, the phosphorus source in step three is liquid phosphorus oxychloride; Furthermore, the method for forming the phosphorus source layer in step three is: coating or spraying to form a diffusion region with a thickness of 0.3 μm; Furthermore, the diffusion temperature in step three is 750~800 ℃.

[0009] An N-type single-crystal silicon wafer is obtained based on the above-mentioned diffusion gettering process for an N-type single-crystal silicon wafer.

[0010] The above technical solution has the following advantages or beneficial effects: This invention provides a diffusion gettering treatment method for N-type monocrystalline silicon wafers. By texturing and cleaning the N-type monocrystalline silicon wafer, dirt, grease, and metallic impurities are removed from the wafer surface, providing a clean surface for subsequent passivation steps. Texturing also forms tiny pyramidal structures on the wafer surface, increasing the surface area and facilitating the adhesion of getter and impurity capture in subsequent steps. This ensures the cleanliness of the wafer surface, reduces defects and performance degradation caused by impurities, and lays a good foundation for subsequent steps. The N-type silicon wafer after texturing and cleaning... Passivation of monocrystalline silicon wafers involves forming a passivation layer, such as a silicon oxide layer, on the wafer surface to reduce the number of dangling bonds and lower the surface state density, thereby improving the stability and minority carrier lifetime of the silicon wafer. The passivation layer also serves as a carrier for subsequent diffusion gettering, enhancing the gettering effect and significantly reducing the defect density on the silicon wafer surface. This improves the electrical performance and photoelectric conversion efficiency of the silicon wafer, while providing the necessary conditions for subsequent diffusion gettering steps. Diffusion gettering of passivated N-type monocrystalline silicon wafers improves HJT (High-Jet Transmission Time). The reduction of the discrete distribution of photoelectric conversion efficiency and miniaturization efficiency of the battery has a significant effect, thereby improving the power distribution concentration of the module and facilitating the management of battery and module products. Therefore, by optimizing the phosphorus diffusion gettering process, the impurity content of the silicon wafer is reduced, and the minority carrier lifetime of the silicon wafer is improved, thereby improving the conversion efficiency of HJT cells. According to the requirements of PECVD and screen printing processes, the texture size and pyramid morphology of the surface are optimized to reduce the surface reflectivity of the silicon wafer. Combined with increasing the aspect ratio of the metal electrodes, the current density and FF of the HJT cells are improved. At the same time, in conjunction with the development of PECVD process, the passivation effect of amorphous silicon is improved by optimizing the cleaning process and the surface state of the silicon wafer, thereby improving Voc and photoelectric conversion efficiency. This invention uses phosphorus diffusion heat treatment technology to form a high-concentration doped layer on the surface of the silicon wafer, so that the metal impurities inside the silicon wafer are enriched in the diffusion layer. Then, the surface diffusion layer is removed by chemical etching to reduce the metal impurity content.

[0011] Furthermore, preliminary cleaning removes basic dirt and impurities from the surface of N-type monocrystalline silicon wafers, providing a relatively clean substrate for subsequent processing. When potassium hydroxide solution chemically etches the silicon wafer surface, it forms a unique pyramidal textured surface due to the different etching rates on different crystal planes of silicon. This structure not only increases the specific surface area of ​​the silicon wafer, helping to improve photoelectric conversion efficiency, but also enhances the contact area between the getter and the silicon wafer in subsequent processing steps, improving the gettering effect. The washing step removes potassium hydroxide solution and other impurities remaining on the silicon wafer surface after etching, ensuring the cleanliness of the silicon wafer surface. (RCA (Radio Corporation of...) RCA cleaning is a standard semiconductor cleaning process that includes multiple cleaning steps, such as using a mixture of ammonia, hydrogen peroxide, and water (SC-1) to remove organic matter, and using a mixture of hydrochloric acid, hydrogen peroxide, and water (SC-2) to remove metal ions. These steps further ensure a high degree of cleanliness on the silicon wafer surface and reduce impurities that may affect subsequent processing steps. After RCA cleaning, a second wash with deionized water is used to thoroughly remove residual cleaning solution and any new impurities that may be introduced. The drying process is to prevent performance degradation or damage to the silicon wafer due to residual moisture during subsequent processing.

[0012] Furthermore, preliminary cleaning with SC1 solution effectively removes organic residues, including grease and photoresist, from the silicon wafer surface. These organic residues, if left on the wafer, can affect subsequent processing and even become new sources of contamination. The strong oxidizing and alkaline properties of SC1 solution give it excellent removal capabilities for organic matter. The concentration of potassium hydroxide solution is controlled within the range of 0.1-0.5 wt%. This concentration range ensures the formation of a uniform, fine, and appropriately deep pyramid-shaped textured surface on the silicon wafer. Excessively high concentrations may lead to rapid corrosion, resulting in a rough and uneven surface; while excessively low concentrations may fail to form a sufficient textured surface, affecting photoelectric conversion efficiency. Therefore, setting this concentration range is crucial for optimizing the silicon wafer surface morphology and improving photoelectric performance.

[0013] Furthermore, as an excellent passivation material, silicon nitride thin film can significantly reduce the dangling bond density and surface state density on the surface of N-type single-crystal silicon wafers, which helps to reduce the number of surface recombination centers, improve the minority carrier lifetime of silicon wafers, and thus improve the photoelectric conversion efficiency of solar cells. Silicon nitride thin film has good density and chemical stability, and can act as a barrier to effectively block the diffusion of external impurities (such as metal ions, water vapor, etc.) into the silicon wafer, which helps to maintain the purity of the silicon wafer and reduce the performance degradation caused by the introduction of impurities. In the subsequent diffusion gettering step, silicon nitride thin film not only acts as a protective layer, but also, through its specific physical and chemical properties, can synergistically work with getter to enhance the ability to capture impurities and defects inside the silicon wafer.

[0014] Furthermore, PECVD utilizes high-energy electrons in plasma to bombard reactive gas molecules, causing them to dissociate into active groups, thereby rapidly depositing silicon nitride thin films on the silicon wafer surface. It boasts advantages such as fast deposition rates and high production efficiency. Simultaneously, PECVD allows for precise control of the film composition and thickness, producing dense and uniform silicon nitride films with excellent passivation effects and the ability to block impurity diffusion. Additionally, the PECVD process is typically performed at relatively low temperatures, which helps reduce thermal stress damage to the silicon wafer during deposition, protecting its structure and performance. Thermal oxidation, on the other hand, involves exposing the silicon wafer to a nitrogen-containing atmosphere (such as nitrogen or ammonia) at high temperatures. The thermal oxidation method involves reacting nitrogen with silicon wafers to form silicon nitride films. This method is simple and requires relatively low-end equipment. Furthermore, the silicon nitride films prepared by thermal oxidation have a tight interface with the silicon wafer, which helps reduce the number of interfacial recombination centers and improve the minority carrier lifetime of the silicon wafer. ALD (Alternating Deposition) achieves layer-by-layer growth of silicon nitride films by alternately pulsed reactants into the reaction chamber, resulting in a self-limiting reaction on the silicon wafer surface. This method offers extremely high deposition precision and thickness control. Moreover, the silicon nitride films prepared by ALD exhibit excellent consistency in thickness, composition, and performance, ensuring that each silicon wafer achieves the same results during processing.

[0015] Furthermore, by selecting a suitable phosphorus source material, it is ensured that the phosphorus source can be uniformly and effectively covered on the surface of the N-type single crystal silicon wafer. Through phosphorus diffusion, metal impurities are attracted to the phosphorus silicon getter layer, reducing the impurity content inside the silicon wafer and improving the cleanliness and purity of the silicon wafer. Phosphorus diffusion gettering effectively removes some impurities in the silicon wafer, reduces recombination centers, and improves the electrical performance of the silicon wafer.

[0016] Furthermore, by using liquid phosphorus oxychloride to form a 0.3 μm thick phosphorus source layer through coating or spraying, the depth to which phosphorus atoms penetrate into the silicon wafer during subsequent diffusion can be precisely controlled. This precise control helps optimize the formation of the phosphorus silicon getter layer, ensuring that impurities are effectively captured and do not diffuse excessively into the depths of the silicon wafer, thus affecting the overall performance of the silicon wafer. The coating or spraying method may be gentler than other methods (such as dip coating, spin coating, etc.) and causes less damage to the surface of the silicon wafer. At the same time, precise control of the phosphorus source layer thickness also helps reduce surface defects such as cracks and peeling that may occur during diffusion due to an excessively thick phosphorus source layer.

[0017] Furthermore, diffusion gettering at 750–800 °C provides a suitable diffusion rate for phosphorus atoms within the silicon wafer. This temperature ensures that phosphorus atoms can fully diffuse into the wafer, dissolve with impurities, and form a phosphorus-silicon getter layer. It also avoids excessively rapid diffusion due to excessively high temperatures, thus reducing ineffective diffusion deep within the wafer and improving diffusion efficiency. The appropriate diffusion temperature also promotes uniform diffusion of phosphorus atoms within the wafer, forming a uniform phosphorus-silicon getter layer. This helps reduce performance fluctuations caused by uneven diffusion and improves the overall performance consistency of the wafer. As the depth of diffusion into the wafer increases, the phosphorus atom concentration increases from 1E20 to 1E21 atoms / cm³. 3 Gradually reduced to 1E15 cells / cm 3 Due to the high solubility of metal impurities in the heavily doped layer and the trapping effect of high-density defects in the diffusion layer on metal atoms, metal impurities gradually accumulate in the diffusion layer. Then, the phosphosilicate glass and the diffusion layer are removed to obtain a silicon wafer with lower impurity content.

[0018] The present invention also provides an N-type single-crystal silicon wafer, which is obtained based on the above-described diffusion gettering method for N-type single-crystal silicon wafers. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of an N-type single-crystal silicon wafer and its diffusion gettering process according to the present invention. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention. To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Example 1: like Figure 1 As shown, the present invention provides an N-type single-crystal silicon wafer and its diffusion gettering process, comprising the following steps: (1) Texturing and cleaning of N-type monocrystalline silicon wafers; (2) Passivate the N-type monocrystalline silicon wafer after texturing and cleaning; (3) Diffusion gettering is performed on the passivated N-type single crystal silicon wafer; Preferably, step one specifically involves: performing preliminary cleaning on the N-type monocrystalline silicon wafer, using potassium hydroxide solution to perform anisotropic etching on the N-type monocrystalline silicon wafer to form a pyramid-shaped textured surface, washing with deionized water, performing RCA cleaning, then washing again with deionized water, and then drying. Preferably, the preliminary cleaning uses SC1 solution; the concentration of the potassium hydroxide solution is 0.1-0.5 wt%. Preferably, step two specifically involves depositing a silicon nitride thin film on the surface of an N-type single-crystal silicon wafer; Preferably, the method for depositing a silicon nitride thin film in step two is: plasma-enhanced chemical vapor deposition, thermal oxidation, or atomic layer deposition. Preferably, step three specifically involves: forming a phosphorus source layer on the surface of an N-type single-crystal silicon wafer using a phosphorus source, followed by diffusion; Preferably, the phosphorus source in step three is liquid phosphorus oxychloride; Preferably, the method for forming the phosphorus source layer in step three is: coating or spraying to form a diffusion region with a thickness of 0.3 μm; Preferably, the diffusion temperature in step three is 750~800 ℃.

[0022] An N-type single-crystal silicon wafer is obtained based on the above-mentioned diffusion gettering process for an N-type single-crystal silicon wafer.

[0023] Example 2: like Figure 1 As shown, the present invention provides an N-type single-crystal silicon wafer and its diffusion gettering process, comprising the following steps: (1) Texturing and cleaning of N-type single crystal silicon wafers; forming tiny pyramid-shaped structures on the surface of the silicon wafers, increasing the surface area, which is beneficial for the adhesion of getter and the capture of impurities in subsequent steps, ensuring the cleanliness of the silicon wafer surface, reducing defects and performance degradation caused by impurities, and laying a good foundation for subsequent steps. Specifically, the N-type monocrystalline silicon wafer is initially cleaned with SC1 solution, then anisotropically etched with a 0.1-0.5 wt% potassium hydroxide solution to form a pyramid-shaped textured surface, washed with deionized water, RCA cleaning is performed, then washed again with deionized water, and finally dried. (2) Passivate the N-type single crystal silicon wafer after texturing and cleaning; form a passivation layer, such as a silicon oxide layer, on the surface of the silicon wafer to reduce the number of dangling bonds on the surface of the silicon wafer and reduce the surface state density, thereby improving the stability and minority carrier lifetime of the silicon wafer. The passivation layer can also serve as a carrier for subsequent diffusion gettering, enhancing the gettering effect, significantly reducing the defect density on the surface of the silicon wafer, improving the electrical performance and photoelectric conversion efficiency of the silicon wafer, and providing the necessary conditions for subsequent diffusion gettering steps. Specifically, a silicon nitride film is deposited on the surface of an N-type single-crystal silicon wafer using plasma-enhanced chemical vapor deposition, thermal oxidation, or atomic layer deposition. (3) Diffusion gettering is performed on the passivated N-type monocrystalline silicon wafer; by optimizing the phosphorus diffusion gettering process, the impurity content of the silicon wafer is reduced and the minority carrier lifetime of the silicon wafer is improved, thereby improving the HJT cell conversion efficiency; according to the requirements of PECVD and screen printing processes, the texture size and pyramid shape structure are optimized to reduce the surface reflectivity of the silicon wafer, and the aspect ratio of the metal electrode is increased, thereby improving the current density and FF of the HJT cell; at the same time, in conjunction with the development of PECVD process, the passivation effect of amorphous silicon is improved by optimizing the cleaning process and the surface state of the silicon wafer, thereby improving the Voc and photoelectric conversion efficiency. Specifically, liquid phosphorus oxychloride is used to form a phosphorus source layer on the surface of an N-type single-crystal silicon wafer by coating or spraying, and then diffusion is carried out at 750~800 °C to form a diffusion region with a thickness of 0.3 μm.

[0024] An N-type single-crystal silicon wafer is obtained based on the above-mentioned diffusion gettering process for an N-type single-crystal silicon wafer.

[0025] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A diffusion gettering process for N-type single-crystal silicon wafers, characterized in that, Includes the following steps: S1, texturing and cleaning of N-type monocrystalline silicon wafers; S2, passivation of the N-type monocrystalline silicon wafer after texturing and cleaning; S3 is used for diffusion gettering of passivated N-type single-crystal silicon wafers.

2. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 1, characterized in that, S1 specifically involves: performing preliminary cleaning on the N-type monocrystalline silicon wafer, using potassium hydroxide solution to perform anisotropic etching on the N-type monocrystalline silicon wafer to form a pyramid-shaped textured surface, washing with deionized water, performing RCA cleaning, then washing again with deionized water, and then drying.

3. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 2, characterized in that, The initial cleaning was performed using SC1 solution; the concentration of the potassium hydroxide solution was 0.1-0.5 wt%.

4. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 1, characterized in that, Specifically, S2 involves depositing a silicon nitride thin film on the surface of an N-type single-crystal silicon wafer.

5. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 4, characterized in that, The method for depositing a silicon nitride thin film in S2 is: plasma-enhanced chemical vapor deposition, thermal oxidation, or atomic layer deposition.

6. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 1, characterized in that, Specifically, S3 involves forming a phosphorus source layer on the surface of an N-type single-crystal silicon wafer using a phosphorus source, followed by diffusion.

7. The diffusion gettering method for N-type single-crystal silicon wafers according to claim 6, characterized in that, The phosphorus source in S3 is liquid phosphorus oxychloride.

8. A diffusion gettering method for N-type single-crystal silicon wafers according to claim 6, characterized in that, The method for forming the phosphorus source layer in S3 is: coating or spraying to form a diffusion region with a thickness of 0.3 μm.

9. A diffusion gettering method for N-type single-crystal silicon wafers according to claim 6, characterized in that, The diffusion temperature in S3 is 750~800 ℃.

10. An N-type single-crystal silicon wafer, characterized in that, This method is based on the diffusion gettering process for N-type single-crystal silicon wafers as described in any one of claims 1-9.

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