A combined manufacturing method of a deep trench isolation structure and a deep trench capacitor structure

Abstract

The application discloses a combined preparation method of a deep trench isolation structure and a deep trench capacitor structure and a semiconductor device. The method comprises the following steps: providing a substrate comprising a first region and a second region; performing a photoetching process to form a first trench pattern and a second trench pattern in the first region and the second region respectively; performing an etching process to form a first trench and a second trench in the first region and the second region simultaneously; forming a first oxide layer on the first trench wall and the second trench wall respectively; forming a first conductive layer on the first oxide layer; forming at least one set of combined layers on the first conductive layer; the first trench, the first oxide layer in the first trench, the first conductive layer on the first oxide layer and the combined layers constitute a deep trench isolation structure, and the second trench, the first oxide layer in the second trench, the first conductive layer on the first oxide layer and the combined layers constitute a deep trench capacitor structure. The application can form the deep trench isolation structure and the deep trench capacitor structure simultaneously through one process.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure, and a semiconductor device. Background Technology

[0002] DTI (Dual Insulation Transmission) technology achieves physical and electrical isolation between power devices and logic circuits by etching insulating trenches several micrometers or even tens of micrometers deep in a silicon substrate. This significantly reduces substrate parasitic current and crosstalk, improving the stability and reliability of devices under high-voltage operating conditions. Meanwhile, Deep Trench Capacitor (DTC) technology has also gained widespread application due to its high capacitance density per unit area, excellent capacitance stability, and good compatibility with CMOS processes. DTC technology integrates large-capacitance capacitors within a limited chip area by constructing capacitor structures within deep trenches, effectively supporting transient current response under high-frequency switching and improving power integrity. However, existing technologies for forming DTI and DTC involve complex and cumbersome processes. Summary of the Invention

[0003] This application provides a method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure, and a semiconductor device. The method simultaneously forms both the deep trench isolation structure and the deep trench capacitor structure in a single process, simplifying the process steps and reducing process complexity. The specific solution is as follows: In a first aspect, embodiments of this application provide a method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure. The method includes: providing a semiconductor substrate having a first region and a second region; performing a photolithography process to form a first trench pattern and a second trench pattern in the first region and the second region, respectively; performing an etching process to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region; forming a first oxide layer on the first trench wall and the second trench wall, respectively; forming a first conductive layer on the first oxide layer; forming at least one set of combined layers on the first conductive layer, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; wherein the first trench in the first region, the first oxide layer in the first trench, and the first conductive layer and combined layer on the first oxide layer in the first trench together constitute a deep trench isolation structure, and the second trench in the second region, the first oxide layer in the second trench, and the first conductive layer and combined layer on the first oxide layer in the second trench together constitute a deep trench capacitor structure.

[0004] Optionally, the depth of the first groove to be formed is greater than the depth of the second groove to be formed, and the width of the first groove pattern is greater than the width of the second groove pattern.

[0005] Optionally, before the first oxide layer is formed on the first trench wall and the second trench wall, a first device and a second device are formed on the substrate, and the first trench is located between the first device and the second device.

[0006] Optionally, forming a first oxide layer on the first trench wall and the second trench wall includes: performing a chemical vapor deposition process to form a first oxide layer on the first trench wall and the second trench wall.

[0007] Optionally, no device is formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall; the formation of the first oxide layer on the first trench wall and the second trench wall includes: performing a high-temperature thermal oxidation process or chemical vapor deposition to form the first oxide layer on the first trench wall and the second trench wall.

[0008] Optionally, forming a first oxide layer on the first trench wall and the second trench wall includes: forming a second oxide layer on the first deep trench wall and the second trench wall; removing the second oxide layer; and forming a first oxide layer on the first deep trench wall and the second trench wall after removing the second oxide layer.

[0009] Optionally, the photolithography process for forming a first trench pattern and a second trench pattern in the first region and the second region respectively includes: forming a third oxide layer and a hard mask layer on the surface of the semiconductor substrate; forming a first trench pattern in the first region on the hard mask layer and a second trench pattern in the second region on the hard mask layer by photolithography.

[0010] Optionally, forming a first conductive layer on the first oxide layer in the first deep trench and the second deep trench includes: performing a furnace tube process to deposit the first conductive layer on the first oxide layer in the first deep trench and the second deep trench and on the surface of the hard mask layer on the substrate surface.

[0011] Optionally, forming at least one set of combined layers on the first conductive layer includes: performing an atomic layer deposition step to form a dielectric layer on the first conductive layer; and performing a furnace tube process to deposit a second conductive layer on the dielectric layer.

[0012] Optionally, after depositing the second conductive layer on the dielectric layer, the method further includes removing the second conductive layer and the dielectric layer from the surface of the substrate.

[0013] Optionally, after removing the second conductive layer and dielectric layer on the substrate surface, the method further includes: defining the region where the lower electrode of the deep trench capacitor structure to be formed is located on the first conductive layer formed on the substrate surface using a photolithography process for the second trench; performing an etching step to remove the first conductive layer deposited in the region of the first conductive layer formed on the substrate surface other than the region where the lower electrode is located, thereby forming the lower electrode.

[0014] Optionally, after forming the lower electrode, the method further includes forming an interlayer dielectric layer on the substrate surface where the lower electrode is formed.

[0015] Optionally, the method further includes: defining via locations on the interlayer dielectric layer using photolithography for the second trench; performing an etching step to form vias on the interlayer dielectric layer for connecting the lower electrode and the upper electrode to the metal layer, wherein the upper electrode is the second conductive layer in the second trench.

[0016] Optionally, the method further includes: forming a first device and a second device in the two side regions of the first trench, wherein the first device and the second device are respectively a bipolar element, a CMOS device, and a DMOS device.

[0017] Secondly, embodiments of this application provide a semiconductor device, characterized in that it is prepared by the method described in the first aspect of this application.

[0018] Compared with the prior art, this application has the following advantages: The method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure provided in this application includes the following steps: providing a semiconductor substrate, wherein the substrate has a first region and a second region; performing a photolithography process to form a first trench pattern and a second trench pattern in the first region and the second region, respectively; performing an etching process to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region; forming a first oxide layer on the first trench wall and the second trench wall, respectively; forming a first conductive layer on the first oxide layer; forming at least one set of combined layers on the first conductive layer, wherein the combined layers include a dielectric layer and a second conductive layer on the dielectric layer; the first trench in the first region, the first oxide layer in the first trench, and the first conductive layer and combined layer on the first oxide layer in the first trench together constitute a deep trench isolation structure, and the second trench in the second region, the first oxide layer in the second trench, and the first conductive layer and combined layer on the first oxide layer in the second trench together constitute a deep trench capacitor structure.

[0019] As can be seen, the method for jointly fabricating deep trench isolation structures and deep trench capacitor structures provided in this application embodiment can simultaneously form a first trench and a second trench in a first region and a second region of the substrate through a single etching process. Both the deep trench isolation structure formed in the first trench and the deep trench capacitor structure formed in the second trench include a first oxide layer, a conductive layer, a dielectric layer, and a conductive layer. The deep trench isolation structure can achieve electrical isolation between devices, and the deep trench capacitor structure can be used to construct high-density, high-performance on-chip capacitors. Therefore, the method for jointly fabricating deep trench isolation structures and deep trench capacitor structures provided in this application embodiment can simultaneously form deep trench isolation structures and deep trench capacitor structures on the substrate in a single process, effectively reducing the number of photolithography steps, lowering manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. Furthermore, the collaborative design of the deep trench isolation structure and deep trench capacitor structure in this application can effectively utilize the vertical space of the chip, avoid wasting planar layout (such as the combination of capacitors and isolation structures in DRAM), increase chip density, and improve overall collaborative optimization. Attached Figure Description

[0020] Figure 1 This is a flowchart of the method for jointly preparing the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0021] Figure 2 This is a schematic diagram of a semiconductor substrate used in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0022] Figure 3 This is a schematic diagram of another semiconductor substrate in the combined fabrication method of deep trench isolation structure and deep trench capacitor structure provided in the embodiments of this application.

[0023] Figure 4 This is a schematic diagram of the formation of the first trench and the second trench in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0024] Figure 5 This is a schematic diagram of the formation of a second oxide layer on the inner wall of the first trench and the inner wall of the second trench in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0025] Figure 6 This is a schematic diagram of removing the second oxide layer from the inner walls of the first and second trenches in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0026] Figure 7This is a schematic diagram of the formation of a first oxide layer on the inner wall of the first trench and the inner wall of the second trench in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0027] Figure 8 This is a schematic diagram of a device pre-formed on a substrate in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0028] Figure 9 This is a schematic diagram of the formation of a first oxide layer on the inner wall of the first trench and the inner wall of the second trench in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0029] Figure 10 This is a schematic diagram of the formation of a first conductive layer on the first oxide layer in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0030] Figure 11 This is a schematic diagram of the formation of a dielectric layer on the first conductive layer in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0031] Figure 12 This is a schematic diagram of the formation of a second conductive layer on the dielectric layer in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0032] Figure 13 This is a schematic diagram of removing the second conductive layer and dielectric layer in the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in the embodiments of this application.

[0033] Figure 14 This is a schematic diagram of the formation of the lower electrode plate in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0034] Figure 15 This is a schematic diagram of the formation of the interlayer dielectric layer in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0035] Figure 16 This is a schematic diagram of the formation of through-holes in the interlayer dielectric layer in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0036] Figure 17 This is a schematic diagram of filling through holes in the combined fabrication method of deep trench isolation structure and deep trench capacitor structure provided in the embodiments of this application. Detailed Implementation

[0037] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0038] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0039] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0040] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0041] The following is a further explanation of the existing technology: BCD (Bipolar-CMOS-DMOS) refers to a semiconductor process technology that integrates bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) on the same chip. It has been widely used in high-growth fields such as new energy vehicles, smart homes, 5G communications, and industrial control.

[0042] To avoid electrical isolation between different device regions in BCD (Browser-Chip-Device) processes, the industry has proposed Deep Trench Isolation (DTI) technology. DTI technology achieves physical and electrical isolation between power devices and logic circuits by etching insulating trenches several micrometers or even tens of micrometers deep in the silicon substrate. This significantly reduces substrate parasitic current and crosstalk, improving the stability and reliability of devices under high-voltage operating conditions. Meanwhile, Deep Trench Capacitor (DTC) technology has also gained widespread application due to its high capacitance density per unit area, excellent capacitance stability, and good compatibility with CMOS processes. DTC technology integrates large-capacitance capacitors within a limited chip area by constructing capacitor structures within deep trenches, effectively supporting transient current response under high-frequency switching and improving power integrity.

[0043] Currently, semiconductor manufacturing processes typically involve two separate steps to form DTC and DTI, which not only makes the process complex and cumbersome but also reduces chip integration.

[0044] For the reasons mentioned above, the first embodiment of this application provides a method for the joint fabrication of a deep trench isolation structure and a deep trench capacitor structure. The deep trench isolation structure and the deep trench capacitor structure are formed in one process, which simplifies the process steps and reduces the process complexity.

[0045] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0046] The following, combined with Figures 1-17 This application describes a method for fabricating a shielded trench power device according to embodiments of the present application.

[0047] like Figure 1 The diagram shown is a flowchart of a method for jointly preparing a deep trench isolation structure and a deep trench capacitor structure according to an embodiment of this application, including the following steps S101 to S106.

[0048] Step S101: Provide a semiconductor substrate, the substrate having a first region and a second region.

[0049] In semiconductor manufacturing processes, a semiconductor substrate refers to the basic material used to fabricate semiconductor devices. Semiconductor substrates can include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process.

[0050] The semiconductor substrate may include at least one first region and at least one second region. The first region is for forming a first trench, and the second region is for forming a second trench. The first trench may be a trench for forming a deep trench isolation (DTI) structure, and the second trench may be a trench for forming a deep trench capacitor (DTC) structure.

[0051] The deep trench isolation structure formed by the first trench can be used to isolate devices. Specifically, a first device and a second device can be formed on both sides of the first trench, respectively. The first device and the second device can be devices among BCD devices. For example, the first device is one of the following BCD devices: Bipolar Transistor, CMOS, and DMOS. The second device is one of the following BCD devices other than the first device: Bipolar Transistor, CMOS, and DMOS. In this way, the first device and the second device can be isolated by the deep trench isolation structure formed by the first trench.

[0052] In one alternative implementation, no device is formed on the substrate before trenches are formed in the first and second regions. For example... Figure 2 The diagram shown is a schematic of a semiconductor substrate used in the combined fabrication method of a deep trench isolation structure and a deep trench capacitor structure provided in this application embodiment. A third oxide layer 02 is formed on the surface of the semiconductor substrate 01, and a hard mask layer 03 is formed on the third oxide layer 02. The semiconductor substrate includes a first region 201 and a second region 202.

[0053] In another alternative embodiment, devices have been pre-formed on the substrate before trenches are formed in the first and second regions. For example... Figure 3The diagram shows another semiconductor substrate in the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this application embodiment. The semiconductor substrate may include an epitaxial layer 01-2 and a substrate layer 01-1, and includes a first region 201 and a second region 202. The epitaxial layer 01-2 is located above the substrate layer 01-1, and an N-well 14 is formed between the epitaxial layer 01-2 and the substrate layer 01-1. An N-well refers to a localized N-type doped region formed in a P-type semiconductor substrate (or P-type epitaxial layer) through ion implantation and diffusion processes. It can be used to accommodate PMOS transistors and achieve electrical isolation between devices. An epitaxial layer refers to a new material layer with a specific doping concentration and crystal structure grown on the original semiconductor substrate through a process called epitaxy (or simply Epi). This process can control the composition, thickness, doping type, and concentration of the new layer, thereby achieving specific electrical properties. The epitaxial layer can be matched with the substrate at the atomic level to form a continuous crystal structure. The epitaxial layer can be made of the same material as the substrate (homogeneous epitaxy) or a different material (heterogeneous epitaxy). Specifically, the epitaxial layer can be silicon-based or silicon carbide-based. A shallow trench structure for shallow trench isolation (STI) can be formed on the surface of epitaxial layer 01-2. The shallow trench is used to achieve electrical isolation between devices, prevent leakage and parasitic conduction, and ensure that each transistor operates independently. After forming the shallow trench, an insulating material, such as silicon dioxide (SiO2), can be filled into the shallow trench until the thickness of the silicon dioxide on the surface of epitaxial layer 01-2 reaches the target thickness, forming a third oxide layer 02. That is, the thickness of the third oxide layer 02 is the target thickness. Then, a hard mask layer 03 can be formed on the surface of the third oxide layer 02. The material of the hard mask layer 03 includes, but is not limited to, at least one of silicon nitride (Si3N4) hard mask layer, silicon dioxide (SiO2) hard mask layer, metal hard mask layer, and amorphous carbon hard mask layer. After forming the hard mask layer 03, chemical vapor deposition or plasma-enhanced tetraethyl orthosilicate CVD (PECVD TEOS) can be performed to form an interlayer dielectric layer 0911 (ILD) on the hard mask layer 03. An interlayer dielectric layer is an insulating material (such as silicon dioxide, silicon nitride, or a low dielectric constant material) deposited between metal interconnect layers or between a metal and a device after the front-end process of a semiconductor device is completed. It is used to achieve electrical isolation between different conductive layers and prevent short circuits and crosstalk.It should be noted that the substrate surface may not be smooth before the interlayer dielectric layer 0911 is deposited. In order to fully cover the uneven structure of the substrate surface, a relatively thick initial interlayer dielectric layer is usually deposited (e.g., the thickness of the initial interlayer dielectric layer is between 8000 Å and 15000 Å, for example, the thickness of the initial interlayer dielectric layer can be any one of 8000 Å, 8500 Å, 9000 Å, 9500 Å, 10000 Å, 10500 Å, 11000 Å, 11500 Å, 12000 Å, 12500 Å, 13000 Å, 14500 Å, 15000 Å, etc.). If the initial interlayer dielectric layer is larger than a preset thickness (e.g., the preset thickness is between 4000 Å and 6000 Å, such as any one of 4000 Å, 4200 Å, 4400 Å, 4600 Å, 4800 Å, 5000 Å, 5200 Å, 5400 Å, 5600 Å, 5800 Å, 6000 Å), then the interlayer dielectric layer can be planarized (e.g., mechanically polished) until the thickness of the interlayer dielectric layer is the preset thickness. On one hand, planarizing the interlayer dielectric layer makes its surface smooth and flat, providing a flat substrate for the next photolithography step; on the other hand, maintaining the thickness of the interlayer dielectric layer at the preset thickness avoids excessive stacking and difficulties in subsequent via etching. After forming the interlayer dielectric layer 0911, the interlayer dielectric layer 0911 can include a device region 203 for which a device is to be formed. The device location of the device to be formed can be defined in the device region 203, and the corresponding device can be formed at the device location. exist. Figure 3 In the example, the device is formed on the semiconductor substrate before the trench is formed.

[0054] exist Figure 2 and Figure 3In this process, the thickness of the third oxide layer 02 is the target thickness, which can be between 50 Å and 150 Å. For example, the target thickness can be any one of 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, etc. The third oxide layer 02 can be formed by performing a chemical vapor deposition (CVD) step and / or a thermal oxidation step. Thermal oxidation is a process of growing silicon dioxide (SiO2) by exposing the substrate to oxygen or water vapor in a high-temperature environment. Thermal oxidation includes dry oxygen oxidation and wet oxygen oxidation. Dry oxygen oxidation refers to using pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxygen oxidation refers to using water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxygen oxidation is faster than that of dry oxygen oxidation, but the oxide layer density is lower than that of dry oxygen oxidation. Chemical vapor deposition is a semiconductor manufacturing process in which a gaseous precursor undergoes a chemical reaction on a heated solid surface to generate a solid thin film, which is then deposited on a substrate. The thickness of the hard mask layer 03 is between 100 Å and 500 Å. For example, the hard mask layer 03 can be any one of 100 Å, 150 Å, 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, or 500 Å. Furthermore, after forming the hard mask layer 03, its surface can be planarized. Specifically, an asher (lasma asher) can be used to lightly clean or activate the surface of the hard mask layer 03, or the surface can be ground to remove organic contaminants, improve photoresist adhesion, and provide a high-temperature resistant and etching-resistant hard mask layer 03 for subsequent deep trench lithography and etching.

[0055] Step S102: Perform photolithography to form a first trench pattern and a second trench pattern in the first region and the second region, respectively.

[0056] This step is used to form a first groove pattern for forming a first groove on the first region and a second groove pattern for forming a second groove on the second region.

[0057] In a specific implementation, after forming a third oxide layer and a hard mask layer on the surface of the semiconductor substrate, a photolithography process can be performed to form a first trench pattern in the first region on the hard mask layer and a second trench pattern in the second region on the hard mask layer. First, a layer of photoresist with a thickness of approximately 3.6 μm is spin-coated onto the surface of the hard mask layer 03. Then, an exposure and development step is performed to define a first trench pattern for the first trench to be formed in the first region on the hard mask layer 03, and a second trench pattern for the second trench to be formed in the second region on the hard mask layer 03.

[0058] When the depth of the first trench to be formed is greater than the depth of the second trench to be formed, the width of the first trench pattern is greater than the width of the second trench pattern; when the depth of the first trench to be formed is less than the depth of the second trench to be formed, the width of the first trench pattern is greater than the width of the second trench pattern. In this embodiment, when forming the first trench pattern and the second trench pattern, a first etching rate for the first trench and a second etching rate for the second trench can be determined based on the depths of the first trench to be formed and the second trench to be formed, wherein the ratio of the first etching rate to the depth of the first trench is the same as the ratio of the second etching rate to the depth of the second trench. Thus, under the same etching environment and etching time, the time spent etching the first trench at the first etching rate and the time spent etching the second trench at the second etching rate are the same. Furthermore, the widths of the first trench pattern and the second trench pattern can be determined based on the first etching rate and the second etching rate. Then, a first trench pattern having the width of the first trench pattern and a second trench pattern having the width of the second trench pattern are formed in the first region and the second region, respectively. This allows control of the first etching rate of the first trench and the second etching rate of the second trench by adjusting the widths of the first and second trench patterns. Specifically, the width of the trench pattern is proportional to the depth of the trench to be formed. If the depth of the first trench to be formed is greater than the depth of the second trench to be formed, then the width of the first trench pattern is greater than the width of the first trench pattern; if the depth of the first trench to be formed is less than the depth of the second trench to be formed, then the width of the first trench pattern is less than the width of the first trench pattern. For example, when the first trench is used to form a deep trench isolation structure (DTI), the width of the corresponding first trench pattern can be approximately 2.7 μm; when the second trench is used to form a deep trench capacitor structure (DTC), the width of the corresponding second trench pattern can be approximately 1.5 μm.

[0059] Step S103: Perform an etching process to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region.

[0060] This step is used to form the second trench in the second region while forming the first trench in the first region.

[0061] The first trench and the second trench can be trenches of the same depth or trenches of different depths. When the first trench is a trench for forming a deep trench isolation structure (DTI) and the second trench is a trench for forming a deep trench capacitor structure (DTC), the first trench and the second trench are trenches of different depths, and the depth of the first trench is greater than the depth of the second trench.

[0062] like Figure 4 The diagram illustrates the formation of the first trench and the second trench in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in this application embodiment. After forming the first trench pattern in the first region 201 on the hard mask layer 03 and forming the second trench pattern in the second region 202 on the hard mask layer 03, an etching step can be performed on the semiconductor substrate using the first trench pattern and the second trench pattern as etching windows. Simultaneously, a first trench 04 corresponding to the first trench pattern is formed in the first region 201 on the substrate, and a second trench 05 corresponding to the second trench pattern is formed in the second region 202 on the substrate. In a specific implementation, a mixed gas of C4F8 (octafluorocyclobutane) and O2 (oxygen) can be used to perform reactive ion etching on the hard mask layer 03 and the third oxide layer 02 to form an etching window in the target region; and a mixed gas of SF6 (sulfur hexafluoride) and O2 (oxygen) can be used to etch the substrate, simultaneously forming the first trench 04 and the second trench 05 in the first region 201 and the second region 202 of the substrate.

[0063] It should be noted that, in this application, the widths of the first and second trench patterns are determined based on the depth of the trench to be formed, and the width of the trench pattern is proportional to the trench depth. Therefore, when the depth of the first trench to be formed is greater than the depth of the second trench, the width of the first trench pattern is also greater than the width of the second trench pattern. Thus, when performing an etching step on the semiconductor substrate using the first and second trench patterns as etching windows, because the width of the first trench pattern is greater than the width of the second trench pattern, the etching rate of the first trench is greater than the etching rate of the second trench. Consequently, within the same etching time, the depth of the first trench formed will be greater than the depth of the second trench. This allows for the simultaneous formation of first and second trenches of different depths in the first and second regions of the substrate through a single etching process.

[0064] Step S104: A first oxide layer is formed on the first trench wall and the second trench wall respectively.

[0065] This step is used to form an isolation layer in the first trench and the second trench respectively, which is the first oxide layer. The thickness of the first oxide layer is between 2000 Å and 6000 Å. For example, the thickness of the first oxide layer can be any one of 2000 Å, 2500 Å, 3000 Å, 3500 Å, 4000 Å, 4500 Å, 5000 Å, 5500 Å, 6000 Å, etc.

[0066] In one embodiment, no device is formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall, respectively. In this case, a high-temperature thermal oxidation process can be performed to form the first oxide layer on the first trench wall and the second trench wall, or a chemical vapor deposition process (such as high-density plasma-assisted chemical vapor deposition (HARP)) can be performed to form the first oxide layer on the first trench wall and the second trench wall.

[0067] Specifically, the formation of a first oxide layer on the first trench wall and the second trench wall by performing a high-temperature thermal oxidation process can be achieved through the following steps: first, perform a thermal oxidation step to form a second oxide layer on the first deep trench wall and the second trench wall; remove the second oxide layer; and then form a first oxide layer on the first deep trench wall and the second trench wall after removing the second oxide layer.

[0068] This embodiment involves forming a thin second oxide layer on the inner walls of the first and second trenches before forming the first oxide layer. This second oxide layer is a temporary sacrificial oxide layer. The second oxide layer is then removed to repair etching damage to the deep trench walls. The thickness of the second oxide layer is between 400 Å and 600 Å. For example, the thickness of the second oxide layer can be any one of 400 Å, 420 Å, 440 Å, 460 Å, 480 Å, 500 Å, 520 Å, 540 Å, 560 Å, 580 Å, or 600 Å.

[0069] The following combination Figures 5-7 The formation of the first oxide layer on the inner walls of the first and second trenches is described in detail. Figure 5 This is a schematic diagram illustrating the formation of a second oxide layer on the inner walls of the first and second trenches in the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this application embodiment. Figure 6 This is a schematic diagram illustrating the removal of the second oxide layer from the inner walls of the first and second trenches in the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this application embodiment. Figure 7This is a schematic diagram of the formation of a first oxide layer on the inner wall of the first trench and the inner wall of the second trench in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0070] like Figure 5 As shown, after forming a first trench 04 and a second trench 05 simultaneously on the first region 201 and the second region 202 on the substrate, a furnace tube process can be performed to grow a second oxide layer 06 on the sidewalls and bottom of the first trench 04 and a second oxide layer 06 on the sidewalls and bottom of the second trench 05 simultaneously through high-temperature thermal oxidation. Then, as... Figure 7 As shown, the second oxide layer 06 on the sidewalls and bottom of the first trench 04 and the second oxide layer 06 on the sidewalls and bottom of the second trench 05 can be removed by dry etching or wet etching. When removing the second oxide layer 06 by wet etching, a solution such as HF (hydrofluoric acid) or DHF (diluted hydrofluoric acid) can be used. This repairs the etching damage to the inner walls of the first trench 04 and the second trench 05, making the inner walls of the first trench 04 and the second trench 05 cleaner and smoother, providing a foundation for forming a high-quality first oxide layer on the inner walls of the first trench 04 and the second trench 05. Then, as... Figure 7 As shown, a furnace tube process can be performed to grow a first oxide layer 07 on the sidewall and bottom of the first trench 04 and simultaneously grow a first oxide layer 07 on the sidewall and bottom of the second trench 05 through high-temperature thermal oxidation.

[0071] In another embodiment, a first device and a second device are formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall, respectively, and the first trench is located between the first device and the second device. Figure 8 The diagram shown illustrates a pre-formed device on a substrate in the combined fabrication method of a deep trench isolation structure and a deep trench capacitor structure provided in this application embodiment. Before the formation of the first oxide layer on the inner walls of the first trench 04 and the second trench 05, respectively, the device is already formed in the device region 203 on the substrate. In this case, as... Figure 9 The diagram shown is a schematic of the formation of a first oxide layer on the inner wall of the first trench and the inner wall of the second trench in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application. A chemical vapor deposition process (such as high-density plasma-assisted chemical vapor deposition (HARP)) can be performed to form a first oxide layer on the first trench wall and the second trench wall.

[0072] It should be noted that if a high-temperature thermal oxidation process is used to form a first oxide layer on the walls of the first and second trenches, since a first and second device have already been formed on the substrate, and these devices are typically complex structures composed of multiple materials (such as metals, polysilicon, etc.), the high-temperature thermal oxidation process may cause the metal in the device to melt or diffuse, or it may cause the polysilicon to recrystallize or deform, thereby damaging the first and / or second devices. In this embodiment, by using chemical vapor deposition to form a first oxide layer on the inner walls of the first and second trenches of the substrate on which the device is pre-formed, damage to the device on the substrate caused by high-temperature thermal oxidation can be effectively avoided.

[0073] Step S105: Form a first conductive layer on the first oxide layer.

[0074] Step S106: Form at least one set of combined layers on the first conductive layer, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer.

[0075] Steps S105 and S106 are used to form a deep trench isolation structure (DTI) for deep trench isolation in the first trench and a deep trench capacitor structure (DTC) in the second trench.

[0076] The first trench in the first region, the first oxide layer in the first trench, and the combined layer on the first oxide layer in the first trench together constitute a deep trench isolation structure, and the second trench in the second region, the first oxide layer in the second trench, and the combined layer on the first oxide layer in the second trench together constitute a deep trench capacitor structure.

[0077] The number of combined layers in the deep trench isolation structure can be one, two, three, etc. For example, the deep trench isolation structure is a structure composed of a first trench, a first oxide layer in the first trench, a first conductive layer on the first oxide layer in the first trench, a dielectric layer on the first conductive layer on the first oxide layer in the first trench, and a second conductive layer on the dielectric layer on the first conductive layer on the first oxide layer in the first trench; or, for example, the deep trench isolation structure is a structure composed of a first trench, a first oxide layer in the first trench, a first conductive layer on the first oxide layer in the first trench, a first dielectric layer on the first conductive layer on the first oxide layer in the first trench, a first second conductive layer on the first dielectric layer, and the first... The structure can be categorized as follows: For example, the deep trench isolation structure can be composed of a first trench, a first oxide layer in the first trench, a first conductive layer on the first oxide layer in the first trench, a first dielectric layer on the first conductive layer on the first oxide layer in the first trench, a first second conductive layer on the first dielectric layer, a second dielectric layer on the first dielectric layer, a second second conductive layer on the first second conductive layer, a second second conductive layer on the second dielectric layer, a third dielectric layer on the second second conductive layer, and a third second conductive layer on the third dielectric layer; etc. For ease of explanation, this application embodiment uses a structure comprising a first trench, a first oxide layer in the first trench, a first conductive layer on the first oxide layer in the first trench, a dielectric layer on the first conductive layer on the first oxide layer in the first trench, and a second conductive layer on the dielectric layer on the first conductive layer on the first oxide layer in the first trench as an example for detailed description.

[0078] Accordingly, the number of combined layers in the deep trench capacitor structure can be one, two, three, etc. For example, the deep trench capacitor structure is composed of a second trench, a first oxide layer in the second trench, a first conductive layer on the first oxide layer in the second trench, a dielectric layer on the first conductive layer on the first oxide layer in the second trench, and a second conductive layer on the dielectric layer on the first conductive layer on the first oxide layer in the second trench; or, for example, the deep trench isolation structure is composed of a second trench, a first oxide layer in the second trench, a first conductive layer on the first oxide layer in the second trench, a first dielectric layer on the first conductive layer on the first oxide layer in the second trench, a first second conductive layer on the first dielectric layer, and a first... The structure can be categorized as follows: For example, the deep trench isolation structure can be composed of a second trench, a first oxide layer in the second trench, a first conductive layer on the first oxide layer in the second trench, a first dielectric layer on the first conductive layer on the first oxide layer in the second trench, a first second conductive layer on the first dielectric layer, a second dielectric layer on the first dielectric layer, a second second conductive layer on the first second conductive layer, a second second conductive layer on the second dielectric layer, a third dielectric layer on the second second conductive layer, and a third second conductive layer on the third dielectric layer; etc. For ease of explanation, this application embodiment uses a deep trench capacitor structure composed of a second trench, a first oxide layer in the second trench, a first conductive layer on the first oxide layer in the second trench, a dielectric layer on the first conductive layer on the first oxide layer in the second trench, and a second conductive layer on the dielectric layer on the first conductive layer on the first oxide layer in the second trench as an example for detailed description.

[0079] The following combination Figures 10-12 The formation of the deep trench isolation structure and the deep trench capacitor structure is described in detail. Figure 10 This is a schematic diagram illustrating the formation of a first conductive layer on the first oxide layer in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in this application embodiment. Figure 11 This is a schematic diagram of the dielectric layer formed on the first conductive layer in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application. Figure 12 This is a schematic diagram of the formation of a second conductive layer on the dielectric layer in the combined preparation method of the deep trench isolation structure and the deep trench capacitor structure provided in the embodiments of this application.

[0080] In specific implementation methods, such as Figure 10As shown, after forming a first oxide layer 07 on the inner walls of the first trench 04 and the second trench 05, a furnace tube process can be performed on the semiconductor substrate to deposit a first conductive layer 08 on the first oxide layer 07 and on the surface of the hard mask layer 03 on the substrate surface. The material of the first conductive layer 08 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)). The thickness of the first conductive layer 08 is between 1500 Å and 2500 Å. For example, the thickness of the first conductive layer 08 can be any one of 1500 Å, 1600 Å, 1700 Å, 1800 Å, 1900 Å, 2000 Å, 2100 Å, 2200 Å, 2300 Å, 2400 Å, 2500 Å, etc.

[0081] like Figure 11 As shown, after forming a first conductive layer 08 on the first oxide layer 07 and the surface of the hard mask layer 03 on the substrate surface, an atomic layer deposition step can be performed to form a dielectric layer 09 on the first conductive layer 08. The dielectric layer 09 can be a single-layer film (such as an oxide layer) or a composite film composed of an oxide layer and a high-dielectric-constant layer (high-k dielectric). The oxide layer can be silicon dioxide, and the high-dielectric-constant layer can be, but is not limited to, at least one of hafnium dioxide (HfO2), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and lanthanum oxide (La2O3). It should be noted that when the dielectric layer 09 is a composite film layer, on the one hand, it can solve the quantum tunneling effect caused by the thinness of a single film layer (such as an oxide layer) being too small (such as less than 2nm), thus avoiding a sharp increase in gate leakage current; on the other hand, the oxide layer in the composite film layer is adjacent to the first conductive layer 08, which can prevent the interface roughness caused by the high dielectric constant layer directly contacting the first conductive layer 08 (such as polysilicon or metal).

[0082] like Figure 12 As shown, after forming a dielectric layer 09 on the first conductive layer 08, a furnace tube process can be performed to deposit a second conductive layer 10 on the dielectric layer 09. That is, the second conductive layer 10 is filled on the dielectric layer 09 in the first trench 04 and the second trench 05, and the second conductive layer 10 is formed on the dielectric layer 09 on the surface of the substrate. Similar to the first conductive layer 08, the material of the second conductive layer 10 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0083] When the second trench 05 is used to form a deep trench capacitor structure (DTC), the first conductive layer 08 serves as the lower electrode of the DTC, and the second conductive layer 10 serves as the upper electrode of the DTC. Furthermore, the second trench 05, the first oxide layer 07 in the second trench 05, the first conductive layer 08 in the second trench 05, the dielectric layer 09 in the second trench 05, and the second conductive layer 10 in the second trench 05 together constitute the deep trench capacitor structure (DTC).

[0084] The deep trench isolation structure and deep trench capacitor structure jointly fabricated by the embodiments of this application include a first oxide layer, a conductive layer, a dielectric layer, and a conductive layer in both the deep trench isolation structure and the deep trench capacitor structure. The deep trench isolation structure can achieve electrical isolation between devices, and the deep trench capacitor structure can be used to construct high-density, high-performance on-chip capacitors. Therefore, the joint fabrication method of deep trench isolation structure and deep trench capacitor structure provided by the embodiments of this application can simultaneously form deep trench isolation structure and deep trench capacitor structure on the substrate in a single process, effectively reducing the number of photolithography steps, reducing manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the synergistic design of deep trench isolation structure and deep trench capacitor structure in this application can effectively utilize the vertical space of the chip, avoid the waste of planar layout (such as the combination of capacitor and isolation structure in DRAM), increase chip density, and improve overall synergistic optimization.

[0085] Furthermore, after depositing the second conductive layer 10 on the dielectric layer 09, the second conductive layer and the dielectric layer on the substrate surface can be removed. When removing the second conductive layer and the dielectric layer on the substrate surface, a portion of the first conductive layer can be removed simultaneously, or the first conductive layer can be left unremoved. This application does not impose any limitations on this. By removing the second conductive layer and the dielectric layer on the substrate surface, the first conductive layer on the substrate surface is exposed, preparing for the formation of the lower electrode of the deep trench capacitor structure.

[0086] like Figure 13 The diagram shown is a schematic of removing the second conductive layer and dielectric layer in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in this application embodiment. The second conductive layer 10 is filled on the dielectric layer 09 in the deep trench and the second conductive layer 10 is formed on the dielectric layer 09 on the substrate surface. The second conductive layer 10 and the dielectric layer 09 on the substrate surface can be removed by mechanical grinding or etching until the first conductive layer 08 on the substrate surface is exposed.

[0087] Furthermore, after removing the second conductive layer and dielectric layer on the substrate surface, for the second trench, the region where the lower electrode of the deep trench capacitor structure to be formed is located can be defined on the first conductive layer formed on the substrate surface by photolithography; an etching step is performed to remove the first conductive layer deposited in the region other than the region where the lower electrode is located in the first conductive layer formed on the substrate surface, thereby forming the lower electrode.

[0088] This step is used to form the lower electrode of the deep trench capacitor structure.

[0089] like Figure 14 The diagram shown illustrates the formation of the lower electrode plate in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in this application embodiment. For the second trench, after the first conductive layer 08 is exposed, a layer of photoresist can be spin-coated onto the first conductive layer 08, and an exposure and development step is performed to define the area where the lower electrode plate of the deep trench capacitor structure to be formed is located on the first conductive layer 08. Then, a wet etching or dry etching step is performed to remove the first conductive layer 08 deposited in the area other than the area where the lower electrode plate is located in the first conductive layer 08 formed on the substrate surface. Thus, the remaining first conductive layer 08 on the substrate surface will form the lower electrode plate of the deep trench capacitor structure.

[0090] It should be noted that if the semiconductor substrate has not yet formed the corresponding device, after the lower electrode is formed, a first device and a second device can be formed on both sides of the first trench, respectively. In this way, electrical isolation between the first device and the second device can be achieved through the deep trench isolation structure formed in the first trench.

[0091] Furthermore, after forming the lower electrode, an interlayer dielectric layer can be formed on the substrate surface where the lower electrode is formed. This step is used to form an interlayer dielectric layer on the substrate surface to provide electrical isolation between multilayer metal interconnects, enable via connections, reduce parasitic capacitance, and ensure subsequent processes through surface planarization, thereby ensuring normal chip operation and high performance.

[0092] like Figure 15The diagram shown is a schematic of the formation of an interlayer dielectric layer in the combined fabrication method of the deep trench isolation structure and the deep trench capacitor structure provided in this application embodiment. After the lower electrode is formed, chemical vapor deposition or plasma-enhanced tetraethyl orthosilicate CVD (PECVD TEOS) can be performed to form an interlayer dielectric layer 11 (ILD (Interlayer Dielectric). The interlayer dielectric layer refers to a layer of insulating material (such as silicon dioxide, silicon nitride, or low dielectric constant material) deposited between metal interconnect layers or between metal and device after the front-end process of semiconductor device is completed. It is used to achieve electrical isolation between different conductive layers and prevent short circuits and crosstalk.

[0093] It should be noted that the substrate surface may not be smooth before the interlayer dielectric layer is deposited. In order to fully cover the uneven structure of the substrate surface, a relatively thick initial interlayer dielectric layer is usually deposited (e.g., the thickness of the initial interlayer dielectric layer is between 8000 Å and 15000 Å, for example, the thickness of the initial interlayer dielectric layer can be any one of 8000 Å, 8500 Å, 9000 Å, 9500 Å, 10000 Å, 10500 Å, 11000 Å, 11500 Å, 12000 Å, 12500 Å, 13000 Å, 14500 Å, 15000 Å, etc.). If the deposited interlayer dielectric layer is larger than a preset thickness (e.g., the preset thickness is between 4000 Å and 6000 Å, such as any one of 4000 Å, 4200 Å, 4400 Å, 4600 Å, 4800 Å, 5000 Å, 5200 Å, 5400 Å, 5600 Å, 5800 Å, 6000 Å, etc.), then the interlayer dielectric layer can be planarized (e.g., mechanically polished) until its thickness reaches the preset thickness. On one hand, planarizing the interlayer dielectric layer ensures a smooth surface, providing a flat substrate for the next photolithography step; on the other hand, maintaining the interlayer dielectric layer at the preset thickness avoids excessive stacking and difficulties in subsequent via etching.

[0094] Furthermore, after forming the interlayer dielectric layer, for the second trench, the location of the via can be defined on the interlayer dielectric layer by photolithography; then, an etching step is performed to form vias on the interlayer dielectric layer for connecting the lower electrode and the upper electrode to the metal layer respectively, wherein the upper electrode is the second conductive layer in the second trench.

[0095] This step is used to etch through-holes so that subsequent metal layers can contact the first and second conductive layers, thereby achieving a low-resistance, high-reliability electrical connection between the electrodes (upper and lower plates) of the deep trench capacitor structure and the upper circuit.

[0096] like Figure 16 The diagram illustrates the formation of vias in the interlayer dielectric layer during the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this application embodiment. After forming the interlayer dielectric layer 11, via locations for connecting the lower electrode and the upper electrode to the metal layer can be defined on the interlayer dielectric layer 11. Then, an etching step is performed to form vias 13 for connecting the lower electrode to the metal layer and vias 12 for connecting the upper electrode to the metal layer on the interlayer dielectric layer 11. This provides a pathway for interconnection between the capacitor electrode and the metal layer.

[0097] like Figure 17 The diagram shown illustrates the filling of vias in the combined fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this application embodiment. After forming vias 13 for connecting the lower electrode to the metal layer and vias 12 for connecting the upper electrode to the metal layer on the interlayer dielectric layer 11, conductive material can be filled into the vias 13 and vias 12 to form conductive channels. The conductive material may include, but is not limited to, one of tungsten (W), copper (Cu), etc.

[0098] The method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure provided in this application includes the following steps: providing a semiconductor substrate, wherein the substrate has a first region and a second region; performing a photolithography process to form a first trench pattern and a second trench pattern in the first region and the second region, respectively; performing an etching process to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region; forming a first oxide layer on the first trench wall and the second trench wall, respectively; forming a first conductive layer on the first oxide layer; forming at least one set of combined layers on the first conductive layer, wherein the combined layers include a dielectric layer and a second conductive layer on the dielectric layer; the first trench in the first region, the first oxide layer in the first trench, and the first conductive layer and combined layer on the first oxide layer in the first trench together constitute a deep trench isolation structure, and the second trench in the second region, the first oxide layer in the second trench, and the first conductive layer and combined layer on the first oxide layer in the second trench together constitute a deep trench capacitor structure.

[0099] As can be seen, the method for jointly fabricating deep trench isolation structures and deep trench capacitor structures provided in this application embodiment can simultaneously form a first trench and a second trench in a first region and a second region of the substrate through a single etching process. Both the deep trench isolation structure formed in the first trench and the deep trench capacitor structure formed in the second trench include a first oxide layer, a conductive layer, a dielectric layer, and a conductive layer. The deep trench isolation structure can achieve electrical isolation between devices, and the deep trench capacitor structure can be used to construct high-density, high-performance on-chip capacitors. Therefore, the method for jointly fabricating deep trench isolation structures and deep trench capacitor structures provided in this application embodiment can simultaneously form deep trench isolation structures and deep trench capacitor structures on the substrate in a single process, effectively reducing the number of photolithography steps, lowering manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. Furthermore, the collaborative design of the deep trench isolation structure and deep trench capacitor structure in this application can effectively utilize the vertical space of the chip, avoid wasting planar layout (such as the combination of capacitors and isolation structures in DRAM), increase chip density, and improve overall collaborative optimization.

[0100] The second embodiment of this application provides a semiconductor device, which can be prepared by the combined preparation method of deep trench isolation structure and deep trench capacitor structure provided in the first embodiment of this application. For details, please refer to the detailed description of the combined preparation method of deep trench isolation structure and deep trench capacitor structure provided in the first embodiment of this application, which will not be repeated here.

[0101] As can be seen, the deep trench isolation structure and deep trench capacitor structure included in the semiconductor device provided in the second embodiment of this application both include a first oxide layer, a conductive layer, a dielectric layer, and a conductive layer. The deep trench isolation structure can achieve electrical isolation between devices, and the deep trench capacitor structure can be used to construct high-density, high-performance on-chip capacitors. Therefore, the joint fabrication method of the deep trench isolation structure and deep trench capacitor structure provided in this embodiment of the application can simultaneously form the deep trench isolation structure and the deep trench capacitor structure on the substrate in a single process, effectively reducing the number of photolithography steps when forming the deep trench isolation structure and the deep trench capacitor structure, reducing manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the synergistic design of the deep trench isolation structure and the deep trench capacitor structure in this application can effectively utilize the vertical space of the chip, avoid the waste of planar layout (such as the combination of capacitor and isolation structure in DRAM), increase chip density, and improve overall synergistic optimization.

[0102] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for jointly fabricating a deep trench isolation structure and a deep trench capacitor structure, characterized in that, The method includes: A semiconductor substrate is provided, wherein a first region and a second region are present on the substrate; A photolithography process is performed to form a first trench pattern and a second trench pattern in the first region and the second region, respectively; An etching process is performed to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region. A first oxide layer is formed on the first trench wall and the second trench wall respectively; A first conductive layer is formed on the first oxide layer; At least one set of combined layers is formed on the first conductive layer, the combined layer including a dielectric layer and a second conductive layer on the dielectric layer; The first trench in the first region, the first oxide layer in the first trench, and the first conductive layer and combined layer on the first oxide layer in the first trench together constitute a deep trench isolation structure, and the second trench in the second region, the first oxide layer in the second trench, and the first conductive layer and combined layer on the first oxide layer in the second trench together constitute a deep trench capacitor structure.

2. The method according to claim 1, characterized in that, The depth of the first groove to be formed is greater than the depth of the second groove to be formed, and the width of the first groove pattern is greater than the width of the second groove pattern.

3. The method according to claim 1, characterized in that, Before the first oxide layer is formed on the first trench wall and the second trench wall respectively, a first device and a second device have been formed on the substrate, and the first trench is located between the first device and the second device.

4. The method according to claim 3, characterized in that, The formation of a first oxide layer on the first trench wall and the second trench wall includes: A chemical vapor deposition process is performed to form a first oxide layer on the first trench wall and the second trench wall.

5. The method according to claim 1, characterized in that, No device is formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall; The formation of a first oxide layer on the first trench wall and the second trench wall includes: A first oxide layer is formed on the first trench wall and the second trench wall by performing a high-temperature thermal oxidation process or chemical vapor deposition.

6. The method according to claim 5, characterized in that, The formation of a first oxide layer on the first trench wall and the second trench wall includes: A second oxide layer is formed on the first deep trench wall and the second trench wall; Remove the second oxide layer; A first oxide layer is formed on the first deep trench wall and the second trench wall where the second oxide layer is removed.

7. The method according to claim 1, characterized in that, The photolithography process, which forms a first trench pattern and a second trench pattern in the first region and the second region respectively, includes: A third oxide layer and a hard mask layer are formed on the surface of the semiconductor substrate; A first trench pattern is formed in the first region on the hard mask layer using photolithography, and a second trench pattern is formed in the second region on the hard mask layer.

8. The method according to claim 1, characterized in that, The step of forming a first conductive layer on the first oxide layer of the first deep trench and the second deep trench includes: A furnace tube process is performed to deposit a first conductive layer on the first oxide layer in the first deep trench and the second deep trench and on the surface of the hard mask layer on the substrate surface.

9. The method according to claim 8, characterized in that, The formation of at least one set of combined layers on the first conductive layer includes: An atomic layer deposition step is performed to form a dielectric layer on the first conductive layer; Perform a furnace tube process to deposit a second conductive layer on the dielectric layer.

10. The method according to claim 9, characterized in that, After depositing a second conductive layer on the dielectric layer, the method further includes: Remove the second conductive layer and dielectric layer from the surface of the substrate.

11. The method according to claim 10, characterized in that, After removing the second conductive layer and dielectric layer from the substrate surface, the method further includes: For the second trench, the area where the lower electrode of the deep trench capacitor structure to be formed is located is defined on the first conductive layer formed on the substrate surface by photolithography. An etching step is performed to remove the first conductive layer deposited in the area outside the region where the lower electrode plate is located from the first conductive layer formed on the substrate surface, thereby forming the lower electrode plate.

12. The method according to claim 11, characterized in that, After forming the lower electrode plate, the method further includes: An interlayer dielectric layer is formed on the surface of the substrate on which the lower electrode plate is formed.

13. The method according to claim 12, characterized in that, The method further includes: For the second trench, via locations are defined on the interlayer dielectric layer using photolithography. An etching step is performed to form through-holes on the interlayer dielectric layer for connecting the lower electrode and the upper electrode to the metal layer, wherein the upper electrode is the second conductive layer in the second trench.

14. The method according to claim 1, characterized in that, The method further includes: A first device and a second device are formed on both sides of the first trench, respectively. The first device and the second device are one of bipolar devices, CMOS devices, and DMOS devices.

15. A semiconductor device, characterized in that, It is prepared by the method described in any one of claims 1 to 14.

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