A method for manufacturing a deep trench isolation structure and a deep trench isolation structure

Abstract

The application discloses a preparation method of a deep trench isolation structure and the deep trench isolation structure. The method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first device region and a second device region; forming a deep trench for a deep trench isolation structure between the first device region and the second device region; forming a first oxide layer on a wall of the deep trench; forming a first conductive layer on the first oxide layer in the deep trench; forming at least one set of combined layers on the first conductive layer, so as to form a capacitor structure in the deep trench, wherein the combined layers comprise a dielectric layer and a second conductive layer on the dielectric layer; and the deep trench, the first oxide layer and the capacitor structure jointly form the deep trench isolation structure between the first device region and the second device region. The deep trench isolation structure formed by the scheme provided by the application can be used for isolating devices and can also be used as a capacitor, so that the process steps are simplified and the process complexity is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for preparing a deep trench isolation structure and the deep trench isolation structure itself. Background Technology

[0002] DTI (Dual Insulation Transmission) technology achieves physical and electrical isolation between power devices and logic circuits by etching insulating trenches several micrometers or even tens of micrometers deep in a silicon substrate. This significantly reduces substrate parasitic current and crosstalk, improving the stability and reliability of devices under high-voltage operating conditions. Meanwhile, Deep Trench Capacitor (DTC) technology has also gained widespread application due to its high capacitance density per unit area, excellent capacitance stability, and good compatibility with CMOS processes. DTC technology integrates large-capacitance capacitors within a limited chip area by constructing capacitor structures within deep trenches, effectively supporting transient current response under high-frequency switching and improving power integrity. However, existing technologies for forming DTI and DTC involve complex and cumbersome processes. Summary of the Invention

[0003] This application provides a method for fabricating a deep trench isolation structure and the deep trench isolation structure itself. This deep trench isolation structure can be used as both an isolation device and a capacitor, simplifying the fabrication process and reducing its complexity. The specific solution is as follows: In a first aspect, embodiments of this application provide a method for fabricating a deep trench isolation structure. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first device region and a second device region; forming a deep trench for the deep trench isolation structure between the first device region and the second device region; forming a first oxide layer on the wall of the deep trench; forming a first conductive layer on the first oxide layer in the deep trench; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the deep trench, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer, and the capacitor structure together constitute a deep trench isolation structure between the first device region and the second device region.

[0004] Optionally, forming a first oxide layer on the deep trench wall includes: performing a thermal oxidation step to form a second oxide layer on the deep trench wall; removing the second oxide layer; and forming a first oxide layer on the deep trench wall where the second oxide layer has been removed.

[0005] Optionally, forming a deep trench for a deep trench isolation structure between the first device region and the second device region includes: forming a third oxide layer and a hard mask layer on the surface of the semiconductor substrate; defining a target region for forming the deep trench between the first device region and the second device region on the hard mask layer by photolithography; and performing an etching step to form the deep trench for the deep trench isolation structure in the target region on the hard mask layer.

[0006] Optionally, forming a first conductive layer on the first oxide layer in the deep trench includes: performing a furnace tube process to deposit the first conductive layer on the first oxide layer in the deep trench and on the surface of the hard mask layer on the substrate surface.

[0007] Optionally, forming at least one set of combined layers on the first conductive layer includes: performing an atomic layer deposition step to form a dielectric layer on the first conductive layer; and performing a furnace tube process to deposit a second conductive layer on the dielectric layer.

[0008] Optionally, after depositing the second conductive layer on the dielectric layer, the method further includes removing the second conductive layer and the dielectric layer from the surface of the substrate.

[0009] Optionally, after removing the second conductive layer and dielectric layer on the substrate surface, the method further includes: defining the region where the lower electrode of the capacitor structure to be formed is located on the first conductive layer formed on the substrate surface by photolithography; performing an etching step to remove the first conductive layer deposited in the region other than the region where the lower electrode is located in the first conductive layer formed on the substrate surface, thereby forming the lower electrode.

[0010] Optionally, after forming the lower electrode, the method further includes: forming an interlayer dielectric layer on the substrate surface where the lower electrode is formed; performing an etching step to form through holes on the interlayer dielectric layer for connecting the lower electrode and the upper electrode to a metal layer, wherein the upper electrode is the second conductive layer.

[0011] Optionally, the method further includes: forming a first device in the first device region and forming a second device in the second device region, wherein the first device and the second device are respectively a bipolar device, a CMOS device, and a DMOS device.

[0012] Secondly, embodiments of this application provide a deep trench isolation structure, the deep trench isolation structure comprising: a semiconductor substrate, the semiconductor substrate including a first device region on which a first device is formed and a second device region on which a second device is formed; a deep trench for the deep trench isolation structure being formed between the first device region and the second device region; a first oxide layer being formed on the wall of the deep trench; and a capacitor structure being formed in the deep trench, the capacitor structure including a first conductive layer formed on the first oxide layer in the deep trench and at least one set of combined layers formed on the first conductive layer, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer and the capacitor structure together constitute the deep trench isolation structure of the first device region and the second device region.

[0013] Thirdly, this application also provides a semiconductor device prepared by the method described in the first or second aspect.

[0014] Compared with the prior art, this application has the following advantages: The method for fabricating a deep trench isolation structure provided in this application includes the following steps: providing a semiconductor substrate, the semiconductor substrate including a first device region and a second device region; forming a deep trench for a deep trench isolation structure between the first device region and the second device region; forming a first oxide layer on the wall of the deep trench; forming a first conductive layer on the first oxide layer in the deep trench; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the deep trench, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer and the capacitor structure together constitute a deep trench isolation structure between the first device region and the second device region.

[0015] As can be seen, the deep trench isolation structure fabrication method provided in this application provides a capacitor structure comprising a conductive layer, a dielectric layer, and a conductive layer. On one hand, the deep trench isolation structure can serve as a DTC (deep trench capacitor) to construct high-density, high-performance on-chip capacitors, applicable to power management chips, charge pumps in BCD processes, and filter circuits. Furthermore, DTCs can achieve larger capacitance values ​​per unit area (greater than planar capacitors), significantly saving chip area. On the other hand, the deep trench isolation structure, located between the first device region and the second device region, can serve as a DTI (deep trench isolation) to achieve electrical isolation between the first device in the first device region and the second device in the second device region. This plays a crucial role, especially in high-voltage integrated circuits, CMOS image sensors (CIS), and 3D integration. DTI can effectively block leakage paths and suppress crosstalk, thereby improving device reliability and performance. Therefore, the deep trench isolation structure fabrication method provided in this application embodiment can place DTI and DTC in the same deep trench isolation structure. The formed deep trench isolation structure can be used as both an isolation device and a capacitor, effectively reducing the number of photolithography steps when forming DTI and DTC, reducing manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the co-design of DTI and DTC in this application can effectively utilize the vertical space of the chip, avoid the waste of planar layout (such as the combination of capacitor and isolation structure in DRAM), increase chip density, and improve overall co-optimization. Attached Figure Description

[0016] Figure 1 This is a flowchart of the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0017] Figure 2 This is a schematic diagram of the semiconductor substrate provided in the method for fabricating the deep trench isolation structure provided in the embodiments of this application.

[0018] Figure 3 This is a schematic diagram of the deep trench structure being formed in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0019] Figure 4 This is a schematic diagram of the formation of a second oxide layer on the deep trench wall in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0020] Figure 5 This is a schematic diagram of removing the second oxide layer from the deep trench wall in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0021] Figure 6 This is a schematic diagram of the formation of a first oxide layer on the deep trench wall in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0022] Figure 7 This is a schematic diagram of the formation of a first conductive layer on the first oxide layer in the preparation method of the deep trench isolation structure provided in this application embodiment.

[0023] Figure 8 This is a schematic diagram of the formation of a dielectric layer on the first conductive layer in the method for preparing the deep trench isolation structure provided in this application embodiment.

[0024] Figure 9 This is a schematic diagram of the formation of a second conductive layer on the dielectric layer in the preparation method of the deep trench isolation structure provided in this application embodiment.

[0025] Figure 10 This is a schematic diagram of the removal of the second conductive layer and dielectric layer in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0026] Figure 11 This is a schematic diagram of the formation of the lower electrode plate in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0027] Figure 12 This is a schematic diagram of the formation of the interlayer dielectric layer in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0028] Figure 13 This is a schematic diagram of forming through holes in the interlayer dielectric layer in the method for preparing the deep trench isolation structure provided in the embodiments of this application.

[0029] Figure 14 This is a schematic diagram of filling through holes in the interlayer dielectric layer in the method for preparing the deep trench isolation structure provided in this application embodiment. Detailed Implementation

[0030] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0031] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0032] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0033] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0034] The following is a further explanation of the existing technology: BCD (Bipolar-CMOS-DMOS) refers to a semiconductor process technology that integrates bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and diffused metal-oxide-semiconductor (DMOS) on the same chip. It has been widely used in high-growth fields such as new energy vehicles, smart homes, 5G communications, and industrial control.

[0035] To avoid electrical isolation between different device regions in BCD (Browser-Chip-Device) processes, the industry has proposed Deep Trench Isolation (DTI) technology. DTI technology achieves physical and electrical isolation between power devices and logic circuits by etching insulating trenches several micrometers or even tens of micrometers deep in the silicon substrate. This significantly reduces substrate parasitic current and crosstalk, improving the stability and reliability of devices under high-voltage operating conditions. Meanwhile, Deep Trench Capacitor (DTC) technology has also gained widespread application due to its high capacitance density per unit area, excellent capacitance stability, and good compatibility with CMOS processes. DTC technology integrates large-capacitance capacitors within a limited chip area by constructing capacitor structures within deep trenches, effectively supporting transient current response under high-frequency switching and improving power integrity.

[0036] Currently, semiconductor manufacturing processes typically involve two separate steps to form DTC and DTI, which not only makes the process complex and cumbersome but also reduces chip integration.

[0037] For the reasons mentioned above, the first embodiment of this application provides a method for preparing a deep trench isolation structure. The resulting deep trench capacitor can be used as both an isolation device and a capacitor, which simplifies the process steps and reduces the complexity of the process.

[0038] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0039] The following, combined with Figures 1-14 This application describes a method for preparing a deep trench isolation structure according to an embodiment.

[0040] like Figure 1 The diagram shown is a flowchart of the preparation method of the deep trench isolation structure provided in this application, including the following steps S101 to S105.

[0041] Step S101: Provide a semiconductor substrate, the semiconductor substrate including a first device region and a second device region.

[0042] In semiconductor manufacturing processes, a semiconductor substrate refers to the basic material used to fabricate semiconductor devices. Semiconductor substrates can include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process.

[0043] The semiconductor substrate may include at least one first device region and at least one second device region. The first device region and the second device region refer to predefined local areas on the semiconductor substrate used to manufacture electronic devices to achieve corresponding electronic device functions. The first device region is the region used to form the first device, and the second device region is the region used to form the second device. The first device and the second device may be devices in a BCD device family. For example, the first device may be one of the following BCD devices: Bipolar Transistor, CMOS, or DMOS; and the second device may be one of the following BCD devices other than the first device.

[0044] In one embodiment, a first device has been pre-formed in the first device region, and a second device has been pre-formed in the second device region. In another embodiment, the first device region has not yet formed the first device, and the second device region has not yet formed the second device. This application does not impose specific limitations in this regard.

[0045] like Figure 2 The diagram shown is a schematic diagram of the semiconductor substrate provided in the method for fabricating a deep trench isolation structure according to an embodiment of this application. The semiconductor substrate may include an epitaxial layer 03 and a substrate layer 01. The epitaxial layer 03 includes a first device region 201 and a second device region 202.

[0046] Among them, the epitaxial layer 03 is located on the substrate layer 01, and an N-well 02 is formed between the epitaxial layer 03 and the substrate layer 01. An N-well is a local N-type doped region formed in a P-type semiconductor substrate (or P-type epitaxial layer) through ion implantation and diffusion processes. It can be used to accommodate PMOS transistors and achieve electrical isolation between devices.

[0047] An epitaxial layer is a new material layer with a specific doping concentration and crystal structure grown on a raw semiconductor substrate through a process called epitaxy (or simply Epi). This process allows control over the composition, thickness, and doping type and concentration of the new layer, thereby achieving specific electrical properties. The epitaxial layer can be atomically matched to the substrate, forming a continuous crystal structure. The epitaxial layer can be the same material as the substrate (homogeneous epitaxy) or a different material (heterogeneous epitaxy). Specifically, the epitaxial layer can be silicon-based or silicon carbide-based.

[0048] Shallow trenches 04 are formed on the surface of epitaxial layer 03 for shallow trench isolation (STI). Shallow trenches 04 are used to achieve electrical isolation between devices, prevent leakage and parasitic conduction, and ensure that each transistor operates independently.

[0049] After forming the shallow trench 04, an insulating material, such as silicon dioxide (SiO2), can be filled into the shallow trench 04 until the thickness of the silicon dioxide on the surface of the epitaxial layer 03 reaches the target thickness, forming the third oxide layer 05. That is, the thickness of the third oxide layer 05 is the target thickness, which is between 50 Å and 150 Å. For example, the target thickness can be any one of 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, or 150 Å. The third oxide layer 05 can be formed by performing a chemical vapor deposition (CVD) step and / or a thermal oxidation step. Thermal oxidation is a process of growing silicon dioxide (SiO2) by exposing the substrate to oxygen or water vapor in a high-temperature environment. Thermal oxidation includes dry oxidation and wet oxidation. Dry oxidation refers to using pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxidation refers to using water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxidation is faster than that of dry oxidation, but the oxide layer density is lower than that of dry oxidation. Chemical vapor deposition is a semiconductor manufacturing process that uses a gaseous precursor to undergo a chemical reaction on a heated solid surface to generate a solid film, which is then deposited on a substrate.

[0050] After forming the third oxide layer 05, a hard mask layer 06 can be formed on the third oxide layer 05. In some examples, the thickness of the hard mask layer 06 can be between 100 Å and 800 Å. For example, the hard mask layer 06 can be any one of 100 Å, 150 Å, 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, 550 Å, 600 Å, 750 Å, and 800 Å. The material of the hard mask layer 06 includes, but is not limited to, at least one of silicon nitride (Si3N4) hard mask layer, silicon dioxide (SiO2) hard mask layer, metal hard mask layer, and amorphous carbon hard mask layer. In this embodiment, silicon nitride is used as an example for the hard mask layer 06.

[0051] After forming the hard mask layer 06, its surface can be planarized. Specifically, an asher (lasma asher) can be used to lightly clean or activate the surface of the hard mask layer 06, or the surface can be ground to remove organic contaminants, improve photoresist adhesion, and provide a high-temperature resistant and etching-resistant hard mask layer 06 for subsequent deep trench lithography and etching.

[0052] Step S102: A deep trench for a deep trench isolation structure is formed between the first device region and the second device region.

[0053] This step is used to form a deep trench between the first device region and the second device region for high-performance electrical isolation of the first device to be formed in the first device region and the second device to be formed in the second device region.

[0054] In a specific implementation, after forming a third oxide layer and a hard mask layer on the surface of the semiconductor substrate, a target area for forming the deep trench can be defined between the first device area and the second device area on the hard mask layer using a photolithography process; an etching step is then performed to form the deep trench for the deep trench isolation structure in the target area on the hard mask layer.

[0055] like Figure 3 The diagram shown illustrates the formation of a deep trench structure in the fabrication method of the deep trench isolation structure provided in this application embodiment. Specifically, firstly, a layer of photoresist can be spin-coated onto the surface of the hard mask layer 06. Then, an exposure and development step is performed to define a target area for forming a deep trench between the first device region 201 and the second device region 202 on the hard mask layer 06. When defining the target area, the width of the target area can be defined according to the depth of the deep trench to be formed. The deep trench to be formed can be used as a DTC or a DTI. When used as a DTI, the width of the target area can be approximately 2.7 μm; when used as a DTC, the width of the target area can be approximately 1.5 μm. Next, the hard mask layer 06 and the third oxide layer 05 can be etched to form an etching window in the target area. The remaining hard mask layer 06 is used as a barrier layer to continue etching the substrate through the etching window, forming a deep trench 07 on the substrate. In practice, a mixture of C4F8 (octafluorocyclobutane) and O2 (oxygen) gas can be used to perform reactive ion etching on the hard mask layer 06 and the third oxide layer 05 to form an etching window in the target area; and a mixture of SF6 (sulfur hexafluoride) and O2 (oxygen) gas can be used to etch the substrate to form a deep trench 07 on the substrate.

[0056] Step S103: A first oxide layer is formed on the wall of the deep trench.

[0057] This step is used to form an isolation layer in the deep trench, which is the first oxide layer. In practical applications, the thickness of the first oxide layer can be determined according to the device voltage. In some examples, the thickness of the first oxide layer can be between 2000A and 6000A. For example, the thickness of the first oxide layer can be any one of 2000A, 2500A, 3000A, 3500A, 4000A, 4500A, 5000A, 5500A, 6000A, etc.

[0058] In one embodiment, a high-density plasma-assisted chemical vapor deposition (HARP) step can be performed to form a first oxide layer on the deep trench wall.

[0059] In another embodiment, a first oxide layer can be formed on the deep trench wall by a thermal oxidation process. Specifically, a thermal oxidation step can be performed first to form a second oxide layer on the deep trench wall; the second oxide layer can be removed; and then the first oxide layer can be formed on the deep trench wall where the second oxide layer has been removed.

[0060] This embodiment involves forming a thin second oxide layer on the deep trench wall before forming the first oxide layer. This second oxide layer is a temporary sacrificial oxide layer. The second oxide layer is then removed to repair etching damage to the deep trench wall. The thickness of the second oxide layer is between 400 Å and 600 Å. For example, the thickness of the second oxide layer can be any one of 400 Å, 420 Å, 440 Å, 460 Å, 480 Å, 500 Å, 520 Å, 540 Å, 560 Å, 580 Å, or 600 Å.

[0061] The following combination Figures 4-6 The formation of the first oxide layer on the wall of the deep trench is described in detail. Figure 4 This is a schematic diagram illustrating the formation of a second oxide layer on the deep trench wall in the method for preparing the deep trench isolation structure provided in this application embodiment. Figure 5 This is a schematic diagram illustrating the removal of the second oxide layer from the deep trench wall in the method for preparing the deep trench isolation structure provided in this application embodiment. Figure 6 This is a schematic diagram of the formation of a first oxide layer on the deep trench wall in the preparation method of the deep trench isolation structure provided in the embodiments of this application.

[0062] like Figure 4 As shown, after forming the deep trench 07, a furnace tube process can be performed to grow a second oxide layer 08 on the sidewalls and bottom of the deep trench 07 through high-temperature thermal oxidation. Then, as... Figure 5As shown, the second oxide layer 08 in the deep trench 07 can be removed using either dry etching or wet etching. When removing the second oxide layer 08 in the deep trench 07 using wet etching, a solution such as HF (hydrofluoric acid) or DHF (diluted hydrofluoric acid) can be used. This repairs etching damage to the inner wall of the deep trench 07, making the inner wall of the deep trench 07 cleaner and smoother, providing a foundation for the formation of a high-quality first oxide layer on the inner wall of the deep trench 07. Then, as... Figure 6 As shown, a furnace tube process can be performed to grow a first oxide layer 09 on the sidewall and bottom of the deep trench 07 through high-temperature thermal oxidation. The first oxide layer 09 is the isolation layer in the deep trench 07.

[0063] Step S104: Form a first conductive layer on the first oxide layer in the deep trench.

[0064] Step S105: Form at least one set of combined layers on the first conductive layer to form a capacitor structure located in the deep trench, wherein the combined layer includes a dielectric layer and a second conductive layer on the dielectric layer.

[0065] Steps S104 and S105 are used to form a capacitor structure in the deep trench.

[0066] The deep trench, the first oxide layer, and the capacitor structure together constitute a deep trench isolation structure between the first device region and the second device region. The capacitor structure includes a first conductive layer and at least one set of combined layers. The number of combined layers in the capacitor structure can be one, two, three, etc. For example, the capacitor structure is a three-layer structure consisting of a first conductive layer, a dielectric layer, and a second conductive layer on the dielectric layer; another example is a five-layer structure consisting of a first conductive layer, a first dielectric layer, a first second conductive layer on the first dielectric layer, a second dielectric layer on the first second conductive layer, and a second conductive layer on the second dielectric layer; yet another example is a seven-layer structure consisting of a first conductive layer, a first dielectric layer, a first second conductive layer on the first dielectric layer, a second dielectric layer on the first second conductive layer, a second second conductive layer on the second dielectric layer, a third dielectric layer on the second second conductive layer, and a third second conductive layer on the third dielectric layer; and so on. For ease of explanation, this application embodiment uses a three-layer structure consisting of a first conductive layer, a dielectric layer, and a second conductive layer on the dielectric layer as an example for detailed description.

[0067] The following combination Figures 7-9 The formation of the capacitor structure in the deep trench is described in detail. Figure 7 This is a schematic diagram of the formation of a first conductive layer on the first oxide layer in the method for preparing the deep trench isolation structure provided in this application embodiment. Figure 8 This is a schematic diagram of the formation of a dielectric layer on the first conductive layer in the method for fabricating the deep trench isolation structure provided in this application embodiment. Figure 9 This is a schematic diagram of the formation of a second conductive layer on the dielectric layer in the preparation method of the deep trench isolation structure provided in this application embodiment.

[0068] In specific implementation methods, such as Figure 7 As shown, after the first oxide layer 09 is formed on the wall of the deep trench 07, a furnace tube process can be performed on the semiconductor substrate to deposit a first conductive layer 10 on the first oxide layer 09 in the deep trench 07 and on the surface of the hard mask layer 06 on the substrate surface. The material of the first conductive layer 10 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)). The thickness of the first conductive layer 10 is between 1500 Å and 2500 Å. For example, the thickness of the first conductive layer 10 can be any one of 1500 Å, 1600 Å, 1700 Å, 1800 Å, 1900 Å, 2000 Å, 2100 Å, 2200 Å, 2300 Å, 2400 Å, 2500 Å, etc.

[0069] like Figure 8 As shown, after forming the first conductive layer 10 on the first oxide layer 09 and the surface of the hard mask layer 06 on the substrate surface, an atomic layer deposition step can be performed to form a dielectric layer 11 on the first conductive layer 10. The dielectric layer 11 can be a single-layer film (such as an oxide layer) or a composite film composed of an oxide layer and a high-k dielectric layer (high-k dielectric). The oxide layer can be silicon dioxide, and the high-k dielectric layer can be at least one of hafnium dioxide (HfO2), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and lanthanum oxide (La2O3). It should be noted that when the dielectric layer 11 is a composite film, on the one hand, it can solve the quantum tunneling effect caused by the thinness of the single-layer film (such as an oxide layer) being too small (such as less than 2nm), avoiding a sharp increase in gate leakage current; on the other hand, the oxide layer in the composite film is adjacent to the first conductive layer, which can prevent the interface roughness problem caused by the high-k dielectric layer directly contacting the first conductive layer (such as polysilicon).

[0070] like Figure 9 As shown, after forming a dielectric layer 11 on the first conductive layer 10, a furnace tube process can be performed to deposit a second conductive layer 12 on the dielectric layer 11. That is, the second conductive layer 12 is filled on the dielectric layer 11 in the deep trench 07 and the second conductive layer 12 is formed on the dielectric layer 11 on the substrate surface. The material of the second conductive layer 12 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0071] When the deep trench 07 is used as a DTC (deep trench capacitor), the first conductive layer 10 is the lower electrode of the DTC, and the second conductive layer 12 is the upper electrode of the DTC. Furthermore, the deep trench 07, the first oxide layer 09, and the capacitor structure (the first conductive layer 10, the dielectric layer 11, and the second conductive layer 12) together constitute a deep trench isolation structure between the first device region and the second device region.

[0072] The deep trench isolation structure fabrication method provided in this application provides a deep trench isolation structure comprising a conductive layer, a dielectric layer, and a capacitor structure. On one hand, the deep trench isolation structure can serve as a DTC (deep trench capacitor) to construct a high-density, high-performance on-chip capacitor. On the other hand, the deep trench isolation structure, located between a first device region and a second device region, can serve as a DTI (deep trench isolation) to achieve electrical isolation between the first device in the first device region and the second device in the second device region. Therefore, the deep trench isolation structure fabrication method provided in this application can integrate DTI and DTC within the same deep trench isolation structure. The resulting deep trench isolation structure can be used as both an isolation device and a capacitor, effectively reducing the number of photolithography steps during DTI and DTC formation, lowering manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. Furthermore, the co-design of DTI and DTC in this application effectively utilizes the chip's vertical space, avoiding waste in planar layouts (such as the combination of capacitors and isolation structures in DRAM), increasing chip density, and improving overall synergistic optimization.

[0073] Further, after depositing the second conductive layer 12 on the dielectric layer 11, the second conductive layer and the dielectric layer on the substrate surface can be removed. When removing the second conductive layer and the dielectric layer on the substrate surface, a portion of the first conductive layer can be removed simultaneously, or the first conductive layer can be left unremoved. This application does not impose any limitations on this. By removing the second conductive layer and the dielectric layer on the substrate surface, the first conductive layer on the substrate surface is exposed, preparing for the formation of the lower electrode of a DTC (deep trench capacitor).

[0074] like Figure 10 The diagram shown is a schematic of the removal of the second conductive layer and dielectric layer in the preparation method of the deep trench isolation structure provided in this application embodiment. After the second conductive layer 12 is filled on the dielectric layer 11 in the deep trench 07 and the second conductive layer 12 is formed on the dielectric layer 11 on the substrate surface, the second conductive layer 12 and dielectric layer 11 on the substrate surface can be removed by mechanical grinding or etching until the first conductive layer 10 on the substrate surface is exposed.

[0075] Furthermore, after removing the second conductive layer and dielectric layer on the substrate surface, the region where the lower electrode of the capacitor structure to be formed is located can be defined on the first conductive layer formed on the substrate surface by photolithography; an etching step is performed to remove the first conductive layer deposited in the region other than the region where the lower electrode is located in the first conductive layer formed on the substrate surface, thereby forming the lower electrode.

[0076] This step is used to form the lower plate of a DTC (deep trench capacitor).

[0077] like Figure 11 The diagram shown is a schematic of the formation of the lower electrode plate in the fabrication method of the deep trench isolation structure provided in this application embodiment. After the first conductive layer 10 is exposed, a layer of photoresist can be spin-coated on the first conductive layer 10, and an exposure and development step is performed to define the area where the lower electrode plate of the capacitor structure to be formed is located on the first conductive layer 10. Then, a wet etching or dry etching step is performed to remove the first conductive layer 10 deposited in the area other than the area where the lower electrode plate is located in the first conductive layer 10 formed on the substrate surface. In this way, the remaining first conductive layer 10 on the substrate surface forms the lower electrode plate.

[0078] It should be noted that if the first device region and the second device region have not yet formed the corresponding first device and second device, then after the lower electrode plate is formed, the first device can be formed in the first device region 201 and the second device can be formed in the second device region 202. In this way, electrical isolation between the first device and the second device can be achieved through the formed deep trench isolation structure.

[0079] Furthermore, after forming the lower electrode plate, an interlayer dielectric layer can be formed on the substrate surface where the lower electrode plate is formed; an etching step is performed to form through holes on the interlayer dielectric layer for connecting the lower electrode plate and the upper electrode plate to the metal layer, wherein the upper electrode plate is the second conductive layer.

[0080] This step is used to etch through-holes so that subsequent metal layers can contact the first and second conductive layers, thereby achieving a low-resistance, high-reliability electrical connection between the electrodes (upper and lower plates) of the DTC (deep trench capacitor) and the upper circuitry.

[0081] The following combination Figure 12 and Figure 13 The formation of through holes is explained. Figure 12 This is a schematic diagram of the formation of the interlayer dielectric layer in the preparation method of the deep trench isolation structure provided in this application embodiment. Figure 13 This is a schematic diagram of forming through holes in the interlayer dielectric layer in the method for preparing the deep trench isolation structure provided in the embodiments of this application.

[0082] like Figure 12 As shown, after the lower electrode is formed, chemical vapor deposition or plasma-enhanced tetraethyl orthosilicate CVD (PECVDTEOS) can be performed to form an interlayer dielectric layer 13 (ILD (Interlayer Dielectric). An interlayer dielectric layer is an insulating material (such as silicon dioxide, silicon nitride, or a low dielectric constant material) deposited between metal interconnect layers or between a metal and a device after the front-end process of a semiconductor device is completed. It is used to achieve electrical isolation between different conductive layers and prevent short circuits and crosstalk.

[0083] It should be noted that the substrate surface may not be smooth before the interlayer dielectric layer is deposited. In order to fully cover the uneven structure of the substrate surface, a relatively thick initial interlayer dielectric layer is usually deposited (e.g., the thickness of the initial interlayer dielectric layer is between 8000 Å and 15000 Å, for example, the thickness of the initial interlayer dielectric layer can be any one of 8000 Å, 8500 Å, 9000 Å, 9500 Å, 10000 Å, 10500 Å, 11000 Å, 11500 Å, 12000 Å, 12500 Å, 13000 Å, 14500 Å, 15000 Å, etc.). If the initial interlayer dielectric layer is larger than a preset thickness (e.g., the preset thickness is between 4000 Å and 6000 Å, such as any one of 4000 Å, 4200 Å, 4400 Å, 4600 Å, 4800 Å, 5000 Å, 5200 Å, 5400 Å, 5600 Å, 5800 Å, or 6000 Å), then the interlayer dielectric layer can be planarized (e.g., mechanically polished) until its thickness reaches the preset thickness. On one hand, planarizing the interlayer dielectric layer ensures a smooth surface, providing a flat substrate for the next photolithography step; on the other hand, maintaining the interlayer dielectric layer at the preset thickness avoids excessive stacking and difficulties in subsequent via etching.

[0084] like Figure 13 As shown, after forming the interlayer dielectric layer 13, via locations for connecting the lower electrode and the upper electrode to the metal layer can be defined on the interlayer dielectric layer 13. Then, an etching step is performed to form vias 15 for connecting the lower electrode to the metal layer and vias 14 for connecting the upper electrode to the metal layer on the interlayer dielectric layer 13. This provides a pathway for interconnection between the capacitor electrode and the metal layer.

[0085] Furthermore, such as Figure 14The diagram shown illustrates the filling of vias in the interlayer dielectric layer during the fabrication of the deep trench isolation structure provided in this application embodiment. After forming vias 15 for connecting the lower electrode to the metal layer and vias 14 for connecting the upper electrode to the metal layer on the interlayer dielectric layer 13, conductive materials can be filled into the vias 14 and 15 to form conductive channels. The conductive materials may include, but are not limited to, tungsten (W), copper (Cu), etc.

[0086] The method for fabricating a deep trench isolation structure provided in this application includes the following steps: providing a semiconductor substrate, the semiconductor substrate including a first device region and a second device region; forming a deep trench for a deep trench isolation structure between the first device region and the second device region; forming a first oxide layer on the wall of the deep trench; forming a first conductive layer on the first oxide layer in the deep trench; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the deep trench, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer and the capacitor structure together constitute a deep trench isolation structure between the first device region and the second device region.

[0087] As can be seen, the deep trench isolation structure fabrication method provided in this application provides a capacitor structure comprising a conductive layer, a dielectric layer, and a conductive layer. On one hand, the deep trench isolation structure can serve as a DTC (deep trench capacitor) to construct high-density, high-performance on-chip capacitors, applicable to power management chips, charge pumps in BCD processes, and filter circuits. Furthermore, DTCs can achieve larger capacitance values ​​per unit area (greater than planar capacitors), significantly saving chip area. On the other hand, the deep trench isolation structure, located between the first device region and the second device region, can serve as a DTI (deep trench isolation) to achieve electrical isolation between the first device in the first device region and the second device in the second device region. This plays a crucial role, especially in high-voltage integrated circuits, CMOS image sensors (CIS), and 3D integration. DTI can effectively block leakage paths and suppress crosstalk, thereby improving device reliability and performance. Therefore, the deep trench isolation structure fabrication method provided in this application embodiment can place DTI and DTC in the same deep trench isolation structure. The formed deep trench isolation structure can be used as both an isolation device and a capacitor, effectively reducing the number of photolithography steps when forming DTI and DTC, reducing manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the co-design of DTI and DTC in this application can effectively utilize the vertical space of the chip, avoid the waste of planar layout (such as the combination of capacitor and isolation structure in DRAM), increase chip density, and improve overall co-optimization.

[0088] A second embodiment of this application provides a deep trench isolation structure, the deep trench isolation structure comprising: a semiconductor substrate, the semiconductor substrate including a first device region on which a first device is formed and a second device region on which a second device is formed; a deep trench for the deep trench isolation structure being formed between the first device region and the second device region; a first oxide layer being formed on the wall of the deep trench; and a capacitor structure being formed in the deep trench, the capacitor structure including a first conductive layer formed on the first oxide layer in the deep trench and at least one set of combined layers formed on the first conductive layer, the combined layers including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer and the capacitor structure together constitute the deep trench isolation structure of the first device region and the second device region.

[0089] For details regarding the deep trench isolation structure provided in the second embodiment of this application, please refer to the detailed description of the preparation method of a deep trench isolation structure provided in the first embodiment of this application, which will not be repeated here.

[0090] As can be seen, the deep trench isolation structure provided in the second embodiment of this application includes: a semiconductor substrate, the semiconductor substrate including a first device region on which a first device is formed and a second device region on which a second device is formed; a deep trench for the deep trench isolation structure is formed between the first device region and the second device region; a first oxide layer is formed on the wall of the deep trench; a capacitor structure is formed in the deep trench, the capacitor structure including a first conductive layer formed on the first oxide layer in the deep trench and at least one set of combined layers formed on the first conductive layer, the combined layer including a dielectric layer and a second conductive layer on the dielectric layer; the deep trench, the first oxide layer and the capacitor structure together constitute the deep trench isolation structure of the first device region and the second device region. This deep trench isolation structure includes a conductive layer, a dielectric layer and a capacitor structure, which, on the one hand, can be used as a DTC (deep trench capacitor) to construct high-density, high-performance on-chip capacitors, and can be used in scenarios such as power management chips, charge pumps and filter circuits in BCD processes, etc., and DTC can achieve a larger capacitance value per unit area (greater than the capacitance value of a planar capacitor), greatly saving chip area. On the other hand, the deep trench isolation structure, located between the first device region and the second device region, can serve as a DTI (deep trench isolation) to achieve electrical isolation between the first device in the first device region and the second device in the second device region. It plays a crucial role, especially in high-voltage integrated circuits, CMOS image sensors (CIS), and 3D integration. DTI effectively blocks leakage paths and suppresses crosstalk, thereby improving device reliability and performance. Therefore, the deep trench isolation structure provided in the second embodiment of this application can house both DTI and DTC within the same deep trench isolation structure. This deep trench isolation structure can be used as both an isolation device and a capacitor, effectively reducing the number of photolithography steps during DTI and DTC formation, lowering manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. Furthermore, the collaborative design of DTI and DTC in this application effectively utilizes the chip's vertical space, avoiding waste in planar layouts (such as the combination of capacitors and isolation structures in DRAM), increasing chip density, and improving overall collaborative optimization.

[0091] The third embodiment of this application provides a semiconductor device, which can be prepared by the method for preparing a deep trench isolation structure provided in the first embodiment of this application. For details, please refer to the detailed description of the method for preparing a deep trench isolation structure provided in the first embodiment of this application, which will not be repeated here.

[0092] As can be seen, the deep trench isolation structure included in the semiconductor device provided in the third embodiment of this application includes a capacitor structure consisting of a conductive layer, a dielectric layer, and a conductive layer. On the one hand, the deep trench isolation structure can be used as a DTC (deep trench capacitor) to construct high-density, high-performance on-chip capacitors, which can be used in scenarios such as power management chips, charge pumps and filter circuits in BCD processes. Furthermore, DTC can achieve a larger capacitance value per unit area (greater than the capacitance value of planar capacitors), greatly saving chip area. On the other hand, the deep trench isolation structure is located between the first device region and the second device region, and can be used as a DTI (deep trench isolation) to achieve electrical isolation between the first device in the first device region and the second device in the second device region. It plays a key role, especially in scenarios such as high-voltage integrated circuits, CMOS image sensors (CIS), and 3D integration. DTI can effectively block leakage paths and suppress crosstalk, thereby improving device reliability and performance. Therefore, the deep trench isolation structure included in the semiconductor device provided in the third embodiment of this application can be used as both an isolation device and a capacitor, effectively reducing the number of photolithography steps when forming DTI and DTC, reducing manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the co-design of DTI and DTC in this application can effectively utilize the vertical space of the chip, avoid the waste of planar layout (such as the combination of capacitors and isolation structures in DRAM), increase chip density, and improve overall co-optimization.

[0093] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for preparing a deep trench isolation structure, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a first device region and a second device region; A deep trench for a deep trench isolation structure is formed between the first device region and the second device region; A first oxide layer is formed on the wall of the deep trench; A first conductive layer is formed on the first oxide layer in the deep trench; At least one set of combined layers is formed on the first conductive layer to form a capacitor structure located in the deep trench, wherein the combined layer includes a dielectric layer and a second conductive layer on the dielectric layer; The deep trench, the first oxide layer, and the capacitor structure together constitute a deep trench isolation structure between the first device region and the second device region.

2. The method according to claim 1, characterized in that, The formation of the first oxide layer on the deep trench wall includes: A thermal oxidation step is performed to form a second oxide layer on the deep trench wall; Remove the second oxide layer; A first oxide layer is formed on the deep trench wall where the second oxide layer is removed.

3. The method according to claim 1, characterized in that, The process of forming a deep trench for a deep trench isolation structure between the first device region and the second device region includes: A third oxide layer and a hard mask layer are formed on the surface of the semiconductor substrate; The target area for forming the deep trench is defined between the first device area and the second device area on the hard mask layer using a photolithography process. An etching step is performed to form the deep trench for the deep trench isolation structure in the target area on the hard mask layer.

4. The method according to claim 3, characterized in that, The formation of a first conductive layer on the first oxide layer in the deep trench includes: A furnace tube process is performed to deposit a first conductive layer on the first oxide layer in the deep trench and on the surface of the hard mask layer on the substrate surface.

5. The method according to claim 4, characterized in that, The formation of at least one set of combined layers on the first conductive layer includes: An atomic layer deposition step is performed to form a dielectric layer on the first conductive layer; Perform a furnace tube process to deposit a second conductive layer on the dielectric layer.

6. The method according to claim 5, characterized in that, After depositing a second conductive layer on the dielectric layer, the method further includes: Remove the second conductive layer and dielectric layer from the surface of the substrate.

7. The method according to claim 6, characterized in that, After removing the second conductive layer and dielectric layer from the surface of the substrate, the method further includes: The region where the lower electrode of the capacitor structure to be formed is located is defined on the first conductive layer formed on the surface of the substrate by photolithography. An etching step is performed to remove the first conductive layer deposited in the area of ​​the first conductive layer formed on the substrate surface, excluding the area where the lower electrode plate is located, to form the lower electrode plate.

8. The method according to claim 7, characterized in that, After forming the lower electrode plate, the method further includes: An interlayer dielectric layer is formed on the surface of the substrate on which the lower electrode plate is formed; An etching step is performed to form through-holes on the interlayer dielectric layer for connecting the lower electrode and the upper electrode to the metal layer, respectively, wherein the upper electrode is the second conductive layer.

9. The method according to claim 1, characterized in that, The method further includes: A first device is formed in the first device region and a second device is formed in the second device region, wherein the first device and the second device are respectively a bipolar device, a CMOS device, and a DMOS device.

10. A deep trench isolation structure, characterized in that, The deep trench isolation structure includes: A semiconductor substrate, the semiconductor substrate including a first device region having a first device formed thereon and a second device region having a second device formed thereon; A deep trench for a deep trench isolation structure is formed between the first device region and the second device region; A first oxide layer is formed on the wall of the deep trench; A capacitor structure is formed in the deep trench. The capacitor structure includes a first conductive layer formed on a first oxide layer in the deep trench and at least one set of combined layers formed on the first conductive layer. The combined layers include a dielectric layer and a second conductive layer on the dielectric layer. The deep trench, the first oxide layer, and the capacitor structure together constitute the deep trench isolation structure of the first device region and the second device region.

11. A semiconductor device, characterized in that, It is prepared by the method described in any one of claims 1 to 9.

Images