A method of forming a semiconductor structure

Abstract

The application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first insulating medium layer on the substrate; forming a through-silicon via and a contact plug; wherein, before etching a via for forming the through-silicon via and / or a contact hole for forming the contact plug, an intermediate medium layer is formed on the first insulating medium layer; a sacrificial structure is formed in the via or the contact hole before the via or the contact hole is filled with a conductive material, and the intermediate medium layer and the sacrificial structure are sequentially removed; forming a metal layer; wherein, the through-silicon via and the contact plug are both in contact with the metal layer; the height difference between the top surface of the through-silicon via and the top surface of the contact plug in a first direction is less than the thickness of the metal layer in the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In the semiconductor technology field, as device feature sizes continue to shrink and integration density continues to increase, Moore's Law faces a dual challenge in terms of physical limits and economic costs. To continue improving system performance, 3D integration technology has become an important development direction that surpasses traditional device scaling. Among them, 2.5D silicon interposer technology, by achieving high-density interconnects and heterogeneous chip integration on a silicon interposer, significantly improves system bandwidth and energy efficiency, and has become a key solution for chip integration in fields such as high-performance computing and artificial intelligence.

[0003] However, 2.5D silicon interposers still have several prominent issues regarding structural reliability. Therefore, there is an urgent need for a new semiconductor structure solution that can simplify the process flow and improve structural reliability to promote the reliable application of 2.5D silicon interposer technology. Summary of the Invention

[0004] This application provides a method for forming a semiconductor structure, which can simplify the process and improve efficiency.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a method for forming a semiconductor structure, the method comprising: providing a substrate; forming a first insulating dielectric layer on the substrate; forming a through-silicon via (TSV) and a contact plug; wherein, before etching the through-hole of the TSV or the contact hole of the contact plug, an intermediate dielectric layer is formed on the first insulating dielectric layer; before filling the through-hole or the contact hole with a conductive material, a sacrificial structure is formed in the through-hole or the contact hole, and the intermediate dielectric layer and the sacrificial structure are removed sequentially; forming a metal layer; wherein, the TSV and the contact plug are both in contact with the metal layer; the height difference between the top surface of the TSV and the top surface of the contact plug in a first direction is less than the thickness of the metal layer in the first direction.

[0006] In some embodiments, the intermediate dielectric layer includes: a first intermediate dielectric layer; forming the through-silicon via (TSV) and the contact plug includes: forming the TSV and a first protective layer; wherein the first protective layer covers the top surface of the TSV and the first insulating dielectric layer; the TSV penetrates the first insulating dielectric layer and at least a portion of the substrate; a patterned first intermediate dielectric layer is formed on the first protective layer; using the patterned first intermediate dielectric layer as a mask, the first protective layer and the first insulating dielectric layer are etched to form the contact hole; the contact hole is filled to form the sacrificial structure; the first intermediate dielectric layer is removed until the first protective layer is exposed; the sacrificial structure is removed and the contact hole is refilled to form the contact plug.

[0007] In some embodiments, the intermediate dielectric layer includes: a second intermediate dielectric layer; forming the through-silicon via and the contact plug includes: forming the contact plug and a second protective layer; wherein the second protective layer covers the top surface of the contact plug and the first insulating dielectric layer; the contact plug penetrates the first insulating dielectric layer; a patterned second intermediate dielectric layer is formed on the second protective layer; using the patterned second intermediate dielectric layer as a mask, the second protective layer, the first insulating dielectric layer, and the substrate are etched to form the via; the via is filled to form a sacrificial structure; the second intermediate dielectric layer is removed until the second protective layer is exposed; the sacrificial structure is removed and the via is refilled to form the through-silicon via; and a first protective layer is formed.

[0008] In some embodiments, the forming method further includes: forming a second insulating dielectric layer covering the inner wall of the through hole before forming the sacrificial structure; wherein the second insulating dielectric layer and the second intermediate dielectric layer are made of the same material; and removing a portion of the second insulating dielectric layer covering the second intermediate dielectric layer during the removal of the second intermediate dielectric layer.

[0009] In some embodiments, an etching process is used to remove the intermediate dielectric layer.

[0010] In some embodiments, after the through hole or the contact hole is filled with conductive material, the conductive material outside the through hole or the contact hole is removed by an etching process.

[0011] In some embodiments, the material of the sacrificial structure is different from the materials of the intermediate dielectric layer and the first insulating dielectric layer.

[0012] In some embodiments, the material of the first protective layer includes silicon nitride; the material of the second insulating dielectric layer includes silicon oxide.

[0013] The embodiments of this application have the following beneficial effects: In this embodiment, before etching the vias to form silicon through-holes and / or the contact holes to form contact plugs, an intermediate dielectric layer is formed on the first insulating dielectric layer. Before filling the vias and / or contact holes with conductive material, a sacrificial structure is formed within the vias or contact holes, and the intermediate dielectric layer and the sacrificial structure are removed sequentially. In this way, by removing the intermediate dielectric layer, this application reduces the height difference between the top surface of the contact plug and the top surface of the silicon through-hole, thereby ensuring that the metal layer can fully cover and reliably contact the top surfaces of the silicon through-hole and the contact plug, avoiding the problem of poor contact between the silicon through-hole and the contact plug due to excessive height difference. Simultaneously, this application does not require additional process steps to flush the top surfaces of the silicon through-hole and the contact plug, simplifying the process and improving efficiency. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 2 ; Figure 3 This is a flowchart illustrating the method for forming a semiconductor structure provided in the embodiments of this application. Figure 1 ; Figure 4 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 2 ; Figure 5 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 3 ; Figure 6 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 4 ; Figure 7 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 5 ; Figure 8 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 6 ; Figure 9 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 7 ; Figure 10 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 8 ; Figure 11 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 9; Figure 12 This is a flowchart illustrating the method for forming a semiconductor structure provided in the embodiments of this application. Figure 2 ; Figure 13 This is a flowchart illustrating the method for forming a semiconductor structure provided in the embodiments of this application. Figure 3 ; Figure 14 This is a flowchart illustrating the method for forming a semiconductor structure provided in the embodiments of this application. Figure 3 ; Figure 15 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 10 ; Figure 16 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application. Figure 10 one. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] Figure 1 This is a schematic diagram of an optional semiconductor structure 100 provided in an embodiment of this application. It should be noted that... Figure 1 The first direction Z shown can be a vertical direction, and the second direction X and the third direction Y intersect and are both perpendicular to the first direction Z. Figure 1 The semiconductor structure 100 shown can be a silicon interposer. In some embodiments, the semiconductor structure 100 can also be a chip such as a memory chip or a logic chip. Figure 1 The example of the through-silicon via 50 only penetrates a portion of the substrate 10. Subsequent back-side thinning of the substrate 10 can be performed according to actual needs, so that the through-silicon via 50 penetrates the thinned substrate 10. Figure 1 The protective layer 30 shown in the example is used to protect the contact plug 60 and the through-silicon via 50, so as to prevent subsequent processes from damaging the through-silicon via 50 and the contact plug 60. During the formation of the metal layer 40, part of the protective layer 30 is removed from the top of the contact plug 60 and the top of the through-silicon via 50, so that the metal layer 40 formed is in contact with the contact plug 60 and the through-silicon via 50.

[0017] Here, for reference Figure 1The semiconductor structure 100 includes a substrate 10, a first insulating dielectric layer 20, a protective layer 30, a metal layer 40, a through-silicon via (TSV) 50, and a contact plug 60. The substrate 10, the first insulating dielectric layer 20, the protective layer 30, and the metal layer 40 are stacked sequentially along a first direction Z. The TSV 50 penetrates the protective layer 30, the first insulating dielectric layer 20, and at least a portion of the substrate 10 along the first direction Z. The contact plug 60 penetrates the first insulating dielectric layer 20 and the protective layer 30 along the first direction Z. Both the TSV 50 and the contact plug 60 are in contact with the metal layer 40. Thus, the semiconductor structure 100 can achieve interconnection between the metal layer 40 and devices (such as transistors and capacitors) formed on (or near the surface of) the substrate 10 through the contact plug 60. The semiconductor structure 100 can use the TSV 50 as an electrical channel for signals, power, and ground lines to pass through the substrate 10, enabling direct connections between different device layers or chips. The first insulating dielectric layer 20 can electrically isolate the silicon via 50 from the contact plug 60, preventing signal crosstalk caused by capacitive coupling and ensuring signal integrity.

[0018] Here, for reference Figure 1 The first insulating dielectric layer 20 can be made of materials such as silicon dioxide. The protective layer 30 can be made of materials such as silicon nitride and silicon carbonitride. The through-silicon via 50 can be made of metals such as copper. The contact plug 60 can be made of metals such as tungsten, cobalt, or copper.

[0019] Here, for reference Figure 1 The height difference between the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60 in the first direction Z is less than the thickness of the metal layer 40 in the first direction Z. For example, the height difference between the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60 can be 1 / 12 of the thickness of the metal layer 40. That is, compared to the thickness of the metal layer 40 in the first direction Z, the height difference between the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60 in the first direction Z is small in this application. In this way, this application can ensure that the metal layer 40 can fully cover and reliably contact the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60, thereby avoiding the problem of poor contact between the through-silicon via 50 and the contact plug 60 and the metal layer 40 due to excessive height difference. Meanwhile, this application does not require additional chemical mechanical polishing or other process steps to flush the top surface 50a of the through-silicon via 50 with the top surface 60a of the contact plug 60, nor does it require depositing conductive structures such as metal layers on the through-silicon via 50 or the contact plug 60 to flush the top surface 50a of the through-silicon via 50 with the top surface 60a of the contact plug 60, thereby simplifying the process and improving efficiency.

[0020] In some embodiments of this application, reference is made to Figure 1The semiconductor structure 100 also includes a capacitor structure 70. The capacitor structure 70 is located between the substrate 10 and the first insulating dielectric layer 20. The capacitor structure 70 is connected to the metal layer 40 via contact plugs 60. For example, the plates of the capacitor structure 70 are led out via contact plugs 60. Thus, the capacitor structure 70 is electrically connected to other circuit elements via contact plugs 60.

[0021] Figure 2 This is a schematic diagram of another optional semiconductor structure 100 provided in this application. It should be noted that... Figure 2 All other structures except for transistor structure 80 can be referenced. Figure 1 The embodiments shown are for reference only and will not be described in detail here.

[0022] In other embodiments of this application, reference is made to Figure 2 The semiconductor structure 100 also includes a transistor structure 80. The transistor structure 80 is located between the substrate 10 and the first insulating dielectric layer 20. The transistor structure 80 is connected to the metal layer 40 via contact plugs 60. For example, the source, drain, and gate of the transistor structure 80 are each connected to the upper metal layer 40 via a corresponding contact plug 60. Thus, the transistor structure 80 is electrically connected to other circuit elements via the contact plugs 60.

[0023] Figure 3 This is a flowchart illustrating an optional semiconductor structure formation method provided in an embodiment of this application, which will be combined with... Figure 3 The steps shown are explained. Figure 3 The formation method shown can be used to form the semiconductor structure 100 of any of the above embodiments.

[0024] S101, Provide substrate.

[0025] S102. A first insulating dielectric layer is formed on the substrate.

[0026] Figure 4 This is a schematic diagram of the formation process of an optional semiconductor structure provided in an embodiment of this application. It should be noted that... Figure 4 The capacitor structure 70 is formed before the first insulating dielectric layer 20. Figure 4 The capacitor structure 70 in the example is only for illustration. The surface of the substrate 10 can also form devices such as transistor structures, which are not limited here.

[0027] In this embodiment of the application, reference is made to Figure 4 The substrate 10 may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.) and at least one III... V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), at least one II VI. The compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, SiC substrates, etc.

[0028] In this embodiment of the application, reference is made to Figure 4 After forming devices such as capacitor structures 70 on the surface of substrate 10, an insulating layer made of materials such as silicon dioxide can be deposited on the surface of substrate 10 through processes such as chemical vapor deposition (CVD), thus forming an insulating layer such as... Figure 4 The first insulating dielectric layer 20 is shown.

[0029] S103, forming a silicon via and a contact plug; wherein, before etching the via to form the silicon via or the contact hole of the contact plug, an intermediate dielectric layer is formed on the first insulating dielectric layer; before filling the via or contact hole with conductive material, a sacrificial structure is formed in the via or contact hole, and the intermediate dielectric layer and the sacrificial structure are removed in sequence.

[0030] Figures 5 to 10 This is a schematic diagram of the formation process of an optional semiconductor structure provided in this application embodiment. It should be noted that, to prevent the through-silicon via 50 from being oxidized by oxidants during etching or other processes, a layer such as... needs to be deposited after the through-silicon via 50 is formed. Figure 5 , Figure 6 , Figure 7 as well as Figure 10 The first protective layer 161 shown covers the through-silicon via 50. The second protective layer 162 is used to protect the contact plug 60, and its function can be understood by referring to the first protective layer 161, so it will not be described again here. The material of the sacrificial structure 131 (or sacrificial structure 132, sacrificial structure 133) is different from the material of the first insulating dielectric layer 20 and the intermediate dielectric layer, so that selective etching can be performed by taking advantage of the material difference.

[0031] It should also be noted that, Figure 5 , Figure 6 and Figure 7 In the example shown, the through-silicon via 50 is formed before the contact plug 60; Figure 8 , Figure 9 and Figure 10 In the example shown, the through-silicon via 50 is formed after the contact plug 60. Figure 5 and Figure 6 The first intermediate dielectric layer 111 shown, and, Figure 8 and Figure 9The second intermediate dielectric layer 112 shown is an intermediate dielectric layer. The intermediate dielectric layer can serve as a hard mask for etching the vias corresponding to the silicon vias 50 and the contact holes corresponding to the contact plugs 60. During the subsequent long-term, high-intensity deep etching process of the first insulating dielectric layer (or substrate), the pattern remains intact, ensuring the formation of deep holes with vertical sidewalls and precise dimensions.

[0032] Here, combined Figure 4 and Figure 5 After forming the through-silicon via 50, this embodiment of the application can form a first intermediate dielectric layer 111 on the first insulating dielectric layer 20. The opening of the first intermediate dielectric layer 111 defines the position and size of the contact plug 60 to be formed subsequently. Then, the first insulating dielectric layer 20 is etched along the opening of the first intermediate dielectric layer 111 to form... Figure 5 The contact hole 121 is shown. Then, the contact hole 121 is filled to form... Figure 6 The sacrificial structure 131 is shown, and the first intermediate dielectric layer 111 and the sacrificial structure 131 are removed sequentially to reopen the contact hole 121. The sacrificial structure 131 fills the contact hole 121 to prevent damage to the contact hole 121 during the removal of the first intermediate dielectric layer 111. Finally, a conductive material is filled into the contact hole 121 to form... Figure 7 The contact plug 60 is shown. In this way, by removing the first intermediate dielectric layer 111, this application reduces the height difference between the top surface of the contact plug 60 and the top surface of the through-silicon via 50.

[0033] Here, combined Figure 4 and Figure 8 After forming the contact plug 60, this embodiment of the application may form a second intermediate dielectric layer 112 on the first insulating dielectric layer 20. The opening of the second intermediate dielectric layer 112 defines the location and size of the subsequent through-silicon vias to be formed. Then, the first insulating dielectric layer 20 and the substrate 10 are etched along the opening of the second intermediate dielectric layer 112 to form... Figure 8 The through hole 122 is shown. Then, the through hole 122 is filled to form... Figure 9 The sacrificial structure 132 is shown, and the second intermediate dielectric layer 112 and the sacrificial structure 132 are removed sequentially to reopen the via 122. The sacrificial structure 132 fills the via 122, preventing damage to the via 122 during the removal of the second intermediate dielectric layer 112. Finally, an insulating material and a conductive material are sequentially filled into the via 122 to form... Figure 10 The through-silicon via 50 is shown. In this way, by removing the second intermediate dielectric layer 112, this application reduces the height difference between the top surface of the contact plug 60 and the top surface of the through-silicon via 50.

[0034] S104. Form a metal layer; wherein, the through-silicon via and the contact plug are both in contact with the metal layer; the height difference between the top surface of the through-silicon via and the top surface of the contact plug in the first direction is less than the thickness of the metal layer in the first direction.

[0035] Figure 11 This is a schematic diagram of the formation process of an optional semiconductor structure provided in an embodiment of this application.

[0036] In this embodiment of the application, combined with Figure 10 and Figure 11 After forming the through-silicon via 50 and the contact plug 60, this embodiment of the application can form a third intermediate dielectric layer 113. The opening of the third intermediate dielectric layer 113 defines the position and size of the conductors in the subsequent metal layer to be formed. Then, the first protective layer 161 is etched along the opening of the third intermediate dielectric layer 113 until the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60 are exposed, forming the first groove 140 and... Figure 1 The protective layer 30 is shown. Finally, conductive material is filled into the first groove 140 to form... Figure 1 Metal layer 40 is shown.

[0037] Understandably, by removing the intermediate dielectric layers (first intermediate dielectric layer 111 and second intermediate dielectric layer 112), this application reduces the height difference between the top surface of the contact plug 60 and the top surface of the through-silicon via 50. This ensures that the metal layer 40 can fully cover and reliably contact the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60, avoiding the problem of poor contact between the through-silicon via 50 and the contact plug 60 and the metal layer 40 due to excessive height difference. Furthermore, this application eliminates the need for additional process steps to align the top surface 50a of the through-silicon via 50 and the top surface 60a of the contact plug 60, simplifying the process and improving efficiency.

[0038] Figure 12 This is a flowchart illustrating an optional semiconductor structure formation method provided in an embodiment of this application, which will be combined with... Figure 7 Step S103 of the above embodiment is implemented by steps S201 to S206.

[0039] S201, Forming a through-silicon via and a first protective layer; wherein the first protective layer covers the top surface of the through-silicon via and a first insulating dielectric layer; the through-silicon via penetrates the first insulating dielectric layer and at least a portion of the substrate.

[0040] S202. A patterned first intermediate medium layer is formed on the first protective layer.

[0041] S203. Using the patterned first intermediate dielectric layer as a mask, etch the first protective layer and the first insulating dielectric layer to form a contact hole.

[0042] Here, combined Figure 5 and Figure 6 After forming a through-silicon via 50 penetrating the substrate 10 and the first insulating dielectric layer 20, a first protective layer 161 made of silicon nitride or silicon carbonitride is deposited on the top surface of the through-silicon via 50 and the first insulating dielectric layer 20 using a process such as chemical vapor deposition. Then, a first intermediate dielectric material layer made of silicon dioxide is formed on the first protective layer 161 using a deposition process such as chemical vapor deposition. Subsequently, photoresist is coated on the first intermediate dielectric material layer, and the target pattern is formed through exposure and development. Figure 5 The first intermediate dielectric layer 111 is shown. The pattern of the first intermediate dielectric layer 111 defines the position and size of the contact plugs to be formed subsequently. Then, using the first intermediate dielectric layer 111 as a mask, the first protective layer 161 and the first insulating dielectric layer 20 are etched until the contact areas of the devices formed on the surface of the substrate 10 (such as the electrodes of the capacitor structure 70) are exposed, forming contact holes 121.

[0043] S204, fill the contact hole to form a sacrificial structure.

[0044] S205. Remove the first intermediate dielectric layer until the first protective layer is exposed.

[0045] S206. Remove the sacrificial structure and refill the contact hole to form a contact plug.

[0046] In this embodiment of the application, combined with Figure 5 and Figure 6 Within the contact hole 121, a sacrificial structure 131 composed of materials such as photoresist or amorphous carbon is formed using deposition processes such as chemical vapor deposition. Then, the first intermediate dielectric layer 111 is removed using processes such as dry etching, with the first protective layer 161 serving as an etching stop layer. Next, the sacrificial structure 131 composed of amorphous carbon is removed using processes such as thermal oxidation (or the sacrificial structure 131 composed of photoresist is removed using oxygen plasma ashing). Finally, a conductive material (such as tungsten) is deposited in the contact hole 121, and excess conductive material outside the contact hole 121 is etched away, forming a structure such as... Figure 7 The contact plug 60 is shown.

[0047] Figure 13 This is a flowchart illustrating an optional semiconductor structure formation method provided in an embodiment of this application, which will be combined with... Figure 7 Step S103 of the above embodiment is implemented by steps S301 to S306.

[0048] S301, forming a contact plug and a second protective layer; wherein the second protective layer covers the top surface of the contact plug and the first insulating dielectric layer; the contact plug penetrates the first insulating dielectric layer.

[0049] S302. A patterned second intermediate medium layer is formed on the second protective layer.

[0050] S303. Using the patterned second intermediate dielectric layer as a mask, etch the second protective layer, the first insulating dielectric layer, and the substrate to form a via.

[0051] Here, combined Figure 4 and Figure 7 After forming the first contact plug 60 penetrating the first insulating dielectric layer 20, a second protective layer 162 made of materials such as silicon nitride or silicon carbonitride is deposited on the top surface of the first contact plug 60 and on the first insulating dielectric layer 20 using processes such as chemical vapor deposition. Then, a second intermediate dielectric material layer made of materials such as silicon dioxide is deposited on the second protective layer 162 using processes such as chemical vapor deposition. Subsequently, photoresist is coated on the second intermediate dielectric material layer, and the target pattern is formed through exposure and development. Figure 8 The second intermediate dielectric layer 112 is shown. The pattern of the second intermediate dielectric layer 112 defines the location and size of the vias to be formed subsequently. Then, using the second intermediate dielectric layer 112 as a mask, the second protective layer 162 and the first insulating dielectric layer 20 are etched until they penetrate a certain depth into the substrate 10, forming... Figure 8 The through-hole 122 shown has a high aspect ratio.

[0052] S304, fill the through-hole to form a sacrificial structure.

[0053] S305. Remove the second intermediate dielectric layer until the second protective layer is exposed.

[0054] S306. Remove the sacrificial structure and refill the via to form a through-silicon via.

[0055] S307, forming the first protective layer.

[0056] In this embodiment of the application, combined with Figure 8 and Figure 9 Within the via 122, a sacrificial layer 132 composed of amorphous carbon or similar materials is formed using a deposition process such as chemical liquid phase deposition (or a sacrificial layer 132 composed of photoresist is formed using a deposition process such as chemical liquid phase deposition). Then, a second intermediate dielectric layer 112 is removed using a process such as dry etching, with a second protective layer 162 serving as an etching stop layer. Next, the sacrificial layer 132 composed of amorphous carbon is removed using a process such as thermal oxidation (or the sacrificial layer 132 composed of photoresist is removed using oxygen plasma ashing). Finally, an insulating layer and a barrier / seed layer are sequentially formed within the via 122, followed by electroplating of copper filler and planarization to form a silicon via 50. Then, a first protective layer 161 composed of silicon nitride or similar materials is formed using a deposition process such as chemical vapor deposition to cover the top surface of the silicon via 50.

[0057] Figure 14 This is a flowchart illustrating an optional semiconductor structure formation method provided in an embodiment of this application, which will be combined with... Figure 7 Step S103 of the above embodiment is implemented by steps S301 to S306.

[0058] S401. Before forming the sacrificial structure, a second insulating dielectric layer is formed to cover the inner wall of the through hole; wherein the second insulating dielectric layer and the second intermediate dielectric layer are made of the same material.

[0059] S402. During the process of removing the second intermediate dielectric layer, the portion of the second insulating dielectric layer covering the second intermediate dielectric layer is also removed.

[0060] Figure 15 and Figure 16 This is a schematic diagram of the formation process of an optional semiconductor structure provided in an embodiment of this application. It should be noted that... Figure 15 Specific examples are given for forming Figure 16 The second insulating dielectric layer 150 of the insulating layer 151, Figure 16 The insulating layer 151 is used to provide electrical isolation between the through-silicon via 50 and the substrate 10.

[0061] In this embodiment of the application, combined with Figure 8 and Figure 15 After forming the via 122, a second insulating dielectric layer 150 made of materials such as silicon dioxide can be formed on the inner wall of the via 122 using deposition processes such as chemical vapor deposition. Then, a sacrificial structure 133 made of amorphous carbon or photoresist is filled into the via 122. Next, a portion of the second insulating dielectric layer 150 and the second intermediate dielectric layer 112 outside the via 122 is etched away using processes such as dry etching; the second protective layer 162 can serve as an etching stop layer. Finally, after removing the sacrificial structure 133, a seed layer is sequentially prepared within the via 122, followed by electroplating of copper filler and planarization to form the silicon via 50.

[0062] It is understood that the embodiments of this disclosure can simultaneously remove the second intermediate dielectric layer 112 and a portion of the second insulating dielectric layer covering the second intermediate dielectric layer 112. Thus, the embodiments of this disclosure do not require additional steps to form the insulating layer of the isolation substrate 10 and the through-silicon via 50, nor do they require additional steps to remove the portion of the second insulating dielectric layer covering the second intermediate dielectric layer, thereby simplifying the process and improving efficiency.

[0063] In some embodiments, an etching process is used to remove the intermediate dielectric layer. This simplifies the process and reduces costs compared to using chemical mechanical polishing to remove excess intermediate dielectric layers outside the vias or contact plugs.

[0064] In some embodiments, after filling the through-hole or contact hole with conductive material, an etching process is used to remove the conductive material outside the through-hole or contact hole. This simplifies the process steps and reduces process costs compared to using chemical mechanical polishing to remove excess conductive material outside the through-hole or contact plug.

[0065] In some embodiments of this application, step S104 of the above embodiments can also be implemented by S501 to S5003, and will be described in conjunction with each step.

[0066] S501. A patterned third intermediate medium layer is formed on the first protective layer.

[0067] Here, for reference Figure 11 On the first protective layer 161, a third intermediate dielectric material layer composed of silicon dioxide or a low dielectric constant material is deposited through deposition processes such as chemical vapor deposition. Subsequently, photoresist is coated on the third intermediate dielectric layer, and after exposure and development, a target pattern is formed. Then, using this pattern as a mask, the third intermediate dielectric material layer is etched to form a patterned third intermediate dielectric layer 113.

[0068] S502. Using the patterned third intermediate dielectric layer as a mask, etch the first protective layer until the top surface of the contact plug and the top surface of the through-silicon via are exposed, forming the first groove.

[0069] Here, for reference Figure 11 Using the patterned third hard mask as a mask, the first protective layer 161 is etched through processes such as dry etching until the top surface of the contact plug (typically tungsten or cobalt) and the top surface of the through-silicon via (typically copper) are exposed. This forms a precisely aligned first groove 140, the sidewalls of which are composed of the remaining third intermediate dielectric layer 113 and the first protective layer 161.

[0070] S503, Fill the first groove to form a metal layer.

[0071] Here, for reference Figure 11 A physical vapor deposition (PVD) process is used to deposit a continuous metal diffusion barrier layer (such as tantalum nitride) and a metal seed layer (such as copper) on the entire surface of the structure, including the first groove 140. Subsequently, an electrochemical electroplating process is used, with the seed layer as the cathode, to electrochemically deposit copper, ensuring that the copper fully fills the first groove 140. After filling, a chemical mechanical polishing (CMP) process is used to remove and planarize the excess copper metal layer, seed layer, and barrier layer outside the first groove 140 area, leaving the metal only within the first groove 140, thus forming a structure as shown in the diagram. Figure 1The isolated and patterned metal layer 40 shown achieves ohmic contact with the contact plug 60 and the through-silicon via 50.

[0072] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first insulating dielectric layer is formed on the substrate; Forming through-silicon vias and contact plugs; wherein, before etching the vias forming the through-silicon vias and / or the contact holes forming the contact plugs, an intermediate dielectric layer is formed on the first insulating dielectric layer; before filling the vias and / or the contact holes with conductive material, a sacrificial structure is formed in the vias or the contact holes, and the intermediate dielectric layer and the sacrificial structure are removed sequentially; A metal layer is formed; wherein the through-silicon via and the contact plug are both in contact with the metal layer; the height difference between the top surface of the through-silicon via and the top surface of the contact plug in the first direction is less than the thickness of the metal layer in the first direction.

2. The forming method according to claim 1, characterized in that, The intermediate dielectric layer includes: a first intermediate dielectric layer; forming the through-silicon via and the contact plug includes: The through-silicon via (TSV) and a first protective layer are formed; wherein the first protective layer covers the top surface of the TSV and the first insulating dielectric layer; the TSV penetrates the first insulating dielectric layer and at least a portion of the substrate; A patterned first intermediate medium layer is formed on the first protective layer; Using the patterned first intermediate dielectric layer as a mask, the first protective layer and the first insulating dielectric layer are etched to form the contact hole; The contact hole is filled to form the sacrificial structure; Remove the first intermediate dielectric layer until the first protective layer is exposed; The sacrificial structure is removed and the contact hole is refilled to form the contact plug.

3. The forming method according to claim 1, characterized in that, The intermediate dielectric layer includes: a second intermediate dielectric layer; forming the through-silicon via and the contact plug includes: The contact plug and the second protective layer are formed; wherein the second protective layer covers the top surface of the contact plug and the first insulating dielectric layer; the contact plug penetrates the first insulating dielectric layer; A patterned second intermediate medium layer is formed on the second protective layer; Using the patterned second intermediate dielectric layer as a mask, the second protective layer, the first insulating dielectric layer, and the substrate are etched to form the via. The through-holes are filled to form a sacrificial structure; Remove the second intermediate dielectric layer until the second protective layer is exposed; The sacrificial structure is removed and the via is refilled to form the silicon via; Forming the first protective layer.

4. The forming method according to claim 3, characterized in that, The forming method further includes: Before forming the sacrificial structure, a second insulating dielectric layer is formed to cover the inner wall of the through hole; wherein the second insulating dielectric layer and the second intermediate dielectric layer are made of the same material; During the removal of the second intermediate dielectric layer, a portion of the second insulating dielectric layer covering the second intermediate dielectric layer is also removed.

5. The forming method according to claim 1, characterized in that, The intermediate dielectric layer is removed using an etching process.

6. The forming method according to claim 1, characterized in that, After filling the through hole or the contact hole with conductive material, the conductive material outside the through hole or the contact hole is removed by an etching process.

7. The forming method according to claim 2 or 3, characterized in that, Forming the metal layer includes: A patterned third intermediate medium layer is formed on the first protective layer; Using the patterned third intermediate dielectric layer as a mask, the first protective layer is etched until the top surface of the contact plug and the top surface of the through silicon via are exposed, forming a first groove; The first groove is filled to form the metal layer.

8. The forming method according to claim 1, characterized in that, The material of the sacrificial structure is different from the materials of the intermediate dielectric layer and the first insulating dielectric layer.

9. The forming method according to claim 8, characterized in that, The material of the sacrificial structure includes either amorphous carbon or photoresist.

10. The forming method according to claim 2 or 3, characterized in that, The material of the first protective layer includes silicon nitride; the material of the second insulating dielectric layer includes silicon oxide.

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