A semiconductor device and a manufacturing method thereof
By employing guided self-assembly technology using molecular brush materials and block copolymer layers in semiconductor device manufacturing to form columnar phase layers, the problem of high-cost lithography machines has been solved, achieving low-cost and high-efficiency metal interconnects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG ELECTRONICS (SHAOXING) CORP
- Filing Date
- 2026-05-07
- Publication Date
- 2026-06-05
AI Technical Summary
Existing technologies require the use of high-precision lithography machines to form metal interconnects, resulting in high production costs and difficulty in effectively reducing the aspect ratio of metal interconnects.
By employing a guided self-assembly technique using molecular brush material layers and block copolymer layers, columnar first and second phase layers are formed in the trenches. Small-sized through-hole patterns are formed by etching, avoiding the use of advanced photolithography machines.
This reduces the production cost of forming metal interconnects, while enabling metal trenches with a smaller aspect ratio, eliminating the need for high-precision lithography machines and improving process efficiency.
Smart Images
Figure CN122161437A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In integrated circuit manufacturing, metal interconnects serve as the medium for signal transmission between peripheral circuits and internal chip devices, playing a crucial role in the integrated circuit. With the continuous development of semiconductor technology, the size of integrated circuit devices is constantly decreasing, and the size of metal interconnects is also shrinking accordingly. This leads to a continuous increase in the aspect ratio of metal trenches, requiring more advanced photolithography machines to obtain metal trenches with even larger aspect ratios, thus increasing production costs. Therefore, there is an urgent need to find a new method for forming small-linewidth metal interconnects to solve these problems.
[0003] In related technologies, a double damascene process is typically used to form metal trenches and contact vias, thereby reducing the aspect ratio of the metal interconnects. Specifically, the dielectric layer is first etched to form contact vias, and then the dielectric layer is etched again in the upper part of the contact vias to form metal trenches. The metal trenches and contact vias constitute a double damascene structure. Next, copper seeds are filled into the double damascene structure, and copper is epitaxially grown. Then, excess copper is removed by chemical mechanical polishing to form copper wires. However, in the process of forming copper wire interconnects, via etching requires a higher precision photomask level, resulting in high manufacturing costs. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, the method comprising: A semiconductor structure is provided, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the semiconductor structure, and a trench is formed in the second dielectric layer; A molecular brush material layer is formed, the molecular brush material layer at least covering the sidewalls and bottom of the trench; A block copolymer layer is formed on the molecular brush material layer, the block copolymer layer at least partially filling the trench; The block copolymer layer is heat-treated to cause phase separation of the block copolymer layer, forming at least a columnar first phase layer and a second phase layer, wherein a columnar first phase layer is formed in the second phase layer within the trench; At least the first phase layer within the trench is removed to form a patterned second phase layer, wherein the patterned second phase layer includes voids located in the trench and penetrating the second phase layer; Using the patterned second phase layer as a mask, the first dielectric layer is etched to form a via through the first dielectric layer, and the patterned second phase layer is removed.
[0006] In one embodiment, when removing the first phase layer, the etching selectivity ratio of the first phase layer to the second phase layer is greater than 2:1.
[0007] In one embodiment, forming a molecular brush material layer, the molecular brush material layer at least covering the sidewalls and bottom of the trench, includes: Molecular brush material is spin-coated at least on the sidewalls and bottom of the trench to form an initial molecular brush material layer; The initial molecular brush material layer is subjected to a first annealing treatment to cause a grafting reaction in a portion of the initial molecular brush material layer; The initial molecular brush material layer that has not undergone grafting reaction is removed by a cleaning process to form a molecular brush material layer.
[0008] In one embodiment, the thickness of the initial molecular brush material layer ranges from 150 nm to 300 nm, and the thickness of the molecular brush material layer ranges from 3 nm to 10 nm.
[0009] In one embodiment, the heat treatment includes a second annealing treatment, wherein the temperature range of the second annealing treatment is 200°C to 300°C, and / or the annealing time of the second annealing treatment is less than 10 minutes.
[0010] In one embodiment, the molecular brush material layer is made of PS-OH or PS-r-PMMA, and the block copolymer layer is made of PS-b-PMMA or PS-b-PDMS.
[0011] In one embodiment, the process of removing at least the first phase layer within the trench includes plasma etching, wherein the etching gas for plasma etching includes at least one gas selected from O2, CO, and CO2.
[0012] In one embodiment, a structure to be connected is formed in the semiconductor structure, the structure to be connected is located below the trench, and an etch barrier layer is formed between the semiconductor structure and the first dielectric layer. The manufacturing method further includes: removing a portion of the etch barrier layer so that the via penetrates the first dielectric layer and the etch barrier layer, and the bottom of the via exposes a portion of the structure to be connected, wherein the structure to be connected includes a metal structure.
[0013] In one embodiment, the second dielectric layer includes an isolation dielectric layer and a hard mask layer located on the isolation dielectric layer, and the manufacturing method further includes: After removing the etch barrier layer at the bottom of the via, a deposited metal material layer fills the trench and the via, and covers the hard mask layer; Remove the metal material layer on the hard mask layer and the hard mask layer to form an interconnect structure within the trench and the via.
[0014] This application also provides a semiconductor device, which is manufactured using the above-described semiconductor device manufacturing method.
[0015] The semiconductor device and manufacturing method of the present application embodiment form a molecular brush material layer in a trench, then form a block copolymer layer on the molecular brush material layer, and perform phase separation of the block copolymer layer through heat treatment to achieve guided self-assembly of the block copolymer to form a columnar first phase layer and a second phase layer. The first phase layer is removed to form a small-sized via pattern, and then the first dielectric layer is etched to form a via. Thus, a small-sized via pattern is formed through a guided self-assembly process, eliminating the need for an advanced photolithography machine to form the via pattern. At the same time, the level of photomask required to form the double damask structure is reduced, thereby reducing production costs. Attached Figure Description
[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0017] In the attached image: Figures 1A-1D A cross-sectional view of a double damask structure formed by sequentially performing the steps of a manufacturing method involving related technologies is shown. Figure 2 A flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of this application; Figures 3A-3I A cross-sectional view of a semiconductor device obtained by sequentially performing a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Detailed Implementation
[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0024] In integrated circuit manufacturing, the back-end processes are primarily responsible for the metal interconnects between transistors within the chip and the signal connections between the chip and external circuits. Metal interconnects serve as the medium for signal transmission between peripheral circuits and internal chip components, playing a crucial role in integrated circuits. With the continuous development of semiconductor technology, the size of integrated circuit devices is constantly decreasing, while the number of devices integrated per unit area is increasing. This means that the linewidth and spacing of the metal interconnects connecting these devices must also decrease accordingly.
[0025] As linewidth shrinks, the metal thickness cannot be reduced proportionally to prevent excessive increase in resistance of the metal conductors. Consequently, the aspect ratio of the metal trenches continues to rise. To form fine metal trench patterns, lithography machines with shorter wavelengths are required, meaning more advanced lithography machines are needed to obtain metal trenches with larger aspect ratios. These lithography machines are extremely expensive, and the costs of supporting consumables such as masks and photoresists also increase significantly, greatly raising production costs. Furthermore, advanced lithography machines not only require substantial investment but are also difficult to obtain in the current environment. Therefore, there is an urgent need to find a new method for forming small-linewidth metal interconnects to solve the above problems.
[0026] In related technologies, a double damascene process is commonly used to form metal trenches and contact vias, thereby reducing the aspect ratio of the metal interconnects. In the double damascene process, copper wire is typically chosen as the metal interconnect because copper has lower resistivity and better resistance to electromigration compared to aluminum. Specifically, firstly, as... Figure 1A As shown, a dielectric layer 11 is formed on the substrate 10, and then, as Figure 1B As shown, the etching dielectric layer 11 forms the contact via 12, and then, as Figure 1C As shown, the etched portion of the dielectric layer 11 forms a metal trench 13. The metal trench 13 and the contact via 12 constitute a damascus structure. Then, as... Figure 1DAs shown, copper seeds are filled into the Damascus structure, and copper layer 14 is epitaxially grown. Finally, the excess copper layer 14 is removed by chemical mechanical polishing to form copper wires as metal interconnects. However, in the process of forming copper wire interconnects, the via etching requires a higher precision photomask level, resulting in high manufacturing costs.
[0027] Therefore, in view of the aforementioned technical problems, this application provides a semiconductor device and a method for manufacturing the same, wherein the method for manufacturing the semiconductor device includes the following steps: Step S1: Provide a semiconductor structure, and sequentially form a first dielectric layer and a second dielectric layer on the semiconductor structure, wherein a trench is formed in the second dielectric layer; Step S2, forming a molecular brush material layer, the molecular brush material layer at least covering the sidewalls and bottom of the trench; Step S3: A block copolymer layer is formed on the molecular brush material layer, the block copolymer layer at least partially filling the trench; Step S4: The block copolymer layer is heat-treated to cause phase separation of the block copolymer layer, forming at least a columnar first phase layer and a second phase layer, wherein a columnar first phase layer is formed in the second phase layer within the trench; Step S5, at least the first phase layer in the trench is removed to form a patterned second phase layer, wherein the patterned second phase layer includes a cavity located in the trench and penetrating the second phase layer; Step S6: Using the patterned second phase layer as a mask, etch the first dielectric layer and the second dielectric layer to form a via through the first dielectric layer, and remove the patterned second phase layer.
[0028] The semiconductor device manufacturing method of this application embodiment forms a molecular brush material layer in a trench, then forms a block copolymer layer on the molecular brush material layer, and performs phase separation of the block copolymer layer through heat treatment to achieve guided self-assembly of the block copolymer to form a columnar first phase layer and a second phase layer. The first phase layer is removed to form a small-sized via pattern, and then the first dielectric layer is etched to form a via. Thus, a small-sized via pattern is formed through guided self-assembly process, eliminating the need for advanced photolithography to form the via pattern. At the same time, the level of photomask required to form the double damask structure is reduced, thereby reducing production costs.
[0029] Below, for reference Figure 2 and Figures 3A-3I The method for manufacturing the semiconductor device of this application is described in detail.
[0030] For example, the method for manufacturing a semiconductor device according to this application includes the following steps: First, refer to Figure 2Step S1 is executed to provide a semiconductor structure, on which a first dielectric layer and a second dielectric layer are sequentially formed, and a trench is formed in the second dielectric layer.
[0031] For example, such as Figure 3A As shown, a semiconductor structure is provided including a substrate 300 and a structure to be connected 301 formed in the substrate 300. The structure to be connected 301 is located below a trench subsequently formed, and the structure to be connected 301 can be a metal structure. The substrate 300 can be any suitable substrate material known in the art, such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, epitaxial silicon substrate, silicon-on-insulator (SoI) substrate, or germanium-on-insulator (GoI) substrate, or a substrate made of other suitable materials, but is not limited thereto.
[0032] An etch barrier layer 302, a first dielectric layer 303, and a second dielectric layer 304 are sequentially formed on a semiconductor structure. The second dielectric layer 304 includes an isolation dielectric layer 3041 and a hard mask layer 3042 located on the isolation dielectric layer 3041. The first dielectric layer 303 is made of the same material as the hard mask layer 3042.
[0033] For example, the material of the etch barrier layer 302 includes, but is not limited to, silicon nitride, and the material of the first dielectric layer 303 includes, but is not limited to, silicon oxide. For example, in a plasma-enhanced chemical vapor deposition (PECVD) apparatus, ethyl orthosilicate (TEOS) is used as a precursor and reacted with oxygen to generate a SiO2 thin film.
[0034] The material of the isolation dielectric layer 3041 includes, but is not limited to, low-k dielectric constant materials. For example, initial oxygen is introduced into the deposition reaction chamber of the PECVD equipment, followed by the introduction of a precursor (such as octamethylcyclotetrasiloxane) into the chamber, and then the power supply is turned on to perform plasma discharge, so that the methyl groups in the octamethylcyclotetrasiloxane molecule are partially retained in the plasma to form Si-CH3 bonds, thereby reducing the dielectric constant of the material and thus forming a low-k dielectric constant isolation dielectric layer 3041.
[0035] Then, continue as follows Figure 3A As shown, a patterned mask layer 305 is formed on the second dielectric layer 304. The patterned mask layer 305 defines the location and size of the trenches to be formed subsequently. For example, the patterned mask layer 305 includes a photoresist layer.
[0036] Next, as shown in Figure 3B, the second dielectric layer 304 is etched using the patterned mask layer 305 as a mask to form trenches 306 in the second dielectric layer 304. Exemplarily, the orthogonal projection of the trenches onto the substrate is an ellipse, and the length of the major axis of this ellipse ranges from 90 nm to 110 nm, for example, the length of the major axis of the ellipse is 90 nm, 100 nm, or 110 nm. Then, the patterned mask layer 305 is removed.
[0037] Next, step S2 is performed to form a molecular brush material layer, which at least covers the sidewalls and bottom of the trench.
[0038] For example, first, the area where the molecular brush material layer is to be formed is cleaned, for example, by using SC1 and SC2 standard cleaning solutions to remove organic contaminants and metal ions from the sidewalls and bottom of the trench. Then, by oxygen plasma treatment, silanol groups are generated on the sidewalls and bottom of the trench. These silanol groups are the "anchors" for subsequent grafting reactions.
[0039] Next, the molecular brush material is dissolved in a suitable solvent to prepare a molecular brush solution. For example, the molecular brush material includes PS-OH (hydroxyl-terminated polystyrene) or PS-r-PMMA (polystyrene-polymethyl methacrylate random copolymer).
[0040] Next, the prepared molecular brush solution is uniformly coated onto the sidewalls and bottom of the trench using a spin-coating method. At this point, the molecular brush material adheres to the sidewalls and bottom of the trench through physical adsorption, forming an initial molecular brush material layer, before chemical bonding has been formed. For example, the thickness of the initial molecular brush material layer ranges from 150 nm to 300 nm, such as 150 nm, 200 nm, or 300 nm.
[0041] Next, the initial molecular brush material layer undergoes a first annealing treatment. For example, the wafer with the initial molecular brush material layer is placed on a hot plate and annealed at high temperature under inert gas protection. The temperature range of the first annealing treatment is 200℃~300℃. Specifically, the temperature of the first annealing treatment is 200℃, 250℃ or 300℃. During the high-temperature annealing process, the hydroxyl groups at the ends of the molecular brush material in some of the initial molecular brush material layer undergo a dehydration condensation reaction with the silanol groups on the sidewalls and bottom of the trench to form covalent bonds (Si-OC), firmly grafting the polymer chains to the sidewalls and bottom of the trench, thereby causing a grafting reaction in some of the initial molecular brush material layer.
[0042] After the grafting reaction is completed, a cleaning process is used to remove the initial molecular brush material layer that has not undergone the grafting reaction. This removes organic residues and particles from the wafer edges and back side, forming a hydrophobic surface. For example, the wafer can be rinsed with a chemical reagent, such as OK73 (a mixture of propylene glycol monomethyl ether and propylene glycol methyl ether acetate) or other common organic solvents. The rinsing time ranges from 30s to 60s, specifically 30s, 45s, or 60s. This removes the unbonded molecular brush material molecules, thus forming a hydrophobic surface. Figure 3C The molecular brush material layer 307 shown is exemplarily defined as having a thickness ranging from 3 nm to 10 nm, for example, a thickness of 3 nm, 5 nm, or 10 nm.
[0043] It is worth mentioning that, such as Figure 3C As shown, the molecular brush material layer 307 can cover not only the sidewalls and bottom of the trench 306, but also the surface of the second dielectric layer 304.
[0044] Next, continue to refer to Figure 2 Step S3 is performed to form a block copolymer layer on the molecular brush material layer, the block copolymer layer at least partially filling the trench.
[0045] For example, such as Figure 3D As shown, a spin-coating process is used to coat a block copolymer layer 308 onto a molecular brush material layer 307. For example, the material of the block copolymer layer 308 includes, but is not limited to, polystyrene-b-polymethyl methacrylate (PS-b-PMMA) or polystyrene-b-polydimethylsiloxane (PS-b-PDMS). The block copolymer layer 308 at least partially fills the trench 306. Specifically, the top surface of the block copolymer layer 308 is not lower than the top surface of the insulating dielectric layer 3041, thereby effectively protecting the sidewalls of the trenches in the double damask structure during subsequent processes. The block copolymer layer 308 can also completely fill the trench 306 and cover the surface of the second dielectric layer 304.
[0046] After the block copolymer layer is coated, the block chains of the block copolymer layer are entangled with each other without obvious phase separation. The block copolymer layer is in a thermodynamic non-equilibrium state with high free energy, and requires external energy input to evolve to the equilibrium state.
[0047] It is worth mentioning that, during the coating process of forming the block copolymer layer, when the roughness of the left and right sidewalls of the trench is approximately the same, the trench is approximately symmetrical, and the trench width is an integer multiple of the intrinsic period of the block copolymer layer, the loading rate of the block copolymer can be adjusted to ensure that the subsequently formed first phase layer is wrapped by the second phase layer and the first phase layer is located in an approximately central position. The loading rate of the block copolymer refers to the filling volume of the block copolymer in the trench, or it can also refer to the thickness of the block copolymer layer. During the coating process of forming the block copolymer layer, the block copolymer symmetrically fills the effective space of the trench without material shortage or unilateral extrusion, so that the interface can be approximately symmetrical. This ensures that the subsequent first phase layer does not have a driving force biased to one side, and thus, during the subsequent heat treatment, the first phase layer falls at the position of approximately the geometric center. At the same time, due to the close packing of the block copolymer molecular chain segments, the higher the loading rate, the more columnar structures can be accommodated. Therefore, by reducing the spin coating speed to increase the thickness of the block copolymer layer and increasing the loading rate, multiple columnar first phase layers can be formed in the second phase layer.
[0048] Next, continue to refer to Figure 2 Step S4 is performed to heat-treat the block copolymer layer to cause phase separation of the block copolymer layer, forming at least a columnar first phase layer and a second phase layer, wherein a columnar first phase layer is formed in the second phase layer within the trench.
[0049] For example, a wafer with a spin-coated block copolymer layer 308 is placed on a hot plate, and the block copolymer layer 308 is subjected to a second annealing treatment under the protection of an inert gas, such as nitrogen or argon. The temperature range of the second annealing treatment is 200°C to 300°C, for example, the temperature of the second annealing treatment is 200°C, 250°C or 300°C, and the time of the second annealing treatment is less than 10 minutes, for example, the time of the second annealing treatment is 10 minutes, 20 minutes or 30 minutes.
[0050] When the temperature rises to the target temperature, the polymer segments in the block copolymer layer change from the glassy state to the rubbery state. The segments gain enough energy to drive the aggregation of the same blocks and the separation of different blocks. As the annealing process continues, the polymer chains move to the enriched regions of the same type through segment diffusion and whole chain migration. Small clusters gradually form characteristic sizes close to the equilibrium state through merging and engulfment. The neutral surface of the molecular brush material layer guides the vertical orientation, while the trench sidewalls provide physical boundaries, thereby constraining the alignment direction.
[0051] The principle of phase separation in the block copolymer layer is the self-assembly behavior of the binary mixture in a planar substrate and an elliptical confined space. The self-assembly behavior can be simulated by self-consistent field theory (SCFT). By self-consistently solving the diffusion equation, SCFT can accurately calculate the density distribution of the polymer and the free energy of the system, thereby predicting the most stable self-assembled structure under different conditions.
[0052] When the system's free energy reaches its minimum, an ordered nanostructure is formed, followed by cooling to form at least the following: Figure 3E The columnar first phase layer 309 and the second phase layer 310 are shown, and the columnar first phase layer 309 is formed in the second phase layer 310 within the trench 306. The columnar first phase layer 309 is surrounded by the second phase layer 310. For example, the diameter of the columnar first phase layer is in the range of 7nm to 26nm, such as 7nm, 15nm or 26nm.
[0053] It is worth mentioning that under heat treatment, different blocks of the block copolymer spontaneously separate and aggregate at the nanoscale due to their different chemical properties, thus forming a periodic ordered nanostructure, i.e., microphase separation occurs, resulting in different phase layers. Blocks with larger volume fractions form a continuous phase, while blocks with smaller volume fractions form columnar structures, periodically dispersed in the continuous phase. For example, when the block copolymer layer is made of polystyrene-b-polymethyl methacrylate (PS-b-PMMA), columnar first and second phase layers are formed after microphase separation. Specifically, when the volume fraction of polymethyl methacrylate is small, it forms a columnar structure dispersed in a continuous matrix composed of polystyrene. In other words, the material of the first phase layer is polymethyl methacrylate (PMMA), and the material of the second phase layer is polystyrene (PS).
[0054] Next, continue to refer to Figure 2 Step S5 is performed to remove at least the first phase layer within the trench to form a patterned second phase layer, wherein the patterned second phase layer includes voids located in the trench and penetrating the second phase layer.
[0055] For example, when the first phase layer 309 is removed using a plasma etching process, the second phase layer 310 may also be removed simultaneously. Therefore, when removing the first phase layer 309, the etching selectivity ratio of the first phase layer 309 to the second phase layer 310 is greater than 2:1. For example, the etching selectivity ratio of the first phase layer 309 to the second phase layer 310 is 2:1, 5:1, or 10:1. In other words, if... Figure 3FAs shown, when plasma etching is used to remove the first phase layer 309, the etching rate of the first phase layer 309 is more than twice that of the second phase layer 310. This results in the first phase layer 309 being consumed at a much higher rate than the second phase layer, ultimately leading to... Figure 3G As shown, a cavity 311 penetrating the second phase layer 310 is formed in the trench 306, thereby forming a patterned second phase layer 312. The size of the cavity 311 is much smaller than the size of the trench 306. The cavity 311 serves as a via pattern for subsequent via formation, thus eliminating the need for photolithography to form a smaller via template, thereby reducing the demand for advanced photolithography equipment. The etching gas used in the plasma etching includes at least one gas selected from O2, CO, and CO2.
[0056] It is worth mentioning that when the block copolymer layer 308 covers the surface of the second dielectric layer 304, after heat treatment, the block copolymer layer 308 on the surface of the second dielectric layer 304 will also undergo phase separation to form a first phase layer 309 and a second phase layer 310, as shown below. Figure 3F As shown, when the first phase layer 309 is etched away, the second phase layer 310 and the first phase layer 309 on the surface of the second dielectric layer 304 are also removed. During the removal of the second phase layer 310 and the first phase layer 309 from the surface of the second dielectric layer 304, because the etching rate of the first phase layer 309 is greater than that of the second phase layer 310, the first phase layer 309 on the surface of the second dielectric layer 304 is removed more quickly, exposing the surface of the second dielectric layer 304 at the corresponding location. Continued etching then forms an inner groove at the corresponding location of the second dielectric layer 304.
[0057] Next, continue to refer to Figure 2 Step S6 is executed, using the patterned second phase layer as a mask, the first dielectric layer is etched to form a via through the first dielectric layer, and the patterned second phase layer is removed.
[0058] For example, such as Figure 3H As shown, using a patterned second phase layer 312 as a mask, the first dielectric layer 303 and the etch barrier layer 302 are etched, removing part of the first dielectric layer 303 and part of the etch barrier layer 302 to form a via 313 penetrating the first dielectric layer 303 and the etch barrier layer 302. The bottom of the via 313 exposes part of the structure 301 to be connected. At the same time as the via 313 is etched to form the via 313, the patterned second phase layer 312 is also removed, exposing the entire trench 306, thereby forming a double damask structure including the trench 306 and the via 313.
[0059] It is worth mentioning that since the first dielectric layer 303 is made of the same material as the hard mask layer 3042, the hard mask layer 3042 will also be partially etched when the first dielectric layer 303 is etched. At this time, the hard mask layer 3042 also protects the isolation dielectric layer 3041 so that the isolation dielectric layer 3041 will not be etched when the first dielectric layer 303 is etched to form a via, thereby ensuring the performance of the semiconductor device.
[0060] Next, a deposited metallic material layer (not shown) fills the trenches 306 and vias 313, and covers them with a hard mask layer 3042. Then, the metallic material layer is planarized to flatten the surface of the double damask structure. Then, as... Figure 3I As shown, the metal material layer on the hard mask layer 3042 and the hard mask layer 3042 are removed to form an interconnect structure 314 in the trench 306 and the via 313. One end of the interconnect structure 314 is connected to the structure to be connected 301, and the other end of the interconnect structure 314 is connected to the external circuit, thereby realizing the connection between the structure to be connected inside the semiconductor structure and the external circuit.
[0061] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0062] The semiconductor device manufacturing method of this application embodiment forms a molecular brush material layer in a trench, then forms a block copolymer layer on the molecular brush material layer, and performs phase separation of the block copolymer layer through heat treatment to achieve guided self-assembly of the block copolymer to form a columnar first phase layer and a second phase layer. The first phase layer is removed to form a small-sized via pattern, and then the first dielectric layer is etched to form a via. Thus, a small-sized via pattern is formed through guided self-assembly process, eliminating the need for advanced photolithography to form the via pattern. At the same time, the level of photomask required to form the double damask structure is reduced, thereby reducing production costs.
[0063] This application also provides a semiconductor device, which is manufactured using the above-described semiconductor device manufacturing method, and the semiconductor device can also achieve the beneficial effects of the above-described manufacturing method.
[0064] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor structure is provided, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the semiconductor structure, and a trench is formed in the second dielectric layer; A molecular brush material layer is formed, the molecular brush material layer at least covering the sidewalls and bottom of the trench; A block copolymer layer is formed on the molecular brush material layer, the block copolymer layer at least partially filling the trench; The block copolymer layer is heat-treated to cause phase separation of the block copolymer layer, forming at least a columnar first phase layer and a second phase layer, wherein the columnar first phase layer is formed in the second phase layer within the trench; At least the first phase layer within the trench is removed to form a patterned second phase layer, wherein the patterned second phase layer includes voids located in the trench and penetrating the second phase layer; Using the patterned second phase layer as a mask, the first dielectric layer is etched to form a via through the first dielectric layer, and the patterned second phase layer is removed.
2. The manufacturing method as described in claim 1, characterized in that, When removing the first phase layer, the etching selectivity ratio of the first phase layer to the second phase layer is greater than 2:
1.
3. The manufacturing method as described in claim 1, characterized in that, The formation of the molecular brush material layer, which at least covers the sidewalls and bottom of the trench, includes: Molecular brush material is spin-coated at least on the sidewalls and bottom of the trench to form an initial molecular brush material layer; The initial molecular brush material layer is subjected to a first annealing treatment to cause a grafting reaction in a portion of the initial molecular brush material layer; The initial molecular brush material layer that has not undergone grafting reaction is removed by a cleaning process to form the molecular brush material layer.
4. The manufacturing method as described in claim 3, characterized in that, The thickness of the initial molecular brush material layer ranges from 150 nm to 300 nm, and the thickness of the molecular brush material layer ranges from 3 nm to 10 nm.
5. The manufacturing method as described in claim 1, characterized in that, The heat treatment includes a second annealing treatment, wherein the temperature range of the second annealing treatment is 200℃~300℃, and / or the annealing time of the second annealing treatment is less than 10 min.
6. The manufacturing method as described in claim 1, characterized in that, The molecular brush material layer is made of PS-OH or PS-r-PMMA, and the block copolymer layer is made of PS-b-PMMA or PS-b-PDMS.
7. The manufacturing method as described in claim 1, characterized in that, The process for removing at least the first phase layer within the trench includes plasma etching, wherein the etching gas for plasma etching includes at least one of O2, CO, and CO2.
8. The manufacturing method as described in claim 1, characterized in that, A structure to be connected is formed in the semiconductor structure, the structure to be connected is located below the trench, and an etch barrier layer is formed between the semiconductor structure and the first dielectric layer. The manufacturing method further includes: removing a portion of the etch barrier layer so that the via penetrates the first dielectric layer and the etch barrier layer, and the bottom of the via exposes a portion of the structure to be connected, wherein the structure to be connected includes a metal structure.
9. The manufacturing method as described in claim 8, characterized in that, The second dielectric layer includes an isolation dielectric layer and a hard mask layer located on the isolation dielectric layer, and the manufacturing method further includes: After removing the etch barrier layer at the bottom of the via, a deposited metal material layer fills the trench and the via, and covers the hard mask layer; Remove the metal material layer on the hard mask layer and the hard mask layer to form an interconnect structure within the trench and the via.
10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method described in any one of claims 1 to 9.