Semiconductor device, method of manufacturing the same, and storage system

Abstract

Embodiments of the present application provide a semiconductor device and a preparation method thereof. The semiconductor device comprises: a stack structure comprising a plurality of gate insulating layers and gate layers arranged in a plurality of layers; a plurality of contact portions, each of which penetrates to a different gate layer along a stacking direction of the stack structure; and a plurality of contact portions comprising a first contact portion and a second contact portion, wherein a projected area of the first contact portion in the stacking direction is greater than a projected area of the second contact portion in the stacking direction. By designing the projected areas of the first contact portion and the second contact portion in the stacking direction to be different in size, more contact portions can be arranged more compactly in a limited space, and the space of the step region can be compressed, thereby reducing the size of the semiconductor device.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on October 27, 2022, with application number 202211324858.4 and title "Semiconductor Device and Preparation Method Thereof and Storage System Thereof". Technical Field

[0002] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device, its fabrication method, and a storage system. Background Technology

[0003] Memory is a storage device used to store information in modern information technology. As the demand for integration and data storage density in various electronic devices continues to increase, ordinary two-dimensional storage devices are finding it increasingly difficult to meet the requirements. In this context, three-dimensional (3D) memory has emerged.

[0004] 3D memory has become a mainstream product in the non-volatile memory market due to its high storage density, controllable production costs, suitable erasure speed, and retention characteristics. As the application scenarios of 3D memory become increasingly diversified, there is a need to maintain a small memory size while achieving high storage capacity, thus placing higher demands on memory size. Summary of the Invention

[0005] In view of this, the present disclosure aims to provide a semiconductor device, a method for fabricating the same, and a memory system.

[0006] This disclosure provides a semiconductor device, including: a stacked structure including multiple overlapping gate insulating layers and gate layers; a plurality of contacts, each of which extends through to a different gate layer along the stacking direction of the stacked structure; the plurality of contacts including a first contact and a second contact, wherein the projected area of ​​the first contact in the stacking direction is greater than the projected area of ​​the second contact in the stacking direction.

[0007] In some implementations, the size of the first contact portion is larger than the size of the second contact portion along the stacking direction.

[0008] In some embodiments, the first contact portion and the second contact portion are arranged along a first direction, and there is a gap between the geometric centers of the projections of the first contact portion and the second contact portion in the first direction, and the first direction intersects the stacking direction.

[0009] In some embodiments, each of the contact portions includes a first connection portion and a second connection portion that are in contact with each other, the first connection portion extending along the stacking direction and the second connection portion extending along a direction perpendicular to the stacking direction and connecting to the gate layer.

[0010] In some embodiments, the stacked structure includes a core region and a connecting region disposed along a first direction; a plurality of first gate gap structures penetrating the stacked structure, located in the core region and the connecting region and extending along the first direction; the plurality of first gate gap structures are arranged along a second direction, the second direction being perpendicular to the first direction and perpendicular to the stacking direction.

[0011] In some embodiments, along the second direction, the minimum distance between the plurality of contact portions arranged along the first direction and the first gate gap structure that is closest to them is equal.

[0012] In some embodiments, it further includes: a second gate gap structure, comprising a plurality of second sub-gate gap structures spaced apart along the first direction; the second gate gap structure is located at least in the core region.

[0013] In some embodiments, the system further includes: a plurality of contact units arranged along the second direction, each contact unit including a plurality of contact portions arranged in a row along the first direction.

[0014] In some embodiments, the geometric centers of the projections of adjacent contact portions located in different contact units in the second direction are spaced apart.

[0015] In some implementations, the contact unit is located in the connection area.

[0016] In some embodiments, the contact unit includes a plurality of channel structures between itself and the nearest first gate gap structure, the plurality of channel structures being arranged along the first direction.

[0017] In some embodiments, the projection shape of the contact portion in the stacking direction can be at least one of a circle or a square.

[0018] This disclosure also provides a method for fabricating a semiconductor device, comprising: forming an initial stacked structure, the initial stacked structure including multiple overlapping gate insulating layers and gate sacrificial layers; forming contact holes, wherein a plurality of contact holes penetrate to different gate sacrificial layers along the stacking direction of the initial stacked structure; the plurality of contact holes including a first contact hole and a second contact hole, wherein the projected area of ​​the first contact hole in the stacking direction is greater than the projected area of ​​the second contact hole in the stacking direction; replacing a portion of each gate sacrificial layer with a gate layer; and forming a contact portion in the contact hole, the contact portion being connected to the gate layer.

[0019] In some implementations, the size of the first contact portion is larger than the size of the second contact portion along the stacking direction.

[0020] In some embodiments, the first contact portion and the second contact portion are arranged along a first direction, the geometric centers of the projections of the first contact portion and the second contact portion in the first direction are spaced apart, and the first direction intersects the stacking direction.

[0021] In some embodiments, each of the contact portions includes a first connection portion and a second connection portion interconnected with each other, the first connection portion extending along the stacking direction and the second connection portion extending perpendicular to the stacking direction and connecting to the gate layer; forming a contact hole includes: etching the initial stacked structure to a gate insulating layer adjacent to and above the target gate sacrificial layer to form an initial contact hole; forming an isolation layer within the initial contact hole; removing the isolation layer covering the bottom of the initial contact hole and exposing the target gate sacrificial layer located below and adjacent to the initial contact hole; removing the exposed portion of the target gate sacrificial layer and the portion surrounding the exposed portion to form a contact hole.

[0022] In some embodiments, the step of replacing a portion of each of the gate sacrificial layers with a gate layer further includes forming a first gate gap isolation trench that extends through the initial stacked structure.

[0023] In some embodiments, the first gate gap isolation trench is located in the connection region and the core region, and the replacement of a portion of each of the gate sacrificial layers with a gate layer includes: replacing the gate sacrificial layer located in the core region and a portion of the gate sacrificial layer located in the connection region with the gate layer via the first gate gap isolation trench.

[0024] In some embodiments, replacing the gate sacrificial layer located in the core region and a portion of the gate sacrificial layer located in the connection region with the gate layer via the first gate gap isolation trench includes: removing a portion of the gate sacrificial layer located in the connection region via the first gate gap isolation trench to form a first groove; removing the gate sacrificial layer located in the core region via the first gate gap isolation trench to form a second groove; and forming the gate layer in the first groove and the second groove.

[0025] This disclosure also provides a storage system including the semiconductor device and controller provided in the first aspect above, wherein the controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0026] This disclosure provides a semiconductor device, its fabrication method, and a memory system. One semiconductor device includes: a stacked structure comprising multiple overlapping gate insulating layers and gate layers; and a plurality of contacts extending through different gate layers along the stacking direction of the stacked structure. Each contact includes a first contact and a second contact, wherein the projected area of ​​the first contact in the stacking direction is larger than the projected area of ​​the second contact in the stacking direction. By using the different projected areas of the first and second contacts in the stacking direction, more contacts can be compactly arranged within a limited space, thereby compressing the space of the step region and reducing the size of the semiconductor device. Attached Figure Description

[0027] Figure 1 This is a top view of a semiconductor device according to some embodiments of the present disclosure; Figure 2a for Figure 1 A cross-sectional view along the middle AA'; Figure 2b for Figure 1 Cross-sectional view at the midline BB'; Figure 3 This is a top view of a semiconductor device according to other embodiments of the present disclosure; Figure 4 This is a top view of a semiconductor device according to other embodiments of the present disclosure; Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments; Figures 6-14 This is a diagram illustrating the fabrication steps of a semiconductor device according to some embodiments; Figure 15 A cross-sectional view of a semiconductor device according to some embodiments; Figure 16a This is a block diagram of a storage system according to some embodiments; Figure 16b A block diagram of a storage system according to some other embodiments; Figure 17 This is a block diagram of an electronic device according to some embodiments. Detailed Implementation

[0028] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0029] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0030] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0031] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0032] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0033] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0034] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0035] This disclosure proposes a three-dimensional memory architecture with a staircase contact (SCT) structure. The SCT architecture eliminates the need for staircase formation, simplifying the complex process and further eliminating the need for filling the staircase with a dielectric layer. It also avoids the space constraints associated with forming virtual channel structures as support structures in contact structures extending to significant depths. However, as the demand for storage capacity and memory size increases, the SCT architecture still faces the challenge of further reducing size while increasing storage capacity.

[0036] To further address the aforementioned problems, this disclosure provides a semiconductor device 100, such as... Figure 1 As shown in Figure 2, the system includes: a stacked structure 1, which includes multiple overlapping gate insulating layers 11 and gate layers 12; and multiple contact portions 2, which extend through different gate layers 12 along the stacking direction Z of the stacked structure 1; the multiple contact portions 2 include a first contact portion 21 and a second contact portion 22, wherein the projected area of ​​the first contact portion 21 in the stacking direction Z is greater than the projected area of ​​the second contact portion 22 in the stacking direction Z.

[0037] The stacked structure includes a core region C and a connection region S disposed along a first direction X, which is perpendicular to the stacking direction Z. The core region C has a storage channel structure 62 with storage function, and the connection region S has multiple contact portions 2. Since the multiple contact portions 2 in the connection region S include first contact portions 21 and second contact portions 22, and the projected areas of the first contact portions 21 and second contact portions 22 are different in the stacking direction Z, it can be understood that the contact portions 2 located in the connection region S are of different sizes. This allows for a more compact arrangement of more contact portions within a limited space, thereby compressing the space of the connection region S and reducing the size of the semiconductor device. Alternatively, it provides more space in the core region to accommodate the storage channel structure, further increasing the storage capacity.

[0038] It is understood that the first contact portion 21 and the second contact portion 22 do not represent a specific contact portion 2, but rather indicate that when comparing two contact portions 2, if the projected areas of the contact portions 2 along the stacking direction are different, then the contact portion 2 with the larger projected area is the first contact portion 21, and the contact portion 2 with the relatively smaller projected area is the second contact portion 22. In some optional embodiments, the contact portions 2 of the semiconductor device 100 located in the connection region S can be provided with two types of contact portions 2 with different projected area sizes, or three or four types of contact portions 2 with different projected area sizes.

[0039] In some optional embodiments, the connection area S may include three different sized contact portions 2. Please refer to [link / reference needed]. Figure 1 , Figure 1 The diagram illustrates a contact group Z, which includes three types of contact portions 21, 22, and 23 of different sizes. The first contact portions 21, 22, and 23 are all the same size. It should be noted that in some optional embodiments, adjacent contact portions 2 are of different sizes. Alternatively, different first contact portions 21 are spaced apart, different second contact portions 22 are spaced apart, and different third contact portions 23 are spaced apart.

[0040] This configuration allows for a more compact arrangement of contacts within a limited space, thereby compressing the space of the connection area S, reducing the size of the semiconductor device, and providing more space for the core area to accommodate the channel structure with storage functionality, further increasing storage capacity. In some optional embodiments, the projection shape of the contacts in the stacking direction Z can be at least one of a circle or a square. The embodiments disclosed herein are described using a circular projection shape as an example.

[0041] The stacked structure 1 includes multiple overlapping gate insulating layers 11 and gate layers 12. The material of the gate insulating layer 11 may include an insulating material, including at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., alumina, hafnium dioxide, etc.) and their silicates, and organic insulating materials. The gate layer 12 may include a first conductive layer 121, which may be made of a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicides. In some optional embodiments, the gate layer 12 may further include a first metal compound layer 122, which is located between the first conductive layer 121, the channel structure 6, and the gate insulating layer 11. The first metal compound layer 122 is configured as an adhesive layer to improve the adhesion between the first conductive layer 121 and the gate insulating layer 11. The material of the first metal compound layer 122 may include at least one of titanium nitride, tantalum nitride, and tungsten carbide. In some embodiments, the gate layer 12 may further include a first dielectric layer 123, which is located between the first metal compound layer 122, the channel structure 6, and the gate insulating layer 11 to reduce the risk of charge flowing from the channel structure 6 to the first conductive layer 121. The dielectric constant of the first dielectric layer 123 is greater than or equal to 7. Exemplarily, the material of the first dielectric layer 123 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0042] The accompanying drawings of this disclosure only illustrate a portion of the gate insulating layer 11 and gate layer 12 of the semiconductor device 100, and do not illustrate the substrate, nor the portion of the gate insulating layer 11 and gate layer 12 of the stacked structure on the substrate. The substrate material can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V group compounds. In actual products, the number of gate insulating layers 11 and gate layer 12 can be 64, 128, 192, 232, 360, etc., and this disclosure does not impose any limitations. Please continue to refer to [the relevant documentation]. Figure 1 As shown in Figure 2, the semiconductor device 100 provided in this disclosure further includes a gate sacrificial layer 12' on the same layer as the gate layer 12. The gate layer 12 is obtained by replacing a portion of the gate sacrificial layer 12'. The gate sacrificial layer 12' and the gate insulating layer 11 constitute an initial stacked structure, and the contact portion 2 penetrates the initial stacked structure to different gate layers 12, realizing the electrical connection between the gate layer 12 and the contact portion 2, thereby realizing the transmission of electrical signals. In some optional embodiments, the material of the gate sacrificial layer 12' includes at least one selected from silicon, silicon oxide, silicon carbide, and silicon nitride.

[0043] Please refer to Figure 2b In some optional embodiments, along the stacking direction Z, the size h1 of the first contact 21 is larger than the size h2 of the second contact 22. It can be understood that the distance from the bottom of the first contact 21 to the substrate (not shown in the figure) is less than the distance from the bottom of the second contact 21 to the substrate. Alternatively, it can be understood that the number of gate sacrificial layers 12' and gate insulating layers 11 penetrated by the first contact 21 is greater than the number of gate sacrificial layers 12' and gate insulating layers 11 penetrated by the second contact 22. In some optional embodiments, multiple first contacts 21 can penetrate different numbers of gate sacrificial layers 12' and gate insulating layers 11, and similarly, multiple second contacts 22 can penetrate different numbers of gate sacrificial layers 12' and gate insulating layers 11.

[0044] Please continue to refer to this. Figure 1In some optional embodiments, taking the orthographic projection of the contact portion 2 onto the stacked structure as a circle, the contact portion of the connection region S may include three different sizes of first contact portion 21, second contact portion 22, and third contact portion 23. The diameter d3 of the projected shape of the third contact portion 23 onto the stacked structure is larger than the diameter d1 of the projected shape of the first contact portion 21 onto the stacked structure, and the diameter d1 of the projected shape of the first contact portion 21 onto the stacked structure is larger than the diameter d2 of the projected shape of the second contact portion 22 onto the stacked structure. The second contact portion 22 penetrates layers 1-120 of the gate insulating layer, the first contact portion 21 penetrates layers 121-241 of the gate insulating layer, and the third contact portion 23 penetrates layers 241-360. In some optional embodiments, when there are three different sizes of first contact portion 21, second contact portion 22, and third contact portion 23, two adjacent contact portions 2 along the first direction X are considered as a group of contact portions. The shortest distance between two adjacent contact portions 2 in the same group of two adjacent groups of contact portions arranged along the first direction X is different. For example, when the three contact portions 21, 22, and 23 are arranged sequentially along the first direction, the shortest distance between the first contact portion 21 and the second contact portion 22 is different from the shortest distance between the second contact portion 22 and the third contact portion 23. This design allows for flexible arrangement of the first contact portion 21 and the second contact portion 22, without being limited by the equal spacing between adjacent contact portions 2. This enables a more compact arrangement of the contact portions 2, saving space in the connection area S and reducing the size of the semiconductor device.

[0045] This design allows for flexible design of the contact size based on the number of stacked layers of the semiconductor device. This reduces the process difficulty in fabricating the contact while decreasing the size of the connection region S, thereby further increasing the storage capacity.

[0046] Please continue to refer to this. Figure 2aIn some optional embodiments, each contact portion 2 in the semiconductor device 100 provided in this disclosure includes a first connection portion 31 and a second connection portion 32 interconnected with each other. The first connection portion 31 extends along the stacking direction Z, and the second connection portion 32 extends perpendicular to the stacking direction Z and connects to the gate layer 12. The first connection portion 31 and the second connection portion 32 are integrally formed, meaning that the first connection portion 31 and the second connection portion 32 are a single unit. It should be explained that the projected area of ​​the first connection portion 31 along the stacking direction Z is smaller than the projected area of ​​the second connection portion 32 along the stacking direction Z. The second connection portion 32 is formed by extending outward from the first connection portion 31, meaning that the geometric centers of the first connection portion 31 and the second connection portion 32 almost overlap. The projected shape and projected area of ​​the contact portion 2 in the stacking direction Z in this disclosure can be understood as the projected area and projected shape of the second connection portion 31 in the stacking direction Z. In some embodiments, the geometric centers of the first connecting portion 31 and the second connecting portion 32 in each contact portion 2 overlap, and the distance between the edge of the orthographic projection of the first connecting portion 31 on the stacked structure and the edge of the orthographic projection of the second connecting portion 32 on the stacked structure along the first direction X is equal.

[0047] Along the stacking direction Z, the first connecting portion 31 includes a top surface and a bottom surface, wherein the surface in contact with the second connecting portion 32 is the bottom surface, and the surface opposite to the bottom surface is the top surface. In some optional embodiments, the top and bottom surfaces of the first connecting portion 31 are identical, i.e., they have approximately the same shape and surface area. Alternatively, it can be understood that the first connecting portion 31 has the same width vertically. In other optional embodiments, the first connecting portion 31 has unequal width vertically; for example, the area of ​​the top surface is larger than the area of ​​the bottom surface. It is understood that the larger the area of ​​the top surface of the first connecting portion 31, the larger the ratio of the area of ​​the bottom surface to the area of ​​the top surface. The area of ​​the top surface of the first connecting portion 31 of the first contact portion 21 is larger than the area of ​​the top surface of the first connecting portion 31 of the second contact portion 22; therefore, the ratio of the area of ​​the bottom surface to the top surface of the first connecting portion 31 of the first contact portion is greater than the ratio of the area of ​​the bottom surface to the top surface of the first connecting portion 31 of the second contact portion 22.

[0048] In some alternative embodiments, please refer to Figure 1 and Figure 2aThe semiconductor device has 268 layers, including the first contact portion 21, the second contact portion 22, and the third contact portion 23 described above. The diameter of the top surface of the first connection portion of the first contact portion 21 can be 0.8 μm, the diameter of the top surface of the first connection portion of the second contact portion 22 can be 0.6 μm, and the diameter of the top surface of the first connection portion of the third contact portion 23 can be 1.1 μm. The second contact portion 22 penetrates layers 1-120 of the gate insulating layer, the first contact portion 21 penetrates layers 121-241 of the gate insulating layer, and the third contact portion 23 penetrates layers 241-268.

[0049] Compared to the scheme where each contact portion 2 is the same size and has a diameter of 1.3 μm, the above design, which uses the first contact portion 21, the second contact portion 22, and the third contact portion 23 of different sizes as a contact group Z, can save at least 90 μm of the length of the connection area S.

[0050] It should be clarified that the terms "same" and "equal" mentioned above should be understood as "same" or "equal" within the range of process error, rather than "absolutely same" or "equal." In some optional embodiments, the contact portion 2 may further include a second conductive layer 221. The material of the second conductive layer 221 may include a conductive material, such as at least one selected from tungsten, cobalt, copper, aluminum, doped silicon, and silicides. In some optional embodiments, the contact portion 2 may further include a second metal compound layer 222, wherein the material of the second metal compound layer 222 includes at least one selected from titanium nitride, tantalum nitride, and tungsten carbide.

[0051] In some optional embodiments, the contact portion 2 may further include a filler layer 223, with a second conductive layer 221 and a second metal compound layer 222 respectively disposed around the filler layer 223. The material of the filler layer 223 may include an insulating material, including at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0052] In some alternative embodiments, the first conductive layer 121 and the second conductive layer 221 are made of the same material, and the first metal compound layer 122 and the second metal compound layer 222 are made of the same material.

[0053] Please continue to refer to this. Figure 1As shown in Figure 2, the semiconductor device 100 provided in this disclosure further includes a gate gap structure, which includes a first gate gap structure 4 and a second gate gap structure 5. The first gate gap structure 4 and the second gate gap structure 5 penetrate the stacked structure 1 along the stacking direction Z and extend along the first direction X. Multiple first gate gap structures 4 are arranged along the second direction Y, which is perpendicular to both the first direction X and the stacking direction Z. It is understood that "perpendicular" in this disclosure refers to perpendicularity within a certain angular error range, such as 85°-95°. The first gate gap structure 4 is located in the core region C and the connection region S. Multiple first gate gap structures 4 arranged along the second direction Y divide the stacked structure into different memory blocks. The second gate gap structure 5 is located at least in the core region and includes multiple second sub-gate gap structures 51 spaced apart along the first direction X. The second gate gap structure 5 divides a memory block into different finger-shaped memory regions. For example, in the second direction Y, for example, a second gate gap structure 5 is located between adjacent first gate gap structures 4, and the finger-shaped memory region can be defined by the first gate gap structure 4 and the second gate gap structure 5. In other examples, more than one second gate gap structure 5 may be located between adjacent first gate gap structures 5, so that finger-shaped memory regions can also be defined by two adjacent second gate gap structures 5. In some optional embodiments, the second gate gap structures 5 may be located only in the core region C; in other optional embodiments, the second gate gap structures 5 may be located in both the core region C and the connection region S. The specific design can be determined according to the actual situation.

[0054] In some alternative embodiments, the gate gap structure may include an insulating layer 41 to prevent short circuits between gate layers 12 and to prevent oxidation of the gate layers 12. The gate gap structure may also include an intermediate fill layer 42 to provide mechanical support. Here, the insulating layer 41 is located between the intermediate fill layer 42 and the stacked structure 1.

[0055] It should be noted that the material of the intermediate filling layer 42 can be a conductive material or an insulating material. When the source signal is led out through the gate gap structure, the material of the intermediate filling layer 42 can be a conductive material, for example, the material of the intermediate filling layer 42 includes polysilicon, but this disclosure is not limited thereto.

[0056] Please refer to Figure 2a and Figure 3In some optional embodiments, along the second direction Y, the minimum distance G2 from the nearest first gate gap structure 4 to the multiple contact portions 2 arranged along the first direction X is equal. It can be understood that the points on the multiple contact portions 4 arranged along the first direction X that are shortest distances to the nearest first gate gap structure 4 are on the same straight line. It should be explained that since the contact portion 2 includes a first connecting portion 31 and a second connecting portion 32, and the second connecting portion 32 is formed by expanding outward from the first connecting portion 31, the minimum distance between the contact portion 2 and the first gate gap structure 4 can be understood as the minimum distance between the second connecting portion 32 and the first gate gap structure 4. In some embodiments, since the geometric centers of the first connecting portion 31 and the second connecting portion 32 in each contact portion 2 overlap, and the distance between the edge of the orthographic projection of each first connecting portion 31 on the stacked structure along the first direction X and the edge of the orthographic projection of the second connecting portion 32 on the stacked structure is equal, it can be understood that the minimum distance from the first connecting portion 31 of the multiple contact portions 2 arranged along the first direction X to the nearest first gate gap structure 4 is also equal. This design helps to control the range of the gate sacrificial layer 12' removed through the first gate gap structure 4, ensuring that the contact portion 2 can be connected to the gate layer 12 in subsequent processes.

[0057] Please continue to refer to this. Figure 3 In some optional embodiments, the first contact portion 21 and the second contact portion 22 are arranged along the first direction X, and there is a gap G1 between the geometric centers of the projections of the first contact portion 21 and the second contact portion 22 in the first direction X. This design allows for flexible arrangement of the first contact portion 21 and the second contact portion 22, without being limited by the requirement that the geometric centers of the contact portions 21 and 22 be on the same straight line. This allows for a more compact arrangement of the contact portions, saving space in the connection area S and reducing the size of the semiconductor device.

[0058] Please refer to Figure 4 In some optional embodiments, the semiconductor device 100 includes a plurality of contact units 20 arranged along a second direction Y, located in the connection region S. Each contact unit 20 includes a plurality of contact portions 2 arranged in a row along a first direction X. It should be explained that each contact unit includes a first contact portion 21 and a second contact portion 22. The geometric centers of the projections of adjacent contact portions 2 located in different contact units 20 in the second direction are spaced apart by a distance G3. This design allows for a sufficiently staggered arrangement of the first contact portions 21 and the second contact portions 22, enabling a more compact arrangement of more contact portions within a limited space. This, in turn, compresses the space of the connection region S along the first direction X, reduces the size of the semiconductor device along the first direction X, provides more space in the core region for setting up a channel structure with storage function, and further improves storage capacity.

[0059] Please continue to refer to this. Figure 4In some optional embodiments, a plurality of channel structures 6 are included between the contact unit 20 and the nearest first gate gap structure 4, and the plurality of channel structures 6 are arranged along a first direction X. The channel structure 6 may be a virtual channel structure 61, which can be understood as a channel structure 6 without storage function. In other embodiments, the channel structure 6 located between the contact unit 20 and the nearest first gate gap structure 4 may also be a storage channel structure 62 with storage function. In some embodiments, the virtual channel structure 61 may be formed synchronously with the storage channel structure 62, and its structure is the same as that of the storage channel structure 62.

[0060] This disclosure does not specifically limit the shape of the channel structure 6; it can be a structure that is wider at the top and narrower at the bottom, or it can be a structure with the same width at both the top and bottom. In some embodiments, the channel structure 6 can be a structure that is narrower at the top and wider at the bottom, providing more space for top wiring. Under this structure, a stacked structure of top-select transistors can be formed separately.

[0061] It is understandable that the contact unit 20 and the nearest first gate gap structure 4 consist of only one row of multiple channel structures 6 arranged along the first direction X. This design reduces the area through which the gate sacrificial layer is removed via the first gate gap structure 4, providing more space for setting more contacts 2, while also allowing for better support of the connection region S.

[0062] This disclosure provides a semiconductor device 100 that, by designing contact portions 2 of different sizes in the connection region S, can arrange more contact portions more compactly in a limited space, thereby compressing the space of the connection region S, reducing the size of the semiconductor device, providing more space for the core region to set up a channel structure with storage function, and further improving the storage capacity.

[0063] This disclosure also provides a method for fabricating the semiconductor device 100 described above, such as... Figure 5 As shown, the preparation method includes steps S100-S400.

[0064] S100: Please refer to Figure 6 This forms the initial layered structure.

[0065] In the above steps, the initial stacked structure 1' includes multiple overlapping gate insulating layers 11 and gate sacrificial layers 12. The materials of the gate insulating layer 11 and the gate sacrificial layer have been described previously and will not be repeated here. It should be noted that the initial stacked structure 1' can be formed on the substrate using any of the following thin-film deposition processes: CVD, PVD, or ALD.

[0066] S200: Please refer to Figures 7 to 8The method for forming contact hole 2' includes steps S210-S240.

[0067] S210: Please refer to Figure 7 The initial stacked structure 1' is etched to the gate insulating layer 11 located adjacent to and above the target gate sacrificial layer 13', forming a plurality of initial contact holes 31'.

[0068] In the above steps, the initial stacked structure 1' can be etched using a dry / wet etching process to form the initial contact hole 31'. Exemplarily, an anisotropic etching process (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation) is used to form the initial contact hole 31'. The target gate sacrificial layer 13' can be understood as the gate sacrificial layer 12' that will subsequently be replaced by the gate layer and electrically connected to the contact portion formed in the contact hole.

[0069] S220: Please refer to Figure 7 and Figure 8 An isolation layer 7 is formed on the sidewall of the initial contact hole 31'.

[0070] In the above steps, the isolation layer 7 covers the sidewalls and bottom of the initial contact hole 31'. The material of the isolation layer 7 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., alumina, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0071] S230: Please refer to Figure 7 and Figure 8 Remove the isolation layer 7 covering the bottom of the initial contact hole 31' and expose the target gate sacrificial layer 13' located below and adjacent to the initial contact hole 31'.

[0072] In the above steps, the material of the isolation layer 7 can be the same as that of the gate insulating layer 11. In this way, the isolation layer 7 covering the bottom wall of the initial contact hole 31' and the gate insulating layer 11 below it can be removed by the same etchant and a single etching process.

[0073] S240: Please refer to Figure 7 and Figure 8 The exposed portion of the target gate sacrificial layer 13' is removed, and the portion surrounding the exposed portion is used to form a contact hole 2'.

[0074] In the above steps, the exposed target gate sacrificial layer 13' can be etched by a dry / wet etching process, so that the target gate sacrificial layer 13' is recessed relative to the gate insulating layer 11 to form a contact hole 2'.

[0075] The plurality of contact holes 2' includes a first contact hole and a second contact hole, wherein the projected area of ​​the first contact hole in the stacking direction Z is greater than the projected area of ​​the second contact hole in the stacking direction. Figure 7 and Figure 8 The diagram only illustrates the fabrication process of one contact hole, without showing the first and second contact holes. It can be understood that the formation of all contact portions requires the formation of corresponding contact holes; the first contact portion corresponds to the first contact hole, and the second contact portion corresponds to the second contact hole. Specifically, along the stacking direction Z, the size of the first contact hole is larger than the size of the second contact hole. Alternatively, the number of gate insulating layer and gate sacrificial layer layers in the stacked structure penetrated by the first contact hole is greater than the number of gate insulating layer and gate sacrificial layer layers in the stacked structure penetrated by the second contact hole. It can also be understood that the size of the first contact portion is larger than the size of the second contact portion.

[0076] In some optional embodiments, the first contact hole and the second contact hole are arranged along the first direction X, and there is a gap between the geometric centers of the projections of the first contact hole and the second contact hole in the first direction X. It is understood that the first contact portion and the second contact portion are arranged along the first direction X, and there is a gap between the geometric centers of the projections of the first contact portion and the second contact portion in the first direction X.

[0077] In some alternative embodiments, a channel structure 6 is formed before forming the contact hole 2'. The channel structure 6 has been described above and will not be repeated here.

[0078] S300: Please refer to Figure 9 to... Figure 13 This forms the gate layer.

[0079] Please refer to Figure 9 Before forming the gate layer, a first sacrificial portion 8 is filled into the contact hole 2'. The material of the first sacrificial portion 8 is different from that of the isolation layer 7, for example, it may include carbon, which is convenient to remove in subsequent processes. Then, a first gate gap isolation trench 4' is formed, which includes a first portion 4'-1 located in the core region C and a second portion 4'-2 located in the connection region S.

[0080] Please refer to Figure 10 A second sacrificial portion 9 is formed within the first portion 4'-1. The second sacrificial portion 9 can be formed within the first portion 4'-1 of the first gate gap isolation trench 4' using any of the following thin-film deposition processes: CVD, PVD, or ALD. The material of the second sacrificial portion 9 is different from the material of the gate insulating layer 11, so that the second sacrificial portion 9 and the gate insulating layer 11 have different etching rates for the same etchant. Here, the material of the second sacrificial portion 9 can be polysilicon, but this disclosure is not limited thereto.

[0081] Please continue to refer to this. Figure 10A portion of the gate sacrificial layer 12' located in the connection region S is removed via the second part 4'-2 in the first gate gap isolation trench 4' to form the first groove C1.

[0082] In the above steps, the second part 4'-2 of the first gate gap isolation trench 4' is used as an etchant channel, and isotropic etching is used to remove part of the gate sacrificial layer 12' located in the connection region S, thereby forming the first groove C1.

[0083] Please refer to Figure 11 The gate sacrificial layer 12' located in the core region C is removed via the first portion 4'-1 in the first gate gap isolation trench 4' to form the second groove C2.

[0084] The above steps also include filling the first groove C1 with the third sacrificial portion 10 and removing the second sacrificial portion 9 from the first portion 4'-1 of the first gate gap isolation trench 4'. The first portion 4'-1 of the first gate gap isolation trench 4' serves as an etchant channel, and isotropic etching is used to remove the gate sacrificial layer 12' located in the core region C, thereby forming the second groove C2. In some embodiments, the material of the third sacrificial portion 10 may be the same as the material of the first sacrificial portion 8.

[0085] Please refer to Figure 12 and Figure 13 A gate layer is formed in the first groove C1 and the second groove C2.

[0086] The above steps also include removing the third sacrificial portion 10 in the first groove C1. Then, using the first gate gap isolation trench 4' as a deposition channel, a gate layer 12 is formed in the first groove C1 and the second groove C2 using any of the following thin-film deposition processes: CVD, PVD, and ALD. At this time, a stacked structure 1 is formed, which includes alternately stacked gate insulating layers 11 and gate layers 12. In some embodiments, the gate layer 121 includes a first dielectric layer 123, a first conductive layer 121, and a first metal compound layer 122. The first dielectric layer 123, the first conductive layer 121, and the first metal compound layer 122 have been described above and will not be repeated here.

[0087] Please continue to refer to this. Figure 13 In some optional embodiments, after the gate layer is formed, a first gate gap structure 4 is formed in the first gate gap isolation trench 4'. The first gate gap structure 4 includes an insulating layer 41 and an intermediate filling layer 42.

[0088] S400: Please refer to Figure 14 , forming contact part 2.

[0089] The above steps also include removing the first sacrificial portion 8 from the contact hole, and then using any one of CVD, PVD, or ALD thin film deposition processes to form a contact portion 2 within the contact hole. The contact portion 2 includes a first connecting portion 31 and a second connecting portion 32, with the second connecting portion 32 contacting and electrically connected to the gate layer 12. In some embodiments, the contact portion 2 includes a fill layer 223 and a second conductive layer 221 and a second metal compound layer 222 sequentially disposed around the fill layer 223. The fill layer 223, the second conductive layer 221, and the second metal compound layer 222 have been described above and will not be repeated here. In some alternative embodiments, the contact portion 12 only includes the second conductive layer 221 and the second metal compound layer 222. It is understood that the second conductive layer 221 can replace the fill layer 223 to fill the contact hole and further form the contact portion 2.

[0090] It should be explained that when the gate layer 12 includes the first dielectric layer 123, before forming the contact portion, the first dielectric layer 123 of the gate layer 12 exposed in the contact hole and on the same layer as the second connection portion 32 needs to be removed, so that the contact portion 2 is electrically connected to the gate layer 12.

[0091] The above-described process method provides only one method for fabricating a semiconductor device under the SCT architecture, but the semiconductor device provided in this disclosure is not limited to the above-described process method. For example, in some optional embodiments, the gate layer 12 can be formed in two steps, forming the gate layer 12 in the first groove C1 located in the connection region S and the second groove C2 located in the core region C, respectively. In some optional embodiments, the contact portion 2 can be formed first, followed by the formation of the gate layer 12. In some optional embodiments, the contact portion 2 and the gate layer 12 can be formed simultaneously.

[0092] It should be noted that, as Figure 15 As shown, the semiconductor device 100 can be a memory cell array 20, or a memory after the memory cell array 20 is bound to the peripheral circuit 30. The embodiments disclosed herein are not specifically limited.

[0093] Please refer to Figure 16 and Figure 17 Some embodiments of this disclosure also provide a storage system 200, including the semiconductor structure 100 and controller 110 described in the above embodiments. The controller 110 is coupled to the semiconductor device to control the semiconductor device to store data.

[0094] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0095] In some embodiments, see Figure 16a The storage system 200 includes a controller 110 and a semiconductor structure 100. The storage system 1000 can be integrated into a three-dimensional memory card.

[0096] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0097] In other embodiments, see Figure 16b The storage system 100 includes a controller 110 and multiple semiconductor structures 100, and the storage system 200 is integrated into a solid state drive (SSD).

[0098] In some embodiments of the storage system 200, the controller 110 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0099] In other embodiments, controller 110 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0100] In some embodiments, controller 110 may be configured to manage data stored in semiconductor structure 100 and to communicate with external devices (e.g., a host). In some embodiments, controller 110 may also be configured to control operations of semiconductor structure 100, such as read, erase, and program operations. In some embodiments, controller 110 may also be configured to manage various functions relating to data stored or to be stored in semiconductor structure 200, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, controller 110 is also configured to process error correction codes relating to data read from or written to semiconductor structure 100.

[0101] Of course, controller 110 can also perform any other suitable function, such as formatting semiconductor structure 100; for example, controller 110 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0102] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0103] Please refer to Figure 17 Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0104] Electronic device 300 may include the storage system 200 and host 210 described above. The host includes at least one of a central processing unit (CPU) and a cache.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The first stacked structure includes a plurality of gate insulating layers and gate layers alternately arranged along the stacking direction; The second stacked structure includes a plurality of first material layers and second material layers alternately arranged along the stacking direction, wherein the first material layer is disposed in the same layer as the gate insulating layer, and the second material layer is disposed in the same layer as the gate layer; Multiple contacts, each of which is connected to a different gate layer; as well as The first contact unit and the second contact unit are arranged adjacently along the second direction. Each of the first contact unit and the second contact unit includes a plurality of contact portions arranged in a row along the first direction. The first direction, the second direction, and the stacking direction are perpendicular to each other. Each of the contact portions includes a first connection portion and a second connection portion that are in contact with each other. The first connection portion extends in the second stacked structure along the stacking direction, and the second connection portion extends in a direction perpendicular to the stacking direction and connects to one of the gate layers. In a plane perpendicular to the stacking direction, the geometric centers of two adjacent contact portions are spaced apart in the first direction, wherein one of the two adjacent contact portions is located in the first contact unit, and the other of the two adjacent contact portions is located in the second contact unit.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A plurality of first gate gap structures, wherein the first gate gap structures penetrate the first stacked structure and the second stacked structure along the stacking direction and extend along the first direction; wherein, Multiple first gate gap structures are arranged along the second direction, and the first contact unit and the second contact unit are located between two adjacent first gate gap structures.

3. The semiconductor device according to claim 2, characterized in that, Also includes: The second gate gap structure extends through the first stacked structure along the stacking direction and includes a plurality of second sub-gate gap structures spaced apart along the first direction; wherein, The second gate gap structure is located between two adjacent first gap structures in the second direction.

4. The semiconductor device according to claim 2, characterized in that, Also includes: Multiple dummy channel structures extending through the first stacked structure along the stacking direction; wherein... Multiple dummy channel structures are located between the first contact unit and the first gate gap structure closest to the first contact unit, and are arranged along the first direction.

5. The semiconductor device according to claim 2, characterized in that, The first gate gap structure includes an insulating layer and an intermediate filling layer, wherein the insulating layer is located between the first stacked structure and the intermediate filling layer.

6. The semiconductor device according to claim 5, characterized in that, The intermediate filler layer comprises polycrystalline silicon.

7. The semiconductor device according to claim 1, characterized in that, Also includes: A plurality of first gate gap structures, wherein the first gate gap structures penetrate the first stacked structure and the second stacked structure along the stacking direction and extend along the first direction; wherein, Along the second direction, the minimum distance between the plurality of contact portions arranged along the first direction and the nearest first gate gap structure is equal.

8. The semiconductor device according to claim 1, characterized in that, The plurality of contact portions include a first contact portion and a second contact portion. In a plane perpendicular to the stacking direction, the size of the first contact portion is larger than the size of the second contact portion, and Along the stacking direction, the size of the first contact portion is larger than the size of the second contact portion.

9. The semiconductor device according to claim 8, characterized in that, The plurality of contact portions further include a third contact portion, In a plane perpendicular to the stacking direction, the size of the third contact portion is larger than the size of the first contact portion, and The first contact portion, the second contact portion, and the third contact portion are arranged adjacent to each other in the first direction and are located in the first contact unit.

10. The semiconductor device according to claim 9, characterized in that, The first contact portion, the second contact portion, and the third contact portion are arranged adjacent to each other in the first direction, and The shortest distance between the first contact portion and the second contact portion is different from the shortest distance between the second contact portion and the third contact portion.

11. The semiconductor device according to claim 8, characterized in that, The plurality of contact portions further include a third contact portion, In a plane perpendicular to the stacking direction, the size of the third contact portion is larger than the size of the first contact portion. The first contact portion, the second contact portion, and the third contact portion are arranged adjacent to each other, and A portion of the first contact portion, the second contact portion, and the third contact portion is located in the first contact unit, and another portion is located in the second contact unit.

12. The semiconductor device according to claim 8, characterized in that, The first stacked structure includes a first sub-stacked structure and a second sub-stacked structure disposed along the stacking direction. Both the first sub-stacked structure and the second sub-stacked structure include a plurality of gate insulating layers and gate layers alternately disposed along the stacking direction. The first contact portion extends through the second sub-stacked structure along the stacking direction and is connected to one of the gate layers in the first sub-stacked structure. The second contact portion is connected to one of the gate layers in the second sub-stack structure.

13. The semiconductor device according to claim 12, characterized in that, Also includes The first contact portion set includes a plurality of first contact portions; and The second contact portion assembly includes multiple second contact portions.

14. The semiconductor device according to claim 13, characterized in that, Multiple first contact portions are spaced apart, and multiple second contact portions are spaced apart.

15. The semiconductor device according to claim 8, characterized in that, The first contact portion and the second contact portion are arranged along the first direction and are located in the first contact unit.

16. The semiconductor device according to claim 15, characterized in that, In a plane perpendicular to the stacking direction, the geometric center of the first contact portion and the geometric center of the second contact portion are spaced apart in the second direction.

17. The semiconductor device according to claim 1 or 15, characterized in that, Also includes: A plurality of first gate gap structures, wherein the first gate gap structures penetrate the first stacked structure and the second stacked structure along the stacking direction and extend along the first direction; wherein, In a plane perpendicular to the stacking direction, the points on the contacts arranged along the first direction that are closest to the nearest first gate gap structure lie on the same straight line.

18. The semiconductor device according to claim 1, characterized in that, The projection shape of the contact portion in the stacking direction can be at least one of a circle or a square.

19. The semiconductor device according to claim 1, characterized in that, The first material layer is made of the same material as the gate insulating layer, and The second material layer is made of a different material than the gate layer.

20. The semiconductor device according to claim 1 or 19, characterized in that, Also includes: An isolation layer is located between the second laminated structure and the contact portion; wherein, The isolation layer includes insulating material.

21. The semiconductor device according to claim 20, characterized in that, The insulating material includes at least one of silicon oxide, silicon nitride, doped silicon oxide, and dielectric metal oxide.

22. The semiconductor device according to claim 1 or 19, characterized in that, The contact portion includes a conductive layer and a filler layer, with the conductive layer located between the second stacked structure and the filler layer.

23. The semiconductor device according to claim 22, characterized in that, The filling layer includes at least one of silicon oxide, silicon nitride, doped silicon oxide, and dielectric metal oxide.

24. The semiconductor device according to claim 1, characterized in that, The first connecting portion includes a first end and a second end disposed along the stacking direction, wherein the dimension of the first end along the first direction is greater than the dimension of the second end along the first direction, or... The dimension of the first end along the second direction is greater than the dimension of the second end along the second direction.

25. The semiconductor device according to claim 1, characterized in that, Also includes: A transistor stacked structure is selected at the top and stacked with the first stacked structure along the stacking direction; as well as A channel structure extends along the stacking direction through the top selected transistor stack structure and the first stack structure; wherein... Along a direction perpendicular to the stacking direction, the size of the portion of the channel structure located in the top selected transistor stack structure is smaller than the size of the portion of the channel structure located in the first stack structure.

Images