Electronic device and method of manufacturing an electronic device

Abstract

Electronic devices and methods of manufacturing electronic devices. The invention relates to a packaged electronic device structure including a first electronic device having a first substrate, a first electronic component coupled to the first substrate, a first encapsulant covering the first electronic component, and a first external interconnect coupled to the first substrate. The first external interconnect is coupled to a second substrate, a second electronic component is coupled to the second substrate, and a second encapsulant is interposed between the first substrate and the second substrate and covers the first external interconnect and the second electronic component. A second electronic device includes a third substrate. A third electronic component is coupled to the third substrate. A vertical interconnect couples the second substrate to the third substrate, and a third encapsulant is interposed between the second substrate and the third substrate and covers the vertical interconnect and the third electronic component. A second external interconnect is coupled to the third substrate.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to electronic devices and methods for manufacturing electronic devices. Background Technology

[0002] Existing electronic device packaging and methods for forming electronic device packages are inadequate, resulting in, for example, excessively high costs, reduced reliability, relatively low performance, or excessively large package sizes. By comparing such methods with this disclosure and referring to the accompanying drawings, those skilled in the art will understand the additional limitations and disadvantages of conventional and traditional methods. Summary of the Invention

[0003] This specification includes structures and associated methods, as well as other features, related to electronic devices that are more resilient to stresses encountered during the manufacture or use of the electronic device. More specifically, structures and methods for reducing stress-related defects, such as solder ball cracking, to improve the reliability of electronic devices are described. In some instances, the structures and methods can be used in stacked package (PoP) structures, in which multiple structures are stacked and bonded to each other. One type of PoP technology is called Intermediate PoP (IPPoP) technology, in which, in some instances, a top intermediary layer is attached to a bottom substrate using thermocompression bonding with metal core balls (such as copper core balls (CCB)). The CCB connection between the bottom substrate and the intermediary layer allows high-speed, high-density interconnects to be connected to the electronic device mounted on top of the intermediary layer.

[0004] In previous IPPoP technologies, gaps or open spaces existed between the electronics and the top side of the interposer, as well as between the interconnects connecting the electronics to the top side of the interposer. In some applications, interconnects were found to be prone to stress cracking, especially with high-density interconnects. Therefore, structures and methods for placing molded encapsulants within these gaps to protect the interconnects are described. In some instances, a transfer molding process is used to place the molded encapsulant between the electronics and the top side of the interposer before attaching the interposer substrate to the bottom substrate. Molded encapsulants offer advantages over other materials, such as capillary underfill materials, including eliminating the need to consider knock-back zones (KOZs), which can unfavorably increase package size. Furthermore, this method avoids the use of tape-assisted processing or other costly molding techniques, reducing process complexity and cost.

[0005] In one example, a packaged electronic device structure includes a first electronic device. The first electronic device includes a first substrate, the first substrate including a first side and a second side opposite to the first side, and a first substrate conductive structure. The first electronic device includes: a first electronic component coupled to the first substrate conductive structure at the first side of the first substrate; a first encapsulation covering the first electronic component; and a first external interconnect coupled to the first substrate conductive structure at the second side of the first substrate. The packaged electronic device structure includes a second substrate, the second substrate including a first side and a second side opposite to the first side, a second substrate conductive structure, and a second substrate dielectric structure. The first external interconnect is coupled to the second substrate conductive structure at the first side of the second substrate. The packaged electronic device structure includes a second electronic component and a second encapsulation, the second electronic component being coupled to the first side of the second substrate, the second encapsulation being interposed between the first substrate and the second substrate, and covering the first external interconnect, the first side of the second substrate, the second side of the first substrate, and the second electronic component. The packaged electronic device structure includes a second electronic device, the second electronic device including a third substrate. The third substrate includes a first side of the third substrate and a second side of the third substrate opposite to the first side of the third substrate, and a third substrate conductive structure. The second electronic device includes a third electronic component coupled to the third substrate conductive structure at the first side of the third substrate. The packaged electronic device structure includes: a vertical interconnect coupled to the second substrate conductive structure at the second side of the second substrate and coupled to the third substrate conductive structure at the first side of the third substrate; a third encapsulation inserted between the second substrate and the third substrate, and covering the vertical interconnect and the third electronic component; and a second external interconnect coupled to the third substrate conductive structure at the second side of the third substrate.

[0006] In one example, a method of manufacturing a packaged electronic device structure includes providing a first electronic device, the first electronic device comprising: a first substrate including a first substrate first side and a first substrate second side opposite to the first substrate first side, and a first substrate conductive structure; a first electronic component coupled to the first substrate conductive structure at the first substrate first side; a first encapsulation covering the first electronic component; and a first external interconnect coupled to the first substrate conductive structure at the second substrate second side. The method includes providing a second substrate including a second substrate first side and a second substrate second side opposite to the second substrate first side, a second substrate conductive structure, and a second substrate dielectric structure. The method includes coupling the first external interconnect to the second substrate conductive structure at the first substrate first side. The method includes providing a second encapsulation interposed between the first substrate and the second substrate, and covering the first external interconnect, the second substrate first side, and the first substrate second side. The method includes providing a first vertical interconnect coupled to the second substrate conductive structure at the second substrate second side. The method includes providing a second electronic device comprising: a third substrate including a first side of the third substrate and a second side of the third substrate opposite to the first side of the third substrate, and a third substrate conductive structure; and a second electronic component coupled to the third substrate conductive structure at the first side of the third substrate. The method includes, after providing a second encapsulation, (a) coupling a first vertical interconnect to the third substrate conductive structure at the first side of the third substrate, and (b) providing a third encapsulation interposed between the second substrate and the third substrate, and covering the first vertical interconnect and the second electronic component.

[0007] In one example, a method of manufacturing a packaged electronic device structure includes providing a first electronic device, the first electronic device comprising: a first substrate including a first substrate first side and a first substrate second side opposite to the first substrate first side, and a first substrate conductive structure; a first electronic component coupled to the first substrate conductive structure at the first substrate first side; a first encapsulation covering the first electronic component; and a first external interconnect coupled to the first substrate conductive structure at the second substrate second side. The method includes providing a second substrate including a second substrate first side and a second substrate second side opposite to the second substrate first side, a second substrate conductive structure, and a second substrate dielectric structure. The method includes coupling the first external interconnect to the second substrate conductive structure at the first substrate first side. The method includes providing a second encapsulation interposed between the first substrate and the second substrate, and covering the first external interconnect, the second substrate first side, and the first substrate second side. The method includes coupling a first vertical interconnect to the second substrate conductive structure at the second substrate second side. The method includes, after providing the second encapsulation, (a) providing a second electronic device including a third substrate including a first side of the third substrate and a second side of the third substrate opposite to the first side of the third substrate and a third substrate conductive structure; and a second electronic component coupled to the third substrate conductive structure at the first side of the third substrate; (b) coupling the first vertical interconnect to the third substrate conductive structure at the first side of the third substrate; and (c) providing a third encapsulation inserted between the second substrate and the third substrate, and covering the first vertical interconnect and the second electronic component. Attached Figure Description

[0008] Figure 1 A cross-sectional view of an example electronic device is shown.

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G A cross-sectional view is shown of an example method for manufacturing an example electronic device; Figure 2BA It shows Figure 2B A plan view of an example electronic device; and Figure 2EA It shows Figure 2E A plan view of an example electronic device.

[0010] Figure 3 A cross-sectional view of an example electronic device is shown.

[0011] The following discussion provides various examples of electronic devices and methods of manufacturing electronic devices. These examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0012] The accompanying drawings illustrate the general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0013] The term "or" refers to any one or more items in a list connected by "or". For example, "x or y" refers to any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y, or z" refers to any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0014] The terms “comprises”, “comprising”, “includes”, and “including” are “open-ended” terms and specify the presence of the stated feature, but do not preclude the presence or addition of one or more other features.

[0015] The terms “first,” “second,” etc., can be used to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element discussed in this disclosure can be referred to as the second element.

[0016] Unless otherwise specified, the term "coupled" can be used to describe two elements in direct contact with each other or to describe two elements indirectly coupled through one or more other elements. For example, if element A is coupled to element B, then element A can be in direct contact with element B or indirectly coupled to element B through an intermediate element C. Similarly, the terms "above" or "on" can be used to describe two elements in direct contact with each other or to describe two elements indirectly coupled through one or more other elements. As used herein, the term "coupled" can refer to mechanical coupling or electrical coupling. Detailed Implementation

[0017] Other examples are included in this disclosure. Such examples may be found in the accompanying drawings, claims, or description of this disclosure.

[0018] Figure 1 A cross-sectional view of an example packaged electronic device structure 10 is shown. Figure 1 In the examples shown, the packaged electronic device structure 10 may include electronic components 110, 210a, 210b, a main substrate 120, an underfill material 130, encapsulants 140, 240, 340, a main external interconnect 150, a substrate 220, die attachment materials 230a and 230b, an external interconnect 250, an interposer substrate 320, and a vertical interconnect 350. In some examples, the packaged electronic device structure 10 may include electronic components 160 and 360.

[0019] In some instances, electronic component 110 includes a first side 111 and a second side 112 opposite to the first side 111; electronic component 210a includes a first side 211a and a second side 212a opposite to the first side 211a; and electronic component 210b includes a first side 211b and a second side 212b opposite to the first side 211b. Electronic components 110, 210a, and 210b may each include contact pads 113, 213a, 213b and interconnects 114, 214a, and 214b respectively located on the first sides 111, 211a, and 211b.

[0020] The main substrate 120 may include a first side 121 and a second side 122 opposite to the first side 121. In some embodiments, the main substrate 120 may include a dielectric structure 123 and a conductive structure 124. The conductive structure 124 may include a main substrate inward terminal 124a positioned on the first side 121 of the main substrate 120 and a main substrate outward terminal 124b positioned on the second side 122 of the main substrate 120. The main substrate 120 may include, or may also be referred to as, a first substrate.

[0021] The substrate 220 may include a first side 221 and a second side 222 opposite to the first side 221. In some embodiments, the substrate 220 may include a dielectric structure 223 and a conductive structure 224. The conductive structure 224 may include a substrate inward terminal 224a positioned on the first side 221 of the substrate 220 and a substrate outward terminal 224b positioned on the second side 222 of the substrate 220.

[0022] The interposer substrate 320 may include a first side 321 and a second side 322 opposite to the first side 321. In some embodiments, the interposer substrate 320 may include a dielectric structure 323 and a conductive structure 324. The conductive structure 324 may include an inwardly positioned interposer substrate terminal 324a on the first side 321 of the interposer substrate 320 and an outwardly positioned interposer substrate terminal 324b on the second side 322 of the interposer substrate 320.

[0023] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G A cross-sectional view is shown of an example method for manufacturing an electronic device, such as an encapsulated electronic device structure 10.

[0024] Figure 2A A cross-sectional view of a packaged electronic device structure 10 in an early stage of manufacturing is shown. Figure 2A In the examples shown, an interposer substrate 320 may be provided. In some examples, the interposer substrate 320 may comprise a substantially planar flat plate structure. The interposer substrate 320 may include a core or may be coreless. In some examples, the interposer substrate 320 may comprise or be referred to as a rigid printed circuit board, a flexible printed circuit board, a rigid laminated substrate, a flexible laminated substrate, an RDL (redistribution layer) substrate, a coreless substrate, a ceramic substrate, a glass substrate, or a silicon substrate. In some examples, the thickness of the interposer substrate 320 may vary, with a maximum range of approximately 3.5 mm and a core thickness falling within the range of approximately 0.05 mm to approximately 1.4 mm. In some examples, the thickness of the interposer substrate 320 may range from approximately 90 micrometers to approximately 3500 micrometers. The interposer substrate 320 is configured to couple electronic components to each other and can protect electronic components from external stresses. In some examples, the interposer substrate 320 may be a strip substrate.

[0025] The interposer substrate 320 may include a first side 321 and a second side 322 opposite to the first side 321. In some embodiments, the first side 321 may include or be referred to as a first surface. In some embodiments, the first side 321 may be configured for attaching or mounting electronic components 360 and external interconnects 250. In some embodiments, the second side 322 of the interposer substrate may include or be referred to as a second surface. In some embodiments, the second side 322 of the interposer substrate may be configured for attaching or mounting vertical interconnects 350. In some embodiments, the second side 322 of the interposer substrate 320 may be configured for mounting to external components or boards.

[0026] Interposer substrate 320 may include dielectric structure 323 and conductive structure 324. In some instances, dielectric structure 323 may include, or may be referred to as, one or more stacked dielectric layers. For example, one or more dielectric layers may include one or more core layers, polymer layers, prepreg layers, or solder mask layers stacked on top of each other. In some instances, one or more layers or elements of conductive structure 324 may be interleaved with dielectric structure 323. In some instances, dielectric structure 323 may include FR4 (copper foil / glass fiber fabric / copper foil laminate), bismaleimide triazine (BT), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), Ajinomoto build-up film (ABF), resin, molding compound, ceramic, glass, or silicon. The thickness of individual layers of dielectric structure 323 may range from approximately 1 micrometer to approximately 1400 micrometers. The combined thickness of all layers of dielectric structure 323 may define the thickness of interposer substrate 320. The dielectric structure 323 can maintain the external shape of the interposer substrate 320 and can also structurally support the conductive structure 324.

[0027] The conductive structure 324 may comprise, or be referred to as, one or more conductive layers, which define signal distribution elements, traces, vias, pads, patterns, conductive paths, or under-bump metal (UBM). In some instances, the conductive structure 324 may comprise copper, aluminum, gold, silver, nickel, palladium, or an alloy. The thickness of the conductive structure 324 may range from approximately 1 micrometer to approximately 50 micrometers. The thickness of the conductive structure 324 may refer to a single layer of the conductive structure 324. The conductive structure 324 may provide electrical signal paths (e.g., vertical or horizontal paths) between electronic components.

[0028] In some embodiments, the conductive structure 324 may include an inwardly facing terminal 324a disposed on a first side 321 of the interposer substrate 320 and an outwardly facing terminal 324b disposed on a second side 322 of the interposer substrate 320. In some embodiments, the inwardly facing terminal 324a and the outwardly facing terminal 324b may be disposed on the first side 321 and the second side 322 of the interposer substrate 320 in a matrix configuration having rows and / or columns, respectively. In some embodiments, the inwardly facing terminal 324a may include or be referred to as a pad, a land, under-bump metallization (UBM), or a spike. In some embodiments, the outwardly facing terminal 324b may include or be referred to as a two-step pad, a pad, or a land. In some embodiments, the thickness of the inwardly facing terminal 324a and the outwardly facing terminal 324b may be in the range of approximately 5 micrometers to 100 micrometers. In some instances, a conductive structure 324 may be provided in the dielectric structure 323 to couple the inner terminal 324a of the interposer substrate to the outer terminal 324b of the interposer substrate.

[0029] In some instances, the interposer substrate 320 may be a redistribution layer (“RDL”) substrate. The RDL substrate may comprise one or more conductive redistribution layers and one or more dielectric layers, and (a) may be formed layer-by-layer over an electronic device coupled to the RDL substrate, or (b) may be formed layer-by-layer over a carrier and may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be fabricated layer-by-layer on a circular wafer using a wafer-level process as a wafer-level substrate, and / or on a rectangular or square panel carrier using a panel-level process as a panel-level substrate. The RDL substrate may be formed using an additive stacking process and may include one or more dielectric layers stacked alternately with one or more conductive layers, defining corresponding conductive redistribution patterns or traces configured to collectively (a) fan out of the electronic device's footprint, and / or (b) fan in into the electronic device's footprint. The conductive patterns may be formed using plating processes such as electroplating or electroless plating. Conductive patterns can contain conductive materials, such as copper or other plated metals. The locations of the conductive patterns can be created using photolithography processes, such as photolithography, and photoresist materials used to form the photomask. The dielectric layer of the RDL substrate can be patterned using photolithography processes and can include a photomask through which light is exposed to desired features of the photopattern, such as vias in the dielectric layer. The dielectric layer can be made of photodeterminable organic dielectric materials, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). This dielectric material can be spin-coated or otherwise coated in liquid form rather than attached as a preform. To allow proper formation of the desired photodeterminable features, such photodeterminable dielectric materials can omit structural reinforcing agents or can be filler-free, free of strands, fabrics, or other particles that may interfere with light from the photopatterning process. In some instances, this filler-free characteristic of filler-free dielectric materials can result in a reduced thickness of the resulting dielectric layer. Although the photodeterminable dielectric material described above can be an organic material, in some instances, the dielectric material of the RDL substrate can comprise one or more inorganic dielectric layers. Examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), and / or silicon oxynitride (SiON). Inorganic dielectric layers can be formed by growing the inorganic dielectric layer using oxidation or nitridation processes instead of using photodeterminable organic dielectric materials. Such inorganic dielectric layers may be filler-free and free of wires, fabrics, or other dissimilar inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and these types of RDL substrates may comprise, or be referred to as, coreless substrates. Other substrates described in this specification may also comprise RDL substrates.

[0030] In some instances, the interposer substrate 320 may be a preformed substrate. The preformed substrate can be fabricated prior to attachment to an electronic device and may contain a dielectric layer situated between corresponding conductive layers. The conductive layer may contain copper and can be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photodefineable layer and may be attached in the form of a preformed film rather than a liquid, and may include a resin with fillers such as wires, fabrics, and / or other inorganic particles for rigid and / or structural support. Because the dielectric layer is non-photodefineable, features such as vias or openings can be formed using drilling or lasers. In some instances, the dielectric layer may contain a prepreg material or an ajinomoto deposited film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material containing bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate, omitting a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the formation of the dielectric and conductive layers and before attachment to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such a preformed substrate may be formed using a semi-additive process or a modified semi-additive process. Other substrates described in this specification may also include preformed substrates. Substrate 220 is an example of a first substrate.

[0031] Figure 2B A cross-sectional view of the packaged electronic device structure 10 in the late stage of manufacturing is shown. Figure 2BA It shows Figure 2B The diagram shows a plan view of the encapsulated electronic device structure 10 in its later stages.

[0032] exist Figure 2B and Figure 2BA In the examples shown, electronic device 200 may be disposed on a first side 321 of the interposer substrate 320. In some examples, electronic device 200 is disposed on the first side 321 in a matrix arrangement. In some examples, electronic device 200 may include electronic component 210a, electronic component 210b, substrate 220, die attachment material 230a, die attachment material 230b, encapsulation 240, and external interconnect 250.

[0033] Substrate 220 may include a first side 221 and a second side 222 opposite to the first side 221. In some examples, substrate 220 may include a dielectric structure 223 and a conductive structure 224. In some examples, conductive structure 224 may include a substrate-inward terminal 224a positioned on the first side 221 and a substrate-outward terminal 224b positioned on the second side 222. In some examples, substrate-inward terminal 224a may be configured for mounting electronic components 210a and 210b. In some examples, substrate-outward terminal 224b may be configured for mounting external interconnects 250. Substrate-outward terminal 224b may be configured for mounting external components or boards. Substrate 220 may include corresponding elements, features, materials, or manufacturing methods similar to those of the interposer substrate 320. The first side 221 is an example of a first side of a first substrate, and the second side 222 is an example of a second side of a first substrate opposite to the first side of the first substrate. The conductive structure 224 is an example of a conductive structure of the first substrate, and the dielectric structure 223 is an example of a dielectric structure of the first substrate.

[0034] In one example, electronic component 210a may be coupled to a first side 221 of substrate 220, and electronic component 210b may be coupled to electronic component 210a. In some examples, electronic component 210b is attached to or mounted to electronic component 210a.

[0035] Electronic component 210a may include a first side 211a and a second side 212a opposite to the first side 211a. In some instances, the first side 211a may include, or may be referred to as, the active side, wherein doped regions and other device structures are disposed on the active side, and the second side 212a of the electronic component may include, or may be referred to as the lower side. In some instances, the second side 212a may include, or may be referred to as the inactive side. Electronic component 210a may include a side 215a connecting the first side 211a and the second side 212a. In some instances, electronic component 210a may include, or may be referred to as a die, chip, or package.

[0036] In some instances, the second side 212a of the electronic component 210a can be coupled, attached, or secured to the first side 221 of the substrate 220 via, using, or employing die attachment material 230a. For example, after the die attachment material 230a is applied or attached to the first side 221 of the substrate 220, a pick-and-place device can pick up the electronic component 210a and place it on top of the die attachment material 230a, thus allowing the electronic component 210a and the substrate 220 to bond together. In some instances, the die attachment material 230a can be provided on the first side 221 of the substrate 220 by coating methods (such as spin coating, blade coating, casting, spraying, mist coating, trench die coating, curtain coating, slide coating, or edge knife coating), printing methods (such as screen printing, pad printing, gravure printing, flexographic printing, or offset printing or inkjet printing), and intermediate techniques between coating and printing, or by direct attachment via bonding film or bonding tape. In some instances, the die attachment material 230a may include or be referred to as an adhesive, adhesive layer, or adhesive film.

[0037] In some instances, electronic component 210a may include contact pads 213a located on a first side 211a. Contact pads 213a may be input / output terminals of electronic component 210a. In some instances, contact pads 213a may be disposed on the first side 211a in a row or column direction, spaced apart from each other. In some instances, contact pads 213a may be bonding pads exposed by a dielectric (such as a silicon oxide film (SiO2) or a silicon nitride film (SiN)) or redistribution layer pads exposed by a dielectric. In some instances, contact pads 213a may comprise conductive materials (such as metallic materials, aluminum, copper, aluminum alloys, copper alloys, combinations thereof) or other materials known to those skilled in the art.

[0038] In some instances, electronic device 200 may include interconnects 214a configured to couple contact pads 213a of electronic component 210a to substrate 220. In some instances, interconnects 214a may comprise or be referred to as wires, leads, tabs, or clips. In some instances, interconnects 214a may comprise gold-coated copper, copper, aluminum, or palladium. In some instances, interconnects 214a may be in the form of wires and may be bonded to contact pads 213a of electronic component 210a using wire bonding equipment, and then to substrate-in-place terminals 224a of substrate 220. Interconnects 214a electrically connect contact pads 213a of electronic component 210a to substrate-in-place terminals 224a of substrate 220. In some instances, the thickness of interconnects 214a may range from approximately 10 micrometers to approximately 100 micrometers.

[0039] In some instances, electronic component 210a may be mounted on a first side 221 of substrate 220 in a flip-chip configuration, with contact pad 213a facing the first side 221. In some instances, in electronic component 210a, contact pad 213a may be connected to substrate-in-place terminal 224a of substrate 220 via interconnects such as bumps, tin-lead (SnPb) bumps, lead-free bumps, CuP, stud bumps, pillars, or posts.

[0040] In some instances, the total thickness of electronic component 210a can range from approximately 50 micrometers to approximately 500 micrometers. In some instances, the area of ​​electronic component 210a can be smaller than the area of ​​substrate 220 and larger than the area of ​​electronic component 210b. Electronic component 210a can be an example of a first electronic component.

[0041] Electronic component 210b may include a first side 211b and a second side 212b opposite to the first side 211b. In some embodiments, the second side 212b of electronic component 210b may be coupled to the first side 211a of electronic component 210a. In some embodiments, the second side 212b may be coupled to and secured to the first side 211a via die attachment material 230b. Die attachment material 230b may include corresponding elements, features, materials, or manufacturing methods similar to those of die attachment material 230a.

[0042] Electronic component 210b may include a contact pad 213b disposed on a first side 211b. Electronic device 200 may include an interconnect 214b that electrically connects the contact pad 213b to a substrate-in-place terminal 224a of substrate 220 or the contact pad 213a of electronic component 210a. Electronic component 210b may include corresponding elements, features, materials, or manufacturing methods similar to those of electronic component 210a. Electronic component 210b may be an example of a second or third electronic component.

[0043] In some instances, encapsulation 240 may cover the first side 221 of substrate 220, electronic components 210a and 210b, die attachment materials 230a and 230b. Encapsulation 240 may comprise or be referred to as a host or molded part. For example, encapsulation 240 may comprise or be referred to as an epoxy molding compound, resin, filler-reinforced polymer, Class B compression film, or gel. Encapsulation 240 may be formed by compression molding, transfer molding, liquid phase host molding, vacuum lamination, paste printing, or film-assisted molding. In some instances, encapsulation 240 may contact the first side 221 of substrate 220, the first side 211a of electronic component 210a, the first side 211b of electronic component 210b, the sidewalls of die attachment materials 230a and 230b, interconnects 214a and 214b. In some instances, the thickness of encapsulation 240 can range from approximately 150 micrometers to approximately 1000 micrometers. Encapsulation 240 can protect electronic components 210a and 210b from the influence of the external environment. In some instances, the sidewalls of encapsulation 240 can be coplanar with the sidewalls of substrate 220. Encapsulation 240 is an example of a first encapsulation.

[0044] In some instances, the external interconnect 250 may be coupled to the substrate-outer terminal 224b. In some instances, the external interconnect 250 may comprise tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, the external interconnect 250 may be formed by using a ball drop method and then performing a remelting process to form a conductive material containing solder on the substrate-outer terminal (224b). The external interconnect 250 may comprise or be referred to as a conductive ball (such as a solder ball), a conductive pillar (such as a copper pillar), or a conductive post with a solder cap disposed on a copper pillar, bump, or pad. In some instances, the size of the external interconnect 250 may range from approximately 50 micrometers to approximately 1000 micrometers. In some instances, the external interconnect 250 may be referred to as an external input / output terminal of the electronic device 200. In some instances, the electronic device 200 may be a planar grid array (LGA), wherein the substrate-facing external terminal 224b serves as an external input / output terminal when the external interconnect 250 is not used. The external interconnect 250 is an example of a first external interconnect.

[0045] In electronic device 200, external interconnect 250 can be coupled to inward terminal 324a of the interposer substrate. In some instances, a pick-and-place device can be used to pick up electronic device 200 and place it on a first side 321 of interposer substrate 320, allowing external interconnect 250 to contact inward terminal 324a. Subsequently, external interconnect 250 of electronic device 200 can contact and bond to inward terminal 324a of interposer substrate via remelting or thermoforming bonding processes. Electronic components 210a and 210b can be coupled, including electrically coupled to conductive structure 324 of interposer substrate 320 via interconnect 214a, interconnect 214b, conductive structure 224 of substrate 220, and external interconnect 250. After testing electronic device 200 and determining that it passes electrical and physical test parameters, electronic device 200 can be placed on interposer substrate 320. In other words, the electronic device 200 can be placed as a known good unit or device, which improves the yield of finished products and manufacturing costs, among other things.

[0046] In some instances, the electronic device 200 may be mounted on the strip-shaped interposer substrate 320 in a matrix configuration having rows or columns. In some instances, the area of ​​the electronic device 200 may be smaller than the area of ​​the interposer substrate 320. In some instances, the total thickness of the electronic device 200 may range from approximately 500 micrometers to approximately 1500 micrometers, and the area of ​​the electronic device 200 may range from approximately 10 mm × 10 mm to approximately 30 mm × 30 mm. The electronic device 200 is an example of a first electronic device. In some instances, the electronic device 200 includes a storage device.

[0047] Before the electronic device 200 is disposed on the first side 321 of the interposer substrate 320, one or more electronic components 360 may be disposed on the first side 321 of the interposer substrate 320. In some instances, the electronic component 360 may be positioned between the electronic device 200 and the interposer substrate 320. The electronic component 360 may contact and be electrically connected to the inward terminal 324a of the interposer substrate. The electronic component 360 may be laterally spaced from the external interconnect 250 of the electronic device 200. In some instances, the electronic component 360 may comprise or be referred to as a passive or active component. The thickness of the electronic component 360 may be less than the height of the external interconnect 250. In some instances, one or more electronic components 360 may be coupled (including mounted) to a second side 222 of the substrate 220. The interposer substrate 320 is an example of a second substrate. The electronic component 360 is an example of a second, third, or fourth electronic component.

[0048] Figure 2C A cross-sectional view of the packaged electronic device structure 10 in the late stages of manufacturing is shown. Figure 2C In the illustrated example, encapsulation 340 may be disposed between substrate 220 and interposer substrate 320. Encapsulation 340 may fill the space between the second side 222 of substrate 220 and the first side 321 of interposer substrate 320. According to this specification, encapsulation 340 is provided before interposer substrate 320 is coupled to main substrate 120. Figure 2E In some instances, the encapsulation 340 is provided before the vertical interconnect 350 is coupled to the second side 322 of the interposer substrate 320. More specifically, the fabrication step of providing the encapsulation 340 occurs before the step of coupling the vertical interconnect 350 to the second side 322 of the interposer substrate 320. In other words, when the encapsulation 340 is provided, the second side 322 of the interposer substrate 320 does not have the vertical interconnect 350.

[0049] Encapsulation 340 may contact the second side 222 of substrate 220, the first side 321 of interposer substrate 320, external interconnects 250, and electronic components 360. Encapsulation 340 may comprise or be referred to as a body, encapsulation body, or molded part. In some instances, encapsulation 340 may comprise an epoxy molding compound, resin, filler-reinforced polymer, Class B compression film, or gel. Encapsulation 340 may be provided by compression molding or transfer molding. In this specification, encapsulation 340 is a material different from the underfill material (including underfill materials provided using capillary dispensing techniques). In this way, encapsulation 340 eliminates the need to consider KOZ requirements for underfill materials, which avoids the need to increase the spacing between external interconnects 250 and the size of substrate 220 or interposer substrate 320. Additionally, in some instances, encapsulation 340 is provided without the use of film-assisted molding or other costly molding techniques, which avoids increased manufacturing complexity and cost. For example, if the interposer substrate 320 is first attached to the main substrate 120 before the electronic device 200 is attached to the first side 321 of the interposer substrate 320, then expensive, specialized, and time-consuming molding techniques would be required to protect the first side 321 of the interposer substrate 320 to avoid problems such as flash contamination. In this specification, transfer molding techniques can be used because the electronic device 200 shields or protects the first side 321 of the interposer substrate 320, and other components, during transfer molding.

[0050] In some instances, the thickness of the encapsulation 340 can range from approximately 100 micrometers to 1000 micrometers. The encapsulation 340 can protect external interconnects 250 and electronic components 360, thereby improving reliability. In some instances, encapsulations 240 and 340 can contain the same material. In some instances, encapsulations 240 and 340 can contain different materials with different coefficients of thermal expansion. In some instances, materials and process techniques are selected to reduce stress and warpage in the encapsulated electronic device structure 10. Encapsulation 340 is an example of a second encapsulation.

[0051] After providing the encapsulation 340, the encapsulation 340 can be individually cleaved from the interposer substrate 320 using processes such as sawing or laser cutting, thereby separating the electronic device 10 into individual electronic devices. The sawing can be performed such that the sidewalls of the encapsulation 340 and the interposer substrate 320 are coplanar with the sidewalls of the electronic device 200. In this example, the encapsulation 340 can be cleaved before being attached to the main substrate 120. Figure 2C The subassembly with encapsulation 340 shown is subjected to electrical testing so that it can be confirmed as a known good unit before further processing. This improves yield and reduces manufacturing costs, among other things.

[0052] Figure 2D A cross-sectional view of the packaged electronic device structure 10 in the late stages of manufacturing is shown. Figure 2D In the example shown, the vertical interconnect 350 can be coupled to the second side 322 of the interposer substrate 320.

[0053] In some instances, the vertical interconnect 350 may contact and be electrically connected to the interposer substrate outward terminal 324b of the interposer substrate 320. In some instances, the vertical interconnect 350 may be arranged along one or more rows or columns along the edge of the second side 322 of the interposer substrate. For example, the central region of the second side 322 may have no or no vertical interconnect 350.

[0054] Vertical interconnect 350 can be electrically connected to electronic components 210a and 210b via interposer substrate 320, external interconnect 250, substrate 220, interconnect 214a, and interconnect 214b.

[0055] In some instances, the vertical interconnect 350 may comprise or be referred to as a solder ball, bump, pillar, stud, copper cube pillar (CCC), metal core ball, stacked ball, through-hole via (TMV), or conductor. In some instances, the vertical interconnect 350 may comprise tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some instances, the vertical interconnect 350 may be formed by ball drop, screen printing, or electroplating. In some instances, the vertical interconnect 350 may be provided by providing solder-coated metal core balls on the outer terminal 324b of the interposer substrate 320 via ball drop and then by a remelting process. The height of the vertical interconnect 350 can range from approximately 100 micrometers to approximately 500 micrometers.

[0056] Figure 2E A cross-sectional view of the packaged electronic device structure 10 in the late stage of manufacturing is shown. Figure 2EA It shows Figure 2E A plan view of the packaged electronic device structure 10 in the late stages of manufacturing is shown. Figure 2E and Figure 2EA In the illustrated example, a packaged electronic device subassembly 10A, including vertical interconnects 350, can be disposed on a first side 121 of the main substrate 120. Here, the packaged electronic device subassembly 10A can be disposed via... Figures 2A to 2D Electronic devices manufactured using the manufacturing process. In some instances, the packaged electronic device subassembly 10A may include electronic components 210a, 210b, 360, substrate 220, die attachment material 230a, die attachment material 230b, encapsulant 240, encapsulant 340, external interconnect 250, interposer substrate 320, and vertical interconnect 350.

[0057] The main substrate 120 may include a first side 121 and a second side 122 opposite to the first side 121. In some embodiments, the main substrate 120 may include a dielectric structure 123 and a conductive structure 124. The conductive structure 124 may include a main substrate inward terminal 124a positioned on the first side 121 and a main substrate outward terminal 124b positioned on the second side 122. The main substrate inward terminal 124a may be configured for mounting or attaching electronic components 110 and for mounting or attaching packaged electronic device subassemblies 10A. In some embodiments, the main substrate may be configured for mounting or attaching to a main external interconnect 150. In some embodiments, the main external interconnect 150 may be configured for coupling to an external component or board. The main substrate 120 may include corresponding elements, features, materials, or manufacturing methods similar to those of the interposer substrate 320. The total thickness of the main substrate 120 can range from approximately 100 micrometers to approximately 500 micrometers, and the area of ​​the electronic device 200 can range from approximately 50 mm × 500 mm to approximately 100 mm × 1000 mm. The main substrate 120 can have a strip shape. The main substrate 120 is an example of a third substrate.

[0058] In the packaged electronic device subassembly 10A, vertical interconnects 350 can contact and be electrically connected to the inward terminal 124a of the main substrate. For example, the packaged electronic device subassembly 10A can be picked up by a pick-and-place device and placed on a first side 121 of the main substrate 120, such that the vertical interconnect line 350 contacts the inward terminal 124a of the main substrate. Subsequently, the vertical interconnect 350 can contact and bond to the inward terminal 124a of the main substrate through a remelting or thermoforming bonding process. Electronic components 210a and 210b can be electrically connected to the main substrate 120 through interconnects 214a, interconnects 214b, substrate 220, external interconnects 250, interposer substrate 320, and vertical interconnect lines 350. After testing the packaged electronic device subassembly 10A and determining that it passes electrical and physical test parameters, the packaged electronic device subassembly 10A can be placed on the main substrate 120. That is, the packaged electronic device subassembly 10A can be placed as a known good unit or device, which improves yield, manufacturing cost, and other aspects. The electronic devices 10A can be mounted on the strip-shaped main substrate 120 in a matrix form with rows or columns. The area of ​​the packaged electronic device subassembly 10A can be smaller than the area of ​​the main substrate 120. The area of ​​the packaged electronic device subassembly 10A can be similar to the area of ​​the electronic device 200.

[0059] Before the packaged electronic device subassembly 10A is disposed on the main substrate 120, the electronic component 110 may be coupled to a first side 121 of the main substrate 120. In some instances, the electronic component 110 may contact and be electrically connected to a main substrate inward terminal 124a of the main substrate 120. In some instances, the electronic component 110 may be disposed in a central region on the first side 121 of the main substrate 120. The electronic component 110 and the vertical interconnect 350 are laterally separated from each other. The electronic component 110 may include a first side 111 and a second side 112 opposite to the first side 111. In some instances, the first side 111 may include or be referred to as the active side, and the second side 112 may include or be referred to as the lower side. In some instances, the second side 112 may include or be referred to as the inactive side. The electronic component 110 may include a side 115 connecting the first side 111 and the second side 112.

[0060] Electronic component 110 may include contact pads 113 located on a first side 111, the contact pads being spaced apart from each other in a row or column direction. In some instances, contact pads 113 may comprise bonding pads exposed by a dielectric (such as a silicon oxide film (SiO2) or a silicon nitride film (SiN)) or redistribution layer pads exposed by a dielectric. In some instances, contact pads 113 may comprise conductive materials, such as metallic materials, aluminum, copper, aluminum alloys, or copper alloys.

[0061] In some instances, interconnect 114 couples contact pad 113 to the host substrate 120. In some instances, interconnect 114 electrically connects contact pad 113 to substrate-in-place terminal 124a. In some instances, interconnect 114 may comprise or be referred to as a bump, SnPb bump, lead-free bump, CuP, stud bump, pillar, or post. In some instances, interconnect 114 may be disposed on contact pad 113 of the electronic component by electroplating or ball drop method. In some instances, interconnect 114 is provided as part of electronic component 110 as part of the wafer fabrication process.

[0062] In some instances, the pick-and-place device can pick up the electronic component 110 and place it on a first side 121 of the main substrate 120. In some instances, the interconnect 114 of the electronic component 110 can be positioned on top of the main substrate inward terminal 124a of the main substrate 120. Subsequently, the contact pad 113 can be contacted and bonded to the main substrate inward terminal 124a via the interconnect 114 through a remelting or thermoforming bonding process. In some instances, the electronic component 110 may comprise or be referred to as a die, chip, or package. The electronic component 110 is an example of a second, third, or fourth electronic component. The main substrate 120 and the electronic component 110 are an example of a second electronic device.

[0063] In some instances, underfill material 130 may be positioned between electronic component 110 and main substrate 120. Underfill material 130 may contact a first side 111 of electronic component 110 and a first side 121 of main substrate 120. Underfill material 130 may contact contact pads 113 and interconnects 114. Underfill material 130 may comprise, or be referred to as, a dielectric layer or nonconductive paste, and may not contain inorganic fillers. In some instances, underfill material 130 may comprise capillary underfill (CUF), nonconductive paste (NCP), nonconductive film (NCF), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). In some instances, when underfill material 130 comprises molded underfill (MUF), electronic component 110, including contact pads and interconnects 114, may be covered by encapsulation 140, and underfill material 130 may be considered part of encapsulation 140 or may be replaced by said encapsulation. In some instances, an underfill material 130 may be disposed between the electronic component 110 and the main substrate 120 and then cured. In some instances, after the underfill material 130 is provided to cover the interior of the main substrate 120, the interconnects 114 of the electronic component 110 may penetrate the underfill material 130 to connect to the inward terminals 124a of the main substrate. The underfill material 130 can prevent the electronic component 110 from separating from the main substrate 120 due to physical or chemical impact.

[0064] Although the electronic component 110 is shown in a face-down or flip-chip configuration, it can also be in a face-up or wire-bonded configuration. For example, in the electronic component 110, the inactive side (i.e., the second side 112 of the electronic component) can be bonded to the first side 121 of the host substrate 120, and the host substrate inward terminal 124a and contact pad 113 can be electrically connected to each other via conductive wires or other types of interconnects. In some instances, the total thickness of the electronic component 110 can range from approximately 50 micrometers to approximately 200 micrometers, and the area of ​​the electronic device 200 can range from approximately 0.5 mm × 0.5 mm to approximately 50 mm × 50 mm. The total thickness of the electronic component 110 can be less than the thickness of the vertical interconnect 350. The second side 112 of the electronic component 110 can be spaced apart from the second side 322 of the interposer substrate 320.

[0065] Figure 2F A cross-sectional view of the packaged electronic device structure 10 in the late stages of manufacturing is shown. Figure 2FIn the illustrated example, encapsulation 140 may be disposed between the main substrate 120 and the interposer substrate 320. Encapsulation 140 may fill the space between a first side 121 of the main substrate 120 and a second side 322 of the interposer substrate 320. Encapsulation 140 may contact the first side 121 of the main substrate 120, the second side 322 of the interposer substrate 320, the electronic component 110 (including the second side 112), and the vertical interconnect 350. Encapsulation 140 may include corresponding elements, features, materials, or manufacturing methods similar to those of encapsulation 340. In some examples, encapsulation 240, encapsulation 340, and encapsulation 140 may comprise different materials with different coefficients of thermal expansion. In some examples, materials and process technologies are selected to reduce stress and warpage of the encapsulated electronic device structure 10. Encapsulation 140 is an example of a third encapsulation.

[0066] The encapsulation 140 protects the electronic components 110 and the vertical interconnects 350, thereby improving reliability. After the encapsulation 140 is provided, it can be individually diced from the main substrate 120 using processes such as sawing or laser cutting, thereby separating the packaged electronic device subassembly 10A into individual electronic devices. In some instances, the dicing can be performed such that the sidewalls of the encapsulation 140 and the sidewalls of the main substrate 120 are coplanar with the sidewalls of the packaged electronic device subassembly 10A. Furthermore, in the presence of the external interconnects 250 and the encapsulation 340, the first side 321, including the inward terminal 324a, is protected from defects such as flash when the encapsulation 140 is provided.

[0067] Figure 2G A cross-sectional view of the packaged electronic device structure 10 in the late stages of manufacturing is shown. Figure 2G In the illustrated example, the primary external interconnect 150 may be disposed on a second side 122 of the primary substrate 120. In some examples, the primary external interconnect 150 is coupled to an outward terminal 124b of the primary substrate. The primary external interconnect 150 may contact and be electrically connected to the outward terminal 124b of the primary substrate. The primary external interconnect 150 may include corresponding elements, features, materials, or manufacturing methods similar to those of the external interconnect 250. The primary external interconnect 150 is an example of a second external interconnect.

[0068] In some instances, one or more electronic components 160 may be coupled to a second side 122 of the main substrate 120 prior to providing the main external interconnect 150. The electronic components 160 may contact and be electrically connected to the main substrate outward terminal 124b. The electronic components 160 may be laterally spaced in-plane from the main external interconnect 150. In some instances, the electronic components 160 may comprise or be referred to as passive or active components. The electronic component 160 is an example of a third, fourth, or fifth electronic component.

[0069] The main external interconnect 150 can be electrically connected to electronic component 160 or electronic component 110 via the main substrate 120. The main external interconnect 150 can be electrically connected to electronic component 360 via the main substrate 120, vertical interconnect 350, and interposer substrate 320. The main external interconnect 150 can be electrically connected to electronic components 210a and 210b via the main substrate 120, vertical interconnect 350, interposer substrate 320, external interconnect 250, and substrate 220. In some embodiments, electronic components 110, 160, 210a, 210b, and 360 can be electrically connected to each other via the main substrate 120, vertical interconnect 350, interposer substrate 320, external interconnect 250, and substrate 220.

[0070] The packaged electronic device structure 10 may include electronic components 110, 210a, 210b, 160, and 360, a main substrate 120, an underfill material 130, encapsulants 140, 240, and 340, a main external interconnect 150, a substrate 220, die attachment materials 230a and 230b, an external interconnect 250, an interposer substrate 320, and a vertical interconnect 350. In the packaged electronic device structure 10, the encapsulant 340 may be disposed and positioned between the main substrate 120 and the interposer substrate 320, and the encapsulant 140 may be positioned between the interposer substrate 320 and the main substrate 120. The encapsulated electronic device structure 10, through encapsulation 140 and encapsulation 340, can protect the vertical interconnect 350, external interconnect 250, electronic component 110 and electronic component 360, thereby improving reliability.

[0071] In some instances, substrate 220 includes a side 225 connecting a first side 221 to a second side 222, interposer substrate 320 includes a side 325 connecting a first side 321 to a second side 322, and main substrate 120 includes a side 125 connecting a first side 121 to a second side 122. In some instances, side 225, side 325, and side 125 are substantially coplanar with each other. In some instances, side 225 is exposed from encapsulation 240 and encapsulation 340, side 325 is exposed from encapsulation 340 and encapsulation 140, and side 125 is exposed from encapsulation 140. This configuration can also be applied to packaged electronic device structure 20.

[0072] Figure 3 A cross-sectional view of the packaged electronic device 20 is shown. Figure 3 In the example shown, the packaged electronic device 20 may include electronic components 110A, 210a, 210b, 160, 360, a main substrate 120, an underfill material 130, an encapsulant 140, an encapsulant 240, an encapsulant 340, a main external interconnect 150, a substrate 220, die attachment materials 230a and 230b, an external interconnect 250, an interposer substrate 320, and a vertical interconnect 350A.

[0073] In this example, the packaged electronic device 20 is similar to the packaged electronic device structure 10; however, in the packaged electronic device 20, the overall thickness of the electronic component 110A and the height of the vertical interconnect 350A can range from approximately 200 micrometers to approximately 1000 micrometers. In this example, the thickness of the electronic component 110A can be increased, thereby improving the thermal efficiency of the packaged electronic device 20. In some examples, the thickness of the electronic component 110A is greater than the combined thickness of electronic components 210a and 210b. In some examples, the vertical interconnect 350A can be made of dual-core balls provided in a stacked configuration to prevent the pitch from increasing due to the increase in height. This maintains a small package footprint. The electronic component 110A is an example of a fourth electronic component.

[0074] In some instances, with the first core ball disposed on the second side 322 of the interposer substrate 320 and the second core ball disposed on the first side 121 of the main substrate 120, vertical interconnects 350A can be provided in a stacked configuration by bonding the core balls together via a remelting process. The vertical interconnects 350A can be made of dual core balls to prevent the pitch from increasing due to the increased height of the electronic component 110A, thereby achieving fine pitch. In addition to a greater thickness, the electronic component 110A may include corresponding elements, features, materials, or manufacturing methods similar to those of the electronic component 110 of the packaged electronic device structure 10.

[0075] In summary, structures and methods relating to packaged electronic components with improved manufacturability, quality, and reliability have been described. More specifically, structures and methods for disposing a molded encapsulant within a gap between the top side of an interposer substrate and the electronic component mounted on the top side have been described to protect interconnects coupling the electronic component to the interposer substrate. In some instances, a transfer molding process is used to dispose the molded encapsulant between the electronic component and the top side of the interposer substrate before attaching the interposer substrate to the main substrate or bottom substrate. Molded encapsulants offer advantages over other materials, such as capillary underfill materials, including the elimination of the need to consider blocking regions that could adversely increase package size. Furthermore, this method avoids the use of tape-assisted processing or other costly molding techniques, reducing process complexity and cost. Further, the method allows for electrical testing before attaching the interposer substrate to the main substrate, improving yield and reducing manufacturing costs.

[0076] This disclosure includes references to certain examples; however, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

Claims

1. A packaged electronic device structure, characterized in that, Include: A first electronic device, the first electronic device comprising: A first substrate, the first substrate comprising: A first side of a first substrate and a second side of a first substrate opposite to the first side of the first substrate; and First substrate conductive structure; A first electronic component, wherein the first electronic component is coupled to a conductive structure of the first substrate at a first side of the first substrate; A first package covering the first electronic component; as well as A first external interconnect is coupled to a conductive structure of the first substrate at a second side of the first substrate; A second substrate, the second substrate comprising: The first side of the second substrate and the second side of the second substrate opposite to the first side of the second substrate; Second substrate conductive structure; as well as The second substrate dielectric structure, wherein: The first external interconnect is coupled to the conductive structure of the second substrate at a first side of the second substrate; A second electronic component, the second electronic component being coupled to a first side of the second substrate; A second encapsulation is inserted between the first substrate and the second substrate, and covers the first external interconnect, the first side of the second substrate, the second side of the first substrate, and the second electronic component; A second electronic device, the second electronic device comprising: A third substrate, the third substrate comprising: The first side of the third substrate and the second side of the third substrate opposite to the first side of the third substrate; and The third substrate conductive structure; and A third electronic component, wherein the third electronic component is coupled to a conductive structure of the third substrate at a first side of the third substrate; A vertical interconnect, wherein the vertical interconnect is coupled to a conductive structure of the second substrate at a second side of the second substrate and to a conductive structure of the third substrate at a first side of the third substrate; A third encapsulation material is inserted between the second substrate and the third substrate, and covers the vertical interconnect and the third electronic component; and A second external interconnect is coupled to the conductive structure of the third substrate at a second side of the third substrate.

2. The encapsulated electronic device structure according to claim 1, characterized in that, It further includes: A fourth electronic component, coupled to the first electronic component and coupled to the first substrate conductive structure, wherein: The first encapsulation covers the third electronic component.

3. The encapsulated electronic device structure according to claim 2, characterized in that: The thickness of the third electronic component is greater than the combined thickness of the first and fourth electronic components.

4. The encapsulated electronic device structure according to claim 1, characterized in that: The second encapsulation contains a molding compound.

5. The encapsulated electronic device structure according to claim 1, characterized in that: The vertical interconnect includes a metal core ball.

6. The encapsulated electronic device structure according to claim 1, characterized in that: Each of the vertical interconnects comprises a dual-core ball arranged in a stacked configuration.

7. The encapsulated electronic device structure according to claim 1, characterized in that, It further includes: Bottom filler, which is inserted between the first side of the third electronic component and the first side of the third substrate.

8. The encapsulated electronic device structure according to claim 1, characterized in that: The first substrate includes a first substrate side surface, which connects a first side surface of the first substrate to a second side surface of the first substrate; The second substrate includes a second substrate side surface, which connects the first side surface of the second substrate to the second side surface of the second substrate; The third substrate includes a third substrate side surface, which connects from a second side of the third substrate to a first side of the third substrate. The first substrate side surface, the second substrate side surface, and the third substrate side surface are coplanar; The side of the first substrate is exposed from the first encapsulation and the second encapsulation; The second substrate sidewalls are exposed from the second encapsulation and the third encapsulation; and The side of the third substrate is exposed from the third encapsulation.

9. A method for manufacturing a packaged electronic device structure, characterized in that, The method includes: A first electronic device is provided, the first electronic device comprising: A first substrate, the first substrate comprising: A first side of a first substrate and a second side of a first substrate opposite to the first side of the first substrate; and First substrate conductive structure; A first electronic component, wherein the first electronic component is coupled to a conductive structure of the first substrate at a first side of the first substrate; A first package covering the first electronic component; as well as A first external interconnect is coupled to a conductive structure of the first substrate at a second side of the first substrate; A second substrate is provided, the second substrate comprising: The first side of the second substrate and the second side of the second substrate opposite to the first side of the second substrate; Second substrate conductive structure; as well as Second substrate dielectric structure; The first external interconnect is coupled to the conductive structure of the second substrate at a first side of the second substrate; A second encapsulation is provided, which is inserted between the first substrate and the second substrate and covers the first external interconnect, a first side of the second substrate and a second side of the first substrate; A first vertical interconnect is provided, the first vertical interconnect being coupled to a conductive structure of the second substrate at a second side of the second substrate; A second electronic device is provided, the second electronic device comprising: A third substrate, the third substrate comprising: The first side of the third substrate and the second side of the third substrate opposite to the first side of the third substrate; and Third substrate conductive structure; as well as A second electronic component is coupled to a conductive structure of the third substrate at a first side of the third substrate; as well as After providing the second package: (a) The first vertical interconnect is coupled to the conductive structure of the third substrate at a first side of the third substrate; as well as (b) A third encapsulation is provided, which is inserted between the second substrate and the third substrate and covers the first vertical interconnect and the second electronic component.

10. The method according to claim 9, characterized in that, It further includes: A second vertical interconnect is provided, the second vertical interconnect being coupled to the third substrate conductive structure, wherein: Coupling the first vertical interconnect includes attaching the first vertical interconnect to the second vertical interconnect; and The third encapsulation includes covering the second vertical interconnect.

11. The method according to claim 10, characterized in that: Providing the first vertical interconnect includes providing a first metal core ball; and Providing the second vertical interconnect includes providing a second metal core ball.

12. The method according to claim 9, characterized in that: Providing the second encapsulation includes transfer molding of the second encapsulation.

13. The method according to claim 9, characterized in that, It further includes: A third electronic component is provided, the third electronic component being attached to a first side of the second substrate, wherein: The second encapsulation covers the third electronic component.

14. The method according to claim 9, characterized in that: The first electronic device includes: A third electronic component is provided, which is coupled to the first electronic component and to the first substrate conductive structure; as well as The first encapsulation is provided, which covers the third electronic component.

15. The method according to claim 14, characterized in that, It further includes: Prior to providing the second encapsulation, a fourth electronic component is provided, the fourth electronic component being coupled to a first side of the second substrate; as well as A second external interconnect is provided, the second external interconnect being coupled to a conductive structure of the third substrate at a second side of the third substrate, wherein: The thickness of the second electronic device is greater than the combined thickness of the first electronic component and the third electronic component.

16. A method for manufacturing a packaged electronic device structure, characterized in that, The method includes: A first electronic device is provided, the first electronic device comprising: A first substrate, the first substrate comprising: A first side of a first substrate and a second side of a first substrate opposite to the first side of the first substrate; and First substrate conductive structure; A first electronic component, wherein the first electronic component is coupled to a conductive structure of the first substrate at a first side of the first substrate; A first package covering the first electronic component; as well as A first external interconnect is coupled to a conductive structure of the first substrate at a second side of the first substrate; A second substrate is provided, the second substrate comprising: The first side of the second substrate and the second side of the second substrate opposite to the first side of the second substrate; Second substrate conductive structure; as well as Second substrate dielectric structure; The first external interconnect is coupled to the conductive structure of the second substrate at a first side of the second substrate; A second encapsulation is provided, which is inserted between the first substrate and the second substrate and covers the first external interconnect, a first side of the second substrate and a second side of the first substrate; A first vertical interconnect is coupled to a conductive structure of the second substrate at a second side of the second substrate; as well as After providing the second package: (a) Providing a second electronic device, the second electronic device comprising: A third substrate, the third substrate comprising: The first side of the third substrate and the second side of the third substrate opposite to the first side of the third substrate; and Third substrate conductive structure; as well as A second electronic component is coupled to a conductive structure of the third substrate at a first side of the third substrate; (b) The first vertical interconnect is coupled to the conductive structure of the third substrate at a first side of the third substrate; as well as (c) A third encapsulation is provided, which is inserted between the second substrate and the third substrate and covers the first vertical interconnect and the second electronic component.

17. The method according to claim 16, characterized in that, Further includes: A second vertical interconnect is provided, the second vertical interconnect being coupled to the third substrate conductive structure, wherein: Coupling the first vertical interconnect includes attaching the first vertical interconnect to the second vertical interconnect; and The third encapsulation includes covering the second vertical interconnect.

18. The method according to claim 17, characterized in that: Providing the first vertical interconnect includes providing a first metal core ball; and Providing the second vertical interconnect includes providing a second metal core ball.

19. The method according to claim 16, characterized in that: Providing the second encapsulation includes transfer molding of the second encapsulation.

20. The method according to claim 16, characterized in that: Providing the second encapsulation occurs before coupling the first vertical interconnect to the second substrate conductive structure.

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