A shift register unit, display panel, display device and driving method

Abstract

A shift register unit, a display panel, a display device and a driving method. The shift register unit comprises a shift register (001), a first driving sub-circuit (002) and a second driving sub-circuit (003). The shift register (001) is configured to control a cascade output end (Scan_n) to output a cascade signal according to a signal of an input signal end (STV). The first driving sub-circuit (002) is configured to output a first driving signal through a first driving output end (Rout_n) in response to signals of a pull-up node (N9) and a cascade node (N10). The second driving sub-circuit (003) is configured to output a second driving signal through a second driving output end (Nout_n) in response to signals of the pull-up node (N9), the cascade node (N10) and a local brush signal control end (N11_N‑n). The shift register unit can realize display panel row refresh while effectively shortening the width of the frame.

Description

Shift register unit, display panel, display device and driving method TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and provides a shift register unit, a display panel, a display device and a driving method. BACKGROUND

[0002] Currently, referring to FIG. 1 and FIG. 2, in a pixel driving circuit in which a transistor for initialization affects a transistor for controlling data voltage writing, a signal for simultaneously controlling control terminals of the two transistors can be used to update or not update the data voltage, in which case two row refresh circuits need to be set for each row of sub-pixels, and the two row refresh circuits are usually arranged on the left and right sides of the display panel, thereby increasing the width of the frame.

[0003] SUMMARY

[0004] The present disclosure provides a shift register unit, a display panel, a display device and a driving method, which can reduce the width of the frame of the display panel on the basis of realizing row local refresh.

[0005] The specific technical solutions provided by the present disclosure are as follows:

[0006] In a first aspect, the present disclosure provides a shift register unit, comprising: a shift register, a first driving sub-circuit and a second driving sub-circuit;

[0007] The shift register is configured to control a cascade output end to output a cascade signal according to a signal of an input signal end;

[0008] The first driving sub-circuit is coupled with a pull-up node and a lower cascade node of the shift register and a first driving output end, and the first driving sub-circuit is configured to output a first driving signal through the first driving output end in response to signals of the pull-up node and the lower cascade node;

[0009] The second driving sub-circuit is coupled with the pull-up node, the lower cascade node, a local refresh signal control end and a second driving output end, and the second driving sub-circuit is configured to output a second driving signal through the second driving output end in response to signals of the pull-up node, the lower cascade node and the local refresh signal control end.

[0010] In some possible embodiments provided by the present disclosure, the second driving signal has the same waveform and phase as the first driving signal.

[0011] In some possible embodiments provided by the present disclosure, the second driving sub-circuit comprises: a driving control unit, a first output unit and a second output unit;

[0012] The driving control unit is coupled with the lower connection node, the local brush signal control end and the first output control node, and is configured to provide a signal of the lower connection node to the first output control node in response to a signal of the local brush signal control end;

[0013] The first output unit is coupled with the pull-up node, the first reference signal end and the second driving output end, and is configured to provide a signal of the first reference signal end to the second driving output end in response to a signal of the pull-up node;

[0014] The second output unit is coupled with the first output control node, the second reference signal end and the second driving output end, and is configured to provide a signal of the second reference signal end to the second driving output end in response to a signal of the first output control node.

[0015] In some possible implementation provided by the present disclosure, the driving control unit comprises a first transistor;

[0016] The control end of the first transistor is coupled with the local brush signal control end, the first end of the first transistor is coupled with the lower connection node, and the second end of the first transistor is coupled with the first output control node.

[0017] In some possible implementation provided by the present disclosure, the second output unit comprises a second transistor;

[0018] The control end of the second transistor is coupled with the first output control node, the first end of the second transistor is coupled with the second driving output end, and the second end of the second transistor is coupled with the second reference signal end.

[0019] In some possible implementation provided by the present disclosure, the second driving sub-circuit further comprises a first control unit coupled with the first output control node and a fourth node in the shift register;

[0020] The first control unit is configured to provide a signal of the fourth node to the first output control node in response to the signal of the fourth node.

[0021] In some possible implementation provided by the present disclosure, the first control unit comprises a third transistor;

[0022] The control end and the first end of the third transistor are coupled with the fourth node, and the second end of the third transistor is coupled with the first output control node.

[0023] In some possible implementation provided by the present disclosure, the first output unit comprises a fourth transistor;

[0024] The control end of the fourth transistor is coupled with the pull-up node, the first end of the fourth transistor is coupled with the first reference signal end, and the second end of the fourth transistor is coupled with the second driving output end.

[0025] In some possible implementation provided by the present disclosure, the second driving sub-circuit further includes a second control unit, wherein the second control unit is coupled between the pull-up node and the first output unit;

[0026] The second control unit is configured to turn on the pull-up node and the first output unit in response to a signal of the local brush signal control end.

[0027] In some possible implementation provided by the present disclosure, the second control unit includes a fifth transistor, a first capacitor and a second capacitor.

[0028] The control end of the fifth transistor is coupled with the local brush signal control end, the first end of the fifth transistor is coupled with the pull-up node, and the second end of the fifth transistor is coupled with the first output unit.

[0029] The first end of the first capacitor is coupled with the second end of the fifth transistor, and the second end of the first capacitor is coupled with the local brush signal control end.

[0030] The first end of the second capacitor is coupled with the second end of the fifth transistor, and the second end of the second capacitor is coupled with the first reference signal end.

[0031] In some possible implementation provided by the present disclosure, the control end of the fifth transistor includes a first control end and a second control end, and the first control end and the second control end are both coupled with the local brush signal control end.

[0032] In some possible implementation provided by the present disclosure, the second driving sub-circuit further includes a third control unit, wherein the third control unit is coupled with the local brush signal control end.

[0033] The third control unit is configured to provide a signal of the second reference signal end to the local brush signal control end in response to a signal of the reset control signal end.

[0034] In some possible implementation provided by the present disclosure, the third control unit includes a sixth transistor.

[0035] The control end of the sixth transistor is coupled with the reset control signal end, the first end of the sixth transistor is coupled with the local brush signal control end, and the second end of the sixth transistor is coupled with the second reference signal end.

[0036] In some possible implementation provided by the present disclosure, the second driving sub-circuit further includes a fourth control unit, wherein the fourth control unit is coupled with the control end of the fourth transistor.

[0037] The fourth control unit is configured to provide a signal of the first reference signal end to the control end of the fourth transistor in response to a signal of the second control signal end.

[0038] In some possible implementation modes provided by the present disclosure, the fourth control unit comprises a seventh transistor.

[0039] The control end of the seventh transistor is coupled with the second control signal end, the first end of the seventh transistor is coupled with the control end of the fourth transistor, and the second end of the seventh transistor is coupled with the first reference signal end.

[0040] In some possible implementation modes provided by the present disclosure, the fourth control unit comprises an eighth transistor and a ninth transistor, and the second control signal end comprises a first control sub-signal end and a second control sub-signal end.

[0041] The control end of the eighth transistor is coupled with the second control sub-signal end, the first end of the eighth transistor is coupled with the first end of the ninth transistor, and the second end of the eighth transistor is coupled with the first reference signal end.

[0042] The control end of the ninth transistor is coupled with the first control sub-signal end, and the second end of the ninth transistor is coupled with the control end of the fourth transistor.

[0043] In some possible implementation modes provided by the present disclosure, the second control sub-signal end is a first output control node, and the first control sub-signal end is a second driving output end.

[0044] In some possible implementation modes provided by the present disclosure, the second driving sub-circuit further comprises a fifth control unit, wherein the fifth control unit is coupled with the local brush signal control end, the third control signal end, the fourth control signal end and the second reference signal end.

[0045] The fifth control unit is configured to provide the signal of the second reference signal end to the local brush signal control end in response to the signals of the third control signal end and the fourth control signal end.

[0046] In some possible implementation modes provided by the present disclosure, there is a phase difference between the effective signals of the third control signal end and the fourth control signal end, and the phase difference between the effective signals of the third control signal end and the fourth control signal end is set to correspond to the phase difference between the second driving signal of the Nth shift register unit and the first driving signal of the N-nth shift register unit.

[0047] In some possible implementation modes provided by the present disclosure, the fifth control unit comprises a tenth transistor and an eleventh transistor,

[0048] The control end of the tenth transistor is coupled with the third control signal end, the first end of the tenth transistor is coupled with the local brush signal control end, and the second end of the tenth transistor is coupled with the first end of the eleventh transistor.

[0049] The control end of the eleventh transistor is coupled with a fourth control signal end, and the second end of the eleventh transistor is coupled with a second reference signal end.

[0050] In some possible implementation provided by the present disclosure, the shift register comprises a first input sub-circuit, a second input sub-circuit, a node control sub-circuit and an output sub-circuit.

[0051] The first input sub-circuit is configured to provide a signal of an input signal end to a first node and a second node in response to a signal of a first clock signal end.

[0052] The second input sub-circuit is configured to provide a signal of a second reference signal end to a third node in response to the signal of the first clock signal end.

[0053] The node control sub-circuit is configured to control signals of a pull-up node and a pull-down node according to signals of the first node, the second node and the third node.

[0054] The output sub-circuit is configured to provide a signal of a first reference signal end to a cascade output end in response to the signal of the pull-up node, and provide a signal of the second reference signal end to the cascade output end in response to the signal of the pull-down node.

[0055] In some possible implementation provided by the present disclosure, the first driving sub-circuit comprises a refresh input unit, a refresh control unit, a third output unit and a fourth output unit.

[0056] The refresh input unit is configured to provide a signal of a row refresh control end to a refresh signal control end in response to signals of a refresh gate end and an input signal end.

[0057] The refresh control unit is configured to provide a signal of a lower node to a second output control node in response to the signal of the refresh signal control end.

[0058] The third output unit is configured to provide a signal of a second reference signal end to a first driving output end in response to a signal of the second output control node.

[0059] The fourth output unit is configured to provide a signal of a first reference signal end to the first driving output end in response to a signal of a pull-up node.

[0060] The present disclosure further provides a gate driving circuit, comprising a plurality of shift register units connected in cascade.

[0061] The input signal end of the first shift register unit is coupled with a frame start signal end.

[0062] The input signal end of a later shift register unit of two adjacent shift register units is connected with a cascade output end of an earlier shift register unit.

[0063] In some possible implementation provided by the present disclosure, the local brush signal control terminal of the current stage shift register unit in the plurality of shift register units is connected with the local brush signal control terminal of the previous n stages of shift register.

[0064] The display panel provided by the embodiments of the present disclosure comprises:

[0065] The display area comprises a plurality of sub-pixels, each of which comprises a light emitting device and a pixel driving circuit connected with the light emitting device;

[0066] The non-display area comprises the gate driving circuit, the first reset signal terminal of the pixel circuit in the current row of sub-pixels is connected with the first driving output terminal of the mth stage shift register unit in the plurality of shift register units, the first scan signal terminal of the pixel circuit in the current row of sub-pixels is connected with the second driving output terminal of the m-nth stage shift register unit in the plurality of shift register units, and n and m are integers greater than 0 and m>n.

[0067] In some possible implementation provided by the present disclosure, the pixel driving circuit comprises a first reset transistor, the control terminal of the first reset transistor is coupled with the first reset signal terminal connected with the sub-pixel, and the first reset signal terminal is coupled with the first driving output terminal of the shift register unit connected with the sub-pixel.

[0068] In some possible implementation provided by the present disclosure, the pixel driving circuit comprises a threshold compensation transistor, the control terminal of the threshold compensation transistor is coupled with the first scan signal terminal connected with the sub-pixel, and the first scan signal terminal is coupled with the second driving output terminal of the shift register unit connected with the sub-pixel.

[0069] In some possible implementation provided by the present disclosure, further comprising: a first reference signal line, a second reference signal line and a third reference signal line arranged at intervals;

[0070] The first reference signal terminal of the shift register in each stage of shift register unit and the first driving sub-circuit is connected with the first reference signal line;

[0071] The first reference signal terminal of the second driving sub-circuit in the odd-numbered stage shift register unit is connected with the second reference signal line;

[0072] The first reference signal terminal of the second driving sub-circuit in the even-numbered stage shift register unit is connected with the third reference signal line.

[0073] The display device provided by the embodiments of the present disclosure comprises the display panel according to any one of the above.

[0074] The embodiment of the present disclosure further provides a driving method applied to the shift register unit of any one of the above, comprising:

[0075] The shift register outputs a cascade signal through a cascade output terminal;

[0076] The first driving sub-circuit outputs a first driving signal through a first driving output terminal in response to signals of the pull-up node and the cascade node;

[0077] The second driving sub-circuit is configured to output a second driving signal through a second driving output terminal in response to signals of the pull-up node, the cascade node and the local brush signal control terminal.

[0078] The present disclosure has the following beneficial effects:

[0079] In summary, the embodiment of the present disclosure provides a shift register unit, a display panel, a display device and a driving method, the shift register unit comprising: a shift register, a first driving sub-circuit and a second driving sub-circuit, the shift register is configured to control a cascade output terminal to output a cascade signal according to a signal of an input signal terminal STV, the first driving sub-circuit is coupled with a pull-up node and a cascade node of the shift register and a first driving output terminal, the first driving sub-circuit is configured to output a first driving signal through the first driving output terminal in response to signals of the pull-up node and the cascade node, the second driving sub-circuit is coupled with the pull-up node, the cascade node, a local brush signal control terminal and a second driving output terminal, the second driving sub-circuit is configured to output a second driving signal through the second driving output terminal in response to signals of the pull-up node, the cascade node and the local brush signal control terminal, the above shift register unit can output three signals to the display panel at the same time, on the basis of realizing row refresh of the display panel, the width of the frame of the corresponding display device is effectively shortened.

[0080] Other features and advantages of the present disclosure will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice according to the present disclosure. The objects and other advantages of the present disclosure can be achieved and obtained by the structure particularly pointed out in the written description, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0081] The drawings described herein are used to provide further understanding of the present disclosure, and form a part of the present disclosure. The illustrative embodiments of the present disclosure and their description serve to explain the present disclosure. They do not limit the present disclosure in any way. In the drawings:

[0082] FIG. 1 is a circuit connection diagram of a first pixel driving circuit in the related art;

[0083] FIG. 2 is a circuit connection diagram of a second pixel driving circuit in the related art;

[0084] Fig. 3 is a connection diagram of a shift register unit in an embodiment of the present disclosure;

[0085] Fig. 4 is a connection diagram of a shift register in an embodiment of the present disclosure;

[0086] Fig. 5 is a circuit connection diagram of a first shift register unit in an embodiment of the present disclosure;

[0087] Fig. 6 is a connection diagram of a first driving sub-circuit in an embodiment of the present disclosure;

[0088] Fig. 7 is a connection diagram of a first second driving sub-circuit in an embodiment of the present disclosure;

[0089] Fig. 8 is a connection diagram of a second second driving sub-circuit in an embodiment of the present disclosure;

[0090] Fig. 9 is a connection diagram of a third second driving sub-circuit in an embodiment of the present disclosure;

[0091] Fig. 10 is a circuit connection diagram of a second shift register unit in an embodiment of the present disclosure;

[0092] Fig. 11 is a connection diagram of a fourth second driving sub-circuit in an embodiment of the present disclosure;

[0093] Fig. 12 is a circuit connection diagram of a third shift register unit in an embodiment of the present disclosure;

[0094] Fig. 13 is a connection diagram of a fifth second driving sub-circuit in an embodiment of the present disclosure;

[0095] Fig. 14 is a circuit connection diagram of a fourth shift register unit in an embodiment of the present disclosure;

[0096] Fig. 15 is a connection diagram of a sixth second driving sub-circuit in an embodiment of the present disclosure;

[0097] Fig. 16 is a circuit connection diagram of a fifth shift register unit in an embodiment of the present disclosure;

[0098] Fig. 17 is a connection diagram of multiple clock signal terminals in an embodiment of the present disclosure;

[0099] Fig. 18 is a circuit connection diagram of a sixth shift register unit in an embodiment of the present disclosure;

[0100] Fig. 19 is a cascade connection diagram of multiple clock signal terminals in an embodiment of the present disclosure;

[0101] Fig. 20 is a timing diagram of a shift register unit in an embodiment of the present disclosure;

[0102] Fig. 21 is a diagram of output waveforms of a gate driving circuit in an embodiment of the present disclosure;

[0103] FIG. 22 is a schematic diagram of connection of a gate driving circuit and a pixel driving circuit according to an embodiment of the present disclosure;

[0104] FIG. 23 is a schematic diagram of connection of a display panel according to an embodiment of the present disclosure;

[0105] FIG. 24 is a flowchart of a driving method applied to a shift register unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0106] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments described in the present disclosure document, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the technical solutions of the present disclosure.

[0107] The terms “first”, “second”, and the like in the specification of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0108] In the related art, in order to realize local refresh of some rows in a display panel, the pixel driving circuit included in the corresponding sub-pixel needs to update the data voltage of the driving transistor, so that the light emitting device included in the sub-pixel emits light under the action of the above-mentioned data voltage, and the data voltage of the sub-pixel corresponding to the row that does not need to be refreshed is in a maintenance state.

[0109] Referring to FIGS. 1 and 2, the one end of the control terminal of the driving transistor coupled with the turn-on control sub-circuit in the pixel driving circuit is also connected with the first initialization sub-circuit. In the row refresh process, after the data write sub-circuit writes the data voltage into the control terminal of the driving transistor through the turn-on control sub-circuit, the first initialization sub-circuit will reset the control terminal of the driving transistor under the control of the effective level. In this case, the turn-on control sub-circuit and the first initialization sub-circuit need to be jointly controlled, so that the data voltage can be normally written into the control terminal of the driving transistor according to the requirement of row refresh.

[0110] For example, the pixel driving circuit includes a driving transistor, a light emitting device, a data write sub-circuit, a turn-on control sub-circuit, a first initialization sub-circuit, and a light emitting control sub-circuit.

[0111] In the implementation process, the data voltage of the data signal end is provided to the control end of the driving transistor through the turned-on data writing sub-circuit and the turned-on control sub-circuit.

[0112] The first case: when the data voltage Data enters the pixel driving circuit through the turned-on data writing transistor M4, whether the data voltage is written to the control end of the driving transistor is controlled by a switch transistor included in the turned-on control sub-circuit, as shown in FIG. 1, the turned-on control sub-circuit includes: a threshold compensation transistor m1, wherein the scan signal end includes a first scan signal end NGate.

[0113] The control end of the threshold compensation transistor m1 is coupled with the first scan signal end NGate, the first end of the threshold compensation transistor m1 is coupled with the control end of the driving transistor, and the second end of the threshold compensation transistor m1 is coupled with the first end of the driving transistor m3.

[0114] In the implementation process, when the signal of the first scan signal end NGate is an effective level, the threshold compensation transistor m1 is turned on, and the control end of the driving transistor m3 is communicated with the first end of the driving transistor m3 through the turned-on threshold compensation transistor m1.

[0115] The first initialization sub-circuit in the pixel driving circuit is coupled with the control end of the driving transistor m3 and is configured to provide the signal of the first reset voltage end Vinit to the control end of the driving transistor m3 in response to the signal of the first reset signal end NReset.

[0116] In the implementation process, when the signal of the first reset signal end NReset is an effective level, the first initialization sub-circuit is turned on, and the reset signal of the first reset voltage end Vinit is provided to the control end of the driving transistor through the turned-on first initialization sub-circuit.

[0117] As shown in FIG. 1, the first initialization sub-circuit includes: a second switch transistor m2.

[0118] The control end of the second switch transistor m2 is coupled with the first reset signal end NReset, the first end of the second switch transistor m2 is coupled with the control end of the driving transistor m3, and the second end of the second switch transistor m2 is coupled with the first reset voltage end Vinit.

[0119] In the implementation process, when the signal of the first reset signal end NReset is an effective level, the second switch transistor m2 is turned on, and the reset signal of the first reset voltage end Vinit is provided to the control end of the driving transistor m3 through the turned-on second switch transistor m2.

[0120] The second case: when the data voltage Data enters the pixel driving circuit through the turned-on data writing transistor M4, whether the data voltage is written into the control terminal of the driving transistor is controlled by two switch transistors included in the turn-on control sub-circuit, as shown in FIG. 2, the turn-on control sub-circuit includes: a threshold compensation transistor M1 and a second switch transistor M2, wherein the scan signal terminal includes a first scan signal terminal NGate and a second scan signal terminal Pgate.

[0121] The control terminal of the threshold compensation transistor M1 is coupled with the first scan signal terminal NGate, the first terminal of the threshold compensation transistor M1 is coupled with the first terminal of the second switch transistor M2, and the second terminal of the threshold compensation transistor M1 is coupled with the first terminal of the driving transistor M9.

[0122] In the implementation process, when the signal of the first scan signal terminal NGate is an effective level, the threshold compensation transistor M1 is turned on, and the first terminal of the driving transistor M9 is in communication with the first terminal of the second switch transistor M2 through the turned-on threshold compensation transistor M1.

[0123] The control terminal of the second switch transistor M2 is coupled with the second scan signal terminal Pgate, and the second terminal of the second switch transistor M2 is coupled with the control terminal of the driving transistor M9.

[0124] In the implementation process, when the signal of the second scan signal terminal Pgate is an effective level, the second switch transistor M2 is turned on, and the control terminal of the driving transistor M9 is in communication with the first terminal of the threshold compensation transistor M1 through the turned-on second switch transistor M2.

[0125] In this case, the first initialization sub-circuit is coupled with the first terminal of the threshold compensation transistor M1 and is configured to provide the signal of the first reset voltage terminal Vinit to the first terminal of the threshold compensation transistor M1 in response to the signal of the first reset signal terminal NReset.

[0126] In the implementation process, when the signal of the first reset signal terminal NReset is an effective level, the first initialization sub-circuit is turned on, and the reset signal of the first reset voltage terminal Vinit is provided to the first terminal of the threshold compensation transistor M1 through the turned-on first initialization sub-circuit.

[0127] As shown in FIG. 2, the first initialization sub-circuit includes: a third switch transistor M3.

[0128] The control terminal of the third switch transistor M3 is coupled with the first reset signal terminal NReset, the first terminal of the third switch transistor M3 is coupled with the first terminal of the threshold compensation transistor M1, and the second terminal of the third switch transistor M3 is coupled with the first reset voltage terminal Vinit.

[0129] In the implementation process, when the signal of the first reset signal terminal NReset is a valid level, the third switch transistor M3 is turned on, and the reset signal of the first reset voltage terminal Vinit is provided to the first end of the threshold compensation transistor M1 through the turned-on third switch transistor M3.

[0130] It should be noted that when the display panel needs to perform row refresh of the picture, the conduction of the above-mentioned conduction control sub-circuit and the first initialization sub-circuit needs to be synchronously controlled, so as to write the data voltage into the driving transistor of the pixel driving circuit corresponding to the corresponding sub-pixel. After the data voltage is written into the control terminal of the driving transistor, the driving transistor can generate a driving current according to the data voltage, so as to realize the update of the data voltage of the corresponding sub-pixel.

[0131] In the above-mentioned pixel driving circuit, the driving transistor is coupled with the light emitting device through the light emitting control sub-circuit, and the light emitting control sub-circuit is configured to provide the driving current generated by the driving transistor to the light emitting device.

[0132] In the implementation process, when the light emitting control sub-circuit is turned on, the driving transistor can be in communication with the light emitting device through the light emitting control sub-circuit, so as to provide the driving current generated by the driving transistor to the light emitting device, and promote the light emitting device corresponding to the above-mentioned sub-pixel to perform light emitting display, thereby realizing the refresh of the picture.

[0133] It should be further noted that if some rows of the display picture do not need to be refreshed, the data voltage of the related row of sub-pixels can be updated, and in the specific implementation process, at least one switch transistor included in the conduction control sub-circuit in the above-mentioned pixel driving circuit is controlled to be turned off, so as to prevent the data voltage from being written into the control terminal of the driving transistor.

[0134] Obviously, in the process of using the above-mentioned pixel driving circuit to perform row refresh, the shift register of the row needs to output at least two signals, that is, the shift register of the row needs to generate the signal supplied to the first scan signal terminal NGate in FIG. 1 and FIG. 2 and the signal of the first reset signal terminal NReset. In the row refresh process, the shift register needs to generate at least two signals to ensure the normal operation of the row scanning process and the pixel driving circuit. In the related art, in order to ensure the row refresh function of the above-mentioned pixel driving circuit, one shift register is usually arranged on each of the left and right sides of the row of sub-pixels to ensure the generation of the signal of the above-mentioned first scan signal terminal NGate and the signal of the first reset signal terminal NReset, thereby increasing the width of the frame of the display panel.

[0135] The preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0136] Referring to FIG. 3, the shift register unit in the embodiment of the present disclosure comprises a shift register 001, a first driving sub-circuit 002 and a second driving sub-circuit 003.

[0137] In the embodiment of the present disclosure, the shift register unit composed of the shift register 001, the first driving sub-circuit 002 and the second driving sub-circuit 003 can generate three signals, which are respectively used to generate a cascade signal, a signal of a first scan signal terminal NGate and a signal of a first reset signal terminal NReset. The shift register unit in the embodiment of the present disclosure is used in cooperation with the pixel driving circuit described above, so as to realize row refreshing of the display panel.

[0138] Next, the shift register 001 described above is introduced. In the embodiment of the present disclosure, the shift register 001 is configured to control a cascade output terminal Scan_n to output a cascade signal according to a signal of an input signal terminal STV.

[0139] Exemplarily, referring to FIG. 4, the shift register 001 comprises a first input sub-circuit 101, a second input sub-circuit 102, a node control sub-circuit 103 and an output sub-circuit 104.

[0140] The first input sub-circuit 101 is configured to provide the signal of the input signal terminal STV to a first node N1 and a second node N2 in response to a signal of a first clock signal terminal CK.

[0141] Exemplarily, referring to FIG. 5, the first input sub-circuit 101 comprises a first cascade transistor T1 and a second cascade transistor T2.

[0142] The control terminal of the first cascade transistor T1 is coupled with the first clock signal terminal CK, the first end of the first cascade transistor T1 is coupled with the input signal terminal STV, and the second end of the first cascade transistor T1 is coupled with the first node N1.

[0143] In the implementation process, when the signal of the first clock signal terminal CK is at a low level, the first cascade transistor T1 is turned on, and the signal of the input signal terminal STV is provided to the first node N1 through the turned-on first cascade transistor T1.

[0144] The control terminal of the second cascade transistor T2 is coupled with the first clock signal terminal CK, the first end of the second cascade transistor T2 is coupled with the input signal terminal STV, and the second end of the second cascade transistor T2 is coupled with the second node N2.

[0145] In the implementation process, when the signal of the first clock signal terminal CK is at a low level, the second cascade transistor T2 is turned on, and the signal of the input signal terminal STV is provided to the second node N2 through the turned-on second cascade transistor T2.

[0146] The second input sub-circuit 102 is configured to provide a signal of the second reference signal terminal VGL to the third node N3 in response to a signal of the first clock signal terminal CK.

[0147] As shown in FIG. 5, the second input sub-circuit 102 includes a third cascade transistor T3.

[0148] The control terminal of the third cascade transistor T3 is coupled with the first clock signal terminal CK, the first terminal of the third cascade transistor T3 is coupled with the signal of the second reference signal terminal VGL, and the second terminal of the third cascade transistor T3 is coupled with the third node N3.

[0149] In the implementation process, when the signal of the first clock signal terminal CK is at a low level, the third cascade transistor T3 is turned on, and the signal of the second reference signal terminal VGL is provided to the third node N3 through the turned-on third cascade transistor T3.

[0150] The node control sub-circuit 103 is configured to control signals of the pull-up node N9 and the pull-down node N8 according to signals of the first node N1, the second node N2 and the third node N3.

[0151] The node control sub-circuit 103 includes a fourth cascade transistor T4, a fifth cascade transistor T5, a sixth cascade transistor T6, a seventh cascade transistor T7, an eighth cascade transistor T8, a ninth cascade transistor T9, a tenth cascade transistor T10, an eleventh cascade transistor T11, a twelfth cascade transistor T12, a thirteenth cascade transistor T13, a first capacitor C1 and a second capacitor C2.

[0152] The control terminal of the fourth cascade transistor T4 is coupled with the signal of the second reference signal terminal VGL, the first terminal of the fourth cascade transistor T4 is coupled with the lower node N10, and the second terminal of the fourth cascade transistor T4 is coupled with the pull-down node N8.

[0153] As shown in FIG. 5, when the signal of the second reference signal terminal VGL is at a low level, the fourth cascade transistor T4 is turned on, and the lower node N10 is in communication with the pull-down node N8 through the turned-on fourth cascade transistor T4.

[0154] The control terminal of the fifth cascade transistor T5 is coupled with the signal of the second reference signal terminal VGL, the first terminal of the fifth cascade transistor T5 is coupled with the second node N2, and the second terminal of the fifth cascade transistor T5 is coupled with the fourth node N4.

[0155] When the signal of the second reference signal terminal VGL is at a low level, the fifth cascade transistor T5 is turned on, and the second node N2 is in communication with the fourth node N4 through the turned-on fifth cascade transistor T5.

[0156] The control end of the sixth cascade transistor T6 is coupled with the fourth node N4, the first end of the sixth cascade transistor T6 is coupled with the fourth node N4, and the second end of the sixth cascade transistor T6 is coupled with the pull-down node N8.

[0157] When the signal of the fourth node N4 is low, the sixth cascade transistor T6 is turned on, and the fourth node N4 is communicated with the pull-down node N8 through the turned-on sixth cascade transistor T6.

[0158] The control end of the seventh cascade transistor T7 is coupled with the first node N1, the first end of the seventh cascade transistor T7 is coupled with the first clock signal end CK, and the second end of the seventh cascade transistor T7 is coupled with the third node N3.

[0159] When the signal of the first node N1 is low, the seventh cascade transistor T7 is turned on, and the signal of the first clock signal end CK is provided to the third node N3 through the turned-on seventh cascade transistor T7.

[0160] The control end of the eighth cascade transistor T8 is coupled with the third node N3, the first end of the eighth cascade transistor T8 is coupled with the fifth node N5, and the second end of the eighth cascade transistor T8 is coupled with the first reference signal end VGH.

[0161] When the signal of the third node N3 is low, the eighth cascade transistor T8 is turned on, and the fifth node N5 is communicated with the first reference signal end VGH through the turned-on eighth cascade transistor T8.

[0162] The control end of the ninth cascade transistor T9 is coupled with the fourth node N4, the first end of the ninth cascade transistor T9 is coupled with the second clock signal end CB, and the second end of the ninth cascade transistor T9 is coupled with the fifth node N5.

[0163] When the signal of the fourth node N4 is low, the ninth cascade transistor T9 is turned on, and the fifth node N5 is communicated with the second clock signal end CB through the turned-on ninth cascade transistor T9.

[0164] The first end of the first capacitor C1 is coupled with the fourth node N4, and the second end of the first capacitor C1 is coupled with the fifth node N5.

[0165] The control end of the tenth cascade transistor T10 is coupled with the second reference voltage signal end VGL, the first end of the tenth cascade transistor T10 is coupled with the third node N3, and the second end of the tenth cascade transistor T10 is coupled with the first end of the second capacitor C2.

[0166] When the signal of the second reference voltage signal end VGL is low, the tenth cascade transistor T10 is turned on, and the third node N3 is communicated with the first end of the second capacitor C2 through the turned-on tenth cascade transistor T10.

[0167] The control end of the eleventh cascade transistor T11 is coupled with the first end of the second capacitor C2, the first end of the eleventh cascade transistor T11 is coupled with the second end of the second capacitor C2, and the second end of the eleventh cascade transistor T11 is coupled with the second clock signal end CB.

[0168] When the signal at the first end of the second capacitor C2 is at a low level, the eleventh cascade transistor T11 is turned on, and the second end of the second capacitor C2 is communicated with the second clock signal end CB through the turned-on eleventh cascade transistor T11.

[0169] The control end of the twelfth cascade transistor T12 is coupled with the second clock signal end CB, the first end of the twelfth cascade transistor T12 is coupled with the second end of the second capacitor C2, and the second end of the twelfth cascade transistor T12 is coupled with the pull-up node N9.

[0170] When the signal at the second clock signal end CB is at a low level, the twelfth cascade transistor T12 is turned on, and the second end of the second capacitor C2 is communicated with the pull-up node N9 through the turned-on twelfth cascade transistor T12.

[0171] The control end of the thirteenth cascade transistor T13 is coupled with the lower cascade node N10, the first end of the thirteenth cascade transistor T13 is coupled with the first reference signal end VGH, and the second end of the thirteenth cascade transistor T13 is coupled with the pull-up node N9.

[0172] When the signal at the lower cascade node N10 is at a low level, the thirteenth cascade transistor T13 is turned on, and the signal at the first reference signal end VGH is provided to the pull-up node N9 through the turned-on thirteenth cascade transistor T13.

[0173] The output sub-circuit 104 is configured to provide the signal at the first reference signal end VGH to the cascade output end Scan_n in response to the signal at the pull-up node N9, and provide the signal at the second reference signal end VGL to the cascade output end Scan_n in response to the signal at the pull-down node N8.

[0174] The output sub-circuit 104 includes a fourteenth cascade transistor T14, a third capacitor C3, and a fifteenth cascade transistor T15.

[0175] The control end of the fourteenth cascade transistor T14 is coupled with the pull-down node N8, the first end of the fourteenth cascade transistor T14 is coupled with the second reference signal end VGL, and the second end of the fourteenth cascade transistor T14 is coupled with the cascade output end Scan_n.

[0176] When the signal at the pull-down node N8 is at a low level, the fourteenth cascade transistor T14 is turned on, and the signal at the second reference signal end VGL is provided to the cascade output end Scan_n through the turned-on fourteenth cascade transistor T14.

[0177] A first end of the third capacitor C3 is coupled to the pull-up node N9, and a second end of the third capacitor C3 is coupled to the first reference signal end VGH.

[0178] A control end of the fifteenth cascade transistor T15 is coupled to the pull-up node N9, a first end of the fifteenth cascade transistor T15 is coupled to the cascade output end Scan_n, and a second end of the fifteenth cascade transistor T15 is coupled to the first reference signal end VGH.

[0179] When the signal of the pull-up node N9 is at a low level, the fifteenth cascade transistor T15 is turned on, and the first reference signal end VGH is provided to the cascade output end Scan_n through the turned-on fifteenth cascade transistor T15.

[0180] After the shift register 001 is introduced, the first driving sub-circuit 002 will be introduced in detail.

[0181] In the embodiments of the present disclosure, the first driving sub-circuit 002 is coupled to the pull-up node N9 and the lower node N10 of the shift register 001, and the first driving sub-circuit 002 is configured to output the first driving signal from the first driving output end Rout_n in response to the signals of the pull-up node N9 and the lower node N10.

[0182] In the implementation process, the first driving sub-circuit 002 outputs the signal of the first reference signal end VGH from the first driving output end Rout_n in response to the signal of the pull-up node N9 of the shift register 001, or the first driving sub-circuit 002 outputs the signal of the second reference signal end VGL from the first driving output end Rout_n in response to the signal of the lower node N10 of the shift register 001.

[0183] Exemplarily, referring to FIGS. 5 and 6, the first driving sub-circuit 002 includes a refresh input unit 201, a refresh control unit 202, a third output unit 203, and a fourth output unit 204.

[0184] The refresh input unit 201 is coupled to the refresh control unit 202, and the refresh input unit 201 is configured to provide the signal of the row refresh control end MS to the refresh signal control end N11_N in response to the signals of the refresh gate end and the input signal end STV.

[0185] In the implementation process, when the signal of the refresh gate end N3_n-2 is at a valid level and the signal of the input signal end STV is at a valid level, the refresh input unit 201 is turned on, and the signal of the row refresh control end MS is provided to the refresh signal control end N11_N through the turned-on refresh input unit 201.

[0186] Exemplarily, referring to FIG. 5, the refresh input unit 201 includes a first drive transistor Q1 and a second drive transistor Q2.

[0187] The control terminal of the first drive transistor Q1 is coupled with a refresh gate N3_n-2, the first terminal of the first drive transistor Q1 is coupled with a row refresh control terminal MS, and the second terminal of the first drive transistor Q1 is coupled with the first terminal of the second drive transistor Q2.

[0188] In implementation, the first drive transistor Q1 is a P-type transistor, when the signal of the refresh gate N3_n-2 is at a low level, the first drive transistor Q1 is turned on, and the signal of the row refresh control terminal MS is provided to the first terminal of the second drive transistor Q2 through the turned-on first drive transistor Q1.

[0189] The control terminal of the second drive transistor Q2 is coupled with an input signal terminal STV, and the second terminal of the second drive transistor Q2 is coupled with a refresh control unit 202.

[0190] In implementation, the second drive transistor Q2 is a P-type transistor, when the signal of the input signal terminal STV is at a low level, the second drive transistor Q2 is turned on, and the signal of the first terminal of the second drive transistor Q2 is provided to a local refresh signal control terminal N11_N through the turned-on second drive transistor Q2, and further provided to the refresh control unit 202 by the local refresh signal control terminal N11_N.

[0191] The refresh control unit 202 is coupled with a third output unit 203, and the refresh control unit 202 is configured to provide the signal of a lower node N10 to a second output control node N12 in response to the signal of the local refresh signal control terminal N11_N.

[0192] In implementation, when the signal of the local refresh signal control terminal N11_N is at a valid level, the refresh control unit 202 is turned on, and the signal of the lower node N10 is provided to the second output control node N12 through the turned-on refresh control unit 202.

[0193] Exemplarily, referring to FIG. 5, the refresh control unit 202 includes a third drive transistor Q3.

[0194] The control terminal of the third drive transistor Q3 is coupled with the local refresh signal control terminal N11_N, the first terminal of the third drive transistor Q3 is coupled with the lower node N10, and the second terminal of the third drive transistor Q3 is coupled with the second output control node N12.

[0195] In implementation, the third driving transistor Q3 is a P-type transistor, when the N11_N at the control end of the local brush signal is at a low level, the third driving transistor Q3 is turned on, and the signal at the lower node N10 is provided to the second output control node N12 through the turned-on third driving transistor Q3. Specifically, refer to FIG. 5, the signal at the lower node N10 is provided to the second output control node N12.

[0196] The third output unit 203 is coupled with the refresh control unit 202, and the third output unit 203 is configured to provide the signal at the second reference signal end VGL to the first driving output end Rout_n in response to the signal at the second output control node N12.

[0197] In implementation, when the signal at the second output control node N12 is at an effective level, the third output unit 203 is turned on, and the signal at the second reference signal end VGL is provided to the first driving output end Rout_n through the turned-on third output unit 203.

[0198] The third output unit 203 includes a fourth driving transistor Q4.

[0199] The control end of the fourth driving transistor Q4 is coupled with the second end of the third driving transistor Q3, the first end of the fourth driving transistor Q4 is coupled with the signal at the second reference signal end VGL, and the second end of the fourth driving transistor Q4 is coupled with the first driving output end Rout_n.

[0200] In implementation, the fourth driving transistor Q4 is a P-type transistor, when the second end of the third driving transistor Q3 is at a low level, the fourth driving transistor Q4 is turned on, and the signal at the second reference signal end VGL is provided to the first driving output end Rout_n through the turned-on fourth driving transistor Q4, so that the first driving output end Rout_n outputs a low-level signal.

[0201] The fourth output unit 204 is coupled with the pull-up node N9, and the fourth output unit 204 is configured to provide the signal at the first reference signal end VGH to the first driving output end Rout_n in response to the signal at the pull-up node N9.

[0202] In implementation, when the signal at the pull-up node N9 is at an effective level, the fourth output unit 204 is turned on, and the signal at the first reference signal end VGH is provided to the first driving output end Rout_n through the turned-on fourth output unit 204.

[0203] The fourth output unit 204 includes a fifth driving transistor Q5.

[0204] The control end of the fifth driving transistor Q5 is coupled with the pull-up node N9, the first end of the fifth driving transistor Q5 is coupled with the signal of the first reference signal end VGH, and the second end of the fifth driving transistor Q5 is coupled with the first driving output end Rout_n.

[0205] In the implementation process, the fifth driving transistor Q5 is a P-type transistor, when the signal of the pull-up node N9 is a low level, the fifth driving transistor Q5 is turned on, and the signal of the first reference signal end VGH is provided to the first driving output end Rout_n through the turned-on fifth driving transistor Q5, so that the first driving output end Rout_n outputs a high level signal.

[0206] In addition, it also needs to be explained that the first driving sub-circuit 002 further comprises a sixth driving transistor Q6.

[0207] The control end of the sixth driving transistor Q6 is coupled with the fourth node N4 and the control end of the ninth cascade transistor T9, the first end of the sixth driving transistor Q6 is coupled with the fourth node N4 and the control end of the ninth cascade transistor T9, and the second end of the sixth driving transistor Q6 is coupled with the control end of the fourth driving transistor Q4.

[0208] In the implementation process, the sixth driving transistor Q6 is a P-type transistor, when the signal of the control end of the fourth node N4 and the ninth cascade transistor T9 is a low level, the sixth driving transistor Q6 is turned on, and the signal of the control end of the fourth node N4 and the ninth cascade transistor T9 is provided to the control end of the fourth driving transistor Q4 through the turned-on sixth driving transistor Q6, so that the signal output by the first driving output end Rout_n can be stabilized.

[0209] In addition, referring to FIG. 16, the first driving sub-circuit 002 further comprises a seventh driving transistor Q7, a first driving capacitor CC1 and a second driving capacitor CC2.

[0210] The control end of the seventh driving transistor Q7 is coupled with the local brush signal control end N11_N, the first end of the seventh driving transistor Q7 is coupled with the pull-up node N9, and the second end of the seventh driving transistor Q7 is coupled with the first end of the first driving capacitor CC1.

[0211] Exemplarily, the seventh driving transistor Q7 can be turned on under the control of the active level of the local brush signal control terminal N11_N, and can be turned off under the control of the inactive level of the local brush signal control terminal N11_N. Exemplarily, the seventh driving transistor Q7 is set as an N-type transistor, and the active level of the signal of the local brush signal control terminal N11_N is high level, and the inactive level of the signal of the local brush signal control terminal N11_N is low level. Alternatively, the seventh driving transistor Q7 is set as a P-type transistor, and the active level of the signal of the local brush signal control terminal N11_N is low level, and the inactive level of the signal of the local brush signal control terminal N11_N is high level.

[0212] Referring to FIG. 16, the seventh driving transistor Q7 is a P-type transistor, and when the signal of the local brush signal control terminal N11_N is low level, the seventh driving transistor Q7 is turned on, and the signal of the pull-up node N9 is provided to the first end of the first driving capacitor CC1 through the turned-on seventh driving transistor Q7, that is, the fourteenth node N14.

[0213] The second end of the first driving capacitor CC1 is coupled with the local brush signal control terminal N11_N.

[0214] The first end of the second driving capacitor CC2 is coupled with the second end of the seventh driving transistor Q7, and the second end of the second driving capacitor CC2 is coupled with the first reference signal terminal VGH.

[0215] It should be noted that, referring to FIG. 16, in an embodiment, the seventh driving transistor Q7 is a double-gate structure, that is, the control terminal of the seventh driving transistor Q7 includes a first control terminal and a second control terminal, and both the first control terminal and the second control terminal are coupled with the local brush signal control terminal N11_N. In this way, when the seventh driving transistor Q7 is turned off, the leakage between the pull-up node N9 and the fourteenth node N14 can be effectively prevented.

[0216] In another embodiment, the seventh driving transistor Q7 is a single-gate structure, that is, the seventh driving transistor Q7 only includes one control terminal, but in this case, the process parameters of the seventh driving transistor Q7 need to be better, so as to effectively prevent the leakage between the pull-up node N9 and the fifteenth node N15.

[0217] In addition, referring to FIG. 16, the first driving sub-circuit 002 further includes an eighth driving transistor Q8 and a ninth driving transistor Q9, and the driving control signal terminal includes a first driving control sub-signal terminal and a second driving control sub-signal terminal, the first driving control sub-signal terminal is the first driving output terminal Rout_n, and the second driving control sub-signal terminal is the second output control node N12.

[0218] The control terminal of the ninth drive transistor Q9 is coupled with the first drive output terminal Rout_n, the first terminal of the ninth drive transistor Q9 is coupled with the first terminal of the second drive capacitor CC2, and the second terminal of the ninth drive transistor Q9 is coupled with the first terminal of the eighth drive transistor Q8.

[0219] Exemplarily, the ninth drive transistor Q9 can be turned on under the control of the active level of the first drive output terminal Rout_n, and can be turned off under the control of the inactive level of the first drive output terminal Rout_n. Exemplarily, the ninth drive transistor Q9 is configured as an N-type transistor, and the active level of the signal of the first drive output terminal Rout_n is high level, and the inactive level of the signal of the first drive output terminal Rout_n is low level. Alternatively, the ninth drive transistor Q9 is configured as a P-type transistor, and the active level of the signal of the first drive output terminal Rout_n is low level, and the inactive level of the signal of the first drive output terminal Rout_n is high level.

[0220] Referring to FIG. 16, the ninth drive transistor Q9 is a P-type transistor, and when the signal of the first drive output terminal Rout_n is low level, the ninth drive transistor Q9 is turned on, and the first terminal of the second drive capacitor CC2 is communicated with the first terminal of the eighth drive transistor Q8 through the turned-on ninth drive transistor Q9.

[0221] The control terminal of the eighth drive transistor Q8 is coupled with the second output control node N12, and the second terminal of the eighth drive transistor Q8 is coupled with the first reference signal terminal VGH.

[0222] Exemplarily, the eighth drive transistor Q8 can be turned on under the control of the active level of the second output control node N12, and can be turned off under the control of the inactive level of the second output control node N12. Exemplarily, the eighth drive transistor Q8 is configured as an N-type transistor, and the active level of the signal of the second output control node N12 is high level, and the inactive level of the signal of the second output control node N12 is low level. Alternatively, the eighth drive transistor Q8 is configured as a P-type transistor, and the active level of the signal of the second output control node N12 is low level, and the inactive level of the signal of the second output control node N12 is high level.

[0223] Referring to FIG. 16, the eighth drive transistor Q8 is a P-type transistor, and when the signal of the second output control node N12 is low level, the eighth drive transistor Q8 is turned on, and the signal of the first reference signal terminal VGH is provided to the second terminal of the ninth drive transistor Q9 through the turned-on eighth drive transistor Q8.

[0224] The eighth drive transistor Q8 and the ninth drive transistor Q9 can make the high level of the fourteenth node N14 more stable. In the implementation process, when the second output control node N12 is low, the eighth drive transistor Q8 is turned on, and when the first drive output end Rout_n is low, the ninth drive transistor Q9 is turned on, so that the level of the fourteenth node N14 is pulled up to the first reference signal end VGH, and the fifth drive transistor Q5 is cut off, which can prevent the influence of the leakage of the fifth drive transistor Q5 on the first drive output end Rout_n, thereby improving the stability of the first drive output end Rout_n. It should be noted that if the ninth drive transistor Q9 is removed, the eighth drive transistor Q8 can also realize the voltage stabilizing effect on the fourteenth node N14 under the action of the second output control node N12.

[0225] In addition, referring to FIG. 16, the first drive sub-circuit 002 further includes:

[0226] The tenth drive transistor Q10 and the eleventh drive transistor Q11, wherein the third drive control signal end includes a first sub-drive control signal end N5_N-1 and a second sub-drive control signal end N5_N-8, the first sub-drive control signal end N5_N-1 is a fifth node N5 in a previous stage shift register unit which is cascaded with the shift register unit of the current stage, and the second sub-drive control signal end N5_N-8 is a fifth node N5 in a previous eight-stage shift register unit which is cascaded with the shift register unit of the current stage.

[0227] It should be noted that since the number of the row refresh control end MS is one, the row refresh control end MS is connected with the shift register unit corresponding to each row of sub-pixels. In order to ensure that the row refresh control end MS can provide refresh signals to the local refresh signal control end N11_N of different rows in time, the effective signals of the first sub-drive control signal end N5_N-1 and the second sub-drive control signal end N5_N-8 are used to control the time length of the refresh signals provided by the row refresh control end MS to the local refresh signal control end N11_N of the current row. The tenth drive transistor Q10 and the eleventh drive transistor Q11 are used to reset the local refresh signal control end N11_N. In order to ensure the effectiveness of the refresh signals, the time difference between the effective signals of the first sub-drive control signal end N5_N-1 and the second sub-drive control signal end N5_N-8 is set to correspond to the phase difference between the second drive signal of the Nth shift register unit and the first drive signal of the N-nth shift register unit.

[0228] It needs to be supplemented here that the local brush signal control end N11_N in the first n-stage shift register which is cascaded with the shift register of the current stage is the same signal end as the local brush signal control end N11_N in the first n-stage shift register. The signal of the local brush signal control end N11_N in the first n-stage shift register will be affected by the second driving transistor Q1, the second driving transistor Q2 and the row refresh control end MS in the first n-stage shift register, which will not be described in detail here.

[0229] Referring to FIG. 16, the control end of the tenth driving transistor Q10 is coupled with the first sub-driving control signal end N5_N-1, the first end of the tenth driving transistor Q10 is coupled with the local brush signal control end N11_N, and the second end of the tenth driving transistor Q10 is coupled with the first end of the eleventh driving transistor Q11.

[0230] Exemplarily, the tenth driving transistor Q10 can be turned on under the control of the effective level of the first sub-driving control signal end N5_N-1, and can be turned off under the control of the ineffective level of the first sub-driving control signal end N5_N-1. Exemplarily, the tenth driving transistor Q10 is set as an N-type transistor, and the effective level of the signal of the first sub-driving control signal end N5_N-1 is high level, and the ineffective level of the signal of the first sub-driving control signal end N5_N-1 is low level. Alternatively, the tenth driving transistor Q10 is set as a P-type transistor, and the effective level of the signal of the first sub-driving control signal end N5_N-1 is low level, and the ineffective level of the signal of the first sub-driving control signal end N5_N-1 is high level.

[0231] In the implementation process, the tenth driving transistor Q10 is a P-type transistor. When the signal of the first sub-driving control signal end N5_N-1 is low level, the tenth driving transistor Q10 is turned on, and the signal of the first end of the eleventh driving transistor Q11 is provided to the local brush signal control end N11_N through the turned-on tenth driving transistor Q10.

[0232] Referring to FIG. 16, the control end of the eleventh driving transistor Q11 is coupled with the second sub-driving control signal end N5_N-8, and the second end of the eleventh driving transistor Q11 is coupled with the second reference signal end VGL.

[0233] Exemplarily, the eleventh drive transistor Q11 can be turned on under the control of the active level of the second sub-drive control signal end N5_N-8, and can be turned off under the control of the inactive level of the second sub-drive control signal end N5_N-8. Exemplarily, the eleventh drive transistor Q11 is configured as an N-type transistor, and the active level of the signal of the second sub-drive control signal end N5_N-8 is high level, and the inactive level of the signal of the second sub-drive control signal end N5_N-8 is low level. Alternatively, the eleventh drive transistor Q11 is configured as a P-type transistor, and the active level of the signal of the second sub-drive control signal end N5_N-8 is low level, and the inactive level of the signal of the second sub-drive control signal end N5_N-8 is high level.

[0234] Referring to FIG. 16, the eleventh transistor L11 is a P-type transistor, and when the signal of the second sub-drive control signal end N5_N-8 is low level, the eleventh drive transistor Q11 is turned on, and the signal of the second reference signal end VGL is provided to the second end of the tenth drive transistor Q10 through the turned-on eleventh drive transistor Q11, and then provided to the local brush signal control end N11_N.

[0235] In the embodiment of the present disclosure, the signal output by the first drive output end Rout_n of the first drive sub-circuit 002 can be provided to the first reset signal end NReset of the pixel drive circuit, that is, used to control whether the second switch transistor m2 in FIG. 1 or the third switch transistor M3 in FIG. 3 is turned on or not. The signal of the first scan signal end NGate of the pixel drive circuit is generated by the second drive sub-circuit 003.

[0236] Based on this, after introducing the shift register 001 and the first drive sub-circuit 002, the second drive sub-circuit 003 will be introduced in detail below.

[0237] The second drive sub-circuit 003 is coupled with the pull-up node N9, the lower connection node N10, the local brush signal control end N11_N-n and the second drive output end Nout_n, and the second drive sub-circuit 003 is configured to make the second drive output end Nout_n output a second drive signal in response to the signals of the pull-up node N9, the lower connection node N10 and the local brush signal control end N11_N-n.

[0238] Exemplarily, the second drive signal has the same waveform and phase as the first drive signal.

[0239] Considering the actual situation of the first scan signal end NGate and the first reset signal end NReset, that is, the first drive signal output by the first drive output end of the first drive sub-circuit 002 has the same waveform and phase as the second drive signal output by the second drive output end Nout_n of the second drive sub-circuit 003.

[0240] In implementation, the second driving sub-circuit 003 outputs the signal of the first reference signal terminal VGH at the second driving output terminal Nout_n in response to the signal of the pull-up node N9 of the shift register 001, or the second driving sub-circuit 003 outputs the signal of the second reference signal terminal VGL at the second driving output terminal Nout_n in response to the signal of the pull-down node N8 and the signal of the brush signal control terminal N11_N-n.

[0241] Referring to FIG. 7, the second driving sub-circuit 003 includes a driving control unit 301, a first output unit 302 and a second output unit 303.

[0242] The driving control unit 301 is coupled with the lower connection node N10, the brush signal control terminal N11_N-n and the first output control node N13, and is configured to provide the signal of the lower connection node N10 to the first output control node N13 in response to the signal of the brush signal control terminal N11_N-n.

[0243] In implementation, when the signal of the brush signal control terminal N11_N-n is at an effective level, the driving control unit 301 is turned on, and the signal of the lower connection node N10 is provided to the first output control node N13 through the turned-on driving control unit 301.

[0244] Exemplarily, referring to FIG. 5, the driving control unit 301 includes a first transistor L1.

[0245] For the convenience of description, the intersection of the second end of the first transistor L1 and the control terminal of the second transistor L2 is referred to as the first output control node N13 in the embodiments of the present disclosure.

[0246] The control terminal of the first transistor L1 is coupled with the brush signal control terminal N11_N-n, the first end of the first transistor L1 is coupled with the lower connection node N10, and the second end of the first transistor L1 is coupled with the first output control node N13.

[0247] Exemplarily, the first transistor L1 can be turned on under the control of the effective level of the brush signal control terminal N11_N-n, and can be turned off under the control of the ineffective level of the brush signal control terminal N11_N-n. Exemplarily, the first transistor L1 is set as an N-type transistor, and the effective level of the signal of the brush signal control terminal N11_N-n is a high level, and the ineffective level of the signal of the brush signal control terminal N11_N-n is a low level. Alternatively, the first transistor L1 is set as a P-type transistor, and the effective level of the signal of the brush signal control terminal N11_N-n is a low level, and the ineffective level of the signal of the brush signal control terminal N11_N-n is a high level.

[0248] Referring to FIG. 5, the first transistor L1 is a P-type transistor, and when the signal of the brush signal control end N11_N-n is at a low level, the first transistor L1 is turned on, and the signal of the lower connection node N10 is provided to the first output control node N13 through the turned-on first transistor L1.

[0249] The second output unit 303 is coupled with the first output control node N13, the second reference signal end VGL, and the second driving output end Nout_n, and the second output unit 303 is configured to provide the signal of the second reference signal end VGL to the second driving output end Nout_n in response to the signal of the first output control node N13.

[0250] In the implementation process, when the signal of the first output control node N13 is at a valid level, the second output unit 303 is turned on, and the signal of the second reference signal end VGL is provided to the second driving output end Nout_n through the turned-on second output unit 303.

[0251] Referring to FIG. 5, the second output unit 303 includes a second transistor L2.

[0252] The control end of the second transistor L2 is coupled with the first output control node N13, the first end of the second transistor L2 is coupled with the second driving output end Nout_n, and the second end of the second transistor L2 is coupled with the second reference signal end VGL.

[0253] Exemplarily, the second transistor L2 can be turned on under the control of the valid level of the first output control node N13, and can be turned off under the control of the invalid level of the first output control node N13. Exemplarily, the second transistor L2 is set as an N-type transistor, and the valid level of the signal of the first output control node N13 is a high level, and the invalid level of the signal of the first output control node N13 is a low level. Alternatively, the second transistor L2 is set as a P-type transistor, and the valid level of the signal of the first output control node N13 is a low level, and the invalid level of the signal of the first output control node N13 is a high level.

[0254] Referring to FIG. 5, the second transistor L2 is a P-type transistor, and when the signal of the first output control node N13 is at a low level, the second transistor L2 is turned on, and the signal of the second reference signal end VGL is provided to the second driving output end Nout_n through the turned-on second transistor L2.

[0255] In addition, referring to FIG. 8, the second driving sub-circuit 003 further includes a first control unit 304, wherein the first control unit 304 is coupled with the first output control node N13 and the fourth node N4 in the shift register.

[0256] The first control unit 304 is configured to provide the signal of the fourth node N4 to the first output control node N13 in response to the signal of the fourth node N4 in the shift register.

[0257] In implementation, when the signal of the fourth node N4 in the shift register is at the active level, the first control unit 304 is turned on, and the signal of the fourth node N4 is provided to the first output control node N13 through the turned-on first control unit 304.

[0258] Referring to FIG. 5, the first control unit 304 comprises a third transistor L3.

[0259] The control end of the third transistor L3 is coupled with the fourth node N4, the first end of the third transistor L3 is coupled with the fourth node N4, and the second end of the third transistor L3 is coupled with the first output control node N13.

[0260] Illustratively, the third transistor L3 can be turned on under the control of the active level of the fourth node N4, and can be turned off under the control of the inactive level of the fourth node N4. Illustratively, the third transistor L3 is set as an N-type transistor, and the active level of the signal of the fourth node N4 is a high level, and the inactive level of the signal of the fourth node N4 is a low level. Alternatively, the third transistor L3 is set as a P-type transistor, and the active level of the signal of the fourth node N4 and the control end of the ninth cascade transistor T9 is a low level, and the inactive level of the signal of the fourth node N4 and the control end of the ninth cascade transistor T9 is a high level.

[0261] Referring to FIG. 5, the third transistor L3 is a P-type transistor, and when the signal of the fourth node N4, that is, the control end of the ninth cascade transistor T9 is at a low level, the third transistor L3 is turned on, and the signal of the fourth node N4 is provided to the first output control node N13 through the turned-on third transistor L3.

[0262] The first output unit 302 is coupled with the pull-up node N9, the first reference signal end VGH, and the second driving output end Nout_n, and the first output unit 302 is configured to provide the signal of the first reference signal end VGH to the second driving output end Nout_n in response to the signal of the pull-up node N9.

[0263] In implementation, when the signal of the pull-up node N9 is at the active level, the first output unit 302 is turned on, and the signal of the first reference signal end VGH is provided to the second driving output end Nout_n through the turned-on first output unit 302.

[0264] Referring to FIG. 5, the first output unit 302 comprises a fourth transistor L4.

[0265] The control end of the fourth transistor L4 is coupled with the pull-up node N9, the first end of the fourth transistor L4 is coupled with the first reference signal end VGH, and the second end of the fourth transistor L4 is coupled with the second driving output end Nout_n.

[0266] Exemplarily, the fourth transistor L4 can be turned on under the control of the effective level of the pull-up node N9, and can be turned off under the control of the ineffective level of the pull-up node N9. Exemplarily, the fourth transistor L4 is set as an N-type transistor, and the effective level of the signal of the pull-up node N9 is high level and the ineffective level of the signal of the pull-up node N9 is low level. Alternatively, the fourth transistor L4 is set as a P-type transistor, and the effective level of the signal of the pull-up node N9 is low level and the ineffective level of the signal of the pull-up node N9 is high level.

[0267] Referring to FIG. 5, the fourth transistor L4 is a P-type transistor, and when the signal of the pull-up node N9 is low level, the fourth transistor L4 is turned on, and the signal of the first reference signal end VGH is provided to the second driving output end Nout_n through the turned-on fourth transistor L4.

[0268] In addition, referring to FIG. 9, the second driving sub-circuit 003 further includes a second control unit 305, wherein the second control unit 305 is coupled between the pull-up node N9 and the first output unit 302.

[0269] The second control unit 305 is configured to turn on the pull-up node N9 and the first output unit 302 in response to the signal of the local brush signal control end N11_N-n.

[0270] In the implementation process, when the signal of the local brush signal control end N11_N-n is the effective level, the second control unit 305 is turned on, and the pull-up node N9 is turned on through the turned-on second control unit 305 and the first output unit 302.

[0271] Referring to FIG. 10, the second control unit 305 includes a fifth transistor L5, a first capacitor c1 and a second capacitor c2.

[0272] The control end of the fifth transistor L5 is coupled with the local brush signal control end N11_N-n, the first end of the fifth transistor L5 is coupled with the pull-up node N9, and the second end of the fifth transistor L5 is coupled with the first end of the first capacitor c1.

[0273] Exemplarily, the fifth transistor L5 can be turned on under the control of the active level of the signal of the local brush signal control terminal N11_N-n, and can be turned off under the control of the inactive level of the signal of the local brush signal control terminal N11_N-n. Exemplarily, the fifth transistor L5 is configured as an N-type transistor, and the active level of the signal of the local brush signal control terminal N11_N-n is high level, and the inactive level of the signal of the local brush signal control terminal N11_N-n is low level. Alternatively, the fifth transistor L5 is configured as a P-type transistor, and the active level of the signal of the local brush signal control terminal N11_N-n is low level, and the inactive level of the signal of the local brush signal control terminal N11_N-n is high level.

[0274] Referring to FIG. 10, the fifth transistor L5 is a P-type transistor, and when the signal of the local brush signal control terminal N11_N-n is low level, the fifth transistor L5 is turned on, and the signal of the pull-up node N9 is provided to the first output unit 302 through the turned-on fifth transistor L5.

[0275] The first end of the first capacitor c1 is coupled with the second end of the fifth transistor L5, and the second end of the first capacitor c1 is coupled with the local brush signal control terminal N11_N-n.

[0276] The first end of the second capacitor c2 is coupled with the second end of the fifth transistor L5, and the second end of the second capacitor c2 is coupled with the first reference signal terminal VGH.

[0277] It should be noted that, referring to FIG. 10, in an embodiment, the fifth transistor L5 is a double-gate structure, that is, the control terminal of the fifth transistor L5 includes a first control terminal and a second control terminal, and the first control terminal and the second control terminal are both coupled with the local brush signal control terminal N11_N-n. In this way, when the fifth transistor L5 is turned off, the leakage between the pull-up node N9 and the fifteenth node N15 can be effectively prevented.

[0278] In another embodiment, referring to FIG. 13, the fifth transistor L5 is a single-gate structure, that is, the fifth transistor L5 only includes one control terminal, but in this case, the process parameters of the fifth transistor L5 need to be better, and the leakage between the pull-up node N9 and the fifteenth node N15 can be effectively prevented.

[0279] In addition, referring to FIG. 11, the second driving sub-circuit 003 further includes a third control unit 306, wherein the third control unit 306 is coupled with the local brush signal control terminal N11_N-n.

[0280] The third control unit 306 is configured to provide the signal of the second reference signal terminal VGL to the local brush signal control terminal N11_N-n in response to the signal of the reset control signal terminal Eout_N.

[0281] In implementation, when the signal of the reset control signal terminal Eout_N is at a valid level, the third control unit 306 is turned on, and the signal of the second reference signal terminal VGL is provided to the local brush signal control terminal N11_N-n through the turned-on third control unit 306.

[0282] Referring to FIG. 12, the third control unit 306 comprises a sixth transistor L6.

[0283] The control terminal of the sixth transistor L6 is coupled with the reset control signal terminal Eout_N, the first terminal of the sixth transistor L6 is coupled with the local brush signal control terminal N11_N-n, and the second terminal of the sixth transistor L6 is coupled with the second reference signal terminal VGL.

[0284] Exemplarily, the sixth transistor L6 can be turned on under the control of the valid level of the reset control signal terminal Eout_N, and can be turned off under the control of the invalid level of the reset control signal terminal Eout_N. Exemplarily, the sixth transistor L6 is set as an N-type transistor, and the valid level of the signal of the reset control signal terminal Eout_N is a high level, and the invalid level of the signal of the reset control signal terminal Eout_N is a low level. Alternatively, the sixth transistor L6 is set as a P-type transistor, and the valid level of the signal of the reset control signal terminal Eout_N is a low level, and the invalid level of the signal of the reset control signal terminal Eout_N is a high level.

[0285] Referring to FIG. 12, the sixth transistor L6 is a P-type transistor, and when the signal of the reset control signal terminal Eout_N is at a low level, the sixth transistor L6 is turned on, and the signal of the second reference signal terminal VGL is provided to the local brush signal control terminal N11_N-n through the turned-on sixth transistor L6.

[0286] It should be noted that the signal of the reset control signal terminal Eout_N is generally valid after the scanning of the current row of gate lines, that is, the reset of row scanning is realized through the sixth transistor L6.

[0287] In addition, referring to FIG. 13, the second driving sub-circuit 003 further comprises a fourth control unit 307, wherein the fourth control unit 307 is coupled with the control terminal of the fourth transistor L4.

[0288] The fourth control unit 307 is configured to provide the signal of the first reference signal terminal VGH to the control terminal of the fourth transistor L4 in response to the signal of the second control signal terminal.

[0289] In implementation, when the signal of the second control signal terminal is at a valid level, the fourth control unit 307 is turned on, and the signal of the first reference signal terminal VGH is provided to the control terminal of the fourth transistor L4 through the turned-on fourth control unit 307.

[0290] In one embodiment, referring to FIG. 12, the fourth control unit 307 comprises a seventh transistor L7, and the second control signal terminal is the first output control node N13.

[0291] The control terminal of the seventh transistor L7 is coupled with the second control signal terminal, the first terminal of the seventh transistor L7 is coupled with the control terminal of the fourth transistor L4, and the second terminal of the seventh transistor L7 is coupled with the first reference signal terminal VGH.

[0292] For example, the seventh transistor L7 can be turned on under the control of the active level of the first output control node N13, and can be turned off under the control of the inactive level of the first output control node N13. For example, the seventh transistor L7 is configured as an N-type transistor, and the active level of the signal of the first output control node N13 is high, and the inactive level of the signal of the first output control node N13 is low. Alternatively, the seventh transistor L7 is configured as a P-type transistor, and the active level of the signal of the first output control node N13 is low, and the inactive level of the signal of the first output control node N13 is high.

[0293] Referring to FIG. 12, the seventh transistor L7 is a P-type transistor, and when the signal of the first output control node N13 is low, the seventh transistor L7 is turned on, and the signal of the first reference signal terminal VGH is provided to the control terminal of the fourth transistor L4 through the turned-on seventh transistor L7.

[0294] In the implementation process, when the first output control node N13 is low, the seventh transistor L7 is turned on, and the signal of the first reference signal terminal VGH is provided to the fifteenth node N15 through the turned-on seventh transistor L7, so as to pull up the level of the fifteenth node N15 to the first reference signal terminal VGH, and the fourth transistor L4 is turned off, thereby preventing the influence of the leakage current of the fourth transistor L4 on the second drive output terminal Nout_n, and improving the stability of the second drive output terminal Nout_n.

[0295] In another embodiment, referring to FIG. 14, the fourth control unit 307 comprises an eighth transistor L8 and a ninth transistor L9, and the second control signal terminal comprises a first control sub-signal terminal and a second control sub-signal terminal, the first control sub-signal terminal is the second drive output terminal Nout_n, and the second control sub-signal terminal is the first output control node N13.

[0296] The control terminal of the ninth transistor L9 is coupled with the first control sub-signal terminal, the first terminal of the ninth transistor L9 is coupled with the first terminal of the eighth transistor L8, and the second terminal of the ninth transistor L9 is coupled with the control terminal of the fourth transistor L4.

[0297] Exemplarily, referring to FIG. 14, the first control sub-signal end is the second driving output end Nout_n, and the ninth transistor L9 can be turned on under the control of the active level of the signal of the first control sub-signal end, and can be turned off under the control of the inactive level of the signal of the first control sub-signal end. Exemplarily, the ninth transistor L9 is set as an N-type transistor, and the active level of the signal of the first control sub-signal end is high level, and the inactive level of the signal of the first control sub-signal end is low level. Alternatively, the ninth transistor L9 is set as a P-type transistor, and the active level of the signal of the first control sub-signal end is low level, and the inactive level of the signal of the first control sub-signal end is high level.

[0298] Referring to FIG. 14, the ninth transistor L9 is a P-type transistor, and when the signal of the second driving output end Nout_n is low level, the ninth transistor L9 is turned on, and the control end of the fourth transistor L4 is communicated with the first end of the eighth transistor L8 through the turned-on ninth transistor L9.

[0299] The control end of the eighth transistor L8 is coupled with the second control sub-signal end, and the second end of the eighth transistor L8 is coupled with the first reference signal end VGH.

[0300] Exemplarily, referring to FIG. 14, the first control sub-signal end is the first output control node N13, and the eighth transistor L8 can be turned on under the control of the active level of the signal of the first output control node N13, and can be turned off under the control of the inactive level of the signal of the first output control node N13. Exemplarily, the eighth transistor L8 is set as an N-type transistor, and the active level of the signal of the first output control node N13 is high level, and the inactive level of the signal of the first output control node N13 is low level. Alternatively, the eighth transistor L8 is set as a P-type transistor, and the active level of the signal of the first output control node N13 is low level, and the inactive level of the signal of the first output control node N13 is high level.

[0301] Referring to FIG. 14, the eighth transistor L8 is a P-type transistor, and when the signal of the first output control node N13 is low level, the eighth transistor L8 is turned on, and the signal of the first reference signal end VGH is provided to the first end of the ninth transistor L9 through the turned-on eighth transistor L8.

[0302] The eighth transistor L8 and the ninth transistor L9 can make the high level of the fifteenth node N15 more stable. In the implementation process, when the first output control node N13 is at a low level, the eighth transistor L8 is turned on, and when the second driving output end Nout_n is at a low level, the ninth transistor L9 is turned on, so as to pull up the level of the fifteenth node N15 to the first reference signal end VGH, and the fourth transistor L4 is cut off, thereby preventing the influence of the leakage of the fourth transistor L4 on the second driving output end Nout_n, and improving the stability of the second driving output end Nout_n. It should be noted that if the ninth transistor L9 is removed, the eighth transistor L8 can also realize the voltage stabilizing effect on the fifteenth node N15 under the action of the first output control node N13.

[0303] In addition, referring to FIG. 15, the second driving sub-circuit 003 further includes a fifth control unit 308, wherein the fifth control unit 308 is coupled with the local brush signal control end N11_N-n, the third control signal end N5_N-1, the fourth control signal end N5_N-8, and the second reference signal end VGL.

[0304] The fifth control unit 308 is configured to provide the signal of the second reference signal end VGL to the local brush signal control end N11_N-n in response to the signals of the third control signal end N5_N-1 and the fourth control signal end.

[0305] In the implementation process, when the signals of the third control signal end N5_N-1 and the fourth control signal end N5_N-8 are at an effective level, the fifth control unit 308 is turned on, and the signal of the second reference signal end VGL is provided to the local brush signal control end N11_N-n through the turned-on fifth control unit 308.

[0306] Referring to FIG. 16, the fifth control unit 308 further includes a tenth transistor L10 and an eleventh transistor L11, wherein the third control signal end N5_N-1 and the fourth control signal end N5_N-8 have a phase difference between the effective signals thereof. The phase difference between the effective signals of the third control signal end N5_N-1 and the fourth control signal end N5_N-8 corresponds to the phase difference between the second driving signal of the Nth shift register unit and the first driving signal of the N-nth shift register unit.

[0307] It should be noted that, since the number of row refresh control ends MS is one, the row refresh control end MS is connected with the shift register unit corresponding to each row of sub-pixels, in order to ensure that the row refresh control end MS can provide refresh signals to the local refresh signal control end N11_N-n of different rows in time, the effective signals of the third control signal end N5_N-1 and the fourth control signal end N5_N-8 are used to control the time length of the refresh signal provided by the row refresh control end MS to the local refresh signal control end N11_N-n, that is, the tenth transistor L10 and the eleventh transistor L11 are used to reset the local refresh signal control end N11_N-n, and in order to ensure the effectiveness of the refresh signal, the phase difference between the effective signals of the third control signal end N5_N-1 and the fourth control signal end N5_N-8 is set to correspond to the phase difference between the second driving signal of the Nth shift register unit and the first driving signal of the N-nth shift register unit.

[0308] Referring to FIG. 16, the control end of the tenth transistor L10 is coupled with the third control signal end N5_N-1, the first end of the tenth transistor L10 is coupled with the local refresh signal control end N11_N-n, and the second end of the tenth transistor L10 is coupled with the first end of the eleventh transistor L11.

[0309] Exemplarily, the tenth transistor L10 can be turned on under the control of the effective level of the third control signal end N5_N-1, and can be turned off under the control of the invalid level of the third control signal end N5_N-1. Exemplarily, the tenth transistor L10 is set as an N-type transistor, and the effective level of the signal of the third control signal end N5_N-1 is high level, and the invalid level of the signal of the third control signal end N5_N-1 is low level. Alternatively, the tenth transistor L10 is set as a P-type transistor, and the effective level of the signal of the third control signal end N5_N-1 is low level, and the invalid level of the signal of the third control signal end N5_N-1 is high level.

[0310] In the implementation process, the tenth transistor L10 is a P-type transistor, when the signal of the third control signal end N5_N-1 is low level, the tenth transistor L10 is turned on, and the signal of the first end of the eleventh transistor L11 is provided to the local refresh signal control end N11_N-n through the turned-on tenth transistor L10.

[0311] Referring to FIG. 16, the control end of the eleventh transistor L11 is coupled with the fourth control signal end N5_N-8, and the second end of the eleventh transistor L11 is coupled with the second reference signal end VGL.

[0312] Exemplarily, the eleventh transistor L11 can be turned on under the control of the active level of the fourth control signal end N5_N-8, and can be turned off under the control of the inactive level of the fourth control signal end N5_N-8. Exemplarily, the eleventh transistor L11 is set as an N-type transistor, and the active level of the signal of the fourth control signal end N5_N-8 is high level, and the inactive level of the signal of the fourth control signal end N5_N-8 is low level. Alternatively, the eleventh transistor L11 is set as a P-type transistor, and the active level of the signal of the fourth control signal end N5_N-8 is low level, and the inactive level of the signal of the fourth control signal end N5_N-8 is high level.

[0313] Referring to FIG. 16, the eleventh transistor L11 is a P-type transistor, and when the signal of the second sub control signal end N5_N-8 is low level, the eleventh transistor L11 is turned on, and the signal of the second reference signal end VGL is provided to the second end of the tenth transistor L10 through the turned-on eleventh transistor L11, and then provided to the brush signal control end N11_N-n.

[0314] In an embodiment, the first reference signal end VGH includes a plurality of different sub reference signal ends. Referring to FIG. 17, the first reference signal end VGH can be realized by different signal ends, i.e., the first reference signal end VGH includes a first sub reference signal end VGH1, a second sub reference signal end VGH2 and a third sub reference signal end VGH3.

[0315] Similarly, the second reference signal end includes a plurality of different reference sub signal ends. Referring to FIG. 12, the second reference signal end includes a first reference sub signal end VGL1, a second reference sub signal end VGL2 and a third reference sub signal end VGL3. In this way, the arrangement of the signal ends can be saved, so as to optimize the layout and wiring, and facilitate the formation of narrow frame.

[0316] In another embodiment, referring to FIG. 17 and FIG. 18, the above-mentioned first reference signal end VGH is also respectively set as different signal ends, and the second reference signal end VGL can be respectively set as different signal ends. In this way, not only the respective signal ends are independent of each other, so as to effectively ensure the normal work of each part of the sub-circuit, but also the voltage values between the respective signal ends can be set according to the requirements, so as to make the design of the circuit more flexible.

[0317] In addition, since a plurality of clock signal ends are provided in the above-mentioned shift register unit, the clock signal ends connected by different transistors can be set as independent signal ends in the implementation process. On the one hand, the influence caused by the connection of different transistors to the same clock signal end can be avoided.

[0318] Referring to FIG. 18 and FIG. 19, the control terminals of the first cascode transistor T1 and the second cascode transistor T2 are connected to the clock signal terminal CK1, the control terminal of the third cascode transistor T3 is connected to the clock signal terminal CK2, the first terminal of the seventh cascode transistor T7 is connected to the clock signal terminal CK2, the first terminal of the ninth cascode transistor T9 is connected to the clock signal terminal CB, and the first terminal of the eleventh cascode transistor T11 is connected to the clock signal terminal CB.

[0319] Referring to FIG. 19, it is to be noted that the clock signal terminals CK1 and CK2 in the shift register units corresponding to different rows can be connected to different clock input terminals outside, which will not be described here.

[0320] On the other hand, setting the clock signal terminals corresponding to different transistors to different values can save power consumption to a certain extent. For example, after the 2 clock signal terminals corresponding to the shift register unit are copied into 4 clock signal terminals, the shift register unit can save about 30% to 50% of power consumption.

[0321] The power consumption calculation formula of the dynamic signal is: f is the signal frequency, C is the total capacitance, and V is the jump voltage.

[0322] For 2CK:

[0323] For 4CK, C(4CK)≈0.7C(2CK), V(4CK)=V(2CK), ideally C(4CK)=0.5C(2CK), actually complex affected by layout environment, about 0.6-0.8, calculated with 0.7. Then:

[0324] Referring to FIG. 20, the main working process of the lower shift register unit will be described below in combination with FIG. 5.

[0325] Among them, 0 represents the low level of the signal, and 1 represents the high level of the signal.

[0326] Timing T1 stage: STV=0, CK=0, CB=1, MS=0

[0327] When the first clock signal terminal CK is at low level, the first cascade transistor T1, the second cascade transistor T2 and the third cascade transistor T3 are turned on, the signal of the input signal terminal STV at low level is provided to the first node N1 and the second node N2 through the turned-on first cascade transistor T1 and the second cascade transistor T2, the low level of the second reference signal terminal VGL is provided to the third node N3 through the turned-on third cascade transistor T3, the low level of the second reference signal terminal VGL turns on the fourth cascade transistor T4, the fifth cascade transistor T5 and the tenth cascade transistor T10, the fourth node N4 and the pull-down node N8 are at low level, the fourteenth cascade transistor T14 is turned on, the second reference signal terminal VGL is provided to the cascade output terminal Scan_n through the turned-on fourteenth cascade transistor T14, so that the Scan_n outputs low level signal; the low level of the fourth node N4 turns on the ninth cascade transistor T9, the low level of the first node N1 turns on the seventh cascade transistor T7, the low level of the first clock signal terminal CK makes the third node N3 and the sixth node N6 at low level through the seventh cascade transistor T7 and the tenth cascade transistor T10, the eleventh cascade transistor T11 is turned on, the high level of the second clock signal terminal CB makes the seventh node N7 at high level, the low level of the first node N1 turns on the thirteenth cascade transistor T13, the high level signal of the first reference signal terminal VGH is written to the ninth node N9 through the turned-on thirteenth cascade transistor T13, and the fifteenth cascade transistor T15 is cut off.

[0328] The low level of the fourth node N4 turns on the sixth drive transistor Q6, and further makes the second output control node N12 at low level, the fourth drive transistor Q4 is turned on under the action of the low level of the second output control node N12, the high level of the ninth node N9 makes the fifth drive transistor Q5 cut off, and the second reference signal terminal VGL is provided to the first drive output terminal Rout_n through the turned-on fourth drive transistor Q4, so that the Rout_n outputs low level signal.

[0329] The low level of the fourth node N4 turns on the third transistor L3, the first output control node N13 is at low level, the second transistor L2 is turned on, the high level of the ninth node N9 makes the fourth transistor L4 cut off, and the second reference signal terminal VGL is provided to the second drive output terminal Nout_n through the turned-on second transistor L2, so that the second drive output terminal Nout_n outputs low level signal.

[0330] Timing T2 stage: STV = 0, CK = 1, CB = 0, MS = 0, Scan_n-1 = 0, N3_n-2 = 0

[0331] The high level of the first clock signal terminal CK makes the first cascade transistor T1 and the second cascade transistor T2 be off, the first node N1 is low, and the seventh cascade transistor T7 is turned on. The high level of the first clock signal terminal CK makes the third cascade transistor T3 be off, and the third node N3 and the sixth node N6 are written into high level through the seventh cascade transistor T7 and the tenth cascade transistor T10. The third node N3 and the sixth node N6 are written into high level, the eleventh cascade transistor T11 is off, the seventh node N7 maintains the high level of the last stage, the second clock signal terminal CB is low, the twelfth cascade transistor T12 is turned on, the ninth node N9 is maintained as high, and the fifteenth cascade transistor T15 is off. At the same time, the fourth node N4 is low, the ninth cascade transistor T9 is turned on, the second clock signal terminal CB writes low voltage into the fifth node N5, the fourth node N4 is pulled to a lower voltage (5-10V lower than VGL) through the first capacitor C1, the sixth cascade transistor T6 is turned on, low voltage is written into the node N8, the fourteenth cascade transistor T14 is fully opened, and the second reference signal terminal VGL is provided to the cascade output terminal Scan_n through the turned-on fourteenth cascade transistor T14, so that the cascade output terminal Scan_n outputs a low level signal.

[0332] The low level of the fourth node N4 makes the sixth drive transistor Q6 be turned on, and the second output control node N12 is low. The fourth drive transistor Q4 is turned on under the action of the low level of the second output control node N12. The high level of the ninth node N9 makes the fifth drive transistor Q5 be off. The second reference signal terminal VGL is provided to the first drive output terminal Rout_n through the turned-on fourth drive transistor Q4, so that the Rout_n outputs a low level signal.

[0333] The low level of the fourth node N4 makes the third transistor L3 be turned on, and the first output control node N13 is low. The second transistor L2 is turned on, and the high level of the ninth node N9 makes the fourth transistor L4 be off. The second reference signal terminal VGL is provided to the second drive output terminal Nout_n through the turned-on second transistor L2, so that the second drive output terminal Nout_n outputs a low level signal.

[0334] When Scan_n-1 and N3_n-2 are both low, the first drive transistor Q1 and the second drive transistor Q2 are turned on. Through the simultaneous opening of the first drive transistor Q1 and the second drive transistor Q2, 1 minimum gate time H (=n*Hsync, n=1-100, generally 2) can be obtained. Thus, when the refresh signal MS is low, the low level of the refresh signal MS in the row refresh control line is written into the refresh signal control terminal N11_N.

[0335] Timing T3 stage: STV=1, CK=0, CB=1, MS=0, Scan_n-1=1, N3_n-2=1

[0336] When the input signal end STV is high level and the first clock signal end CK is low level, the first cascade transistor T1 and the second cascade transistor T2 are turned on, the first node N1 and the second node N2 are written to high level, the second reference signal end VGL makes the fourth cascade transistor T4 and the fifth cascade transistor T5 conduct, the pull-down node N8 and the fourth node N4 are high level, and the fourteenth cascade transistor T14 is cut off; the fourth node N4 is high level, the ninth cascade transistor T9 is cut off, the first node N1 is high level, the seventh cascade transistor T7 is cut off, the second cascade transistor T2 and the third cascade transistor T3 are turned on, the second reference signal end VGL writes the third node N3 to low level through the turned-on third cascade transistor T3, the second reference signal end VGL is low level, the tenth cascade transistor T10 is turned on, the sixth node N6 is written to low level, the eleventh cascade transistor T11 is turned on, the second clock signal end CB writes high level to the seventh node N7, the twelfth cascade transistor T12 is cut off, the first node N1 is high, the thirteenth cascade transistor T13 is cut off, the ninth node N9 maintains high level, ensures that the fifteenth cascade transistor T15 is cut off, and the cascade output end Scan_n maintains the output state of the last stage. Similarly, the first driving output end Rout_n and the second driving output end Nout_n also maintain the output state of the last stage.

[0337] When the Scan_n-1 and the N3_n-2 are both high level, the first driving transistor Q1 and the second driving transistor Q2 are both cut off, and the local brush signal control end N11_N can be prevented from writing the refresh signal of other time.

[0338] Timing T4 stage: STV=1, CK=1, CB=0, MS=0, Scan_n-1=1, N3_n-2=0

[0339] The first clock signal end CK is high level, the first cascade transistor T1 and the third cascade transistor T3 are cut off, the first node N1 is high level, the seventh cascade transistor T7 is turned on, the first clock signal end CK is high level, the second cascade transistor T2 is cut off, the third node N3 and the sixth node N6 maintain low level, the eleventh cascade transistor T11 is turned on, the second clock signal end CB is low level, the twelfth cascade transistor T12 is turned on, low voltage is written into the seventh node N7 and the ninth node N9, the fifteenth cascade transistor T15 is turned on, the first reference signal end VGH is provided to the cascade output end Scan_n through the turned-on fifteenth cascade transistor T15, namely, the cascade output end Scan_n outputs high level signal; meanwhile, the fourth node N4 is high level, the ninth cascade transistor T9 is cut off, and the voltage of the fifth node N5 is maintained unchanged.

[0340] The low level of the local brush signal control end N11_N makes the third drive transistor Q3 and the seventh drive transistor Q7 conduct, the ninth node N9 and the fourteenth node N14 are low level, the second output control node N12 and the pull-down node N8 are both high level, the fourth drive transistor Q4 is cut off, the low level of the fourteenth node N14 makes the fifth drive transistor Q5 conduct, and the high level signal of the first reference signal end VGH is provided to the first drive output end Rout_n through the conductive fifth drive transistor Q5, so that the VGH pulse output of the first drive output end Rout_n can be ensured.

[0341] Similarly, when the local brush signal control end N11_N-n of the current n-stage shift register is low level, the first transistor L1 and the fifth transistor L5 are turned on, the high level of the first node N1 and the first output control node N13 makes the second transistor L2 cut off, the fifteenth node N15 and the ninth node N9 are both low level, the fourth transistor L4 is turned on, and the high level signal of the first reference signal end VGH is provided to the second drive output end Nout_n through the conductive fourth transistor L4, so that the VGH pulse output of the second drive output end Nout_n can be ensured.

[0342] Timing T5 stage: STV=0, CK=1, CB=0, MS=0, Scan_n-1=0, N3_n-2=1

[0343] When the input signal end STV is low level, the first clock signal end CK is high level, the first cascade transistor T1 and the third cascade transistor T3 are cut off, the first node N1 and the second node N2 maintain the previous high level, and the remaining stages maintain the timing T4 stage unchanged, so that the cascade output end Scan_n maintains the output state of the previous stage.

[0344] Scan_n-1 is high level, the second drive transistor Q2 is cut off, can avoid local brush signal control end N11_N write other time refresh signal. The ninth node N9 and the fourteenth node N14 maintain low level, the fifth drive transistor Q5 is turned on, the high level signal of the first reference signal end VGH is provided to the first drive output end Rout_n through the fifth drive transistor Q5 which is turned on, and the VGH pulse output of the first drive output end Rout_n can be ensured.

[0345] Similarly, the fifteenth node N15 and the ninth node N9 maintain low level, the fourth transistor L4 is turned on, and the high level signal of the first reference signal end VGH is provided to the second drive output end Nout_n through the fourth transistor L4 which is turned on, and the VGH pulse output of the second drive output end Nout_n can be ensured.

[0346] Timing T6 stage: STV=0, CK=0, CB=1, MS=0, Scan_n-1=0, N3_n-2=1

[0347] When the first clock signal end CK is low level, the first cascade transistor T1 and the second cascade transistor T2 are turned on, the first node N1 and the second node N2 are written to VGL+Vth, the VGL of the second reference signal end makes the fourth cascade transistor T4 and the fifth cascade transistor T5 conductive, ensures that the pull-down node N8 and the fourth node N4 are low voltage, the fourteenth cascade transistor T14 is turned on, and the Scan_n outputs VGL; the fourth node N4 is low level, which makes the ninth cascade transistor T9 conductive, the first node N1 is low level, which makes the seventh cascade transistor T7 conductive, the third cascade transistor T3 is turned on when the first clock signal end CK is low level, the third node N3 and the sixth node N6 are pulled low, the eleventh cascade transistor T11 is turned on, the second clock signal end CB writes high level to the seventh node N7, the first node N1 is low level, which makes the thirteenth cascade transistor T13 conductive, the ninth node N9 is pulled high to high level by the first reference signal end VGH, and the fifteenth cascade transistor T15 is cut off.

[0348] When N3_n-2 is high level, the first drive transistor Q1 is cut off, which can avoid the local brush signal control end N11_N from writing refresh signals at other times. The high level of the ninth node N9 makes the fourteenth node N14 also high level, and the fifth drive transistor Q5 is cut off. The low level of the fourth node N4 makes the sixth drive transistor Q6 conductive, the second output control node N12 is low level, the fourth drive transistor Q4 is turned on, and the low level signal of the second reference signal end VGL is provided to the first drive output end Rout_n through the fourth drive transistor Q4 which is turned on, and the first drive output end Rout_n outputs low level signal.

[0349] Similarly, the high level of the ninth node N9 makes the fifteenth node N15 also high level, and the fourth transistor L4 is cut off. The low level of the fourth node N4 makes the third transistor L3 conduct, the first output control node N13 is low level, the second transistor L2 is conduct, and the low level signal of the second reference signal end VGL is provided to the second driving output end Nout_n through the conduct second transistor L2, so that the second driving output end Nout_n outputs low level signal.

[0350] Timing T7 stage: STV=0, CK=0, CB=1, MS=1

[0351] When the first clock signal end CK is low level, the first cascade transistor T1, the second cascade transistor T2 and the third cascade transistor T3 are conduct, the signal of the input signal end STV is low level and is provided to the first node N1, the second node N2 and the third node N3, the low level of the second reference signal end VGL makes the fourth cascade transistor T4, the fifth cascade transistor T5 and the tenth cascade transistor T10 conduct, the fourth node N4 and the pull-down node N8 are low level, and the fourteenth cascade transistor T14 is conduct; the low level of the fourth node N4 makes the ninth cascade transistor T9 conduct, the low level of the first node N1 makes the seventh cascade transistor T7 conduct, and the low level of the first clock signal end CK makes the third node N3 and the sixth node N6 low level through the seventh cascade transistor T7 and the tenth cascade transistor T10, the eleventh cascade transistor T11 is conduct, the high level of the second clock signal end CB makes the seventh node N7 high level, the low level of the first node N1 makes the thirteenth cascade transistor T13 conduct, and the high level signal of the first reference signal end VGH is written to the ninth node N9 through the conduct thirteenth cascade transistor T13, and the fifteenth cascade transistor T15 is cut off.

[0352] The low level of the fourth node N4 makes the sixth driving transistor Q6 conduct, and further makes the second output control node N12 low level, and the fourth driving transistor Q4 is conduct under the action of the low level of the second output control node N12, and the second reference signal end VGL is provided to the first driving output end Rout_n through the conduct fourth driving transistor Q4, so that the Rout_n outputs low level signal.

[0353] The low level of the fourth node N4 makes the third transistor L3 conduct, the first output control node N13 is low level, the second transistor L2 is conduct, and the second reference signal end VGL is provided to the second driving output end Nout_n through the conduct second transistor L2, so that the second driving output end Nout_n outputs low level signal.

[0354] Timing T8 stage: STV=0, CK=1, CB=0, MS=1

[0355] The high level of the first clock signal terminal CK makes the first cascade transistor T1 and the second cascade transistor T2 be off, the first node N1 is low, and the seventh cascade transistor T7 is turned on. The high level of the first clock signal terminal CK makes the third cascade transistor T3 be off, and the third node N3 and the sixth node N6 are written to high level through the turned-on seventh cascade transistor T7 and the tenth cascade transistor T10. The eleventh cascade transistor T11 is off, the seventh node N7 maintains the high level of the previous stage, the second clock signal terminal CB is low, the twelfth cascade transistor T12 is turned on, the ninth node N9 is maintained as high, and the fifteenth cascade transistor T15 is off. At the same time, the fourth node N4 is low, the ninth cascade transistor T9 is turned on, the second clock signal terminal CB writes low voltage to the fifth node N5, the fourth node N4 is pulled to a lower voltage (5-10V lower than VGL) through the first capacitor C1, the sixth cascade transistor T6 is turned on, low voltage is written to the node N8, the fourteenth cascade transistor T14 is fully turned on, and the second reference signal terminal VGL is provided to the cascade output terminal Scan_n through the turned-on fourteenth cascade transistor T14, so that the cascade output terminal Scan_n outputs a low level signal.

[0356] The low level of the fourth node N4 makes the sixth drive transistor Q6 be turned on, and the second output control node N12 is low. The fourth drive transistor Q4 is turned on under the action of the low level of the second output control node N12, the second reference signal terminal VGL is provided to the first drive output terminal Rout_n through the turned-on fourth drive transistor Q4, so that the Rout_n outputs a low level signal.

[0357] The low level of the fourth node N4 makes the third transistor L3 be turned on, and the first output control node N13 is low. The second transistor L2 is turned on, and the second reference signal terminal VGL is provided to the second drive output terminal Nout_n through the turned-on second transistor L2, so that the second drive output terminal Nout_n outputs a low level signal.

[0358] When Scan_n-1 and N3_n-2 are both low, the first drive transistor Q1 and the second drive transistor Q2 are turned on. Through the simultaneous opening of the first drive transistor Q1 and the second drive transistor Q2, 1 minimum gate time H (=n*Hsync, n=1-100, generally 2) can be obtained. In this way, when the refresh signal MS is high, the high level of the refresh signal MS in the row refresh control line is written to the refresh signal control terminal N11_N.

[0359] Timing T9 stage: STV=1, CK=0, CB=1, MS=1

[0360] When the input signal end STV is high level, and the first clock signal end CK is low level, the first cascade transistor T1 and the second cascade transistor T2 are turned on, the first node N1 and the second node N2 are written into high level, the second reference signal end VGL makes the fourth cascade transistor T4 and the fifth cascade transistor T5 conduct, the node N8 and the fourth node N4 are high level, the fourteenth cascade transistor T14 is cut off; the fourth node N4 is high level, the ninth cascade transistor T9 is cut off, the first node N1 is high level, the seventh cascade transistor T7 is cut off, the second clock signal end CB is low level, the second cascade transistor T2 and the third cascade transistor T3 are turned on, the second reference signal end VGL writes the third node N3 into low level through the turned-on third cascade transistor T3, the second reference signal end VGL is low level, the tenth cascade transistor T10 is turned on, the sixth node N6 is written into low level, the eleventh cascade transistor T11 is turned on, the second clock signal end CB writes high level into the seventh node N7, the twelfth cascade transistor T12 is cut off, the first node N1 is high, the thirteenth cascade transistor T13 is cut off, the ninth node N9 maintains high level, the fifteenth cascade transistor T15 is cut off, and the cascade output end Scan_n maintains the output state of the previous stage. Similarly, the first driving output end Rout_n and the second driving output end Nout_n also maintain the output state of the previous stage.

[0361] When the Scan_n-1 and the N3_n-2 are both high level, the first driving transistor Q1 and the second driving transistor Q2 are both cut off, and the local brush signal control end N11_N can be prevented from writing the refresh signal at other times.

[0362] Timing T10 stage: STV=0, CK=1, CB=0, MS=1

[0363] The first clock signal end CK is high level, the first cascade transistor T1 and the third cascade transistor T3 are cut off, the first node N1 is high level, the seventh cascade transistor T7 is turned on, the first clock signal end CK is high level, the second cascade transistor T2 is cut off, the third node N3 and the sixth node N6 maintain low level, the eleventh cascade transistor T11 is turned on, the second clock signal end CB is low level, the twelfth cascade transistor T12 is turned on, low voltage is written into the seventh node N7 and the ninth node N9, the fifteenth cascade transistor T15 is turned on, the first reference signal end VGH is provided to the cascade output end Scan_n through the turned-on fifteenth cascade transistor T15, so that the cascade output end Scan_n outputs high level signal.

[0364] The high level of the local brush signal control end N11_N makes the third driving transistor Q3 and the seventh driving transistor Q7 cut off, and the first driving output end Rout_n maintains the output state of the previous stage.

[0365] Similarly, when the shift register of the current n stage is controlled by the high level of the flush signal control end N11_N-n, the first transistor L1 and the fifth transistor L5 are cut off, and the second drive output end Nout_n also maintains the output state of the previous stage.

[0366] Timing T11 stage: STV = 0, CK = 1, CB = 0, MS = 1

[0367] When the input signal end STV is low and the first clock signal end CK is high, the first cascade transistor T1 and the third cascade transistor T3 are cut off, and the first node N1 and the second node N2 maintain the previous high level. The remaining stages maintain the timing T4 stage unchanged, ensuring that the cascade output end Scan_n maintains the output state of the previous stage. Similarly, the first drive output end Rout_n and the second drive output end Nout_n also maintain the output state of the previous stage.

[0368] Timing T12 stage: STV = 0, CK = 0, CB = 1, MS = 1

[0369] When the first clock signal end CK is low, the first cascade transistor T1 and the second cascade transistor T2 are turned on, and the first node N1 and the second node N2 are written to VGL+Vth. The VGL of the second reference signal end makes the fourth cascade transistor T4 and the fifth cascade transistor T5 conductive, ensuring that the pull-down node N8 and the fourth node N4 are low voltage. The fourteenth cascade transistor T14 is turned on, and the signal of the second reference signal end VGL is provided to the cascade output end Scan_n through the fourteenth cascade transistor T14, that is, the cascade output end Scan_n outputs low level. The fourth node N4 is low to make the ninth cascade transistor T9 conductive, the first node N1 is low to make the seventh cascade transistor T7 conductive, and the first clock signal end CK is low to make the third cascade transistor T3 conductive. The third node N3 and the sixth node N6 are pulled low, the eleventh cascade transistor T11 is turned on, the second clock signal end CB writes high level to the seventh node N7, the first node N1 is low to make the thirteenth cascade transistor T13 conductive, and the first reference signal end VGH pulls the ninth node N9 high to high level, ensuring that the fifteenth cascade transistor T15 is cut off.

[0370] When N3_n-2 is high level, the first driving transistor Q1 is cut off, so as to avoid the local brush signal control terminal N11_N from writing the refresh signal at other time. The high level of the ninth node N9 makes the fourteenth node N14 also high level, and the fifth driving transistor Q5 is cut off. The low level of the fourth node N4 makes the sixth driving transistor Q6 conduct, the second output control node N12 is low level, the fourth driving transistor Q4 is conduct, and the low level signal of the second reference signal end VGL is provided to the first driving output end Rout_n through the conduct fourth driving transistor Q4, and the first driving output end Rout_n outputs low level signal.

[0371] Similarly, the high level of the ninth node N9 makes the fifteenth node N15 also high level, and the fourth transistor L4 is cut off. The low level of the fourth node N4 makes the third transistor L3 conduct, the first output control node N13 is low level, the second transistor L2 is conduct, and the low level signal of the second reference signal end VGL is provided to the second driving output end Nout_n through the conduct second transistor L2, and the second driving output end Nout_n outputs low level signal.

[0372] Based on the same inventive concept, the disclosure provides a gate driving circuit, comprising:

[0373] a plurality of cascaded shift register units as described above;

[0374] the input signal end of the first stage shift register unit is coupled with the frame start signal end;

[0375] the input signal end of the last stage shift register unit in the two adjacent stage shift register units is connected with the cascaded output end of the former stage shift register unit.

[0376] Exemplarily, the local brush signal control terminal N11_N of the current stage shift register unit in the plurality of shift register units is connected with the local brush signal control terminal N11_N-n of the former n stage shift register.

[0377] Referring to FIG. 21 and FIG. 22, taking eight cascaded shift register units in the gate driving circuit as an example, the waveforms of the three output ends signals Scan_n, Rout_n and Nout_n of the same stage shift register unit are the same, and the phases are the same. The waveforms of the three output ends signals of the next stage shift register unit are the same as the waveforms of the three output ends signals of the former stage shift register unit, and the phases are different. When the eighth row of sub-pixel corresponding pixel driving circuit needs to be locally refreshed, i.e. when Rout_n and Nout_n need to be provided to the pixel driving circuit, the Rout_n of the first stage shift register unit and the Nout_n of the eighth stage shift register unit are connected.

[0378] Based on the same inventive concept, referring to FIG. 23, the display panel provided in the embodiment of the present disclosure includes a display area including a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines, each sub-pixel including a light emitting device and a pixel driving circuit connected to the light emitting device, and one data line connected to the pixel driving circuits of at least some of the sub-pixels in one row.

[0379] In the embodiment of the present disclosure, the plurality of data lines in the display panel are arranged longitudinally, and the plurality of gate lines are arranged transversely, and each sub-pixel includes the pixel driving circuit and the light emitting device.

[0380] The non-display area includes the gate driving circuit, the first reset signal end NReset of the pixel circuit in the current row of sub-pixels is connected to the first driving output end Rout_n of the mth shift register unit in the plurality of shift register units, the first scan signal end NGate of the pixel circuit in the current row of sub-pixels is connected to the second driving output end Nout_n of the m-nth shift register unit in the plurality of shift register units, and n and m are integers greater than 0 and m>n.

[0381] In order to realize local refresh in the row direction of the display panel, the embodiment of the present disclosure is provided with a row refresh control line, one end of the row refresh control line is connected to the source chip, the other end of the row refresh control line is connected to the shift register unit of each row, and different shift register units are provided with refresh signals in time division. On the basis of ensuring that the gate lines are scanned row by row through the cascade output end of the shift register unit, the shift register unit can generate two signals for local refresh in the row direction according to the refresh signal: the first driving signal and the second driving signal, further provide the first driving signal to the first scan signal end NGate of the pixel driving circuit, and provide the second driving signal to the first reset signal end NReset of the pixel driving circuit, so that the pixel driving circuit updates the data voltage.

[0382] In addition, the pixel driving circuit includes a first reset transistor, i.e., the second switch transistor m2 in FIG. 1 or the third switch transistor M3 in FIG. 3, the control end of the first reset transistor is coupled to the first reset signal end NReset connected to the sub-pixel, and the first reset signal end NReset is coupled to the first driving output end Rout_n of the shift register unit connected to the sub-pixel.

[0383] In addition, the pixel driving circuit includes a threshold compensation transistor, i.e., the threshold compensation transistor m1 in FIG. 1 or the threshold compensation transistor M1 in FIG. 3, the control end of the threshold compensation transistor is coupled to the first scan signal end NGate connected to the sub-pixel, and the first scan signal end NGate is coupled to the second driving output end Nout_n of the shift register unit connected to the sub-pixel.

[0384] Exemplarily, referring to FIG. 2, the first driving signal is provided to the first scan signal terminal NGate of the pixel driving circuit, that is, whether the threshold compensation transistor is turned on or not is controlled through the first scan signal terminal NGate, and the second driving signal is provided to the first reset signal terminal NReset of the pixel driving circuit, that is, whether the third switch transistor is turned on or not is controlled through the first reset signal terminal NReset, and the updating of the data voltage is realized in combination with the second switch transistor.

[0385] Exemplarily, the display panel further comprises: a first reference signal line, a second reference signal line and a third reference signal line which are arranged at intervals.

[0386] In combination with FIG. 18, the first reference signal terminal connected with the shift register in the shift register unit and the first driving sub-circuit is connected with the first reference signal line.

[0387] The first reference signal terminal connected with the second driving sub-circuit in the first odd-numbered shift register unit is connected with the second reference signal line.

[0388] The first reference signal terminal connected with the second driving sub-circuit in the first even-numbered shift register unit is connected with the third reference signal line.

[0389] That is, in the embodiment of the present disclosure, an independent power supply line can also be arranged, that is, the first reference signal line, the second reference signal line and the third reference signal line which are arranged at intervals. On this basis, the first reference signal terminal connected with the shift register in the shift register unit is connected with the first reference signal line.

[0390] Exemplarily, the first reference signal terminal coupled with the second terminal of the fifteenth cascade transistor T15 is connected with the first reference signal line, that is, the first reference signal terminal VGH1 is connected with the second terminal of the fifteenth cascade transistor T15.

[0391] Similarly, the first reference signal terminal connected with the first driving sub-circuit in the shift register unit is connected with the first reference signal line.

[0392] Exemplarily, the first reference signal terminal VGH connected with the first terminal of the fifth driving transistor Q5 is connected with the first reference signal line, that is, the first reference signal line provides a voltage with a voltage value of VGH1 for the first reference signal terminal, so as to realize the connection between the first reference signal terminal VGH1 and the first terminal of the fifth driving transistor Q5.

[0393] In addition, the first reference signal terminal connected with the second driving sub-circuit in the first odd-numbered shift register unit is connected with the second reference signal line.

[0394] Exemplarily, the first reference signal end VGH connected with the first end of the fourth transistor L4 is connected with the second reference signal line, that is, the second reference signal line provides a voltage with a voltage value of VGH2 for the first reference signal end, so as to realize the connection of the first reference signal end VGH2 with the first end of the fourth transistor L4.

[0395] It also needs to be explained that the first reference signal end connected with the second driving sub-circuit in the even-numbered stage shift register unit is connected with the third reference signal line.

[0396] Exemplarily, the first reference signal end VGH connected with the first end of the fourth transistor L4 is connected with the third reference signal line, that is, the third reference signal line provides a voltage with a voltage value of VGH3 for the first reference signal end, so as to realize the connection of the first reference signal end VGH3 with the first end of the fourth transistor L4.

[0397] In addition, it needs to be supplemented that when the display panel is designed as 1 drive 2 of the first scan signal end NGate, the above-mentioned odd-numbered stage shift register unit includes the shift register units arranged in two adjacent rows of the display panel, for example, the odd-numbered stage shift register unit includes the shift register units arranged in the first row and the second row of the display panel; and the above-mentioned even-numbered stage shift register unit also includes the shift register units arranged in two adjacent rows of the display panel, for example, the even-numbered stage shift register unit includes the shift register units arranged in the third row and the fourth row of the display panel.

[0398] In the embodiment of the application, the first scan signal end NGate serves to control the switch transistor directly related to charging in the pixel driving circuit, that is, the first switch transistor m1 in the pixel driving circuit shown in FIG. 1 and the threshold compensation transistor M1 in the pixel driving circuit shown in FIG. 2, and the second driving output end of the second driving sub-circuit in the adjacent stage shift register unit outputs the second driving signal, which will have a large noise due to the interference between the first reference signal ends VGH, so that the noise of the second driving signal has a great influence on the transistor related to charging in the pixel driving circuit, especially in the display panel with 1 drive 2 of the first scan signal end NGate, the noise in two rows in a cycle will cause the difference in charging of the pixels in the odd and even rows, and the difference in brightness between the odd and even rows. In the embodiment of the disclosure, the VGH2 / 3 odd-even routing scheme is adopted, so as to reduce the mutual interference between the routings, avoid the difference in brightness between the odd and even rows, and solve the display unevenness caused by the noise difference of the power supply line in the local refresh display process.

[0399] Based on the same inventive concept, the display device provided in the embodiment of the disclosure includes the above-mentioned display panel.

[0400] Exemplarily, the source chip is coupled with at least part of the data lines and the row refresh control lines of the display panel respectively, and the source chip is configured to output a data voltage signal to the data line connected therewith and output a refresh signal to the row refresh control line within a frame display time of the display panel.

[0401] In the implementation process, within a frame display time of the display panel, the source chip outputs a data voltage signal to the data line connected therewith, and in addition, the source chip also outputs a refresh signal to the row refresh control line, and through the input of the refresh signal, the shift register unit can generate a driving signal for local refresh in the row direction.

[0402] The display device provided by the embodiments of the present disclosure can be a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function. Other essential components of the display device should be understood by those skilled in the art, and are not described here to avoid repetition. Neither should it be considered as a limitation on the present disclosure.

[0403] Based on the same inventive concept, referring to FIG. 24, a driving method of the shift register unit applied to any of the above is provided in the embodiments of the present disclosure, comprising:

[0404] Step 201: The shift register 001 outputs a cascade signal through the cascade output end Scan_n.

[0405] In the implementation process, the shift register 001 in the embodiments of the present disclosure mainly outputs a cascade signal through the cascade output end Scan_n to ensure that the next row of gate lines is scanned after the current row of scanning is completed.

[0406] Step 202: The first driving sub-circuit 002 outputs a first driving signal through the first driving output end Rout_n in response to the signals of the pull-up node N9 and the lower node N10.

[0407] In the implementation process, the first driving sub-circuit 002 outputs the signal of the first reference signal end VGH through the first driving output end Rout_n in response to the signal of the pull-up node N9 of the shift register, or the first driving sub-circuit 002 outputs the signal of the second reference signal end VGL through the first driving output end Rout_n in response to the signal of the lower node N10 of the shift register. The pull-up node N9 here is the pull-up node N9 in the shift register corresponding to the current row of sub-pixels.

[0408] Step 203: The second driving sub-circuit 003 is configured to output a second driving signal through the second driving output end Nout_n in response to the signals of the pull-up node N9, the lower node N10, and the local refresh signal control end N11_N-n.

[0409] In the implementation process, the second driving sub-circuit 003 responds to the signal of the pull-up node N9 of the shift register, and makes the second driving output end Nout_n output the signal of the first reference signal end VGH, or the second driving sub-circuit responds to the signals of the lower connection node N10 and the local brush signal control end N11_N-n, and makes the second driving output end Nout_n output the signal of the second reference signal end VGL. It needs to be explained that the above local brush signal control end N11_N-n is the node N11_N in the shift register corresponding to the front n rows of sub-pixels.

[0410] To sum up, in the embodiment of the present disclosure, a shift register unit, a display panel, a display device and a driving method are provided, the shift register unit comprises: a shift register, a first driving sub-circuit and a second driving sub-circuit, the shift register is configured to control the cascade output end to output a cascade signal according to the signal of the input signal end STV, the first driving sub-circuit is coupled with the pull-up node and the lower connection node of the shift register and the first driving output end, the first driving sub-circuit is configured to output a first driving signal through the first driving output end in response to the signals of the pull-up node and the lower connection node, the second driving sub-circuit is coupled with the pull-up node, the lower connection node, the local brush signal control end and the second driving output end, and the second driving sub-circuit is configured to output a second driving signal through the second driving output end in response to the signals of the pull-up node, the lower connection node and the local brush signal control end, the above shift register unit can output three signals to the display panel at the same time, and on the basis of realizing the row refresh of the display panel, the width of the frame of the corresponding display device is effectively shortened.

[0411] Those skilled in the art will understand that the embodiments of the present disclosure can be provided as a method, a system or a computer program product system. Therefore, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0412] The present disclosure is described with reference to flowcharts and / or block diagrams according to the method, device (system) and computer program product system of the present disclosure. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flows in the flowchart and / or one or more blocks in the block diagram.

[0413] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart or flowsheets and / or block or blocks of the block diagrams.

[0414] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flowsheets and / or block or blocks of the block diagrams.

[0415] Obviously, numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the present disclosure, the disclosure can be practiced otherwise than as specifically described. Thus, unless specifically stated otherwise, concepts disclosed herein are not to be limited to only the specific orders and / or sequences described.

Claims

1. A shift register unit, wherein, The application relates to a shift register, a first driving sub-circuit and a second driving sub-circuit. The shift register is configured to control a cascade output end to output a cascade signal according to a signal of an input signal end. The first driving sub-circuit is coupled with a pull-up node and a lower cascade node of the shift register and a first driving output end, and the first driving sub-circuit is configured to output a first driving signal through the first driving output end in response to signals of the pull-up node and the lower cascade node. The second driving sub-circuit is coupled with the pull-up node, the lower cascade node, a brush signal control end and a second driving output end, and the second driving sub-circuit is configured to output a second driving signal through the second driving output end in response to signals of the pull-up node, the lower cascade node and the brush signal control end. The second driving signal has the same waveform and phase as the first driving signal.

2. The shift register cell of claim 1, wherein, The second driving sub-circuit comprises a driving control unit, a first output unit and a second output unit.

3. The shift register cell of claim 1, wherein, The driving control unit is coupled with the lower cascade node, the brush signal control end and a first output control node, and the driving control unit is configured to provide a signal of the lower cascade node to the first output control node in response to a signal of the brush signal control end. The first output unit is coupled with the pull-up node, a first reference signal end and the second driving output end, and the first output unit is configured to provide a signal of the first reference signal end to the second driving output end in response to a signal of the pull-up node. The second output unit is coupled with the first output control node, a second reference signal end and the second driving output end, and the second output unit is configured to provide a signal of the second reference signal end to the second driving output end in response to a signal of the first output control node. The driving control unit comprises a first transistor.

4. The shift register cell of claim 3, wherein, A control end of the first transistor is coupled with the brush signal control end, a first end of the first transistor is coupled with the lower cascade node, and a second end of the first transistor is coupled with the first output control node. The second output unit comprises a second transistor.

5. The shift register cell of claim 3, wherein, A control end of the second transistor is coupled with the first output control node, a first end of the second transistor is coupled with the second driving output end, and a second end of the second transistor is coupled with the second reference signal end. The second driving sub-circuit further comprises a first control unit coupled with a fourth node in the shift register and the first output control node.

6. The shift register cell of any of claims 3-5, wherein, The first control unit is configured to provide a signal of the fourth node to the first output control node in response to a signal of the fourth node. The first control unit comprises a third transistor.

7. The shift register cell of claim 6, wherein, A control end and a first end of the third transistor are coupled with the fourth node, and a second end of the third transistor is coupled with the first output control node. The first output unit comprises a fourth transistor.

8. The shift register cell of claim 3, wherein, A control end of the fourth transistor is coupled with the pull-up node, a first end of the fourth transistor is coupled with the first reference signal end, and a second end of the fourth transistor is coupled with the second driving output end. A control terminal of the fourth transistor is coupled with the pull-up node, a first terminal of the fourth transistor is coupled with the first reference signal terminal, and a second terminal of the fourth transistor is coupled with the second driving output terminal.

9. A shift register cell as claimed in any one of claims 3-8, wherein, The second driving sub-circuit further includes a second control unit, wherein the second control unit is coupled between the pull-up node and the first output unit. The second control unit is configured to turn on the pull-up node and the first output unit in response to a signal of the local brush signal control terminal. The second control unit includes a fifth transistor, a first capacitor, and a second capacitor.

10. The shift register cell of claim 9, wherein, A control terminal of the fifth transistor is coupled with the local brush signal control terminal, a first terminal of the fifth transistor is coupled with the pull-up node, and a second terminal of the fifth transistor is coupled with the first output unit. A first terminal of the first capacitor is coupled with the second terminal of the fifth transistor, and a second terminal of the first capacitor is coupled with the local brush signal control terminal. A first terminal of the second capacitor is coupled with the second terminal of the fifth transistor, and a second terminal of the second capacitor is coupled with the first reference signal terminal. The control terminal of the fifth transistor includes a first control terminal and a second control terminal, and both the first control terminal and the second control terminal are coupled with the local brush signal control terminal.

11. The shift register cell of claim 10, wherein, The second driving sub-circuit further includes a third control unit, wherein the third control unit is coupled with the local brush signal control terminal.

12. The shift register cell of any of claims 2-10, wherein, The third control unit is configured to provide a signal of the second reference signal terminal to the local brush signal control terminal in response to a signal of a reset control signal terminal. The third control unit includes a sixth transistor.

13. The shift register cell of claim 12, wherein, A control terminal of the sixth transistor is coupled with the reset control signal terminal, a first terminal of the sixth transistor is coupled with the local brush signal control terminal, and a second terminal of the sixth transistor is coupled with the second reference signal terminal. The second driving sub-circuit further includes a fourth control unit, wherein the fourth control unit is coupled with the control terminal of the fourth transistor.

14. The shift register cell of claim 8, wherein, The fourth control unit is configured to provide a signal of the first reference signal terminal to the control terminal of the fourth transistor in response to a signal of a second control signal terminal. The fourth control unit includes a seventh transistor. A control terminal of the seventh transistor is coupled with the second control signal terminal, a first terminal of the seventh transistor is coupled with the control terminal of the fourth transistor, and a second terminal of the seventh transistor is coupled with the first reference signal terminal.

15. The shift register cell of claim 14, wherein, The fourth control unit includes an eighth transistor and a ninth transistor, and the second control signal terminal includes a first control sub-signal terminal and a second control sub-signal terminal. A control terminal of the eighth transistor is coupled with the second control sub-signal terminal, a first terminal of the eighth transistor is coupled with a first terminal of the ninth transistor, and a second terminal of the eighth transistor is coupled with the first reference signal terminal.

16. The shift register cell of claim 14, wherein, A control terminal of the ninth transistor is coupled with the first control sub-signal terminal, and a second terminal of the ninth transistor is coupled with the control terminal of the fourth transistor. ​ ​ 17. The shift register cell of claim 16, wherein, The second control sub-signal end is the first output control node, and the first control sub-signal end is the second driving output end.

18. The shift register cell of any of claims 2-17, wherein, The second driving sub-circuit further comprises a fifth control unit, wherein the fifth control unit is coupled with the local brush signal control end, the third control signal end, the fourth control signal end and the second reference signal end. The fifth control unit is configured to provide a signal of the second reference signal end to the local brush signal control end in response to signals of the third control signal end and the fourth control signal end.

19. The shift register cell of claim 18, wherein, The third control signal end and the fourth control signal end have a phase difference between effective signals, and the phase difference between the effective signals of the third control signal end and the fourth control signal end corresponds to a phase difference between a second driving signal of an Nth shift register unit and a first driving signal of an N-nth shift register unit.

20. The shift register cell of claim 18 or 19, wherein, The fifth control unit comprises a tenth transistor and an eleventh transistor, a control end of the tenth transistor is coupled with the third control signal end, a first end of the tenth transistor is coupled with the local brush signal control end, and a second end of the tenth transistor is coupled with a first end of the eleventh transistor; a control end of the eleventh transistor is coupled with the fourth control signal end, and a second end of the eleventh transistor is coupled with the second reference signal end.

21. The shift register cell of any of claims 1-20, wherein, The shift register comprises a first input sub-circuit, a second input sub-circuit, a node control sub-circuit and an output sub-circuit. The first input sub-circuit is configured to provide a signal of an input signal end to the first node and the second node in response to a signal of a first clock signal end. The second input sub-circuit is configured to provide a signal of a second reference signal end to a third node in response to a signal of the first clock signal end. The node control sub-circuit is configured to control signals of the pull-up node and the pull-down node according to signals of the first node, the second node and the third node. The output sub-circuit is configured to provide a signal of a first reference signal end to the cascaded output end in response to a signal of the pull-up node, and provide a signal of a second reference signal end to the cascaded output end in response to a signal of the pull-down node.

22. The shift register cell of any one of claims 1 to 21, wherein, The first driving sub-circuit comprises a refresh input unit, a refresh control unit, a third output unit and a fourth output unit. The refresh input unit is configured to provide a signal of a row refresh control end to the local brush signal control end in response to signals of a refresh gate end and an input signal end. The refresh control unit is configured to provide a signal of the lower node to a second output control node in response to a signal of the local brush signal control end. The third output unit is configured to provide a signal of a second reference signal end to the first driving output end in response to a signal of the second output control node. The fourth output unit is configured to provide a signal of a first reference signal end to the first driving output end in response to a signal of the pull-up node. A plurality of shift register units as claimed in any one of claims 1 to 22 are cascaded.

23. A gate drive circuit comprising: ​ The input signal end of the first-stage shift register unit is coupled with the frame start signal end; The input signal end of the next-stage shift register unit in the adjacent two-stage shift register units is connected with the cascade output end of the previous-stage shift register unit.

24. The gate drive circuit of claim 23, wherein, The local brush signal control end of the current-stage shift register unit in the plurality of shift register units is connected with the local brush signal control end of the previous-n-stage shift register.

25. A display panel, wherein, Comprising: The display area comprises a plurality of sub-pixels, each of the sub-pixels comprising a light emitting device and a pixel driving circuit connected with the light emitting device; The non-display area comprises the gate driving circuit as claimed in claim 23 or 24, the first reset signal end of the pixel circuit in the current row of sub-pixels is connected with the first driving output end of the mth-stage shift register unit in the plurality of shift register units, the first scan signal end of the pixel circuit in the current row of sub-pixels is connected with the second driving output end of the m-nth-stage shift register unit in the plurality of shift register units, and the n and the m are integers greater than 0 and m>n.

26. The display panel of claim 25, wherein, The pixel driving circuit comprises a first reset transistor, the control end of the first reset transistor is coupled with the first reset signal end connected with the sub-pixel, and the first reset signal end is coupled with the first driving output end of the shift register unit connected with the sub-pixel.

27. The display panel of claim 25 or 26, wherein, The pixel driving circuit comprises a threshold compensation transistor, the control end of the threshold compensation transistor is coupled with the first scan signal end connected with the sub-pixel, and the first scan signal end is coupled with the second driving output end of the shift register unit connected with the sub-pixel.

28. The display panel of claim 25, wherein, Further comprising: The first reference signal line, the second reference signal line and the third reference signal line are arranged at intervals; The first reference signal end of the shift register in each-stage shift register unit and the first driving sub-circuit is connected with the first reference signal line; The first reference signal end of the second driving sub-circuit in the odd-numbered-stage shift register unit is connected with the second reference signal line; The first reference signal end of the second driving sub-circuit in the even-numbered-stage shift register unit is connected with the third reference signal line.

29. A display device comprising: Comprising: The display panel as claimed in any one of claims 25 to 28.

30. A driving method applied to the shift register unit as claimed in any one of claims 1 to 22, wherein Comprising: The shift register outputs a cascade signal through the cascade output end; The first driving sub-circuit outputs a first driving signal through the first driving output end in response to the signals of the pull-up node and the next-link node; The second driving sub-circuit is configured to output a second driving signal through the second driving output end in response to the signals of the pull-up node, the next-link node and the local brush signal control end.

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