Reducing overlap for current source converters using gate current mirrors

Abstract

A control circuit for a current source converter having a current generator comprising an inductance and having two or more half bridges, each half bridge having an upper leg provided with upper switching devices and a lower leg provided with lower switching devices, the upper leg switching devices and the lower leg switching devices being controlled by a controller to provide overlap between upper leg off switching devices and upper leg on switching devices and to provide overlap between lower leg on switching devices and lower leg off switching devices by gate pull-up and pull-down pulse signals input to gate driver buffers of the switching devices, characterized in that the gate driver circuit comprises: - a gate current mirror circuit for each upper leg switching device and each lower leg switching device, the gate current mirror circuit providing a gate pull-down signal on a source branch of the gate driver buffer of the switching device when the switching device is off, the gate pull-down signal being connected to a control line of a gate buffer of a respective other upper leg switching device or other lower leg switching device, - a positive gate command connection path from a positive gate command output of a pre-driver for each upper leg switching device and each lower leg switching device, the positive gate command connection path providing a reset signal for the gate pull-down signal of the respective other upper leg switching device or respective other lower leg switching device.

Description

Technical Field

[0001] This disclosure relates to the field of current source converters, which include at least two switched half-bridges, each having an upper switching device and a lower switching device. To avoid current interruption, the on-states of the upper or lower switching devices with opposite switching cycles of the two half-bridges need to overlap, which can cause overvoltages in the converter. Priority is claimed to European Patent Application No. EP23306949.1, filed on October 10, 2023, the contents of which are incorporated herein by reference. Background Technology

[0002] Current-source converters are used in various applications, such as HVDC, motor drives, or power factor correction. The main limitation of such converters is the use of bulky input inductors and power modules designed for conventional switching units. However, the increasing availability of wide-bandgap devices with lower conduction and switching losses (such as silicon carbide and / or gallium nitride) has opened up new possibilities for current-source converter designs by reducing size and increasing efficiency. Summary of the Invention

[0003] The problem that this invention will solve

[0004] Current source power converters (CSCs) consist of at least two half-bridges, where the switches in the upper branches of the two half-bridges and the switches in the lower branches of the two half-bridges are controlled in a complementary manner, switching from on to off and from off to on. Between these transitions, an overlap is used where two of the upper switches or two of the lower switches are on. The main reason for this overlap is due to the nature of the current source, which acts as an induction source, and should not be interrupted. Current interruption can be caused by a variety of factors, including a control signal error in one of the two switches, an open-circuit fault in the device, or a gate driver failure. In such a case, the lack of a current path for the DC current can cause significant damage because the current interruption in the current source or current-fed converter causes a rapid increase in voltage across the semiconductor device, exceeding the breakdown voltage of that semiconductor, which can destroy the power converter. In such a case, the power switching device causing the overvoltage may enter "avalanche mode," in which energy stored in the inductor is dissipated. Because these devices cannot withstand prolonged high voltage and high current conditions, such a condition can destroy them. This situation has led to problems in current source converters (such as...) Figure 1In inverters of the type shown, the switching cycles of the half-bridge must overlap between opposite upper or lower switching devices. Nevertheless, shortening the overlap time is still beneficial for overall converter operation. Firstly, excessively long overlap times lead to high total harmonic distortion (THD) of the output current. Software solutions can be implemented within the control loop to mitigate this side effect. Additionally, in the case of CSCs with bidirectional current characteristics, such as... Figure 1 As shown in circle A, shortening the overlap time can reduce losses. The control of two devices placed in series depends on the overlap time; the longer the overlap time, the longer one of the body diodes conducts. Therefore, due to the higher forward voltage, the conduction loss increases.

[0005] Problem Solving Methods

[0006] This disclosure improves upon the aforementioned situation by providing a switching system in which the overlap between the power semiconductor switches in a current-feed converter turning on and off and between off and on can be reduced without reducing the overlap calculated by the converter's controller. More specifically, this disclosure proposes a control circuit for a current-source converter having a current generator including an inductor and having two or more half-bridges, each half-bridge having an upper branch and a lower branch, the upper branch having an upper switching device and the lower branch having a lower switching device. The upper branch switching device and the lower branch switching device are controlled by a controller to provide overlap between the upper branch off switching device and the upper branch on switching device, and overlap between the lower branch on switching device and the lower branch off switching device, by means of gate pull-up pulse signals and gate pull-down pulse signals input to the gate driver buffer of the switching device, characterized in that the gate driver circuit includes:

[0007] - A gate current mirror circuit for each upper branch switching device and each lower branch switching device, the gate current mirror circuit being on the source branch of the gate driver buffer of the switching device, providing a gate pull-down signal when the switching device is turned off, the gate pull-down signal being connected to the control line of the gate buffer of the corresponding other upper branch switching device or the other lower branch switching device.

[0008] - A positive gate command connection path originating from the positive gate command output of the pre-driver for each upper branch switch and each lower branch switch, the positive gate command connection path providing a reset signal for the gate pull-down signal of the corresponding other upper branch switch and the corresponding other lower branch switch.

[0009] The gate pull-down signal can be output from a MOS transistor that receives pulses generated from the gate current mirror circuit at the gate, and the MOS transistor may or may not have a filter capacitor between the gate and source.

[0010] The gate pull-down signal can be the output of an SR gate, which takes a current mirror of the gate current as its input, and the gate pull-down signal is generated from the gate current mirror circuit.

[0011] The control circuit may include an inverter gate to provide the reset signal from the positive gate connection path.

[0012] The reset signal can polarize the gate of the MOS transistor to discharge the gate of the MOS transistor or to discharge the gate of the MOS transistor and the filter capacitor.

[0013] When the gate pull-down signal is the output of an SR gate with the gate current mirror as input and is generated from the gate current mirror circuit, the reset signal can be connected to the reset input of the SR gate.

[0014] The pre-driver can provide the first electrical insulation between the controller circuitry and the gate buffer.

[0015] The control unit may include a second electrical insulator between the gate current mirror circuit and the gate pull-down signal circuit.

[0016] The second electrical insulation component can be provided by a transformer in the collector branch of a current mirror transistor.

[0017] The second electrical insulation component can also be provided by an optocoupler in the collector branch of a current mirror transistor or another insulating component.

[0018] This disclosure also relates to a converter or inverter comprising a current source, a controller, and at least two half-bridges, each half-bridge having an upper branch switching device and a lower branch switching device, each of the switching devices being controlled by the controller via a gate driver, wherein the gate driver includes control circuitry according to any one of the preceding claims.

[0019] This disclosure further relates to a method for switching power switching devices of a branch of a half-bridge of a current source converter with a shortened overlap time, wherein the ON and OFF states of the power switching devices of the branch are driven by a controller via a gate driver having a gate buffer, characterized in that during a switching transition between a first upper branch power switching device and a second upper branch power switching device, or between a first lower branch power switching device and a second lower branch power switching device, the switching transition is initiated by the controller via the gate driver of the power switching device, the method comprising: prior to inputting a gate pulse generated from the controller to the gate driver of the second switching device, using a mirror gate current or a voltage proportional to the mirror gate current from one of the power switching devices transitioning from an OFF state to an ON state, so as to cause the other of the switching devices to transition from an ON state to an OFF state, the gate pulse being provided for causing the other of the switching devices to transition from the ON state to the OFF state.

[0020] The method may include providing a gate pull-down pulse signal generated from the mirror gate current or a voltage proportional to the mirror gate current, the gate pull-down pulse signal being used to switch the other of the switching devices from the on state to the off state.

[0021] The mirror gate current may be the mirror source current of the gate buffer that drives the power switching device.

[0022] The method may include: latching the mirror gate current or the voltage proportional to the mirror gate current to provide the gate pull-down pulse signal, and resetting the gate pull-down pulse signal at the end of the transition.

[0023] Effects of the present invention

[0024] The purpose of this disclosure is to provide a switching system that reduces the overlap between power semiconductor switches in a current-fed converter turning on and off, and between off and on, without reducing the overlap calculated by the converter's controller. Attached Figure Description

[0025] Other features, details, and advantages will be shown in the following detailed description and in the accompanying drawings, in which:

[0026] Figure 1 This is a schematic diagram of a single-phase current source inverter.

[0027] Figure 2 This is a schematic diagram of an example of a control circuit according to an embodiment of the present disclosure.

[0028] Figure 3 An example of the control circuitry for the two branches of the converter of this disclosure is shown.

[0029] Figure 4 A schematic diagram of a traditional three-phase current source inverter is shown. Detailed Implementation

[0030] Figure 1 This is a schematic diagram of a DC / AC current source converter (also known as an "inverter"). This converter includes a DC source 1, an inductor 2, and two half-bridges. The first half-bridge includes a first upper branch power switching device 11 and a first lower branch power switching device 12. The first upper branch power switching device 11 has an IGBT Q1 and a diode 21, and the first lower branch power switching device 12 has an IGBT Q2 and a diode 22. The second half-bridge includes a second upper branch power switching device 13 and a second lower branch power switching device 14. The second upper branch power switching device 13 has an IGBT Q3 and a diode 23, and the second lower branch power switching device 14 has an IGBT Q4 and a diode 24. The IGBT+diode design shown can be replaced with a series-connected IGBT with a reverse freewheeling diode, or a series-connected reverse-polarity MOSFET with an inherent body diode, or an additional freewheeling diode (as shown in circle A).

[0031] The half-bridge of the current source converter is connected to the AC voltage and current load 4.

[0032] The switches are controlled by gate drivers. A first gate driver 31 is used for the first upper branch switch device 11 of the first half-bridge, a second gate driver 32 is used for the first lower branch switch device 12 of the first half-bridge, a third gate driver 33 is used for the second upper branch switch device 13 of the second half-bridge, and a fourth gate driver 34 is used for the second lower branch switch device 14 of the second half-bridge. In this converter, to generate AC current in the AC load 4, reverse switching between the upper branch power switches and between the lower branch power switches are required. Due to the induced current source caused by the inductor 2, overlap is forced when one power switch device on the upper or lower branch side is turned off and the other power switch device is turned on.

[0033] from Figure 1 Starting with a basic schematic diagram, this disclosure relates to a driver circuit designed to reduce overlap in order to reduce losses in the converter and heat dissipation in the power switch.

[0034] To achieve this, such as Figure 2 or Figure 3 The driver circuit is designed in a way that adds the function of turning off the first switch in advance when the second switch is turned on at the same branch level (upper branch level or lower branch level).

[0035] exist Figure 2 In the middle, the driver circuit 31 includes a pre-driver 7, which provides the controller power supply V. DD V SS The first electrical insulator between the power switch X-gate buffer circuit 6 and the power switch X-gate buffer circuit 6 has V DDx and V SSx power supply.

[0036] In the presented circuit, the gate current mirror circuit 51 with transistors T3 and T4 is located in the source branch of the push-pull buffer 6 with transistors T1 and T2.

[0037] Obtain a mirror image of the source current of buffer 6 at the junction of resistor Rmon and the collector of transistor T5.

[0038] This source current corresponds to the gate current of power switching device X during its transition from off to on.

[0039] exist Figure 2 In the process, before the controller switch closing signal I- is received, the second electrical insulator 52, which is composed of optocoupler 52a, transmits the signal extracted from the current mirror to the SR gate, and the SR gate outputs signal Gp. y As discussed below, the signal Gp y Used to turn off power switching devices Y, such as Figure 3 What I saw.

[0040] On the other side, the same driver circuit is implemented for power switch Y. During the transition of power switch Y from off to on, before the controller signal is received, power device Y further provides a Gpx signal, which will turn off power switch X.

[0041] The aforementioned content can be found Figure 3 The image shows a complete driver circuit for either the upper or lower branch of the converter.

[0042] exist Figure 3 In the driver circuit of the gate Y of power switch Y, the SR gate is replaced by MOS transistors Q1x and Q2x, and in the driver circuit of the gate X of power switch X, the SR gate is replaced by MOS transistors Q1y and Q2y.

[0043] These MOS transistors receive a mirror image of the gate driver current through transformers TRx and Try, which replace optocoupler 52a to provide a second electrical insulation.

[0044] Here, the mirror image of the gate driver current from switch Y passes through Schottky diode D1x and enters the gate of Q2x to provide signal GPx, which pulls down the gate buffer of switch X. The mirror image of the gate driver current from switch X passes through Schottky diode D1y and enters the gate of Q2y to provide signal GPy, which pulls down the gate buffer of switch Y.

[0045] On the other side, the O+ signal of switch Y is provided by inverter 71 as signal RSTy, which is provided to pull down the gate of MOS transistor Q2y through transistor Q1y. The O+ signal of switch X is provided by another inverter 71 as signal RSTx, which is provided to pull down the gate of MOS transistor Q2x through MOS transistor Q1x.

[0046] This second implementation mode, based solely on transistors and passive components, is, for example... Figure 2 The logic components are easier to embed into the power module and provide the same functionality.

[0047] The disclosed circuit provides a simple method to reduce the overlap of switching on without causing an open circuit condition, because the method is based on detecting the transition of a first switch from off to on to anticipate the transition of a second switch, controlled in a complementary manner to the first switch, from on to off.

[0048] This invention is not limited to the circuit described herein, and as an example, the described control circuit combines the gate command signals and gate pull-down detection signals of the three half-bridges by using modified logic circuitry and insulating components, and can be applied to [the following]... Figure 4 A three-phase output current source converter. This disclosure can also be applied to DC / AC converters and AC / DC converters (where the source and load are reversed).

[0049] In addition, the present invention can be combined with circuits designed to protect current source converters, such circuits using current sinking mirror circuits, similar to the depicted source current mirror.

[0050] [List of reference symbols]

[0051] 2...Inductor 6...Buffer 7...Pre-driver 11, 13...Upper Switching Device 12, 14...Lower Switching Device 40...Controller 51...Gate Current Mirror Circuit 52...Second Electrical Insulation 52a...Optocoupler 53...SR Gate 71...Inverter Gate Cl...Control Lines C2x, C2y...Filter Capacitor G+...Positive Gate Command Connection Path GPx, Gpy...Gate Pull-down Signals Q2x, Q2y...MOS Transistor RSTx, RSTy...Reset Signal Q1x, Q1y...MOS Transistor TRx, TRy...Transformer T5x, T5y...Current Mirror Transistor

Claims

1. A control circuit for a current source converter, the current source converter having A current generator including an inductor, and having Two or more half-bridges, each half-bridge having an upper branch and a lower branch, the upper branch having an upper switching device and the lower branch having a lower switching device, the upper branch switching devices and the lower branch switching devices being controlled by a controller to provide overlap between the upper branch turn-off switching device and the upper branch turn-on switching device, and to provide overlap between the lower branch turn-on switching device and the lower branch turn-off switching device, by means of gate pull-up pulse signals and gate pull-down pulse signals input to the gate driver buffers of the switching devices. The gate driver circuit includes: - A gate current mirror circuit for each upper branch switching device and each lower branch switching device, the gate current mirror circuit being on the source branch of the gate driver buffer of the switching device, providing a gate pull-down signal when the switching device is turned off, the gate pull-down signal being connected to the control line of the gate buffer of the corresponding other upper branch switching device or the other lower branch switching device. - A positive gate command connection path originating from the positive gate command output of the pre-driver for each upper branch switch and each lower branch switch, the positive gate command connection path providing a reset signal for the gate pull-down signal of the corresponding other upper branch switch and the corresponding other lower branch switch.

2. The control circuit according to claim 1, wherein... The gate pull-down signal is received from the MOS transistor output by the gate receiving pulse generated from the gate current mirror circuit, and the MOS transistor has or does not have a filter capacitor between the gate and source.

3. The control circuit according to claim 1, wherein... The gate pull-down signal is the output of the SR gate, which takes the current mirror of the gate current as its input, and the gate pull-down signal is generated from the gate current mirror circuit.

4. The control circuit according to claim 1, further comprising: An inverter gate that provides the reset signal from the positive gate command connection path.

5. The control circuit according to claims 2 and 4, wherein The reset signal polarizes the gate of the MOS transistor to discharge the gate of the MOS transistor or to discharge the gate of the MOS transistor and the filter capacitor.

6. The control circuit according to claims 3 and 4, wherein The reset signal is connected to the reset input of the SR gate.

7. The control circuit according to any one of claims 1 to 6, wherein The pre-driver provides a first electrical insulation between the controller circuitry and the gate buffer.

8. The control circuit according to any one of claims 1 to 7, further comprising: A second electrical insulator between the gate current mirror circuit and the gate pull-down signal circuit.

9. The control circuit according to claim 8, wherein... The second electrical insulation is provided by a transformer in the collector branch of a current mirror transistor.

10. The control circuit according to claim 8, wherein The second electrical insulation is provided by an optocoupler in the collector branch of a current mirror transistor.

11. A converter, such as an inverter, comprising: Current source Controller At least two half-bridges, each half-bridge having an upper branch switching device and a lower branch switching device, each of which is controlled by the controller via a gate driver, wherein... The gate driver includes a control circuit according to any one of claims 1 to 10.

12. A method for switching power switching devices of a branch of a half-bridge of a current source converter with a shortened overlap time, wherein the on / off state of the power switching devices of the branch is driven by a controller via a gate driver having a gate buffer, characterized in that: During a switching transition between a first upper branch power switch and a second upper branch power switch, or between a first lower branch power switch and a second lower branch power switch, the switching transition is initiated by the controller via the gate driver of the power switch, the method comprising: Before the gate pulse generated from the controller is input to the gate driver of the second switching device, a mirror gate current or a voltage proportional to the mirror gate current from one of the power switching devices transitioning from the off state to the on state is used to transition the other of the switching devices from the on state to the off state, the gate pulse being provided for transitioning the other of the switching devices from the on state to the off state.

13. The method of claim 12, further comprising: A gate pull-down pulse signal is provided, generated from the mirror gate current or a voltage proportional to the mirror gate current, the gate pull-down pulse signal being used to switch the other of the switching devices from the on state to the off state.

14. The method according to claim 12 or 13, wherein The mirror gate current is the mirror source current of the gate buffer that drives the power switching device.

15. The method of claim 13, further comprising: The mirror gate current or a voltage proportional to the mirror gate current is latched to provide the gate pull-down pulse signal, and the gate pull-down pulse signal is reset at the end of the transition.

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