Hybrid bonded inverted memory-logic component stack

Abstract

The memory layer and the digital device layer are configured as a three-dimensional integrated circuit (IC) die stack. The digital device layer (304) has a first surface (side) positioned closest to the cooling solution (308), and the memory layer is positioned on a second surface (side) of the digital device layer opposite the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer (304) and the memory layer (302). Through-silicon vias (TSVs) (314) through the memory layer and reaching the digital device layer are used to interconnect signals, controls, and power supply voltages to circuitry in these layers. Some of the TSVs are used to couple to external connections of the memory stack device. The digital device layer can be a complex electronic device layer such as a microprocessor or microcontroller for improved high speed signal transfer.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to integrated circuit packages of memory and logic component dies, and more specifically to configurations of memory and logic component dies arranged in a stack for use in integrated circuit packages, which have improvements in thermal management of these integrated circuit packages. Background Technology

[0002] Vertically stacked and interconnected memory and logic components (e.g., processors and peripherals) dies are attracting interest from memory and processor vendors and users with the aim of further increasing memory bandwidth, reducing memory latency, reducing data movement power, and increasing component integration density. Current literature / prior art focuses on packaging topologies that stack memory dies on top of logic component dies. These topologies can lead to significant thermal challenges because the memory die acts as the primary thermal insulator between the typically hotter logic component (processor) die and the cooling solution (e.g., a heatsink), trapping processor heat and resulting in higher die temperatures, lower performance, and reduced reliability. Considerations and use of microbump-based memory die interconnects have poor thermal / electrical conductivity properties because the microbump spacing between dies and the filler material between dies further reduce the thermal conductivity of the die stack.

[0003] Memory (e.g., dynamic random access memory (DRAM)) comprising stacked semiconductor dies (e.g., high-bandwidth memory (HBM)) in integrated circuit packages faces thermal challenges due to the potentially large number of layers in the stacked semiconductor dies. These potentially large number of layers introduce increased thermal resistance to heat dissipation of cooling solutions from the bottom to the top of the die stack. Typically, most of the power generation / consumption of a memory die stack originates from the bottom layer, which may contain at least one digital processor, including computational logic components, physical electronics (PHY layer) for serializers / deserializers (SerDes), address, read, write, and refresh logic components, data and address input receivers and output drivers, and DC voltage regulators for interfacing with the memory and external circuitry. The processor computational logic components and PHY layer consist largely of higher-activity / higher-power circuitry located at the bottom of the die stack within the integrated circuit package, furthest from cooling solutions (e.g., finned air-cooled radiators, liquid-cooled pipes) typically located at the top of the integrated circuit package. Therefore, the heat generated from the processor's computing logic components and the PHY layer die must travel through the memory layer die.

[0004] Excessive heat in memory circuitry can lead to performance degradation and require more frequent and higher refresh power to maintain the memory data stored within. Currently, the primary solutions for dealing with high memory temperatures are to somehow slow down the memory / computer system to reduce power consumption sufficiently to mitigate excessive heat, and / or to use more expensive / unique cooling solutions (e.g., liquid cooling, cold plates, immersion cooling), neither of which is desirable. Another solution to ensure reliable DRAM operation at higher temperatures is to increase the refresh rate, which ultimately results in lower performance / fewer instructions per cycle (IPC) and increased power consumption. Summary of the Invention

[0005] In one example of this disclosure, an IC die stack includes a digital device layer having a memory interface; a cooling solution located on a first side of the digital device layer; and multiple memory layers located on a second side of the digital device layer opposite to the first side.

[0006] In one example of this disclosure, an IC die stack includes a first digital device layer having at least two memory interfaces; a cooling solution located on a first side of the first digital device layer; at least two memory stacks, each memory stack including a plurality of memory layers located on a second side of the first digital device layer opposite to its first side; an interface layer located between the first digital device layer and the at least two memory stacks; and a package substrate coupled to the at least two memory stacks on a side opposite to the first digital device layer.

[0007] In one example of this disclosure, an IC die stack includes a plurality of computing modules, wherein at least one of the plurality of computing modules has a memory interface. A cooling solution is located on a first side of the plurality of computing modules. At least two memory stacks, each memory stack including a plurality of memory layers located on a second side of the plurality of computing modules opposite to their first side. Interpolation layers are located between the plurality of computing modules and the at least two memory stacks. A bridge electrically couples these interpolation layers. A package substrate is coupled to the at least two memory stacks on a side opposite to the first digital device layer. Attached Figure Description

[0008] To gain a more detailed understanding of the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to examples, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical examples of the invention and should therefore not be considered as limiting the scope of the invention, as the invention may allow for other equivalent embodiments.

[0009] Figure 1 A representative schematic elevation section layout of existing technology memory, peripheral logic components and microprocessor stacks is illustrated.

[0010] Figure 2 Representative schematic elevation sectional layouts of other existing technology memory and processor stacks are illustrated.

[0011] Figure 3 A representative schematic elevation section layout of a three-dimensional digital device / memory stack with digital device layers interposed between a cooling solution and multiple memory layers is illustrated according to an example.

[0012] Figure 4 A representative schematic elevation section layout of a three-dimensional digital device / memory stack, according to an example, is shown, illustrating the power, ground, and signal connections between a digital device layer having multiple memory layers and a package substrate.

[0013] Figure 5 A representative schematic elevation cross-sectional layout of a three-dimensional digital device / memory stack, according to an example, is shown, illustrating a through-hole / through-dielectric via (TDV) directly between the digital device and the package substrate.

[0014] Figure 6 and Figure 7 A representative schematic elevation section layout of a three-dimensional memory stack, according to an example, is shown, having at least one non-memory silicon die located next to the memory stack, providing direct connectivity between the digital device and the package substrate.

[0015] Figure 8 A representative schematic elevation section layout of a three-dimensional digital device / memory stack, according to an example, is shown, illustrating multiple computing modules and active interpolator layers located between a cooling solution and multiple memory layers.

[0016] Figure 9 A representative schematic elevation section layout of a three-dimensional digital device / memory stack with digital device layers interposed between multiple stacks of cooling solutions and multiple memory layers is illustrated according to an example.

[0017] Figure 10 and Figure 11A representative schematic elevation section layout of a three-dimensional digital device / memory stack using different types of electrical bonding techniques is illustrated according to the example.

[0018] Figure 12 and Figure 13 A representative schematic elevation section layout of a three-dimensional digital device / memory stack is illustrated, having at least two digital device modules connected to at least two memory stacks via various silicon bridging technologies.

[0019] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures, and lowercase letters are added where elements are substantially the same. It is conceivable that elements of one embodiment can be advantageously incorporated into other embodiments. Detailed Implementation

[0020] refer to Figure 1 This diagram depicts a representative schematic elevation cross-sectional layout of a prior art memory, peripheral logic component, and microprocessor stack. The three-dimensional memory (e.g., dynamic random access memory (DRAM)), peripheral logic component, and microprocessor stack, generally indicated by reference numeral 100, comprises multiple integrated circuit (IC) semiconductor wafers: a DRAM layer 102, a peripheral logic component layer 104, and a processor core layer 106 stacked vertically one on top of the other, with the processor core layer 106 located at the bottom of the stack of DRAM layers 102. A cooling solution 108 (e.g., a heatsink with fins, a liquid cooling pipe, etc.) is implemented on top of the DRAM, peripheral logic component, and microprocessor stack 100 and receives and dissipates heat from the DRAM layer 102, peripheral logic component layer 104, and processor core layer 106. Figure 1 An example three-dimensional DRAM, peripheral logic components, and microprocessor stack 100 (e.g., a system-on-a-chip (SoC)) is depicted, which is typical of current technology implementations for high-capacity and high-speed memory (e.g., high-bandwidth memory (HBM)). The bottom-facing peripheral logic component layer 104 may consist of circuitry to the DRAM layer 102 and the processor core layer 106. The bottom-facing processor core layer 106 may be electrically coupled to the peripheral logic component layer 104, the DRAM layer 102, and external IC package connections (e.g., primarily power delivery and memory interface signals (address, command, and data signals) to the DRAM layer 102 and the peripheral logic component layer 104), and may also include additional circuitry and connections for debugging, testing, control, etc., of the DRAM layer 102, the peripheral logic component layer 104, and the processor core layer 106.

[0021] The peripheral logic layer 104 and processor core layer 106 are positioned closest to the substrate for external interconnections of the SoC integrated circuit package. This is typically because the peripheral logic layer 104 and processor core layer 106 have numerous electrical connections, such as for power, ground, and data / address input / output (I / O). When the peripheral digital device core die is located at the bottom of the stack 100, these electrical connections are more easily routed from the peripheral logic layer 104 and processor core layer 106 (die) to the IC package substrate, such as... Figure 1 As shown. However, this leads to thermal conduction challenges, as heat from the peripheral logic layer 104 and the processor core layer 106 faces increased thermal resistance due to the memory layer 102 being located between the peripheral logic layer 104 / processor core layer 106 and the cooling solution 108.

[0022] In particular, the memory and peripheral logic unit interfaces of the processor core layer 106 typically operate at very high speeds to achieve high data rate capacity transfer performance. Memory interface circuitry operating at high data transfer rates can consume a significant amount of power. The power consumption of stack 100 generates heat (flame icon 110), which must then travel upwards through the rest of stack 100 (memory layer 102) to reach the heat-removable cooling solution 108. In a high-bandwidth memory (HBM) processor stack, for example, approximately 40 percent or more of the total power can be dissipated within the processor core layer 106. As the DRAM layers 102 are stacked higher (e.g., eventually reaching 12 to 16 layers high), the temperature of the processor core layer 106 and peripheral logic unit layer 104 can increase dramatically due to the distance between the processor core layer 106 and peripheral logic unit layer 104 and the cooling solution 108, and the insulating properties of the DRAM layers 102. This increased temperature, particularly for DRAM circuitry, can impact performance (due to the need for more frequent refreshes), power consumption (again due to the need for more frequent refreshes), and reliability.

[0023] Several 3D integrated circuit (IC) stack configurations with a processor positioned between the memory layer and the cooling solution have been designed and evaluated. In one design / research project (“3D-MAPS: 3D Massively Parallel Processor with Stacked Memory” by Dae Hyun Kim et al. at ISSCC 2012), an academic prototype positioned the processor between the memory and the cooling solution. This design has several challenges / drawbacks that make it impractical for serious industrial / commercial use. For example, all power (and I / O) conductors are routed around the outside / periphery of the entire logic component / memory stack and then delivered to the side of the logic component die opposite to the side at the memory. Modern high-power IC dies cannot reliably receive all their power / current from the die periphery alone without suffering significant voltage (IR) drops. Furthermore, routing the power and ground conductors to the top of the logic component die at the top of the stack necessarily isolates the top silicon layer (digital device die) from the cooling solution. This suppresses heat transfer from the digital device die to the cooling solution because a molding compound (thermal insulator) must be used to separate the top of the digital device die from the thermal interface material (TIM) and the heat sink (cooling solution).

[0024] Another existing technical paper considers a 3D stack of memory with microbump connections located beneath the processor die. This is from Agarwal et al. at MICRO 2017. "Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks ( Xylem Enhancement 3D processor - Vertical heat conduction in memory stacks ” . refer to Figure 2 This depicts a representative schematic elevation section layout of other existing technology memory and processor stacks. Figure 2 In (a), the processor is placed above the memory (DRAM), and power and ground are coupled to the processor via through-silicon vias (TSVs) and microbumps. These TSVs and microbumps cause a significant voltage (IR) drop from the motherboard to the processor. This is why existing 3D memory / processor stacks place the processor closest to the printed circuit motherboard with its high-current landing pads, as... Figure 2 (b) shows. However, when the processor is placed closest to the printed circuit board, the multiple die-to-die (D2D) layers between silicon wafers and surrounding the microbumps add significant thermal resistance between the processor and the cooling solution (heat sink).

[0025] According to the teachings of this disclosure, digital device layers and multiple memory layers (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), serial shift registers, eDRAM, flash memory, phase-change memory, resistive RAM, ferromagnetic RAM, spin-torque transfer RAM, etc.) can be configured in a three-dimensional memory stack. This digital device / memory stack may have a logic / processing layer and multiple memory layers that are inverted from the construction of prior art memory stacks. The inverted memory stack has a first surface (side) of the logic / processing layer located closest to the cooling solution and multiple memory layers located on a second surface (side) of the memory interface layer opposite to its first surface (side). This inverted digital device / memory stack configuration substantially mitigates and / or alleviates the thermal challenges of efficiently removing heat from the memory interface layer because it is now closest to the cooling solution and is not thermally insulated by the memory layers.

[0026] Placing the higher-heat-generating digital device (DD) layer closer to the cooling solution improves the efficiency of heat transfer from this layer. Placing the memory layer between the DD layer and the substrate for coupling to the printed circuit board requires power conductors to have sufficient current-carrying capacity and sufficiently low voltage drop from the substrate through the memory layer to the DD layer. This can be achieved by eliminating microbumps in the power delivery path and replacing them with metal bonding pads (e.g., hybrid bonding, copper hybrid bonding) with significantly lower resistance. This addresses the significant voltage drop issue associated with using microbumps for power circuit connections. An added benefit is the elimination of die-to-die (D2D) layers between silicon wafers, allowing direct metal-to-metal electrical connections (hybrid bonding) between die layers, further reducing the resistance of these connections. Another added benefit is the elimination of power, ground, and signal TSVs through the DD die. Therefore, removing the need to drill vias to the (expensive) DD die with TSVs, which would otherwise be required when the DD logic components are positioned between the substrate and the memory layer, is a significantly beneficial factor in DD die manufacturing. Some current and future cutting-edge silicon digital device designs may not support TSVs. Furthermore, memory dies have a more free die area available for TSVs to pass through compared to dies for complex digital devices.

[0027] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of features of these examples. They are not intended to provide an exhaustive description of the following examples, nor are they intended to limit the scope of the claims. Furthermore, the illustrated examples need not possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described. Referring now to the drawings, the details of the examples are representative layouts schematically illustrated. The same elements in the drawings will be indicated by the same numerals, and similar elements will be indicated by the same numerals with different lowercase letter suffixes.

[0028] refer to Figure 3 This image depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack with digital device layers interposed between a cooling solution and multiple memory layers, according to an example. The three-dimensional digital device / memory stack, generally indicated by reference numeral 300, includes a digital device layer 304 and multiple integrated circuit (IC) semiconductor memory (die) layers 302 stacked vertically below it, with the digital device layer 304 being closest to the cooling solution 308. The cooling solution 308 may be a heat dissipation device with heat transfer enhancement structures, such as, but not limited to, a heat sink, a finned heat sink, a liquid cooling pipe, an evaporation chamber, a heat pipe, a cold plate, etc.

[0029] Cooling solution 308 is adapted to receive and dissipate heat from digital device layer 304 and multiple memory layers 302. Digital device layer 304 adjacent to cooling solution 308 may include interface circuitry for external IC package connections (e.g., memory interface signals (address, command, and data) to memory layers 302 and / or digital device layer 304), and may also include other circuitry and connections for debugging, testing, control, etc., of the multiple memory layers 302. Power delivery to the multiple memory layers 302 and digital device layer 304 may be provided directly from the bottom of stack 300, for example, via package substrate 312 (part of an integrated circuit package), which has electrical connections (e.g., ball grid arrays) suitable for coupling to printed circuitry.

[0030] The higher power dissipation circuitry (digital device layer 304) can be placed adjacent to the cooling solution 308 within the digital device / memory stack 300, rather than having multiple memory layers 302 located between the higher power dissipation circuitry and the cooling solution. This significantly reduces the thermal resistance between the circuitry in digital device layer 304 and the cooling solution 308, allowing the multiple memory layers 302 to maintain lower operating temperatures. Most of the heat is generated by digital device layer 304 and travels a much shorter distance to the cooling solution 308, as indicated by flame arrow 310. Digital device die (layer) 304 is typically not thinned (or not as much as other memory layers 302) because it does not require integration with through-silicon vias (TSVs). This, in turn, improves lateral heat diffusion by reducing thermal resistance, a key property for reducing the severity of localized semiconductor die hotspots. Several considerations exist for this organization. First, connections from external signal paths (address / command / data) must be routed through multiple memory layers 302 to the digital device layer 304, which may require more TSVs for power and ground, which in turn increases the die area required for the TSVs of each of the multiple memory layers 302.

[0031] Through-silicon vias (TSVs) 314 through multiple memory layers 302 can be used to electrically connect digital device layers 304 to a package substrate 312. Multiple TSVs 314 can be used to provide power and ground conductors to ensure sufficient power delivery to the digital device layers 304 (minimizing voltage drop). TSVs 314 can be distributed across various locations within the multiple memory layers 302 to provide sufficient current carrying capacity to different regions of the digital device layers 304. Depending on the layout of the stacked memory layers 302, if the TSVs 314 can be placed in empty / unused areas of the multiple memory layers 302, these TSVs may not significantly increase area overhead. Otherwise, additional silicon area within the memory layers 302 can be allocated to accommodate additional TSVs 314 for power and ground. For example, for a TSV 314 with a 9µm pitch, each capable of carrying 10mA of current (slightly conservative compared to current designs), to support 100 watts of power at 100 amps and one (1) volt, approximately 1.62mm² of 10,000 TSVs (10mA each) for voltage plus 10,000 TSVs for return current (ground) would be required. 2 The area. Considering that 3D memory stacks (such as high-bandwidth memory (HBM)) have an area greater than 100 mm². 2 The area is 1.62 mm. 2It has an area overhead of only about 1.62% or less. Additional TSVs 314 can be similarly assigned for input-output (I / O) signals, and these additional TSVs connect the digital device layer 304 to the package substrate 312 via multiple memory layers 302. Flush conductive pads 316 can be used to electrically connect the TSVs 314 using, for example, but not limited to, hybrid bonding, copper hybrid bonding. The face of the connection pads 316 is polished to be substantially flush with the surface of the silicon die. The connection pads 316 of the semiconductor die are then electrically connected using hybrid bonding. The peripheral logic component 104 and processor core 106 layers have multiple memory layers 102 between them and the cooling solution 108. Figure 1 Compared to the enormous effort that would otherwise be required, the incremental area overhead of using multiple memory layers 302 is preferable.

[0032] refer to Figure 4 This illustration depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack, illustrating power, ground, and signal connections between a digital device layer with multiple memory layers located therebetween and a package substrate, according to an example. The three-dimensional digital device / memory stack, generally indicated by reference numeral 400, includes a digital device layer 304, multiple integrated circuit (IC) semiconductor memory (die) layers 302 stacked vertically below each other and located between the digital device layer 304 and the package substrate 312. The digital device layer 304 is closest to the cooling solution 308 for optimal cooling. Multiple TSVs 422 for DC+ power and DC- ground deliver the power required by the circuitry of the digital device layer 304 and the multiple memory layers 302. TSVs 420 can be provided for all input-output (I / O), control, and test signal requirements as needed. TSVs 420 and 422 represent I / O control and power connections between the package substrate 312 and the circuitry of the digital device layer 304. The digital device layer 304 also provides power and I / O signals to the multiple memory layers 302.

[0033] refer to Figure 5 This depicts a representative schematic elevation cross-sectional layout of a three-dimensional digital device / memory stack, illustrating a through-hole / through-dielectric via (TDV) directly located between the digital device and the package substrate, according to an example. The three-dimensional digital device / memory stack, generally indicated by reference numeral 500, is essentially... Figure 4A digital device / memory stack 400 is constructed in which through-mold / through-dielectric vias (TDVs) 524, 526 are added directly between the digital device layer 304 and the package substrate 312, bypassing multiple memory layers 302. These TDVs 524, 526 may potentially be larger (in diameter) than TSVs 420, 422, and thus have lower resistance and higher current carrying capacity, both of which can benefit power delivery (to reduce, for example, but not limited to, IR drop, better electromigration characteristics) or signal integrity of I / O signals (lower resistance-capacitance (RC) of TDV 524). TDV 524 can be used for signal I / O, and TDV 526 can be used for power and power common (ground). TDVs 524, 526 can be encapsulated in molding material 528, and the size and number of these TDVs are limited only by the area / volume available between the digital device layer 304 and the package substrate 312.

[0034] refer to Figure 6 and Figure 7 This depicts a representative schematic elevation section layout of a three-dimensional memory stack, according to an example, having at least one non-memory silicon die located next to the memory stack, providing direct connectivity between the digital device and the package substrate. In one example, the overall designation is marked 600 ( Figure 6 The three-dimensional digital device / memory stack represented by () may include a passive silicon die 630, which includes only electrical connections from the digital device layer 304 to the package substrate 312. These electrical connections may be coupled to a TDV 626 for DC power and ground and a TDV 624 for input-output (I / O) signals.

[0035] In another example, the total is marked 700 ( Figure 7 The three-dimensional memory stack represented by () may include an active silicon die 730 having, for example, but not limited to, input-output drivers and associated logic components. A TDV 724 may be connected from the digital device layer 304 to circuitry within the active silicon die 730, which can then be connected to the package substrate 312 for directly driving package-level signals. This can be advantageous because it allows more sensitive analog I / O circuitry to directly interface with the package substrate, which is consistent with... Figure 6 The I / O driver shown must compete with the additional resistor-capacitor (RC) time delay introduced by the TDV 624 to access the package interface 312.

[0036] refer to Figure 8This paper depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack, according to an example, showing multiple computing modules and active interpolator layers located between a cooling solution and multiple memory layers. The logic component portion may consist of more complex modules comprising multiple logic devices integrated together to form a composite semiconductor module. The three-dimensional digital device / memory stack, generally indicated by reference numeral 800, may include multiple computing modules (chiplets) 840, active interpolator layers 842 coupled to the multiple computing modules 840, multiple memory layers 302, and a package substrate 312. The multiple computing modules 840 are adjacent (closest to) the cooling solution 308 for optimal cooling of it. The multiple computing modules 840 and the active interpolator layers 842 constitute a composite semiconductor module 844. The active interpolator layers 842 are also electrically coupled to the multiple memory layers 302. Electrical connections between the active interpolator layers 842 and the package substrate 312 can be made via TSV and TDV, as shown and disclosed herein. The computing module 840 may be, for example, but not limited to, a microcontroller, microprocessor, mixed signal processor, central processing unit (CPU), programmable logic array (PLA), application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), field-programmable gate array (FPGA), neural processing unit, tensor processing unit, etc.

[0037] refer to Figure 9 This paper depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack having digital device layers interposed between multiple stacks of cooling solutions and multiple memory layers, according to an example. The three-dimensional digital device / memory stack, generally indicated by reference numeral 900, includes a digital device layer 304 and at least two memory stacks 902a, 902b. Each memory stack 902a, 902b includes multiple memory layers 302 stacked vertically below each other, with the digital device layer 304 adjacent (closest to) the cooling solution 308. The digital device layer 304 is electrically coupled to at least two memory stacks 902a, 902b. Electrical connections between the digital device layer 304 and the package substrate 912 can be made via TSV 920 / 922, as shown and disclosed herein.

[0038] refer to Figure 10 and Figure 11 This depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack using different types of electrical bonding technologies, based on an example. (Example) Figure 10 As shown, the three-dimensional digital device / memory stack, generally indicated by label 1000, can utilize microbump or copper micropillar technology to electrically interconnect the digital device layer 304 to multiple memory layers 302, wherein the microbump / micropillar interface 1050 is located between the digital device layer and the multiple memory layers. Figure 11 As shown, the three-dimensional digital device / memory stack, generally indicated by reference numeral 1100, may include a hybrid bonding interface 1152 that electrically interconnects the digital device layer 304 to multiple memory layers 302 using a hybrid bonding technique.

[0039] While the microbump / micropillar interface 1050 results in higher resistance compared to using hybrid bonding, the digital device / memory stack 1000 can use microbumps only at a single memory and logic component interface (while continuing to utilize hybrid bonding within the memory stack itself), which is much more manageable in terms of resistance / IR drop issues. This is related to... Figure 1 This is compared to the prior art method shown (Agarwal et al.), in which microbumps are used between each layer of the memory stack 100 (which would be a much more challenging voltage drop (IR) situation to deal with in modern DRAM stacks that are up to eight layers deep).

[0040] The information disclosed in this article Figures 3 to 11 The examples shown and their descriptions may include multiple digital device modules connected via various silicon bridging technologies. Reference Figure 12 and Figure 13 The paper depicts a representative schematic elevation section layout of a three-dimensional digital device / memory stack having at least two digital device modules connected to at least two memory stacks via various silicon bridging technologies.

[0041] Figure 12 A three-dimensional digital device / memory stack, generally indicated by reference numeral 1200, is shown. This stack may include a first digital device layer 1204a / 1206a and a second digital device layer 1204b / 1206b in close thermal proximity to a cooling solution 1208. Using any of the aforementioned interconnect technologies, the first digital device layer 1204a / 1206a is electrically coupled to the first memory stack 1202a via interface 1252a. Using any of the aforementioned interconnect technologies, the second digital device layer 1204b / 1206b is electrically coupled to the second memory stack 1202b via interface 1252d. A silicon bridge 1254 may be used to provide electrical coupling between the first and second digital device layers using the silicon bridge and the interface layers 1252b and 1252c between the silicon bridge and the first and second digital device layers 1204a / 1206a and 1204b / 1206b. Microbump / micropillar technology can be used for connections to interface layer 1252. The first digital device layer 1204a / 1206a and the second digital device layer 1204b / 1206b can be connected to the package substrate 1212 using TSV and / or TDV (not shown) as disclosed herein.

[0042] Figure 13 A three-dimensional digital device / memory stack, generally indicated by reference numeral 1300, is shown. This stack may include multiple computing modules 1340, at least two interpolators 1356, a bridge 1354, at least two memory stacks 1202, and a package substrate 1312. The computing modules 1340 are in close thermal proximity to a cooling solution 1308. Some of the computing modules 1340a and 1340b are electrically coupled to a first memory stack 1202a using a first interpolator 1356a, and some other computing modules 1340c and 1340d are electrically coupled to a second memory stack 1202b using a second interpolator 1356b. The interpolators 1356 may be active or passive. A silicon bridge 1354 may be used to provide electrical coupling between the first active interpolator 1356a and the second active interpolator 1356b. Interconnections between multiple computing modules 1340, at least two active interpolators 1356, bridges 1354, at least two memory stacks 1202, and package substrate 1312 can be fabricated using a composite structure employing hybrid bonding techniques (e.g., hybrid-bonded small outline integrated circuit (SOIC)-L bridges, etc.). Connections from individual layers to the package substrate 1312 can be made using TSVs and / or TDVs (not shown) as disclosed herein. Within the scope of this invention, it is contemplated that interpolators 1356 may be active or passive.

[0043] Placing digital devices / computing modules on top of active interpolators on top of the memory stack provides a more natural data flow from cache misses (core chiplets) to the data architecture and from the memory controller (active interpolator) to the memory. Within the scope of this invention, it is envisioned that semiconductor memory may consist of one or more memory technologies, including but not limited to DRAM, SRAM, PCM, FeRAM, STT-MRAM, eDRAM, etc. One or more memory layers may include additional functionality such as computation or processing (e.g., processing in memory, or PIM). Furthermore, the use / need for TSVs (Through-the-Memory Vessels) traversing the most expensive logic components / computing chiplets is avoided.

[0044] As will be understood and benefited by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, apparatus, or computer-programmed products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0045] The techniques disclosed above can also be expressed in the following non-limiting embodiments.

[0046] Example 1. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: a digital device layer having a memory interface; a cooling solution located on a first side of the digital device layer; and a plurality of memory layers located on a second side of the digital device layer opposite to its first side.

[0047] Example 2. According to the IC die stack of Example 1, the IC die stack further includes a packaging substrate, which is attached to the side opposite to the digital device layer of the plurality of memory layers.

[0048] Example 3. The IC die stack according to Example 1, wherein the digital device layer and the plurality of memory layers are electrically interconnected.

[0049] Example 4. The IC die stack according to Example 2, wherein the digital device layer and the plurality of memory layers are electrically interconnected by through-silicon vias (TSVs).

[0050] Example 5. An IC die stack according to Example 4, wherein the TSV is adapted to be coupled to an external connection on the package substrate.

[0051] Example 6. The IC die stack according to Example 5, wherein the external connections are adapted to couple to power supply, ground, and input-output and control signals.

[0052] Example 7. The IC die stack according to Example 1, wherein the digital device layer is selected from any or a combination of the following: microcontroller, microprocessor, mixed signal processor, central processing unit (CPU), programmable logic array (PLA), application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), field-programmable gate array (FPGA), neural processing unit, and tensor processing unit.

[0053] Example 8. According to the IC die stack of Example 1, the plurality of memory layers are selected from the group consisting of: dynamic random access memory (DRAM), static random access memory (SRAM), serial shift register, eDRAM, flash memory, phase change memory, resistive RAM, ferromagnetic RAM and spin torque transfer RAM.

[0054] Example 9. The IC die stack according to Example 1, wherein the cooling solution is a heat dissipation device with a heat transfer enhancement structure, the heat dissipation device being selected from the group consisting of: heat sink, finned heat sink, liquid cooling pipe, evaporation chamber, heat pipe and cold plate.

[0055] Example 10. According to the IC die stack of Example 2, the IC die stack further includes a through-hole / through-dielectric via (TDV), which is adapted to directly couple power, ground, and input-output and control signals between the digital device layer and the package substrate.

[0056] Example 11. The IC die stack according to Example 10, wherein the IC die stack further includes a passive silicon die, the passive silicon die being directly coupled to the digital device layer and the packaging substrate via TDV.

[0057] Example 12. The IC die stack according to Example 10, wherein the IC die stack further includes an active silicon die, the active silicon die being directly coupled to the packaging substrate and the digital device layer via TDV.

[0058] Example 13. The IC die stack according to Example 1, wherein the digital device layer includes a plurality of computing modules, and at least one of the plurality of computing modules has a memory interface.

[0059] Example 14. According to the IC die stack described in Example 13, the IC die stack further includes an active interpolator layer, which is located between the plurality of computing modules and the plurality of memory layers.

[0060] Example 15. The IC die stack according to Example 1 further includes a logic component layer electrically coupled to the digital device layer.

[0061] Example 16. The IC die stack according to Example 1, wherein the metal pads between the plurality of memory layers are coupled together using hybrid bonding.

[0062] Example 17. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: a first digital device layer having at least two memory interfaces; a cooling solution located on a first side of the first digital device layer; at least two memory stacks, each memory stack comprising a plurality of memory layers located on a second side of the first digital device layer opposite to its first side; an interface layer located between the first digital device layer and the at least two memory stacks; and a package substrate coupled to the at least two memory stacks on a side of the at least two memory stacks opposite to the coupling of the first digital device layer.

[0063] Example 18. The IC die stack according to Example 17, the IC die stack further includes a second digital device layer and a bridge, the bridge coupling the first digital device layer and the second digital device layer through the interface layer.

[0064] Example 19. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: A plurality of computing modules, wherein at least one of the plurality of computing modules has a memory interface; a cooling solution located on a first side of the plurality of computing modules; at least two memory stacks, each memory stack including a plurality of memory layers located on a second side of the plurality of computing modules opposite to their first side; an interpolator layer located between the plurality of computing modules and the at least two memory stacks; a bridge electrically coupling the interpolator layer; and a package substrate coupled to the at least two memory stacks on the side of the at least two memory stacks opposite to the side coupled to the interpolator layer.

[0065] Example 20. An IC die stack according to Example 19, wherein the interpolator layer includes active logic components.

[0066] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: A digital device layer having a memory interface; A cooling solution, wherein the cooling solution is located on the first side of the digital device layer; and Multiple memory layers are located on a second side of the digital device layer opposite to its first side.

2. The IC die stack according to claim 1, wherein the IC die stack further comprises a packaging substrate attached to the opposite side of the plurality of memory layers to which the digital device layers are attached.

3. The IC die stack according to claim 1, wherein the digital device layer and the plurality of memory layers are electrically interconnected.

4. The IC die stack of claim 2, wherein the digital device layer and the plurality of memory layers are electrically interconnected by through-silicon vias (TSVs).

5. The IC die stack according to claim 1, wherein the digital device layer is selected from any or a combination of the following: microcontroller, microprocessor, mixed signal processor, central processing unit (CPU), programmable logic array (PLA), application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), field-programmable gate array (FPGA), neural processing unit, and tensor processing unit.

6. The IC die stack according to claim 1, wherein the plurality of memory layers are selected from the group consisting of: dynamic random access memory (DRAM), static random access memory (SRAM), serial shift register, eDRAM, flash memory, phase change memory, resistive RAM, ferromagnetic RAM, and spin torque transfer RAM.

7. The IC die stack according to claim 2, wherein the IC die stack further includes a through-hole / through-dielectric via (TDV), the through-hole / through-dielectric via (TDV) being adapted to directly couple power, ground, and input-output and control signals between the digital device layer and the package substrate.

8. The IC die stack according to claim 7, wherein the IC die stack further includes a passive silicon die or an active silicon die, wherein the passive silicon die or the active silicon die is directly coupled to the packaging substrate and the digital device layer via TDV.

9. The IC die stack according to claim 1, wherein the digital device layer comprises a plurality of computing modules, and at least one of the plurality of computing modules has a memory interface.

10. The IC die stack according to claim 9, wherein the IC die stack further comprises an active interpolator layer, the active interpolator layer being located between the plurality of computing modules and the plurality of memory layers.

11. The IC die stack according to claim 1, wherein the IC die stack further comprises a logic component layer electrically coupled to the digital device layer.

12. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: A first digital device layer, the first digital device layer having at least two memory interfaces; A cooling solution, wherein the cooling solution is located on a first side of the first digital device layer; At least two memory stacks, each memory stack comprising multiple memory layers located on a second side of the first digital device layer opposite to its first side; An interface layer, wherein the interface layer is located between the first digital device layer and the at least two memory stacks; and A packaging substrate, which is coupled to the at least two memory stacks on the opposite side of the first digital device layer.

13. The IC die stack according to claim 12, wherein the IC die stack further comprises a second digital device layer and a bridge, the bridge coupling the first digital device layer and the second digital device layer through the interface layer.

14. An integrated circuit (IC) die stack, the integrated circuit (IC) die stack comprising: Multiple computing modules, wherein at least one of the multiple computing modules has a memory interface; A cooling solution is provided, wherein the cooling solution is located on the first side of the plurality of computing modules; At least two memory stacks, each memory stack comprising multiple memory layers located on a second side opposite to the first side of the plurality of computing modules; An interpolator layer is located between the plurality of computing modules and the at least two memory stacks; A bridge that electrically couples the interpolator layers; and A packaging substrate, which is coupled to the at least two memory stacks on the opposite side of the interpolator layer.

15. The IC die stack of claim 14, wherein the interpolator layer includes active logic components.

Images