Dmos devices including field plates and superlattices for drift region diffusion and related methods

Abstract

A double-diffused MOS (DMOS) device can include a semiconductor layer having a first conductivity type, a drift region of a second conductivity type in a semiconductor substrate, spaced apart source and drain regions in the semiconductor layer, and a first superlattice on the semiconductor layer. The first superlattice can include stacked groups of layers, where each group of layers includes stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of the adjacent base semiconductor portions. The semiconductor device can also include a gate over the first superlattice, and a field plate layer adjacent to the drift region and configured to deplete the drift region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to double-diffused metal-oxide-semiconductor (DMOS) devices and related methods. Background Technology

[0002] Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses a strained material layer of silicon, silicon-germanium, and relaxable silicon, and also includes an impurity-free region that would otherwise lead to performance degradation. Biaxial strain occurring in the upper silicon layer alters the carrier mobility, enabling devices with higher speeds and / or lower power. U.S. Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on a similar strained silicon technique.

[0003] Takagi's U.S. Patent No. 6,472,685 B2 discloses a semiconductor device comprising silicon and carbon layers sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Having a smaller effective mass, and with electrons induced by the electric field applied to the gate electrode confined within the second silicon layer, the n-channel MOSFET is said to have higher mobility.

[0004] U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which multiple layers (fewer than eight monolayers, and comprising fractional, binary, or binary compound semiconductor layers) are epitaxially grown alternately. The direction of the main current flow is perpendicular to each layer of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short-period superlattice with high mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Patent No. 5,683,934 to Candelaria discloses a MOSFET with enhanced mobility comprising an alloy containing silicon and a second material, the second material being present in a percentage of the silicon lattice to subject the channel layer to tensile stress.

[0006] US Patent No. 5,216,262 issued by Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2 / Si layers, typically ranging in thickness from two to six monolayers. A much thicker silicon portion is sandwiched between the barriers.

[0007] A paper titled "Phenomena in silicon nanostructure devices," also authored by Tsu and published online on September 6, 2000, in *Applied Physics and Materials Science & Processing* (pp. 391-402), discloses a silicon-oxygen semiconductor-atomic superlattice (SAS). It demonstrates that Si / O superlattices can be used for silicon quantum and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS can comprise semiconductor layers separated by adsorbed materials such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed oxygen monolayer is described as epitaxy with a considerably low defect density. One SAS structure includes a 1.1 nm thick silicon portion, approximately eight silicon atomic layers, while another structure has twice the thickness of the silicon portion. The article entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published by Luo et al. in Volume 89, Issue 7 of Physical Review Letters (August 12, 2002) further discusses Tsu’s luminescent SAS structure.

[0008] US Patent No. 7,105,895 to Wang et al. discloses a thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen barrier building block that reduces the current flowing vertically through the lattice by more than four orders of magnitude. This insulating / barrier layer allows for the deposition of low-defect epitaxial silicon next to the insulating layer.

[0009] Published UK patent application No. 2,347,520 by Mears et al. discloses that the principles of aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application discloses that material parameters (e.g., minimum band positions, effective mass, etc.) can be tailored to produce new aperiodic materials with desired bandgap structure properties. Other parameters (such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability) are disclosed as also being designed into the material.

[0010] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating layer or barrier layer for semiconductor devices. This method includes depositing a layer of silicon and at least one additional element on a silicon substrate, such that the deposited layer is substantially defect-free, thereby enabling the deposition of substantially defect-free epitaxial silicon on the deposited layer. Alternatively, a monolayer of one or more elements (preferably containing oxygen) is adsorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon layers form a barrier composite material.

[0011] Despite these methods, further enhancements may still be desired in order to improve the performance of semiconductor devices using advanced semiconductor materials and processing techniques. Summary of the Invention

[0012] A double-diffused MOS (DMOS) device may include a semiconductor layer having a first conductivity type, a drift region of a second conductivity type in a semiconductor substrate, spaced-apart source and drain regions in the semiconductor layer, and a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked layers, each layer comprising a plurality of stacked substrate semiconductor monolayers defining substrate semiconductor portions, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. The semiconductor device may also include a gate above the first superlattice and a field plate layer adjacent to the drift region and configured to deplete the drift region.

[0013] In one example embodiment, the DMOS device may further include a second superlattice in a semiconductor layer beneath the drift region, and the second superlattice may include multiple stacked layers, each layer including multiple stacked substrate semiconductor monolayers defining substrate semiconductor portions, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. Furthermore, the DMOS may include at least one resurf region in the substrate beneath the second superlattice. In one example embodiment, the at least one resurf region may include a lower resurf region and an upper resurf region between the lower resurf region and the second superlattice. Additionally, the DMOS device may include a semiconductor overlay layer on the second superlattice, defining a channel between the source and drain regions.

[0014] In one example implementation, the field plate layer may be electrically coupled to the source region. In some embodiments, the DMOS may further include body implantation in a semiconductor layer adjacent to the source region. In one example embodiment, the gate may include a gate dielectric layer on the semiconductor layer and a gate electrode layer on the gate dielectric layer, and the gate dielectric layer may have a first portion and a second portion, wherein the second portion is thicker than the first portion. For example, the substrate semiconductor monolayer may include silicon, and the non-semiconductor monolayer may include oxygen.

[0015] A method of manufacturing a double-diffused MOS (DMOS) device may include forming a semiconductor layer having a first conductivity type, forming drift regions of a second conductivity type in a semiconductor substrate, forming spaced-apart source and drain regions in the semiconductor layer, and forming a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked layers, each layer including a plurality of stacked substrate semiconductor monolayers defining substrate semiconductor portions, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. The method may further include forming a gate over the first superlattice and forming a field plate layer adjacent to the drift regions and configured to deplete the drift regions.

[0016] In one example embodiment, the method may further include forming a second superlattice in a semiconductor layer below the drift region. The second superlattice may include multiple stacked layers, each layer including multiple stacked substrate semiconductor monolayers defining substrate semiconductor portions, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. Furthermore, the method may further include forming at least one reduced surface electric field region in a substrate below the second superlattice. In one example embodiment, the at least one reduced surface electric field region may include a lower reduced surface electric field region and an upper reduced surface electric field region located between the lower reduced surface electric field region and the second superlattice. Additionally, the method may further include forming a semiconductor capping layer on the second superlattice, defining a channel between a source region and a drain region.

[0017] In one example implementation, the field plate layer may be electrically coupled to the source region. In some embodiments, the method may further include forming a body region implantation in a semiconductor layer adjacent to the source region. In one example embodiment, the gate may include a gate dielectric layer on the semiconductor layer and a gate electrode layer on the gate dielectric layer, and the gate dielectric layer may have a first portion and a second portion, wherein the second portion is thicker than the first portion. For example, the substrate semiconductor monolayer may include silicon, and the non-semiconductor monolayer may include oxygen. Attached Figure Description

[0018] Figure 1 This is a greatly enlarged schematic cross-sectional view of a superlattice in a semiconductor device according to an example embodiment.

[0019] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of the superlattice shown.

[0020] Figure 3 This is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice according to one example embodiment.

[0021] Figure 4-7These are schematic cross-sectional views of various DMOS devices that include one or more superlattice layers in different example embodiments.

[0022] Figure 8 It is an explanation and Figure 5-8 A process flow diagram related to the manufacturing methods of DMOS devices.

[0023] Figure 9A yes Figure 4 A schematic cross-sectional view of an alternative embodiment of a DMOS device, including a field plate for drift region depletion.

[0024] Figure 9B It is shown Figure 9A Doping distribution diagrams of doping concentration versus depth for example implementations of DMOS devices (and similar devices without a superlattice layer).

[0025] Figure 10 yes Figure 6 A schematic cross-sectional view of an alternative embodiment of a DMOS device, including a field plate for drift region depletion.

[0026] Figure 11 yes Figure 7 A schematic cross-sectional view of an alternative embodiment of a DMOS device, including a field plate for drift region depletion. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are illustrated. However, these embodiments may be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete. Similar numbers throughout refer to similar elements, and apostrophes are used to indicate similar elements in different embodiments.

[0028] In general, this disclosure relates to semiconductor devices having an enhanced semiconductor superlattice to provide performance enhancement characteristics. In this disclosure, the enhanced semiconductor superlattice may also be referred to as an "MST" layer or "MST technology".

[0029] More specifically, MST technology involves advanced semiconductor materials, such as superlattices 25, which are further described below. In previous work, the applicant theoretically presumed that certain superlattices described herein reduce the effective mass of charge carriers, thereby resulting in higher charge carrier mobility. See, for example, U.S. Patent No. 6,897,472, the entire contents of which are incorporated herein by reference.

[0030] The applicant's further research has confirmed that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials, for example, at the interface between silicon and an insulator (such as SiO2 or HfO2). The applicant theoretically presumes (but does not wish to be bound by) that this may occur due to various mechanisms. One mechanism is by reducing the concentration of charged impurities near the interface, by reducing the diffusion of these impurities, and / or by trapping impurities, preventing them from reaching the vicinity of the interface. Charged impurities cause Coulomb scattering, which reduces mobility. Another mechanism is by improving the quality of the interface. For example, oxygen emanating from the MST film can provide oxygen to the Si-SiO2 interface, reducing the substoichiometric SiO2 concentration. x The presence of interstitial silicon near the Si-SiO2 interface can be reduced by trapping interstitial atoms through the MST layer, thereby reducing the formation of substoichiometric SiO2. x The trend. The substoichiometric SiO2 at the Si-SiO2 interface is known. x Compared to stoichiometry, SiO2 exhibits poor insulating properties. Reducing the substoichiometric SiO2 at the interface... x The amount of [insert value here] can more effectively confine free carriers (electrons or holes) within silicon, thereby increasing the mobility of these carriers due to the electric field applied parallel to the interface, which is standard practice in field-effect transistor (“FET”) structures. Scattering caused by the direct influence of the interface is called “rough surface scattering,” which can be advantageously reduced by bringing the MST layer closer and subsequently annealing or during thermal oxidation.

[0031] In addition to the enhanced mobility properties of MST structures, they can also be formed or used in ways that enable them to provide piezoelectric, thermoelectric, and / or ferroelectric properties, which are advantageous for use in a variety of different types of devices, as will be discussed further below.

[0032] Now for reference Figure 1 and Figure 2 These materials or structures take the form of a superlattice 25, whose structure is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, as detailed in [reference needed]. Figure 1 A schematic cross-sectional view is perhaps the best way to understand this.

[0033] Each layer group 45a-45n of the superlattice 25 exemplarily includes a plurality of stacked substrate semiconductor monolayers 46 defining corresponding substrate semiconductor portions 46a-46n, and one or more non-semiconductor monolayers 50 thereon. For clarity of illustration, Figure 1 In the diagram, dots are used to represent a non-semiconductor monolayer 50.

[0034] The non-semiconductor monolayer 50 exemplary includes a non-semiconductor monolayer confined within the lattice of adjacent substrate semiconductor portions. "Confined within the lattice of adjacent substrate semiconductor portions" means that at least some semiconductor atoms from opposing substrate semiconductor portions 46a-46n are chemically bonded together through the intervening non-semiconductor monolayer 50, such as... Figure 2 As shown. Generally, this configuration can be achieved by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition techniques, such that not all (i.e., less than complete or 100% coverage) of the available semiconductor bonding sites are occupied by bonds with non-semiconductor atoms, as will be discussed further below. Therefore, when a further semiconductor material monolayer 46 is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0035] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that the terms "non-semiconductor" or "semiconductor monolayer" herein mean that the material used for the monolayer, if formed in bulk, would be either non-semiconductor or semiconductor. That is, a single monolayer material, such as silicon, may not necessarily exhibit the same properties as when formed in bulk or as a relatively thick layer, as will be understood by those skilled in the art.

[0036] The applicant theoretically presumes (but does not wish to be bound by) that the non-semiconductor monolayer 50 and the adjacent substrate semiconductor portions 46a-46n result in the superlattice 25 having an effective mass of appropriate conductivity with lower charge carriers in the parallel layer direction than in other cases. Alternatively, this parallel direction is orthogonal to the stacking direction. The band-modification layer 50 can also result in the superlattice 25 having a common band structure, while also advantageously acting as an insulator between layers or regions above and below the superlattice in the vertical direction.

[0037] Furthermore, this superlattice structure can advantageously act as a barrier for dopant and / or material diffusion between layers above and below the superlattice 25 in the vertical direction. Therefore, these properties can advantageously allow the superlattice 25 to provide an interface for the high-k dielectric, which not only reduces the diffusion of the high-k material into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility, as those skilled in the art will understand.

[0038] Furthermore, it is theoretically assumed that semiconductor devices incorporating superlattice 25 can enjoy higher charge carrier mobility than otherwise exhibited, based on a lower effective conductivity quality. In some embodiments, as a result of band engineering implemented in this embodiment, superlattice 25 may also have a substantially direct band gap, which would be particularly advantageous for, for example, optoelectronic devices.

[0039] The superlattice 25 also includes, by way of example, a capping layer 52 on the upper group 45n. The capping layer 52 may include a plurality of substrate semiconductor monolayers 46. The capping layer 52 may have 2 to 100 substrate semiconductor monolayers, more preferably, between 10 and 50 monolayers.

[0040] Each substrate semiconductor portion 46a-46n may include a substrate semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductor also includes Group IV-IV semiconductors, as those skilled in the art will understand. More specifically, for example, the substrate semiconductor may include at least one of silicon and germanium.

[0041] Each non-semiconductor monolayer 50 may comprise a non-semiconductor selected from, for example, the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also expected to be thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art. More specifically, for example, the substrate semiconductor may comprise at least one of silicon and germanium.

[0042] It should be noted that the term monolayer is intended to include both a single atomic layer and a single molecular layer. It should also be noted that a non-semiconductor monolayer 50 provided by a single monolayer is also intended to include monolayers where not all possible sites are occupied (i.e., there is less than complete or 100% coverage). See, for example, a specific reference. Figure 2 The atomic diagram shows a 4 / 1 repeating structure with silicon as the substrate semiconductor material and oxygen as the bandgap modifier. In the illustrated example, only half of the possible sites for oxygen are occupied.

[0043] In other embodiments and / or when using different materials, this half-occupancy may not be the case, as those skilled in the art will understand. Indeed, even in this schematic diagram, it can be seen that individual oxygen atoms in a given monolayer are not precisely aligned along a flat plane, as those skilled in the art of atomic deposition will also understand. For example, a preferred occupancy range is from approximately one-eighth to one-half of the possible oxygen sites being filled, although other values ​​may be used in some embodiments.

[0044] Silicon and oxygen are currently widely used in conventional semiconductor processing, and therefore, manufacturers will be able to readily employ these materials described herein. Atomic or monolayer deposition is also now widely used. Therefore, semiconductor devices incorporating the superlattice 25 according to the embodiments can be readily adopted and implemented, as will be understood by those skilled in the art.

[0045] Now refer to another source Figure 3Another embodiment of the superlattice 25' with different properties according to the present embodiment is now described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is shown. More specifically, the lowest substrate semiconductor portion 46a' has three monolayers, and the second lowest substrate semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. Each non-semiconductor monolayer 50' may comprise a single monolayer. For this Si / O-containing superlattice 25', the enhancement of charge carrier mobility is independent of the in-plane orientation of the layers. Figure 3 Other elements not specifically mentioned above are referenced in the text. Figure 1 The similarities discussed need not be further elaborated here.

[0046] In some device embodiments, all substrate semiconductor portions of the superlattice may have the same number of monolayer thicknesses. In other embodiments, at least some of the substrate semiconductor portions may have different numbers of monolayer thicknesses. In still other embodiments, all substrate semiconductor portions may have different numbers of monolayer thicknesses.

[0047] Go to Figure 4 An example double-diffused MOS (DMOS) device 100 incorporating the above-described MST technology is now described. The DMOS 100 exemplarily includes a substrate 101 in which shallow P-regions and shallow N-regions 102 and 103 are formed, respectively, and source and drain implants 104 and 105. An MST film 125 is formed on the upper surface of the substrate 101, and a capping layer 152 may define a channel for the device below a gate 106. In some embodiments, the channel may also extend into the MST film 125. For example, the capping layer 152 may have a thickness in the range of 5 nm to 100 nm, and the shallow N-region 103 may have a thickness in the range of 100 nm to 1000 nm, although other dimensions may be used in different embodiments.

[0048] As previously mentioned, the aforementioned MST film can advantageously provide intrinsic mobility under certain configurations through bandgap modification effects. However, in this application, the performance improvement of the DMOS device 100 is achieved as a result of the improved doping distribution achievable due to the presence of the MST film 125. This results in increased mobility due to lower surface roughness scattering, lower Coulomb scattering, and increased conductivity in the near-surface region 117. In other words, this technical advantage can be achieved without considering and without relying on the bandgap modification capability of the MST film.

[0049] Now refer to Figure 5 In an alternative embodiment of the DMOS device 101', the MST layer 125' is buried in the substrate 101', instead of being on the substrate surface as in the DMOS device 100 described above. Figure 6In another example embodiment of the DMOS device 101'' shown, a dual-layer MST configuration is provided, which includes both a buried (lower) MST layer 125a'' and a surface (upper) MST layer 125b''.

[0050] Reference Figure 7 Another dual-layer MST DMOS device 100''' includes dual reduced surface electric field (PSF) N-regions and P-regions 107''', 108'''. This configuration provides a thinner drift region achieved through the dual PSF and dual MST layers 125a''', 125b''' configuration. Furthermore, as those skilled in the art will understand, the MST layer 125a''' advantageously reduces compensation for the drift region by reducing surface electric field doping. In some embodiments, the N and P PSF doping 107''', 108''' can be implemented using the same mask as the drift region mask to advantageously reduce cost. The PSF N-region 107''' can be connected to the drain region 105'''.

[0051] Now refer to Figure 8 Process flow diagram 200 describes an example method for manufacturing the aforementioned DMOS devices 100-100'''. The batch begins at laser processing module 201. If either of the dual MST layer DMOS devices 100'' or 100''' is to be formed, a low-temperature (LT) shallow trench isolation (STI) module 202 is performed. Otherwise, the process proceeds to pad oxidation module 203, followed by nitride hard mask module 204 and active region mask module 205. Shallow trench isolation (STI) module 206 is then performed.

[0052] If one of DMOS devices 100', 100'', or 100''' is being fabricated, the buried MST epitaxial module 207 is performed after the STI module 206. Otherwise, the process proceeds to the shallow P and N mask / implantation modules 208 and 209, respectively, and the well rapid thermal annealing (RTA) module 210. If one of DMOS devices 100, 100'', or 100''' is being fabricated, the surface MST epitaxial module 211 is performed after the well RTA module 210. The process continues with the RTA oxidation module 212, the thick chemical vapor deposition (CVD) oxide module 213, and the thick oxide mask / etch module 214. Gate formation includes the gate oxide module 215, the gate polysilicon deposition module 216, the poly mask / etch module 217, and the poly re-oxidation module 218. The method also includes, by way of example, a lightly doped drain (LDD) / halo mask / implantation module 219, an LDD RTA module 220, a nitride spacer module 221, and / or other LDD RTA modules 222, a spacer formation module 223, an N+ / P+ mask / implantation module 224, and a source / drain RTA module 225.

[0053] In the aforementioned DMOS devices with a surface MST layer, the MST surface layer enables the formation of a flip-chip distribution near the substrate surface, resulting in higher mobility (lower Coulomb scattering). Furthermore, due to lower surface roughness scattering (SRS), the MST surface layer improves mobility below / near the gate oxide interface. Another technical advantage is that, in the case of high interface charge, the MST layer allows for customized doping distributions to guide current flow away from the drift region interface. Additionally, the MST layer can advantageously prevent compensation of the drift region by reducing doping in the surface electric field region, leading to higher bulk mobility. This allows for a thinner drift region compared to conventional devices.

[0054] Now go to Figure 9A This describes another example DMOS device 200. DMOS 200 is similar to DMOS device 100 and exemplarily includes a substrate 201 in which shallow P (body) regions 202 and shallow N (drift) regions 203 are formed, as well as source and drain implants 204 and 205, respectively. An MST film 225 is formed on the upper surface of the substrate 201, along with a capping layer 252 that can define a device channel beneath the gate 206. Here, the gate has a stepped gate oxide layer 230 (having a thinner first portion and a thicker second portion) and a gate electrode layer 231 on the stepped gate oxide layer. As described above, in some embodiments, the channel may also extend into the MST film 225. The capping layer 252 and the drift region 203 may have similar dimensions to those described above.

[0055] This configuration offers numerous technical advantages. In particular, compared to similar devices without this MST layer, the dopant retention properties of the MST film 225 allow for a steeper dopant distribution concentrated in the drift region, as seen in... Figure 9A As seen in graphs 236 and 237 in Figure 235, the resulting doping distribution advantageously provides a relatively low drift region resistance path, as those skilled in the art will understand.

[0056] The DMOS 200 also exemplarily includes a conductive field plate 240 (e.g., a tungsten plug field plate) above the gate 206 adjacent to the drift region 203. This provides another significant technical advantage because it allows the drain-source breakdown voltage BVdss to remain unaffected. This is because the drift region is completely depleted from the top by the field plate 240, which is grounded together with the source region 204 and the body injection region 202. Furthermore, the drift region can also be depleted from the bottom by P-RESURF injection.

[0057] Now refer to Figure 10 In an alternative embodiment of the DMOS device 201', a dual-layer MST configuration is provided, comprising both a buried (lower) MST layer 225a' and a surface (upper) MST layer 225b', as referenced above. Figure 6 Similar to the description. This embodiment also provides the technical advantage of reduced Ron resistance because the lower MST layer 225b' helps prevent the mixing of N-drift regions and P-RESURF dopants. In some embodiments, only a buried MST layer 225a' may be present (similar to the one described above). Figure 7 (Described embodiments).

[0058] Reference Figure 11 Another double-layer MST DMOS device 200'' includes dual N-region and P-region 207'' and 208'' for reducing surface electric field. (See above for reference.) Figure 7 As discussed, this provides a thinner drift region 203'' achieved through a dual reduced surface electric field and dual MST layer 225a'', 125b'' configuration. Furthermore, as those skilled in the art will understand, the MST layer 125a'' advantageously reduces compensation for the drift region by reducing surface electric field doping. Returning to this point, in some embodiments, the N and P reduced surface electric field injections 207'', 208'' can be implemented using the same mask as the drift region mask to advantageously reduce cost, and the reduced surface electric field N region 207'' can be connected to the drain region 205''. This configuration also provides significant improvements in Ron and BVdss. That is, as those skilled in the art will understand, the PN superjunction RESURF configuration achieved by MST allows for lower Ron and higher BV due to reduced dopant mixing and a larger vertical depletion region.

[0059] Many modifications and other embodiments of the invention will arise for those skilled in the art from the teachings presented in the foregoing description and the associated drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A double-diffused MOS (DMOS) device, comprising: A semiconductor layer having a first conductivity type; A drift region of the second conductivity type in the semiconductor layer; The source and drain regions spaced apart in the semiconductor layer; A first superlattice on the semiconductor layer, the first superlattice comprising a plurality of stacked layers, each layer comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. The gate above the first superlattice; as well as A field plate layer adjacent to the drift region and configured to deplete the drift region.

2. The DMOS device of claim 1, further comprising a second superlattice in the semiconductor layer below the drift region, the second superlattice comprising a plurality of stacked layers, each layer comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion.

3. The DMOS device of claim 2, further comprising at least one reduced surface electric field region in the substrate beneath the second superlattice.

4. The DMOS device according to claim 3, wherein the at least one reduced surface electric field region comprises a lower reduced surface electric field region and an upper reduced surface electric field region located between the lower reduced surface electric field region and the second superlattice.

5. The DMOS device of claim 1, further comprising a semiconductor capping layer on the first superlattice, wherein the semiconductor capping layer defines a channel between the source region and the drain region.

6. The DMOS device according to claim 1, wherein the field plate layer is electrically coupled to the source region.

7. The DMOS device of claim 1, further comprising body region implantation in the semiconductor layer adjacent to the source region.

8. The DMOS device of claim 1, wherein the gate comprises a gate dielectric layer on the semiconductor layer and a gate electrode layer on the gate dielectric layer; and wherein the gate dielectric layer has a first portion and a second portion, wherein the second portion is thicker than the first portion.

9. The DMOS device of claim 1, wherein the substrate semiconductor monolayer comprises silicon.

10. The DMOS device of claim 1, wherein the non-semiconductor monolayer comprises oxygen.

11. A method for manufacturing a double-diffused MOS (DMOS) device, comprising: Forming a semiconductor layer having a first conductivity type; A drift region of a second conductivity type is formed in the semiconductor layer; Spacing out source and drain regions are formed in the semiconductor layer; A first superlattice is formed on the semiconductor layer. The first superlattice includes a plurality of stacked layer groups, each layer group including a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion. A gate is formed above the first superlattice; as well as A field plate layer is formed, the field plate layer being adjacent to the drift region and configured to deplete the drift region.

12. The method of claim 11, further comprising forming a second superlattice in the semiconductor layer below the drift region, the second superlattice comprising a plurality of stacked layers, each layer comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer constrained within a lattice of an adjacent substrate semiconductor portion.

13. The method of claim 12, further comprising forming at least one reduced surface electric field region in the substrate beneath the second superlattice.

14. The method of claim 13, wherein the at least one reduced surface electric field region comprises a lower reduced surface electric field region and an upper reduced surface electric field region located between the lower reduced surface electric field region and the second superlattice.

15. The method of claim 11, further comprising forming a semiconductor capping layer on the first superlattice, wherein the capping layer defines a channel between the source region and the drain region.

16. The method of claim 11, wherein the field plate layer is electrically coupled to the source region.

17. The method of claim 11, further comprising forming a body region implantation in the semiconductor layer adjacent to the source region.

18. The method of claim 11, wherein forming the gate comprises forming a gate dielectric layer on the semiconductor layer and forming a gate electrode layer on the gate dielectric layer; and wherein the gate dielectric layer has a first portion and a second portion, wherein the second portion is thicker than the first portion.

19. The method of claim 11, wherein the substrate semiconductor monolayer comprises silicon.

20. The method of claim 11, wherein the non-semiconductor monolayer comprises oxygen.

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