Semiconductor device, display device, and electronic device

Abstract

A semiconductor device with reduced off-state current is provided. The semiconductor device includes a driver transistor, a first transistor, a second transistor, a third transistor, a first capacitor, and a light emitting device. A back gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor. A gate of the first transistor is electrically connected to a first wiring, a gate of the second transistor is electrically connected to the first wiring, and a gate of the third transistor is electrically connected to a second wiring. One of a source and a drain of the first transistor is electrically connected to a gate of the driver transistor and a first terminal of the first capacitor. One of a source and a drain of the driver transistor is electrically connected to a second terminal of the first capacitor and one of an anode and a cathode of the light emitting device.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, a method of operation, or a method of manufacturing. Furthermore, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specifically, examples of the technical fields of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. Background Technology

[0003] In recent years, various improvements have been made to display devices used in XR (Extended Reality) technologies such as VR (Virtual Reality), AR (Augmented Reality), including wearable devices, monitors, mobile phones (e.g., smartphones), smartwatches, tablets, and PCs. For example, display devices have been developed with the aim of improving screen resolution, color reproduction (NTSC ratio), miniaturizing drive circuitry, and reducing power consumption.

[0004] As an improvement method for display devices, the use of transistors containing oxide semiconductors in pixel circuits, driving circuits, etc., has attracted attention. As oxide semiconductors, in addition to oxides of single-unit metals such as indium oxide and zinc oxide, oxides of multi-unit metals are also known. Among multi-unit metal oxides, research on In-Ga-Zn oxides (hereinafter also referred to as IGZO) is particularly active.

[0005] By using In-Ga-Zn oxide as the active layer to fabricate an n-channel transistor, the off-state current of the transistor can be made extremely small (see Non-Patent Document 1). Furthermore, Patent Document 1, Patent Document 2, Non-Patent Document 2, and Non-Patent Document 3 report LSI (Large Scale Integration) and display devices utilizing the above-mentioned characteristics. In particular, Patent Document 1 and Patent Document 2 disclose techniques for reducing the power consumption of liquid crystal displays and organic EL displays by utilizing the extremely small off-state current characteristic of this transistor to reduce the refresh rate when displaying static images.

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2011-141522 [Patent Document 2] Japanese Patent Application Publication No. 2011-141524 [Non-patent literature] [Non-Patent Literature 1] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Literature 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217 [Non-Patent Literature 3] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629. The technical problem to be solved by the invention. Summary of the Invention

[0007] The technical problem that the invention aims to solve When a display device displays a static image, the frame rate can be reduced because there is no image change, thereby reducing the refresh rate. Reducing the refresh rate lowers the power consumption of the drive circuitry (e.g., source drive circuitry, gate drive circuitry, etc.) in the display device. The extent to which the frame rate can be reduced depends on the amount of off-state current (leakage current flowing in the off state) of the write transistors in the pixel circuitry; therefore, it is important to construct pixel circuitry that minimizes the off-state current of the write transistors.

[0008] For example, when the write transistor is an n-channel transistor, supplying a high-level potential to the gate of the write transistor as a selection signal can turn the write transistor into the on state, and supplying a low-level potential to the gate of the write transistor as a non-selection signal can turn the write transistor into the off state. In particular, by setting the low-level potential to a low potential, the off-state current of the write transistor can be reduced. For example, the low-level potential is preferably set to 0V or a negative potential.

[0009] Furthermore, the select signal line connected to the gate of the write transistor is repeatedly input with select and non-select signals. When the low-level potential of the non-select signal is negative, generating the non-select signal each time by the signal generation circuit consumes a significant amount of power. Therefore, in existing structures, the low-level potential of the non-select signal is often set to 0V.

[0010] One objective of this invention is to provide a semiconductor device that increases the on-state current when in an on state and decreases the off-state current when in a off state. Another objective of this invention is to provide a semiconductor device that reduces the refresh rate. Another objective of this invention is to provide a semiconductor device that reduces power consumption. Another objective of this invention is to provide a display device including the above-described semiconductor device. Another objective of this invention is to provide an electronic device including the above-described display device. Finally, another objective of this invention is to provide a novel semiconductor device, a novel display device, or a novel electronic device.

[0011] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above and other objectives. Furthermore, one aspect of the present invention does not need to achieve all of the above and other objectives.

[0012] means of solving technical problems One aspect of the present invention is a semiconductor device for the purposes described above, the semiconductor device comprising a first transistor, a second transistor, and a third transistor. Furthermore, the first transistor includes a back gate.

[0013] The back gate of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor. Furthermore, the gates of the first transistor and the second transistor are connected to a first signal line. Additionally, the gate of the third transistor is connected to a second signal line.

[0014] In particular, the first signal line and the second signal line are input with signals that are logically inverted from each other. For example, when the first signal line is input with a high level potential, the second signal line is input with a low level potential, and, for example, when the first signal line is input with a low level potential, the second signal line is input with a high level potential.

[0015] Furthermore, the second terminal of the second transistor is supplied with a fixed potential, the same as the high-level potential input to the first signal line. Additionally, the second terminal of the third transistor is supplied with a fixed negative potential.

[0016] Furthermore, the aforementioned first transistor can be used as a write transistor in a pixel circuit.

[0017] The following describes an example of a semiconductor device, display device, and electronic device used to solve the above-mentioned problems. (1) One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. Furthermore, the first transistor, the second transistor, and the third transistor all contain oxide semiconductor in their channel forming regions. Note that the first transistor includes a back gate. The back gate of the first transistor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. Furthermore, the gate of the first transistor is electrically connected to a first wiring, the gate of the second transistor is electrically connected to the first wiring, and the gate of the third transistor is electrically connected to a second wiring. Note that the first wiring is input to one of a high-level potential and a low-level potential, and the second wiring is input to the other of a high-level potential and a low-level potential. Furthermore, the other of the source and drain of the second transistor is input to a high-level potential, and the other of the source and drain of the third transistor is input to a potential less than 0V. (2) Furthermore, in (1) above, one aspect of the present invention may also have an oxide semiconductor structure comprising one or more selected from indium, zinc and element M.

[0020] Note that element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (3) Furthermore, one aspect of the present invention is a semiconductor device including a driving transistor, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. Furthermore, the driving transistor, the first transistor, the second transistor, and the third transistor all contain oxide semiconductor in the channel forming region. Note that the first transistor includes a back gate. The back gate of the first transistor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. Furthermore, the gate of the first transistor is electrically connected to a first wiring, the gate of the second transistor is electrically connected to the first wiring, and the gate of the third transistor is electrically connected to a second wiring. Furthermore, one of the source and drain of the first transistor is electrically connected to the gate of the driving transistor and a first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to a second terminal of the first capacitor and one of the anode and cathode of the light-emitting device. (4) Furthermore, one aspect of the present invention is a semiconductor device including a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a light-emitting device. Furthermore, the driving transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor all contain oxide semiconductor in the channel forming region. Note that the first transistor and the fourth transistor both include a back gate. The back gate of the first transistor and the back gate of the fourth transistor are electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. Furthermore, the gate of the first transistor is electrically connected to a first wiring, the gate of the second transistor is electrically connected to the first wiring, the gate of the fourth transistor is electrically connected to the first wiring, and the gate of the third transistor is electrically connected to a second wiring. Furthermore, one of the source and drain of the first transistor is electrically connected to the gate of the driving transistor and a first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to a second terminal of the first capacitor, one of the anode and cathode of the light-emitting device, and one of the source and drain of the fourth transistor. (5) Furthermore, in (3) or (4) above, one aspect of the present invention may also have a structure in which the light-emitting device comprises an organic EL material. (6) In (5) above, one aspect of the present invention may also have an oxide semiconductor structure comprising one or more selected from indium, zinc and element M.

[0025] Note that element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (7) Furthermore, one embodiment of the present invention may also include the semiconductor device, the first driving circuit, and the second driving circuit described in (6) above. Particularly preferred is that the first driving circuit has the function of sending an image signal to the other of the source and drain of the first transistor, and the second driving circuit has the function of sending a group of selection signals that are logically inverted to each other to the first wiring and the second wiring. (8) Furthermore, one aspect of the present invention is an electronic device comprising the display device described above (7) and a housing. (9) Furthermore, one aspect of the present invention is a semiconductor device including a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a light-emitting device. Moreover, the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor all contain oxide semiconductor in the channel forming region. Note that the driving transistor, the first transistor, the fourth transistor, the fifth transistor, and the seventh transistor all include a back gate. The back gate of the first transistor and the back gate of the fourth transistor are electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. Furthermore, the gate of the first transistor is electrically connected to a first wiring, the gate of the second transistor is electrically connected to the first wiring, the gate of the fourth transistor is electrically connected to the first wiring, and the gate of the third transistor is electrically connected to a second wiring. One of the source and drain of the first transistor is electrically connected to the gate of the driving transistor, one of the source and drain of the fifth transistor, and a first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the second capacitor, one of the source and drain of the fourth transistor, the other of the source and drain of the fifth transistor, and one of the source and drain of the sixth transistor. Additionally, the other of the source and drain of the sixth transistor is electrically connected to one of the anode and cathode of the light-emitting device. Furthermore, the back gate of the fifth transistor and the back gate of the seventh transistor are electrically connected to one of the source and drain of the eighth transistor and one of the source and drain of the ninth transistor. Furthermore, the gate of the fifth transistor is electrically connected to the third wiring, the gate of the seventh transistor is electrically connected to the third wiring, the gate of the eighth transistor is electrically connected to the third wiring, and the gate of the ninth transistor is electrically connected to the fourth wiring. Additionally, one of the source and drain of the seventh transistor is electrically connected to the back gate of the driving transistor and the second terminal of the second capacitor. (10) Furthermore, in the above (9), one aspect of the present invention may also have a structure in which the light-emitting device comprises an organic EL material. (11) Furthermore, in the above (10), one aspect of the present invention may also have an oxide semiconductor structure comprising one or more selected from indium, zinc and element M.

[0031] Note that element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (12) Furthermore, one aspect of the present invention is a display device comprising the semiconductor device described in any one of (9) or (11) above, a first driving circuit, and a second driving circuit. The first driving circuit has the function of sending an image signal to the other of the source and drain of the first transistor. Furthermore, the second driving circuit has the function of sending a group of first selection signals that are logically inverted to each other to the first wiring and the second wiring, and the function of sending a group of second selection signals that are logically inverted to each other to the third wiring and the fourth wiring. (13) Furthermore, one aspect of the present invention is an electronic device comprising the display device described above (12) and a housing. (14) Furthermore, one aspect of the present invention is a semiconductor device including a driving transistor, a first transistor, a second transistor, a first capacitor, and a light-emitting device. Furthermore, the driving transistor, the first transistor, and the second transistor all contain oxide semiconductor in the channel formation region. The gate of the first transistor is electrically connected to a first wiring, and the gate of the second transistor is electrically connected to the first wiring. Furthermore, one of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor, and the other of the source and drain of the second transistor is electrically connected to the gate of the driving transistor and a first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to a second terminal of the first capacitor and one of the anode and cathode of the light-emitting device. (15) Furthermore, in the above (14), one embodiment of the present invention may also include a third transistor and a fourth transistor. Particularly preferred is that both the third and fourth transistors contain oxide semiconductors in the channel formation region. Preferably, the gate of the third transistor is electrically connected to the second wiring, and the gate of the fourth transistor is electrically connected to the second wiring. Furthermore, preferably, one of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor, and the other of the source and drain of the fourth transistor is electrically connected to one of the source and drain of the driving transistor, the second terminal of the first capacitor, and one of the anode and cathode of the light-emitting device. (16) Furthermore, in the above (15), one aspect of the present invention may also have a structure in which the light-emitting device comprises an organic EL material. (17) Furthermore, in the above (16), one aspect of the present invention may also have an oxide semiconductor structure comprising one or more selected from indium, zinc and element M.

[0038] Note that element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (18) Furthermore, one aspect of the present invention is a display device comprising the semiconductor device described in any one of (15) to (17) above, a first driving circuit, and a second driving circuit. The first driving circuit has the function of sending an image signal to the other of the source and drain of a first transistor. Furthermore, the second driving circuit has the function of sending a first selection signal to a first wiring and a second selection signal to a second wiring. (19) Furthermore, one aspect of the present invention is an electronic device comprising the display device described above (18) and a housing.

[0041] Invention Effects In (1) above, the first wiring is supplied with a high-level potential and the second wiring is supplied with a low-level potential, thereby enabling the first transistor to be in the on state. Furthermore, at this time, the second transistor is in the on state and the third transistor is in the off state, thus the second terminal of the second transistor is in a conducting state with the back gate of the first transistor. Here, when the second terminal of the second transistor is supplied with a fixed potential equal to the high-level potential supplied to the first wiring, the potential of the back gate of the first transistor rises to a potential equal to the fixed potential minus the threshold voltage of the second transistor. As a result, the threshold voltage of the first transistor drifts to the negative side, and therefore the current flowing through the first transistor when it is in the on state is greater than before the threshold voltage drifted to the negative side.

[0042] Furthermore, the first wiring is supplied with a low-level potential and the second wiring is supplied with a high-level potential, thereby turning the first transistor off. Meanwhile, the second transistor is off and the third transistor is on, thus creating a conduction connection between the second terminal of the third transistor and the back gate of the first transistor. Here, by supplying a negative potential as a fixed potential to the second terminal of the third transistor, the back gate of the first transistor is input with this negative potential. As a result, the threshold voltage of the first transistor shifts to the positive side, and therefore the off-state current flowing through the first transistor when it is off is smaller than before the threshold voltage shifted to the positive side.

[0043] In other words, with the structure described in (1) above, the on-state current can be increased when the first transistor is in the on state, and the off-state current can be decreased when the first transistor is in the off state.

[0044] Furthermore, the structure described in (1) can be incorporated into the pixel circuit of the display device. For example, by using the first transistor in (1) as the write transistor of the pixel circuit, the on-state current of the first transistor increases when the first transistor is in the on state, thereby increasing the writing speed of image data to the pixel circuit. In addition, the off-state current of the first transistor decreases when the first transistor is in the off state, thereby allowing the image data to be held in the pixel circuit for a longer period of time. Since the image data can be held in the pixel circuit for a longer period of time, the refresh rate of the image data and the frame rate of the display device can be reduced.

[0045] According to one aspect of the present invention, a semiconductor device that increases the on-state current when in an on state and decreases the off-state current when in a off state can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that reduces the refresh rate can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that reduces power consumption can be provided. Furthermore, according to one aspect of the present invention, a display device including the above-described semiconductor device can be provided. Furthermore, according to one aspect of the present invention, an electronic device including the above-described display device can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0046] Note that the effects of one aspect of the present invention are not limited to those described above. The described effects do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. Moreover, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes not have the above-described effects.

[0047] Brief description of the attached figures Figure 1 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0048] Figure 2A and Figure 2B This is a circuit diagram illustrating an example of the structure of a pixel circuit.

[0049] Figure 3A This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit. Figure 3B This is a timing diagram of an example of the operation of the switching section.

[0050] Figure 4 This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0051] Figure 5 This is a timing diagram illustrating an example of how a pixel circuit works.

[0052] Figure 6A and Figure 6B This is a circuit diagram showing an example of the structure of a pixel circuit.

[0053] Figure 7 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0054] Figure 8 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0055] Figures 9A to 9C This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0056] Figures 10A to 10D This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0057] Figures 11A to 11D This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0058] Figure 12A and Figure 12B This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0059] Figure 13A and Figure 13B This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0060] Figure 14 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0061] Figures 15A to 15C This is a timing diagram illustrating an example of how a pixel circuit works.

[0062] Figure 16 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0063] Figure 17 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0064] Figure 18A and Figure 18B This is a circuit diagram showing an example of the structure of the switching section included in a pixel circuit.

[0065] Figures 19A to 19D This is a circuit diagram showing an example of the structure of a pixel circuit.

[0066] Figure 20A and Figure 20B This is a circuit diagram showing an example of the structure of a pixel circuit.

[0067] Figure 21A and Figure 21B This is a circuit diagram showing an example of the structure of a pixel circuit.

[0068] Figure 22 This is a circuit diagram showing an example of the structure of a pixel circuit.

[0069] Figure 23 This is a block diagram illustrating an example of the structure of a display device.

[0070] Figures 24A to 24C This is a three-dimensional schematic diagram showing an example of the structure of a display device.

[0071] Figure 25 This is a block diagram illustrating an example of the structure of a display device.

[0072] Figure 26 This is a cross-sectional schematic diagram showing an example of the structure of a display device.

[0073] Figure 27A This is a planar schematic diagram showing an example of a transistor structure. Figure 27B and Figure 27C This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0074] Figure 28A This is a planar schematic diagram showing an example of a transistor structure. Figure 28B and Figure 28C This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0075] Figures 29A to 29C This is a cross-sectional schematic diagram showing a structural example of a part of a display device.

[0076] Figure 30 This is a cross-sectional schematic diagram showing an example of the structure of a display device.

[0077] Figure 31 This is a cross-sectional schematic diagram showing an example of the structure of a display device.

[0078] Figure 32 This is a cross-sectional schematic diagram showing an example of the structure of a display device.

[0079] Figure 33A This is a planar schematic diagram showing an example of a transistor structure. Figures 33B to 33D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0080] Figures 34A to 34CThis is a cross-sectional schematic diagram illustrating an example of a transistor structure.

[0081] Figure 35A This is a planar schematic diagram showing an example of a transistor structure. Figures 35B to 35D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0082] Figure 36 This is a cross-sectional schematic diagram showing an example of the structure of a display device.

[0083] Figure 37A and Figure 37B This is a diagram showing an example of the structure of a display module.

[0084] Figures 38A to 38I This is a perspective view showing an example of an electronic device.

[0085] Figures 39A1 to 39A7 and Figures 39B1 to 39B6 It is a circuit diagram illustrating electrical connections.

[0086] Methods of implementing the invention (Notes regarding this instruction manual) In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as a circuit that includes semiconductor elements (e.g., transistors, diodes, and photodiodes) and a device that includes such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. Furthermore, a chip incorporating an integrated circuit can also be cited as an example of a semiconductor device, as can an electronic component containing a chip in a package. Additionally, for example, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0087] In this specification, “connection” includes, for example, “electrical connection”.

[0088] When the connection relationship of circuit elements is represented as an "electrical connection" to define an object, "electrical connection" includes, for example, "direct connection" and "indirect connection". "Direct connection between A and B" means, for example, that A and B are connected without a circuit element (such as a transistor or switch. Note that wiring is not a circuit element). On the other hand, "indirect connection between A and B" means, for example, that A and B are connected by one or more circuit elements.

[0089] Here, the definition of "A and B indirectly connected" refers to the following connection relationship: That is, when assuming the circuit is operating, if there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during circuit operation, such a circuit can be defined as "A and B indirectly connected." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, if there is an exchange of electrical signals or the interaction of potentials between A and B during circuit operation, it can still be defined as "A and B indirectly connected." Note that "A and B indirectly connected" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as "A and B indirectly connected" (note that, as an example, this is limited to the case where there is an exchange of electrical signals or the interaction of potentials between A and B during circuit operation when the circuit is supplied with a power supply voltage).

[0090] The following are specific examples of "indirect connection". First, as an example of "A and B are indirectly connected", there is the following... Figure 39A1 and Figure 39A2 Examples of "indirect connection between A and B" include cases where A and B are connected via the source and drain of one or more transistors. Other examples of "indirect connection between A and B" include cases where A and B are connected via one or more switches. In the case of "indirect connection between A and B," assuming the circuit is operational, at least once a transistor between A and B is in an on-state, a conducting state, or a state where current can flow. Furthermore, the case of "indirect connection between A and B" also includes cases where one transistor between A and B is in a off-state or a non-conducting state. In the case of "indirect connection between A and B," when multiple transistors are connected between A and B, assuming the circuit is operational, at least once each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow. That is, in the case of "indirect connection between A and B," multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, the case of "indirect connection between A and B" includes cases where multiple transistors between A and B are in an off-state or a non-conducting state simultaneously or at different times. As another example, such as Figure 39A3As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0091] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 39A4 The case shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 39A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0092] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 39A6 and Figure 39A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and the nodes between the transistors are supplied with a fixed potential V from the power supply or GND. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 39A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 39A6 and Figure 39A7 Since they are the same relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0093] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0094] Next, specific examples of the "direct connection" case are shown. As an example of the case where "A and B are directly connected," such as... Figure 39B1 , Figure 39B2 and Figure 39B3 As shown, there are cases where A and B are not connected through circuit components. Furthermore, as... Figure 39B4 and Figure 39B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 39B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0095] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0096] Furthermore, even when independent components are connected to each other in a circuit diagram, sometimes one component can function as multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film serves as both a wiring and an electrode. Therefore, the scope of "connection" in this specification also includes such cases where a conductive film functions as multiple components.

[0097] In this specification, a "resistive element" can be, for example, a circuit element having a resistance value greater than 0 Ω or a wiring having a resistance value greater than 0 Ω. Therefore, in this specification, a "resistive element" includes wiring with a resistance value, a transistor, a diode, or a coil through which current flows between the source and drain. Therefore, "resistive element" can sometimes be referred to as "resistor," "load," or "area with a resistance value." Conversely, "resistor," "load," or "area with a resistance value" can sometimes be referred to as "resistive element." As for the resistance value, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, it can also be 1 Ω or more and 1 × 10⁻¹⁰. 9 Below Ω.

[0098] In this specification, etc., "capacitor" can refer to, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, or the gate capacitance of a transistor. Furthermore, "capacitor" or "gate capacitance" is sometimes referred to as "capacitor" in the same way. In contrast, "capacitor" is sometimes referred to as "capacitor" or "gate capacitance". Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors holding the insulator. Thus, the "pair of conductors" of a "capacitor" can be referred to as a "pair of electrodes", a "pair of conductive regions", a "pair of regions", or a "pair of terminals". Furthermore, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. Furthermore, the electrostatic capacitance value can be, for example, 0.05fF or more and 10pF or less. Furthermore, for example, it can also be 1pF or more and 10μF or less.

[0099] In addition, in this specification, a switch refers to a component that controls whether current flows by changing to an on or off state. Alternatively, a switch refers to a component that selects and switches the current path.

[0100] In this specification, "conducting state" refers to a state in which current may flow between the two input / output terminals, and "non-conducting state" refers to a state in which the two input / output terminals are electrically disconnected. Furthermore, in this specification, the open state of a switch falls within the category of "conducting state," and the closed state falls within the category of "non-conducting state." Therefore, in this specification, the "conducting state" and "open state" of the switch can be interchanged, as can the "non-conducting state" and "closed state."

[0101] Furthermore, switches sometimes include two or more terminals besides the control terminals, allowing current to flow through. As an example, electrical switches or mechanical switches can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0102] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, MIS (Metal-insulator-semiconductor) diodes, or diode-connected transistors), or logic circuits that combine these components. When a transistor is used as a switch, the "on state" or "turn-on state" of a transistor refers, for example, to the state where current can flow between the source and drain electrodes of the transistor. Conversely, the "off state" or "turn-off state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conduction type).

[0103] As an example of a mechanical switch, a switch utilizing MEMS (microelectromechanical systems) technology can be cited. This switch has mechanically movable electrodes, and operates by controlling the on and off states through the movement of these electrodes.

[0104] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the switching between the transistor's on and off states. The two terminals used as the source or drain are the transistor's input and output terminals. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the two input / output terminals is used as the source, and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. In this specification, when describing the transistor's connection relationship, the terms "one of the source and drain" and "the other of the source and drain" are used. In this specification, sometimes one of the source and drain is referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other is referred to as the "second electrode of the transistor" or "second terminal of the transistor." Furthermore, depending on the transistor's structure, sometimes a back gate is included in addition to the three terminals mentioned above. In this case, in this specification, sometimes one of the transistor's gate and back gate is referred to as the first gate, and the other is referred to as the second gate. Furthermore, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc. in this specification.

[0105] For example, as described in this specification, a multi-gate transistor with two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure in which multiple transistors are connected in series. Therefore, by using a multi-gate structure, the off-state current can be reduced, and the transistor's voltage withstand capability (reliability) can be improved. Alternatively, by utilizing a multi-gate structure, when the transistor is operating in the saturation region, even if the voltage between the drain and source changes, the change in the drain and source current is not significant, thereby obtaining a voltage-current characteristic with a flat tilt angle. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with extremely high resistance can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0106] Furthermore, circuit diagrams illustrating a single circuit element sometimes include cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram illustrating a resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram illustrating a capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram illustrating a transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram illustrating a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0107] Furthermore, in this specification and other materials, the term "node" may also be referred to as "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit structure and device structure. Additionally, "terminal," "wiring," etc., may also be referred to as "node."

[0108] Furthermore, in this specification, etc., a selector sometimes refers to, for example, a circuit that includes multiple input terminals and one output terminal, and selects one from the multiple input terminals and establishes a conduction state between the selected input terminal and the output terminal. In other words, a selector sometimes refers to a circuit that selects one from each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to, for example, a circuit that includes multiple output terminals and one input terminal, and selects one from the multiple output terminals and establishes a conduction state between the selected output terminal and the input terminal. In other words, a selector sometimes refers to a circuit that selects one from multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. That is to say, a selector sometimes refers to a multiplexer or a multiplexer. In particular, in the case of inputting or outputting analog potentials or analog currents, a selector sometimes refers to an analog multiplexer or an analog multiplexer.

[0109] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and a reference potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0110] Furthermore, in this specification and other materials, "high-level potential" and "low-level potential" do not imply specific potentials. For example, if two wires are both labeled as "wires used to supply a high-level potential," the high-level potentials supplied by the two wires may be different. Similarly, if two wires are both labeled as "wires used to supply a low-level potential," the low-level potentials supplied by the two wires may be different.

[0111] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current is input to element A" can be replaced with the description "current is output from element A."

[0112] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. For example, in this specification and other documents, a "first" constituent element in one embodiment may be referred to as a "second" constituent element in other embodiments or claims. Furthermore, for example, in this specification and other documents, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0113] In this specification and other materials, for convenience, terms such as "upper" and "lower" are sometimes used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation in which each component is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately replaced as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180°.

[0114] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, if the expression is "electrode B on insulating layer A," it is not necessarily required that electrode B is formed in direct contact with insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, for example, if the expression is "electrode B above insulating layer A," it is not necessarily required that electrode B is formed in direct contact with insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, for example, if the expression is "electrode B below insulating layer A," it is not necessarily required that electrode B is formed in direct contact below insulating layer A; it may also include situations where other constituent elements are included between insulating layer A and electrode B.

[0115] Furthermore, in this specification and other materials, terms such as "row" and "column" are sometimes used to describe the matrix-like configuration of constituent elements and their positional relationships. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, by rotating the orientation of the accompanying drawings by 90°, the expression "row direction" may sometimes be replaced with "column direction."

[0116] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged depending on the context. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer." Additionally, depending on the situation, other terms may be used instead of "film" and "layer." For example, "conductive layer" or "conductive film" may sometimes be replaced with "conductor." Furthermore, "insulating layer" or "insulating film" may sometimes be replaced with "insulator."

[0117] Note that in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where one or more of "electrode," "wiring," and "terminal" are formed as one unit. Therefore, for example, an "electrode" can be part of "wiring" or "terminal," and vice versa. Furthermore, the terms "electrode," "wiring," or "terminal" are sometimes replaced with terms such as "area," depending on the context.

[0118] In this instruction manual and other documents, the terms "wiring," "signal line," or "power line" may be interchanged depending on the situation or circumstances. For example, sometimes "wiring" may be changed to "signal line." Similarly, sometimes "wiring" may be changed to "power line." Conversely, sometimes "signal line" or "power line" may be changed to "wiring." Sometimes "power line" may be changed to "signal line." Conversely, sometimes "signal line" may be changed to "power line." Furthermore, depending on the situation or circumstances, sometimes the "potential" applied to the wiring may be changed to "signal." Conversely, sometimes "signal" may be changed to "potential."

[0119] Furthermore, in this specification and the like, timing diagrams are sometimes used to illustrate the operation of semiconductor devices. Moreover, the timing diagrams used in this specification and the like show ideal operating examples, and unless otherwise specified, are not limited to the periods, signal (e.g., potential or current) magnitudes, and timing shown in the timing diagram. In the timing diagrams of this specification and the like, the magnitudes and timing of signals (e.g., potential or current) input to each wiring (including nodes) in the timing diagram can be changed depending on the situation. For example, even if two periods are shown at equal intervals in the timing diagram, the lengths of the two periods may sometimes be different. Furthermore, for example, even if one period is shown to be longer than the other, the lengths of the two periods may sometimes be the same, or sometimes one period may be shorter than the other. Additionally, to clearly illustrate the timing diagram, sometimes overlapping signals are intentionally staggered in the illustration.

[0120] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor that has at least one of amplification, rectification, and switching functions, the metal oxide can be called a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0121] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0122] Furthermore, in this specification and the like, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 at.% are considered impurities. When impurities are present, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0123] In this specification, "parallel" means the angle between two straight lines is -10° or higher and less than 10°. Therefore, it also includes angles between -5° or higher and less than 5°. "Approximately parallel" means the angle between two straight lines is -30° or higher and less than 30°. Furthermore, "perpendicular" means the angle between two straight lines is 80° or higher and less than 100°. Therefore, it also includes angles between 85° or higher and less than 95°. "Approximately perpendicular" means the angle between two straight lines is 60° or higher and less than 120°.

[0124] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0125] Furthermore, the content described in one embodiment (part or all of it) may be applied / combined / replaced with at least one of the other content described in that embodiment (part or all of it) and the content described in one or more other embodiments (part or all of it).

[0126] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0127] Furthermore, more figures can be formed by combining the figures shown in one embodiment (part or all of them) with other parts of the figures, other figures shown in that embodiment (part or all of them), and at least one figure shown in one or more other embodiments (part or all of them).

[0128] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0129] In this specification and other materials, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in the accompanying drawings and other materials, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other materials, these symbols are sometimes omitted.

[0130] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings illustrate idealized examples and are not limited to the shapes or values ​​shown.

[0131] (Implementation Method 1) This embodiment describes a pixel circuit of a semiconductor device according to one aspect of the present invention.

[0132] First, the circuit structure of the existing pixel circuit will be described. This pixel circuit is arranged in a matrix in the pixel array of the display device, and can display an image (in this specification, "image" includes both static and dynamic images) by sending specified signals to the wiring extending in the rows and columns.

[0133] Figure 2A This is an example of a circuit diagram illustrating the circuit structure of a conventional pixel circuit, which includes three transistors, a capacitor, and a light-emitting device. Specifically, Figure 2A The pixel circuit PX1 shown includes transistor DM, transistor M1, transistor M2, capacitor C1, and light-emitting device ED.

[0134] In particular, transistor M1 is used as a write transistor, in which image data is written to and retained in pixel circuit PX1. Furthermore, transistor M2 is used as a transistor to determine whether a fixed potential (sometimes referred to as the initialization potential) is applied to the anode of the light-emitting device ED and the first terminal of transistor DM. Note that both transistors M1 and M2 are used as switching transistors, and both are sometimes referred to as switching transistors.

[0135] Furthermore, the transistor DM is used as a driving transistor, where the amount of current flowing between the source and drain is determined based on the image data. Therefore, the transistor DM is sometimes referred to as a driving transistor.

[0136] As an example, transistors M1, M2, and DM are preferably OS transistors. In particular, the metal oxide contained in the channel forming region of the OS transistor can be, for example, indium oxide, gallium oxide, and zinc oxide. Furthermore, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Note that element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0137] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO) is preferred. Alternatively, an oxide containing indium, tin, and zinc (also denoted as ITZO (registered trademark)) is preferred. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also denoted as IAZO) is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also denoted as IAGZO) is preferred. The OS transistor will be described in detail in Embodiment 5.

[0138] Furthermore, transistors other than OS transistors can be used, selected from one or more of transistors M1, M2, and DM. For example, transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors) can be cited as examples of transistors other than OS transistors. In addition, as silicon, examples include monocrystalline silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)).

[0139] In addition, as transistors other than OS transistors and Si transistors, examples include transistors containing germanium in the channel formation region, transistors containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region.

[0140] Note that, although Figure 2A Transistors M1, M2, and DM shown are n-channel transistors, but they can also be p-channel transistors depending on the situation. That is, the polarities of transistors M1, M2, and DM can be either n-channel or p-channel. Furthermore, in Figure 2A In replacing an n-channel transistor with a p-channel transistor, the potential input to the pixel circuit PX1 needs to be appropriately changed to ensure its proper operation. Furthermore, the connections of the anode and cathode of the light-emitting device (ED) also need to be altered. For example, when the transistor DM is a p-channel transistor, it is preferable that the anode of the ED is connected to the wiring CTH, and the cathode of the ED is connected to the first terminal of the transistor DM, using the wiring CTH as a power supply. AN The wiring, and the wiring AN is used as the supply V. CTH Wiring.

[0141] Note that regarding the choice of polarity for the aforementioned transistors, besides... Figure 2A In addition, the transistors described in other parts of the specification or shown in other figures are the same. Furthermore, in this embodiment, the structure and operation of the pixel circuit PX1 are described assuming that transistors M1, M2, and DM are n-channel transistors.

[0142] Furthermore, the transistor DM, as the driving transistor, preferably operates such that the current corresponding to the gate-source voltage flows between the source and drain, but the current corresponding to the source-drain voltage does not flow. In other words, the transistor DM preferably operates in the saturation region when in the on-state. By operating the transistor DM in the saturation region, the amount of current flowing through the transistor DM can be determined based on the gate-source voltage. Furthermore, by operating the transistor DM in the saturation region, even if the source-drain voltage of the transistor DM changes, the change in drain current is minimal. That is, by determining the amount of current flowing through the transistor DM based on the gate-source voltage, the transistor DM can ensure a stable current flows between the anode and cathode of the light-emitting device ED. Additionally, depending on the situation, the transistor DM may also operate in the linear region when in the on-state. Furthermore, the transistor DM may also operate in the subthreshold region.

[0143] Furthermore, the above description of the transistor can be applied not only to transistor DM, but also to transistors described in other parts of the specification and those shown in the accompanying drawings.

[0144] As the light-emitting device (ED), examples include organic EL elements (OLEDs, inorganic EL elements, LEDs (including micro-LEDs), QLEDs (quantum-dot light-emitting diodes), or semiconductor lasers. Note that in this embodiment, the pixel circuit PX1 is described using a light-emitting device containing organic EL materials. In particular, the brightness of the light emitted from a light-emitting device capable of emitting light with high brightness can, for example, be 500 cd / m². 2 The above is preferably 1000 cd / m 2 Above and 10000 cd / m 2 The following is more preferably 2000 cd / m 2 Above and 5000 cd / m 2 the following.

[0145] The first terminal of transistor M1 is connected to the gate of transistor DM and the first terminal of capacitor C1. Furthermore, the first terminal of transistor M2 is connected to the first terminal of transistor DM, the second terminal of capacitor C1, and the anode of the light-emitting device ED.

[0146] Note that in Figure 2AIn the diagram, the region where the first terminal of transistor M1, the gate of transistor DM, and the first terminal of capacitor C1 are connected to each other is illustrated as node N1. Furthermore, the region where the first terminal of transistor M2, the first terminal of transistor DM, the second terminal of capacitor C1, and the anode of light-emitting device ED are connected to each other is illustrated as node N2.

[0147] The second terminal of transistor M1 is connected to wiring SL. Furthermore, the gate of transistor M1 is connected to wiring GL1. Furthermore, the second terminal of transistor M2 is connected to wiring V0E. Furthermore, the second terminal of transistor DM is connected to wiring AN. Furthermore, the cathode of the light-emitting device ED is connected to wiring CTH.

[0148] As an example, wiring GL1 and wiring GL2 are used as selection signal lines corresponding to pixel circuit PX1. In particular, wiring GL1 is used as a first selection signal line (sometimes referred to as a first gate line) to select the pixel circuit PX1 to be written during image data writing operations. Furthermore, wiring GL2 is used as a second selection signal line (sometimes referred to as a second gate wiring) to select the pixel circuit PX1 including node N2 when it is desired to supply a fixed potential from wiring V0E to node N2.

[0149] Note that, as an example, in pixel circuit PX1, the select signal sent to routing GL1 is a high-level potential, and the non-select signal sent to routing GL1 is a low-level potential. Furthermore, as an example, the select signal sent to routing GL2 is a high-level potential, and the non-select signal sent to routing GL2 is a low-level potential.

[0150] As an example, wiring SL is used as wiring (sometimes referred to as source line or data line) to send image signals corresponding to image data written to pixel circuit PX1.

[0151] As an example, wiring V0E is used to supply a fixed potential (the potential used for initialization) to node N2. Note that in this specification, for convenience, this fixed potential is denoted as V0.

[0152] As an example, wiring AN is used as the wiring to supply a fixed potential to the second terminal of transistor DM. Note that, for convenience, this fixed potential is denoted as V in this specification. AN Furthermore, wiring AN is also used as wiring to allow current to flow through the anode of the light-emitting device ED. Additionally, as an example, wiring CTH is used as wiring to supply a fixed potential to the cathode of the light-emitting device ED. Note that in this specification, for convenience, this fixed potential is denoted as V. CTH .

[0153] Furthermore, in the operation of the pixel circuit PX1, it is preferable to operate with V0-V CTH V0 is set in a manner lower than the threshold voltage at which the light-emitting device (ED) emits light. Therefore, V0 can also be lower than V CTH The potential. Through V0-V CTH If the voltage is below the threshold voltage at which the light-emitting device (ED) emits light, the ED can be prevented from emitting light when V0 is supplied from wiring V0E to node N2.

[0154] In addition, V AN V is preferred CTH A potential above V0 is applied. Therefore, a forward bias voltage is applied between the anode and cathode of the light-emitting device (ED), allowing the ED to emit light according to the brightness of the image data written to the pixel circuit PX.

[0155] Next, an example of how the pixel circuit PX1 works will be explained.

[0156] When image data is written to pixel circuit PX1, firstly, a high-level potential is supplied to wiring GL2 as a selection signal. This high-level potential is then supplied to the gate of transistor M2, thus turning transistor M2 on.

[0157] When transistor M2 is in the ON state, the first terminal of transistor DM, the first terminal of capacitor C1, and the anode of light-emitting device ED are in a conductive state with wiring VOE. Therefore, the potential of node N2 is V0 supplied by wiring VOE.

[0158] Next, while transistor M2 is in the ON state, a high-level potential is supplied to wiring GL1 as a selection signal. This high-level potential is then supplied to the gate of transistor M1, thus putting transistor M1 in the ON state.

[0159] While transistor M1 is in the ON state, an image signal corresponding to the image data is transmitted from wiring SL to pixel circuit PX1. Therefore, the potentials of the gate of transistor DM and the first terminal of the first capacitor are corresponding to the potentials of this image signal. Here, this potential is V. PS .

[0160] After the image signal is written to the pixel circuit PX1, a low-level potential is supplied to wiring GL1 as a non-selection signal. Consequently, the gate of transistor M1 is supplied with this low-level potential, and therefore transistor M1 is in the off state. At this time, node N1 is in a floating state, V PS The voltage of V0 is maintained between the first and second terminals of capacitor C1. Furthermore, V PS -V0 is also the gate-source voltage of transistor DM.

[0161] Similarly, after the image signal is written to the pixel circuit PX1, a low-level potential is supplied to the wiring GL2 as a non-selection signal. As a result, the gate of transistor M2 is supplied with this low-level potential, and therefore transistor M2 is in the off state.

[0162] Here, when transistor DM is in the ON state, in other words, when the gate-source voltage V of transistor DM is... PS When V0 exceeds the threshold voltage of transistor DM, node N2 is supplied with charge from wiring AN, and the potential of node N2 rises from V0. Meanwhile, node N1 is in a floating state; therefore, through capacitive coupling with capacitor C1, the potential of node N1 rises as the potential of node N2 rises. Ideally, the potential rise of node N1 should be equal to the potential rise of node N2, and the gate-source voltage of transistor DM should remain at V0. PS -V0 without change.

[0163] Note that in this embodiment, the potential rise of nodes N1 and N2 is set as ΔV. Therefore, the potential of node N1 is V0 + ΔV, and the potential of node N2 is V0 + ΔV. PS +ΔV. Note that ΔV is V. CTH The above and V AN The potentials below are determined by the voltage division between the transistor DM and the light-emitting device ED. Specifically, ΔV depends on the resistance values ​​of the transistor DM and the light-emitting device ED.

[0164] Furthermore, when transistor DM operates in the saturation region, a voltage V corresponding to the gate-source voltage V flows between the source and drain of transistor DM. PS -V0 is the amount of current. In addition, this current is input to the anode of the light-emitting device (ED), so the ED emits light with a brightness corresponding to this amount of current.

[0165] Through the above process, image data is written into pixel circuit PX1, and light corresponding to the brightness of the image data is emitted from pixel circuit PX1, thereby displaying the image data.

[0166] Note that in Figure 2A In the diagram, pixel circuit PX1 is connected to two selection signal lines, GL1 and GL2. However, GL1 and GL2 can also be combined into a single wiring configuration. According to the description of the operation of pixel circuit PX1, transistors M1 and M2 are in the on or off state simultaneously. Therefore, the two selection signal lines, GL1 and GL2, can be combined into one. For example... Figure 2B Showing will Figure 2AWiring GL1 and wiring GL2 are combined into a single wiring structure called wiring GL1. Therefore, wiring GL1 is connected to the gates of transistor M1 and M2. For example... Figure 2B As shown, in Figure 2A In this process, by combining wiring GL1 and wiring GL2 into a single wiring GL1, the number of wirings extending on the pixel array can be reduced, thus increasing the aperture ratio of the pixel circuitry. Furthermore, this improves the screen resolution of the pixel array and enhances its sharpness.

[0167] Furthermore, in display devices including pixel circuit PX1, when primarily displaying static images, it is preferable to operate the display device at a low frame rate. Compared to dynamic images, the image rewrite frequency required for displaying static images is less, thus allowing for a lower frame rate. Consequently, the number of operations of the drive circuit is reduced, thereby lowering the power consumption of the display device.

[0168] Furthermore, when the display device operates at a low frame rate, the refresh frequency of the image data written to the pixel circuit PX1 is also reduced. Therefore, the pixel circuit PX1 preferably has a structure that can retain image data in node N1 for a long time. On the other hand, in Figure 2A and Figure 2B In this process, when the off-state current (sometimes called leakage current) of transistor M1 is large, the potential corresponding to the image data held in node N1 changes due to the discharge of this off-state current, thus degrading the image data. Consequently, the display quality of the image displayed by the display device decreases.

[0169] In addition, Figure 2A and Figure 2B In the process, when the off-state current of transistor M2 is large, during the display of the image in pixel circuit PX1, current sometimes flows from the first terminal of transistor DM through the source-drain junction of transistor M2 and through wiring V0E. As a result, the amount of current flowing through the light-emitting device ED is less than the predetermined amount, thus reducing the brightness of the light emitted by the light-emitting device ED, thereby degrading the display quality of the image displayed by the display device.

[0170] <Structure example of pixel circuit PX1A> One aspect of the semiconductor device of the present invention is a pixel circuit for the purposes described above, which can reduce the off-state current of transistors M1 and M2.

[0171] Figure 1 The pixel circuit PX1A shown is a semiconductor device according to one aspect of the present invention, and is a modification. Figure 2A The pixel circuit PX1 circuit. Figure 1 The pixel circuit PX1A and Figure 2AThe pixel circuit PX1 differs in that it includes transistors T1A, T1B, T2A, and T2B. Furthermore, Figure 1 The pixel circuit PX1A and Figure 2A The difference between the pixel circuit PX1 and the former is that transistors M1 and M2 include a back gate.

[0172] Specifically, as an example, Figure 1 The transistors M1 and M2 shown are transistors that include gates at the top and bottom of the channel. Both transistors M1 and M2 include a gate (sometimes referred to as a first gate) and a back gate (sometimes referred to as a second gate). Furthermore, the gate and back gate can be interchanged. Therefore, in this specification, etc., "gate" can be referred to as "back gate." Similarly, "back gate" can be referred to as "gate." Specifically, the connection structure of "gate connected to the first wiring and back gate connected to the second wiring" can be replaced by the connection structure of "back gate connected to the first wiring and gate connected to the second wiring."

[0173] also, Figure 1 The pixel circuit PX1A shown includes a switching section SW1 and a switching section SW2. Switching section SW1 includes the aforementioned transistors M1, T1A, and T1B, and switching section SW2 includes the aforementioned transistors M2, T2A, and T2B. When... Figure 1 The pixel circuit PX1A and Figure 2A When comparing the pixel circuit PX1, Figure 1 The pixel circuit PX1A can be said to have in Figure 2A The pixel circuit PX1 has a structure in which transistor M1 is replaced by switch SW1 and transistor M2 is replaced by switch SW2.

[0174] Transistors T1A, T1B, T2A, and T2B can be transistors that can be applied to transistors M1, M2, or DM, for example.

[0175] In the switching section SW1, the back gate of transistor M1 is connected to the first terminal of transistor T1A and the first terminal of transistor T1B. Furthermore, the second terminal of transistor T1A is connected to wiring V2A, and the gate of transistor T1A is connected to wiring GL1. Additionally, the second terminal of transistor T1B is connected to wiring V3A, and the gate of transistor T1B is connected to wiring GL1B.

[0176] In particular, wiring GL1 is preferably connected to the gate of transistor M1 and the gate of transistor T1A.

[0177] Furthermore, in the switching section SW2, the back gate of transistor M2 is connected to the first terminal of transistor T2A and the first terminal of transistor T2B. Additionally, the second terminal of transistor T2A is connected to wiring V2B, and the gate of transistor T2A is connected to wiring GL2. Furthermore, the second terminal of transistor T2B is connected to wiring V3B, and the gate of transistor T2B is connected to wiring GL2B.

[0178] In particular, wiring GL2 is preferably connected to the gate of transistor M2 and the gate of transistor T2A.

[0179] Wiring GL1B is used as a selection signal line for pixel circuit PX1A. Specifically, wiring GL1B is a selection signal line paired with wiring GL1; when pixel circuit PX1A is operating, wiring GL1B is a signal whose logic is inverted by the signal sent to wiring GL1. Specifically, for example, when pixel circuit PX1A is selected as the object of image data writing and the logic of the selection signal input to wiring GL1 corresponds to "1", the logic of the selection signal input to wiring GL1B is "0". Furthermore, when pixel circuit PX1A is not selected as the object of image data writing, the logic of the non-selection signal input to wiring GL1 is "0" and the logic of the non-selection signal input to wiring GL1B is "1".

[0180] In other words, when pixel circuit PX1A is selected as the target for writing image data, wiring GL1 and wiring GL1B supply a set of selection signals to pixel circuit PX1A. Furthermore, when pixel circuit PX1A is not selected as the target for writing image data, wiring GL1 and wiring GL1B supply a set of non-selection signals to pixel circuit PX1A.

[0181] Note that in pixel circuit PX1A, the logic level for "1" is high and the logic level for "0" is low. Therefore, when pixel circuit PX1A is selected as the target for image data writing, wiring GL1 is input with a high-level potential as a selection signal, and wiring GL1B is input with a low-level potential as a selection signal. In other words, when pixel circuit PX1A is selected as the target for image data writing, as the selection signal group, wiring GL1 supplies a high-level potential to pixel circuit PX1A, and wiring GL1B supplies a low-level potential to pixel circuit PX1A.

[0182] Furthermore, when pixel circuit PX1A is not selected as the object to be written to for image data, wiring GL1 is supplied with a low-level potential as a non-selection signal, and wiring GL1B is supplied with a high-level potential as a non-selection signal. In other words, when pixel circuit PX1A is not selected as the object to be written to for image data, wiring GL1 supplies a low-level potential to pixel circuit PX1A, and wiring GL1B supplies a high-level potential to pixel circuit PX1A as a non-selection signal group.

[0183] Furthermore, wiring GL2B is used as a selection signal line for pixel circuit PX1A. Specifically, wiring GL2B is a selection signal line paired with wiring GL1; when pixel circuit PX1A is operating, wiring GL2B is a signal whose logic is inverted by the signal sent to wiring GL2. Specifically, for example, when pixel circuit PX1A is selected as the object of image data writing and the logic of the selection signal input to wiring GL2 corresponds to "1", the logic of the selection signal input to wiring GL2B is "0". Furthermore, when pixel circuit PX1A is not selected as the object of image data writing, the logic of the non-selection signal input to wiring GL2 is "0" and the logic of the non-selection signal input to wiring GL2B is "1".

[0184] In other words, when pixel circuit PX1A is selected as the object to be written to for image data, wiring GL2 and wiring GL2B supply a group of selection signals to pixel circuit PX1A, similar to wiring GL1 and wiring GL1B. Furthermore, when pixel circuit PX1A is not selected as the object to be written to for image data, wiring GL1 and wiring GL1B supply a group of non-selection signals to pixel circuit PX1A.

[0185] Furthermore, as described above, in pixel circuit PX1A, the logic of "1" corresponds to a high-level potential, and the logic of "0" corresponds to a low-level potential. At this time, when pixel circuit PX1A is selected as the object to be written to for image data, a high-level potential is input to wiring GL2 as a selection signal, and a low-level potential is input to wiring GL2B as a selection signal. That is, when pixel circuit PX1A is selected as the object to be written to for image data, as a group of selection signals, wiring GL2 supplies a high-level potential to pixel circuit PX1A, and wiring GL2B supplies a low-level potential to pixel circuit PX1A.

[0186] Furthermore, when pixel circuit PX1A is not selected as the object to be written to for image data, wiring GL2 is supplied with a low-level potential as a non-selection signal, and wiring GL2B is supplied with a high-level potential as a non-selection signal. In other words, when pixel circuit PX1A is not selected as the object to be written to for image data, wiring GL2 supplies a low-level potential to pixel circuit PX1A, and wiring GL2B supplies a high-level potential to pixel circuit PX1A as a non-selection signal group.

[0187] As an example, wiring V2A is used to supply a fixed potential. In particular, this fixed potential is preferably the same as or higher than the high-level potential of the selection signal supplied to wiring GL1.

[0188] As an example, wiring V2B is used as a wiring to supply a fixed potential. In particular, this fixed potential is preferably the same as or higher than the high-level potential of the selection signal supplied to wiring GL2.

[0189] As an example, wiring V3A is used to supply a fixed potential. In particular, this fixed potential is preferably negative. Furthermore, when the threshold voltage of transistor T1B is V... th_T1B When this fixed potential is preferably -V th_T1B .

[0190] As an example, wiring V3B is used to supply a fixed potential. In particular, this fixed potential is preferably negative. Furthermore, when the threshold voltage of transistor T2B is V... th_T2B When this fixed potential is preferably -V th_T2B .

[0191] <<Switch Section SW1 and Switch Section SW2>> Next, we will explain the working examples of switch section SW1 and switch section SW2.

[0192] Figure 3A It is an excerpt Figure 1 The diagram shows the circuit diagram of the switching section SW1, wiring GL1, and wiring GL1B of the pixel circuit PX1A. Note that in Figure 3A In this configuration, the second terminal of transistor M1 is used as terminal ITA of switch SW1, and the first terminal of transistor M1 is used as terminal ITB of switch SW1.

[0193] also, Figure 3B Show Figure 3A The timing diagram shows an example of the operation of the switching unit SW1. Specifically, Figure 3B The timing diagram shows the potential variations of wiring GL1 and wiring GL1B from time T01 to time T04 and in the vicinity. Furthermore, in this example, the high-level potential is denoted as V. H Let the low-level potential be denoted as V. L .

[0194] Furthermore, as described above, the signal input to wiring GL1B is the logic signal that is inverted by the signal input to wiring GL1. For example, when wiring GL1 is input to V... H At that time, wiring GL1B is input V L Furthermore, when wiring GL1 is input to V L At that time, wiring GL1B is input V H .

[0195] In addition, V2A is supplied as a fixed potential and V is input to wiring GL1. HThe same potential. Furthermore, the wiring V3A is supplied with a negative potential -V as a fixed potential. th_T1B Note that V th_T1B It is the threshold voltage of transistor T1B.

[0196] During the period from time T01 to time T02, wiring GL1 is input to V. L The wiring GL1B is input to V. H At this time, the gates of transistors M1 and T1A are respectively input with V. L The gate of transistor T1B is input V H Therefore, transistors M1 and T1A are both in the off state, while transistor T1B is in the on state.

[0197] Therefore, the back gate of transistor M1 is connected to wiring V3A through transistor T1B. Consequently, the back gate of transistor M1 is supplied with a negative potential -V from wiring V3A. th_T1B As a result, the threshold voltage of transistor M1 shifts to the positive side, thus reducing the off-state current of transistor M1.

[0198] During the period from time T02 to time T03, wiring GL1 is input to V. H The wiring GL1B is input to V. L At this time, the gates of transistors M1 and T1A are respectively input with V. H The gate of transistor T1B is input V L Therefore, transistors M1 and T1A are both in the ON state, while transistor T1B is in the OFF state.

[0199] Therefore, the back gate of transistor M1 is connected to wiring V2A through transistor T1A. Thus, the charge from wiring V2A is supplied from wiring GL1B through the first and second terminals of transistor T1A to the back gate of transistor M1. Furthermore, transistor T1A is an n-channel transistor, and when the threshold voltage of transistor T1A is V... th_T1A At that time, the potential of the back gate of transistor M1 rises to V. H -V th_T1A Therefore, the potential of the back gate of transistor M1 is used as a potential close to a high level to supply V. H -V th_T1A Therefore, the threshold voltage of transistor M1 drifts to the negative side, thereby increasing the on-state current of transistor M1.

[0200] During the period from time T03 to time T04, wiring GL1 is input to V. L The wiring GL1B is input to V. HThis is the same as the operation of the switch unit SW1 during the period from time T01 to time T02. Therefore, the explanation of the operation during the period from time T03 to time T04 can refer to the explanation of the operation of the switch unit SW1 during the period from time T01 to time T02.

[0201] Therefore, by configuring the switching section SW1, the on-state current of transistor M1 can be increased and the current flowing between terminals ITA and ITB can be increased when transistor M1 is in the on state. Furthermore, the off-state current of transistor M1 can be decreased and the leakage current flowing between terminals ITA and ITB can be decreased when transistor M1 is in the off state.

[0202] also, Figure 1 The circuit structure of the switching section SW2 is the same as that of the switching section SW1. Therefore, the operation of the switching section SW2 can be described with reference to the operation of the switching section SW1 described above. Thus, by configuring the switching section SW2, the on-state current of the transistor M2 can be increased when the transistor M2 is in the on state, and the off-state current of the transistor M2 can be decreased when the transistor M2 is in the off state.

[0203] Note that in Figure 3A In the switching section SW1, neither transistor T1A nor transistor T1B includes a back gate, but both transistors T1A and T1B may also include a back gate. Furthermore, one or both of transistors T1A and T1B may have a structure where the gate and back gate are connected to each other. Figure 4 In the switch section SW1 shown, the gate and back gate of transistor T1A are connected to each other, and the gate and back gate of transistor T1B are also connected to each other. Thus, by using transistors with their gates and back gates connected, the on-state current of the transistor can be increased, and the off-state current can be decreased. In particular, by increasing the on-state current, the charge accumulation rate at the back gate of transistor T1B also increases, thereby improving the switching speed (switching speed) between the on and off states of terminals ITA and ITB in the switch section SW1.

[0204] Furthermore, unless otherwise specified, the presence or absence of a back gate in the illustrated transistors is not limited in this specification, the accompanying drawings, etc. For example, in the accompanying drawings, even if a back gate is not provided in the transistor, the transistor may include a back gate depending on the circumstances. Moreover, when a transistor includes a back gate, the connection object of the back gate can be determined during the design phase. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, [the following is possible:] ... Figure 4Similarly, transistors T1A or T1B can also have their gates connected to their back gates. Furthermore, for example, in a transistor including a back gate, to vary the threshold voltage of the transistor or reduce its off-state current, wiring connected to an external circuit can be provided to supply a fixed or variable potential to the back gate of the transistor through that external circuit.

[0205] <<Examples of PX1A Pixel Circuit Operation>> Next, the explanation Figure 1 The image shows a working example of the pixel circuit PX1A.

[0206] Figure 5 Show Figure 1 The timing diagram shows an example of the operation of the pixel circuit PX1A. Specifically, Figure 5 The timing diagram shows the potential variations of routing GL1 and GL1B, routing GL2, routing GL2B, node N1, and node N2 from time T11 to time T17 and in the vicinity. Furthermore, Figure 5 The timing diagram also shows the image signal sent to the wiring SL. Furthermore, in this working example, the high-level potential is denoted as V. H Let the low-level potential be denoted as V. L .

[0207] Furthermore, as described above, the signal input to wiring GL1B is the logic signal that is inverted by the input to wiring GL1. For example, when wiring GL1 is input to V... H At that time, wiring GL1B is input V L Furthermore, when wiring GL1 is input to V L At that time, wiring GL1B is input V H Similarly, the signal input to GL2B is the inverted logic signal input to GL2. For example, when GL2 is input to V... H At that time, the wiring GL2B is input to V L Furthermore, in the wiring GL2, the input V L At that time, the wiring GL2B is input to V H .

[0208] In addition, V0 is supplied as a fixed potential for wiring V0E, and V is supplied as a fixed potential for wiring AN. AN For wiring CTH, a fixed potential is supplied with V. CTH .

[0209] In addition, V2A is supplied as a fixed potential and V is input to wiring GL1. H The same potential. Furthermore, the wiring V3A is supplied with a negative potential -V as a fixed potential. th_T1B Note that V th_T1BThis is the positive threshold voltage of transistor T1B. Furthermore, wiring V3B is supplied with a fixed potential along with the V input to wiring GL2. H The same potential. Furthermore, the wiring V3B is supplied with a negative potential -V as a fixed potential. th_T2B Note that V th_T2B This is the positive threshold voltage of transistor T2B.

[0210] In addition, Figure 5 In the time series diagram, before time T11, the potential of node N1 is V. N1 The potential of node N2 is V. N2 .

[0211] During the period from time T11 to time T12, groups of wiring GL1 and GL1B, and groups of wiring GL2 and GL2B, are sent as non-selection signals to pixel circuit PX1A. Specifically, as a selection signal group, wiring GL1 is input to V. L The signal V input to the wiring GL1B is the inverted input of the logic signal to the wiring GL1. H Furthermore, as a group of selection signals, wiring GL2 is input to V. L And the wiring GL2B is input V H The signal is the logic inversion of the signal input to wiring GL2.

[0212] Therefore, the gate of transistor M1 is supplied with V from wiring GL1. L Transistor M1 is in the off state. Furthermore, the gate of transistor M2 is also supplied with V from wiring GL2. L Transistor M2 is also in the off state.

[0213] Furthermore, in the switching section SW1, the gate of transistor T1A is supplied with V from wiring GL1. L Transistor T1A is in the off state. Furthermore, the gate of transistor T1B is supplied with V from wiring GL1B. H Transistor T1B is in the ON state.

[0214] With transistor T1A in the off state and transistor T1B in the on state, the back gate of transistor M1 is supplied with a negative potential (-V) from wiring V3A through transistor T1B. th_T1B In other words, the threshold voltage of transistor M1 shifts to the positive side, thereby reducing the off-state current of transistor M1.

[0215] Furthermore, in the switching section SW2, the gate of transistor T2B is supplied with V from wiring GL2. L Transistor T2A is in the off state. Furthermore, the gate of transistor T2B is supplied with V from wiring GL2B. HTransistor T2B is in the ON state.

[0216] With transistor T2A in the off state and transistor T2B in the on state, the back gate of transistor M2 is supplied with a negative potential of -V through transistor T2B from wiring V3B. th_T2B In other words, the threshold voltage of transistor M2 shifts to the positive side, thereby reducing the off-state current of transistor M2.

[0217] During the period from time T12 to time T13, wiring GL2 and wiring GL2B are sent a group of selection signals to select pixel circuit PX1A. As a result, the potential of wiring GL2 changes from V... L Migrate to V H Furthermore, the potential of wiring GL2B is from V H Migrate to V L .

[0218] Therefore, in the switching section SW2, the gate of transistor M2 is supplied with V from wiring GL2. H Transistor M2 is in the ON state. Furthermore, the gate of transistor T2A is supplied with V from wiring GL2. H Transistor T2A is in the ON state. Furthermore, the gate of transistor T2B is supplied with V from wiring GL2B. L Transistor T2B is in the off state.

[0219] With transistor T2A in the ON state and transistor T2B in the OFF state, charge accumulates at the back gate of transistor M2 through transistor T2A from wiring V2B, causing the potential of the back gate of transistor M2 to rise to V. H -V th_T2A As a result, the threshold voltage of transistor M2 shifts to the negative side, while the on-state current of transistor M2 increases.

[0220] Furthermore, since transistor M2 is in the ON state, the first terminal of transistor DM, the second terminal of capacitor C1, and the anode of the light-emitting device ED are supplied with potential V0 from wiring V0E. Therefore, the potential of node N2 is V0.

[0221] Note, for example, by setting V0 to V CTH At the following potentials, current does not easily flow from the anode to the cathode of the light-emitting device (ED), thus preventing the ED from emitting light.

[0222] During the period from time T13 to time T16, the wiring SL is sent with the image signal PS.

[0223] During the period from time T14 to time T15, wiring GL1 and wiring GL1B are sent with a group of selection signals to select pixel circuit PX1A. As a result, the potential of wiring GL1 changes from V...L Migrate to V H Furthermore, the potential of wiring GL1B is from V H Migrate to V L .

[0224] Therefore, in the switching section SW1, the gate of transistor M1 is supplied with V from wiring GL1. H Transistor M1 is in the ON state. Furthermore, the gate of transistor T1A is supplied with V from wiring GL1. H Transistor T1A is in the ON state. Furthermore, the gate of transistor T1B is supplied with V from wiring GL1B. L Transistor T1B is in the off state.

[0225] With transistor T1A in the ON state and transistor T1B in the OFF state, charge accumulates at the back gate of transistor M1 through transistor T1A from wiring V2A, causing the potential of the back gate of transistor M1 to rise to V. H -V th_T1A As a result, the threshold voltage of transistor M1 shifts to the negative side, while the on-state current of transistor M1 increases.

[0226] Furthermore, transistor M1 is in the ON state, therefore the gate of transistor DM and the first terminal of capacitor C1 are supplied with the potential V from wiring SL according to the image signal PS. PS Therefore, the potential of node N1 is V. PS .

[0227] During the period from time T15 to time T16, wiring GL1 and wiring GL1B are sent a group of non-selection signals. As a result, the potential of wiring GL1 changes from V... H Migrate to V L Furthermore, the potential of wiring GL1B is from V L Migrate to V H .

[0228] Therefore, in the switching section SW1, the gate of transistor M1 is supplied with V from wiring GL1. L Transistor M1 is in the off state. Furthermore, the gate of transistor T1A is supplied with V from wiring GL1. L Transistor T1A is in the off state. Furthermore, the gate of transistor T1B is supplied with V from wiring GL1B. H Transistor T1B is in the ON state.

[0229] With transistor T1A in the off state and transistor T1B in the on state, the back gate of transistor M1 is supplied with a negative potential of -V through transistor T1B from wiring V3A. th_T1BIn other words, the threshold voltage of transistor M1 shifts to the positive side, thereby reducing the off-state current of transistor M1.

[0230] With transistor M1 in the off state, the potential V PS Remain at node N1. Furthermore, at this time, the gate-source voltage of transistor DM is V. PS -V0. Furthermore, the off-state current of transistor M1 decreases, thus preventing the potential V held at node N1 due to leakage current in transistor M1 from being lost. PS The decrease in voltage V can thus reduce the potential V PS It remains at node N1 for an extended period of time.

[0231] During the period from time T16 to time T17, wiring GL2 and wiring GL2B are sent a group of non-selection signals. As a result, the potential of wiring GL2 changes from V... H Migrate to V L Furthermore, the potential of wiring GL2B is from V L Migrate to V H .

[0232] Therefore, in the switching section SW2, the gate of transistor M2 is supplied with V from wiring GL2. L Transistor M2 is in the off state. Furthermore, the gate of transistor T2A is supplied with V from wiring GL2. L Transistor T2A is in the off state. Furthermore, the gate of transistor T2B is supplied with V from wiring GL2B. H Transistor T2B is in the ON state.

[0233] With transistor T2A in the off state and transistor T2B in the on state, the back gate of transistor M2 is supplied with a negative potential of -V through transistor T2B from wiring V3B. th_T2B In other words, the threshold voltage of transistor M2 shifts to the positive side, thereby reducing the off-state current of transistor M2.

[0234] Here, when transistor DM is in the ON state, in other words, when the gate-source voltage V of transistor DM is... PS When V0 exceeds the threshold voltage of transistor DM, node N2 is supplied with charge from wiring AN, and the potential of node N2 rises from V0. Meanwhile, node N1 is in a floating state; therefore, through capacitive coupling with capacitor C1, as the potential of node N2 rises, the potential of node N1 also rises by ΔV. Ideally, the potential rise of node N1 should be equal to the potential rise of node N2 by ΔV, and the gate-source voltage of transistor DM should remain at V. PS -V0 remains unchanged. Note that at this point, the potential of node N1 is V. PS+ΔV, the potential of node N2 is V0+ΔV.

[0235] Furthermore, when transistor DM operates in the saturation region, a voltage V corresponding to the gate-source voltage V flows between the source and drain of transistor DM. PS -V0 is the amount of current. In addition, this current is input to the anode of the light-emitting device (ED), so the ED emits light with a brightness corresponding to this amount of current.

[0236] Furthermore, by reducing the off-state current of transistor M2, the leakage current flowing from node N2 to wiring VOE can be reduced. Reducing this leakage current decreases the reduction in the anode-cathode current of the light-emitting device ED. Consequently, the light-emitting device ED can emit light according to the brightness of the image signal PS, thus preventing a degradation in the display quality of the image displayed by the pixel circuit PX1A.

[0237] <<Example 1 of a variation of the PX1A pixel circuit>> Next, the explanation Figure 1 The example shown is a modified circuit structure of the pixel circuit PX1A.

[0238] exist Figure 1 In this configuration, when the fixed potentials supplied by wiring V2A and wiring V2B are equal, wiring V2A and wiring V2B can be combined into a single wiring. By combining wiring V2A and wiring V2B into a single wiring, the number of wirings extending in the pixel array can be reduced, thus increasing the aperture ratio of the pixel circuitry. Furthermore, the screen resolution of the pixel array can be improved. Additionally, the sharpness of the pixel array can be enhanced.

[0239] Note that when the fixed potentials supplied by wiring V3A and wiring V3B are equal, wiring V3A and wiring V3B can be combined into a single wiring. Combining wiring V3A and wiring V3B into a single wiring reduces the number of wirings extending in the pixel array, thus increasing the aperture ratio of the pixel circuitry. Furthermore, it improves the screen resolution of the pixel array and enhances its sharpness.

[0240] Figure 6A An example structure of pixel circuit PX1A is shown, wherein wiring V2A and wiring V2B are combined into one wiring as wiring V2E, and wiring V3A and wiring V3B are combined into one wiring as wiring V3E. As described above, when the fixed potentials supplied by wiring V2A and wiring V2B are equal and the fixed potentials supplied by wiring V3A and wiring V3B are equal, such as Figure 6A As shown, by combining wiring into one, the number of wirings extending in the pixel array can be reduced.

[0241] Furthermore, when the wiring CTH supplies V CTH When the fixed potential supplied by wiring V3E is equal to that of wiring CTH and wiring V3E, wiring CTH and wiring V3E can also be combined into one wiring. For example, Figure 6B Showing will Figure 6A The cabling CTH and cabling V3E are combined into a single cabling structure as cabling V3E.

[0242] In addition, Figure 5 In the working example of the timing diagram, selection or non-selection signals can also be sent to routing GL1 and routing GL2 in the same timing sequence. In other words, in Figure 1 Alternatively, wiring GL1 and GL2 can be combined into one wiring, and wiring GL1B and GL2B can be combined into another wiring. By combining wiring GL1 and GL2 into one wiring and wiring GL1B and GL2B into one wiring, the number of wirings extending in the pixel array can be reduced, thus increasing the aperture ratio of the pixel circuit. Furthermore, the screen resolution of the pixel array can be improved. Additionally, the sharpness of the pixel array can be enhanced.

[0243] In addition, Figure 1 In the pixel circuit PX1A, the switching section SW1 and the switching section SW2 have the same circuit structure. Therefore, as described above, by combining wiring GL1 and wiring GL2 into one and combining wiring GL1B and wiring GL2B into another wiring, transistor T1A and transistor T1B can also be combined into one transistor and transistor T2A and transistor T2B can also be combined into one transistor. Figure 7 The pixel circuit PX1B shown is Figure 6A A modified example of the pixel circuit PX1A, having a circuit structure that combines wiring GL1 and wiring GL2 into wiring GL, combines wiring GL1B and wiring GL2B into wiring GLB, combines transistor T1A and transistor T1B into transistor T1, and combines transistor T2A and transistor T2B into transistor T2.

[0244] Figure 7 The number of transistors in the pixel circuit PX1B shown is compared to Figure 6A The pixel circuitry of the PX1A is less. Therefore, compared to the pixel circuitry of the PX1A, Figure 7 The pixel circuit PX1B can reduce its footprint, and by using the pixel circuit PX1B as a pixel circuit configured in the pixel array, the screen resolution of the pixel array can be improved. Furthermore, the sharpness of the pixel array can be improved.

[0245] <Structure Example of PX1C Pixel Circuit> Next, the structure of a pixel circuit of a semiconductor device according to one aspect of the present invention, which differs from the pixel circuit PX1A, will be described.

[0246] Figure 8 The pixel circuit PX1C shown is a semiconductor device according to one aspect of the present invention, and is a modification. Figure 2A The pixel circuit PX1 circuit. Figure 8 The pixel circuit PX1C has a structure in which transistor M1 in pixel circuit PX1 is replaced with transistors M1a and M1b, and transistor M2 in pixel circuit PX1 is replaced with transistors M2a and M2b. Furthermore, transistors M1a, M1b, M2a, and M2b all include a back gate.

[0247] also, Figure 8 The pixel circuit PX1C shown includes a switching section SW1A and a switching section SW2A. Switching section SW1A includes the aforementioned transistors M1a and M1b, and switching section SW2A includes the aforementioned transistors M2a and M2b. When... Figure 8 The pixel circuit PX1C and Figure 2A When comparing the pixel circuit PX1, Figure 8 The pixel circuitry of the PX1C can be said to have... Figure 2A The pixel circuit PX1 has a structure in which transistor M1 is replaced by switch SW1A and transistor M2 is replaced by switch SW2A.

[0248] Transistors M1a, M1b, M2a, and M2b can be transistors that can be applied to transistors M1, M2, or DM.

[0249] In the switching section SW1A, the gate and back gate of transistor M1a are connected to wiring GL1, and the gate and back gate of transistor M1b are also connected to wiring GL1. Furthermore, the first terminal of transistor M1a is connected to the first terminal of transistor M1b, the second terminal of transistor M1a is connected to wiring SL, and the second terminal of transistor M1b is connected to the gate of transistor DM and the first terminal of capacitor C1.

[0250] Furthermore, in the switching section SW1B, the gate and back gate of transistor M2a are connected to wiring GL2, and the gate and back gate of transistor M2b are also connected to wiring GL2. Additionally, the first terminal of transistor M2a is connected to the first terminal of transistor M2b, the second terminal of transistor M2a is connected to wiring VOE, and the second terminal of transistor M2b is connected to the first terminal of transistor DM, the second terminal of capacitor C1, and the anode of the light-emitting device ED.

[0251] Both switching sections SW1A and SW2A have a structure in which two transistors are connected in series and their gates are connected to the same wiring. In other words, the two transistors included in each of switching sections SW1A and SW2A are used as a single transistor. Furthermore, by connecting the two transistors in series, the channel length of the single transistor can be extended. By extending the channel length, the off-state current of the single transistor can be reduced, thus reducing the leakage current flowing through either switching section SW1A or SW2A when it is in the off state.

[0252] In particular, by reducing leakage current in the switching section SW1A, the release of charge corresponding to the image signal held at node N1 via transistors M1a and M1b can be prevented. In other words, the potential of node N1 can be maintained for a long time, and the pixel circuit PX1C can operate at a low frame rate suitable for still images.

[0253] Furthermore, in the switching section SW1B, by reducing leakage current, leakage of current flowing from wiring AN to wiring CTH through transistors M2a and M2b can be prevented. In other words, the current corresponding to the image signal flows through the light-emitting device ED with almost no reduction, thus preventing a decrease in the brightness of the light emitted by the light-emitting device ED due to a reduction in current. Therefore, a decrease in the display quality of the image displayed by the pixel circuit PX1C can be prevented.

[0254] Notice, Figure 8 For an example of how the pixel circuit PX1C works, please refer to... Figure 2A Explanation of the operation of the pixel circuit PX1 shown.

[0255] <<Examples of PX1C pixel circuit variations>> Next, the explanation Figure 1 The example shown is a modified circuit structure of the pixel circuit PX1A.

[0256] Figure 8 The switch section SW1A and switch section SW2A shown each have a structure that connects two transistors in series, but switch section SW1A or switch section SW2A may also have a structure that connects three or more transistors in series.

[0257] also, Figure 8 The switch section SW1A and switch section SW2A shown each have a structure in which the gates of two transistors are connected to a wiring, but the gates of the two transistors can also have a structure in which they are connected to different wirings respectively. For example, Figure 9A The switch unit SW1B shown is Figure 8In a modified example of the switching section SW1A, the gate of transistor M1a is connected to wiring GL1a, and the gate of transistor M1b is connected to wiring GL1b.

[0258] Note that in Figure 9A In this configuration, the second terminal of transistor M1 is used as terminal ITA of switch SW1B, and the first terminal of transistor M1 is used as terminal ITB of switch SW1B.

[0259] By connecting the gates of two transistors to different wirings, the number of transistors connected to a single wiring can be reduced. This means that the load and parasitic capacitance applied to a single wiring can be reduced, thereby increasing the input speed of select or non-select signals.

[0260] Note that in Figure 9A In the middle, as Figure 8 A modified example of the switch section SW1A is shown as switch section SW1B, but... Figure 8 The switch section SW2A can also be modified in the same way as described above.

[0261] In addition, Figure 8 In the switch section SW1A shown, a capacitor CW can be provided between the first terminal of transistor M1a and the first terminal of transistor M1b. For example, Figure 9B The switch unit SW1C shown is Figure 8 In a modified example of the switching section SW1A, a capacitor CW is provided between the first terminal of transistor M1a and the first terminal of transistor M1b.

[0262] Note that in Figure 9B In, with Figure 9A Similarly, the second terminal of transistor M1 is used as terminal ITA of switch SW1B, and the first terminal of transistor M1 is used as terminal ITB of switch SW1.

[0263] exist Figure 9B In the switching section SW1C, the first terminal of capacitor CW is connected to the first terminal of transistor M1a and the first terminal of transistor M1b, and the second terminal of capacitor CW is connected to wiring VCN.

[0264] As an example, a VCN (Vehicle Networking Center) is used as a wiring supplying a fixed potential. Note that this fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential.

[0265] By connecting the first terminals of transistors M1a and M1b to the first terminal of capacitor CW, when transistors M1a and M1b are in the ON state, the potential of terminal ITA or terminal ITB can be written to the first terminal of capacitor CW. Alternatively, by switching each of transistors M1a and M1b from the ON state to the OFF state, this potential can be maintained in the first terminal of capacitor CW.

[0266] Furthermore, by maintaining a potential corresponding to the image signal at the first terminal of capacitor CW, for example, even if the off-state current of transistor M1b increases for some reason, fluctuations in the potential maintained at node N1 can be prevented. When the off-state current of transistor M1b increases, charge is distributed between the first and second terminals of transistor M1b, but the first terminal of capacitor CW maintains a potential almost identical to that of node N1, so the distribution of charge can be suppressed as much as possible. As a result, the amount of potential fluctuation at node N1 can be reduced.

[0267] Note that in Figure 9B In the middle, as Figure 8 A modified example of the switch section SW1A is shown as switch section SW1C, but... Figure 8 The switch section SW2A can also be modified in the same way as described above.

[0268] also, Figure 9B The switch unit SW1C shown is Figure 9A Similarly, in the switching section SW1B, the gates of transistor M1a and transistor M1b can be connected to different wiring respectively. For example, Figure 9C The switch unit SW1D shown is Figure 9B In a modified example of the switching section SW1C, the gate of transistor M1a is connected to wiring GL1a, and the gate of transistor M1b is connected to wiring GL1b.

[0269] By connecting the gates of transistor M1a and transistor M1b to different wiring, it is possible to... Figure 9A Similarly, the switching section SW1B reduces the number of transistors connected to a single wire. This means that the load and parasitic capacitance applied to a single wire can be reduced, thereby increasing the input speed of select or non-select signals.

[0270] Furthermore, when different potentials can be applied to wiring GL1a and wiring GL1b, capacitor CW can be used as a backup storage element. For example, Figure 9C The switch section SW1D and Figure 9BSimilarly, in the switching section SW1C, when both transistors M1a and M1b are in the on state, the potential of terminal ITA or terminal ITB can be input to the first terminal of capacitor CW. By switching transistors M1a and M1b from the on state to the off state, this potential can be maintained at the first terminal of capacitor CW. Here, when the potential of terminal ITB (the potential of node N1) changes for some reason, by supplying a high-level potential to wiring GL1b, transistor M1b is turned on, and the charge maintained at the first terminal of capacitor CW can be supplied to the terminal ITB (node ​​N1) side. That is to say, by performing the above operations, Figure 9C The switch unit SW1D shown can decode the image data held at node N1.

[0271] Notice, Figure 8 The switch section SW2A can also be changed to Figure 9C The structure of the switch section SW1D.

[0272] In addition, Figure 8 In the switch section SW1A shown, the gate and back gate of transistor M1a are connected to each other, and the gate and back gate of transistor M1b are connected to each other. However, the back gates of transistors M1a and M1b can also be connected to each other. For example, Figure 10A The switch unit SW1E shown is Figure 8 In a modified example of the switching section SW1A, the back gate of transistor M1a is connected to the wiring VBG but not to the gate of transistor M1a, and the back gate of transistor M1b is connected to the wiring VBG but not to the gate of transistor M1b.

[0273] Note that in Figure 10A In this configuration, the second terminal of transistor M1 is used as terminal ITA of switch SW1B, and the first terminal of transistor M1 is used as terminal ITB of switch SW1B.

[0274] Furthermore, as an example, the VBG wiring is used to supply a fixed potential. Note that this fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. Additionally, as an example, the VBG wiring can also be used to supply a variable potential, such as a pulse potential.

[0275] By connecting the back gates of transistors M1a and M1b to the wiring VBG, a single wiring VBG can supply potential to the back gates of transistors M1a and M1b. For example, when it is desired to reduce the off-state current of transistors M1a and M1b, a ground potential, a negative potential, or the like can be supplied to the wiring VBG to shift the threshold voltages of transistors M1a and M1b towards the positive side. This reduces the off-state current of transistors M1a and M1b, thus allowing the potential corresponding to the image signal on the ITB (node ​​N1) side to be maintained for an extended period.

[0276] also, Figure 10A The switch section SW1A shown has a structure where the back gates of two transistors are connected to a single wiring; however, the back gates of the two transistors can also be connected to different wirings respectively. For example, Figure 10B The switch unit SW1F shown is Figure 10A In a modified example of the switching section SW1E, the back gate of transistor M1a is connected to wiring VBGa, and the back gate of transistor M1b is connected to wiring VBGb.

[0277] By connecting the back gates of two transistors to different wirings, the number of transistors connected to a single wiring can be reduced. In other words, the load and parasitic capacitance applied to a wiring can be reduced, thereby increasing the power supply speed to that wiring.

[0278] In addition, Figure 10B In the switching section SW1F, wiring VBGa and wiring VBGb can be supplied with the same potential or different potentials. For example, in order to increase the on-state current of transistor M1a, wiring VBGa can be supplied with a high-level potential, and in order to reduce the off-state current of transistor M1b, wiring VBGb can be supplied with a ground potential, a negative potential, etc.

[0279] also, Figure 10A Switching section SW1E and Figure 10B The switch section SW1F and Figure 9B and Figure 9C Similarly, a capacitor CW can be connected between transistors M1a and M1b.

[0280] For example, by connecting the first terminals of transistor M1a and transistor M1b to the first terminal of capacitor CW, Figure 10A The switching section SW1E can have Figure 10C The structure of the switch section SW1G is shown. Furthermore, by connecting the first terminals of transistor M1a and transistor M1b to the first terminal of capacitor CW, Figure 10B The switching section SW1F can have Figure 10D The structure of the switch section SW1H is shown. Note that in... Figure 10C Switching section SW1G and Figure 10D In the switching section SW1H, the second terminal of capacitor CW is connected to wiring VCN. Furthermore, regarding wiring VCN, please refer to... Figure 9B Switching section SW1C and Figure 9C Description of the SW1D switch section.

[0281] exist Figure 10C Switching section SW1G and Figure 10D In the switch section SW1H shown, by connecting the first terminals of transistor M1a and transistor M1b to the first terminal of capacitor CW, and... Figure 9B Switching section SW1C and Figure 9C Similarly, the switching section SW1D can suppress the distribution of charge between the first and second terminals of transistor M1b when the off-state current of transistor M1b increases, thereby reducing the potential fluctuation of node N1.

[0282] also, Figure 10A Switch section SW1E, Figure 10B Switch section SW1F, Figure 10C Switching section SW1G and Figure 10D The switching section SW1H and each Figure 9A Switching section SW1B and Figure 9C Similarly, in the switching section SW1D, the gates of the two transistors in the switching section can also be connected to different wirings.

[0283] Figure 11A The switch section SW1I shown has in Figure 10A The switching section SW1E has a structure where the gate of transistor M1a is connected to wiring GLa and the gate of transistor M1b is connected to wiring GLb. Furthermore, Figure 11B The switch unit SW1J shown has in Figure 10B The switching section SW1F has a structure where the gate of transistor M1a is connected to wiring GLa and the gate of transistor M1b is connected to wiring GLb. Furthermore, Figure 11C The switch unit SW1K shown has in Figure 10C The switching section SW1G has a structure in which the gate of transistor M1a is connected to wiring GLa and the gate of transistor M1b is connected to wiring GLb.

[0284] As described above, by Figure 10A Switch section SW1E, Figure 10B Switch section SW1F, Figure 10C The switch section SW1G or Figure 10D The switch section SW1H was changed to Figure 11A Switching section SW1I, Figure 11B Switch section SW1J, Figure 11C The switch section SW1K or Figure 11D The switching section SW1L reduces the number of transistors connected to a single wiring. This means it reduces the load and parasitic capacitance applied to a single wiring, thereby increasing the input speed of select or non-select signals.

[0285] In addition, with Figure 8 Switching section SW1A and Figures 9A to 11D Similarly, each switch section can also include... Figure 1 The structure of transistor M1 (or transistor M2) in the switch section SW1 (or switch section SW2) shown is changed to a structure in which two transistors are connected in series.

[0286] Figure 12A Having in Figure 1 In the switching section SW1, transistor M1 is replaced with two transistors M1a and M1b connected in series. Furthermore, the back gate of transistor M1a is connected to a structure having a... Figure 1 The first terminal of transistor T1aA, which has the same function as transistor T1A shown, and has the same Figure 1 The first terminal of transistor T1aB has the same function as transistor T1B shown. Furthermore, the back gate of transistor M1b is connected to... Figure 1 The first terminal of transistor T1bA, which has the same function as transistor T1A shown, and has the same Figure 1 The first terminal of transistor T1bB has the same function as transistor T1B shown.

[0287] Furthermore, the second terminals of transistors T1aA and T1bA are connected to wiring V2A, and the second terminals of transistors T1aB and T1bB are connected to wiring V3A. Additionally, the gates of transistors T1aA and T1bA are connected to wiring GL1, and the gates of transistors T1aB and T1bB are connected to wiring GL1B.

[0288] like Figure 12A As shown, by Figure 1 The transistor M1 in the switching section SW1 is replaced with two transistors M1a and M1b connected in series, and... Figure 8 Switching section SW1A and Figures 9A to 11D Similarly, in each switching section, the leakage current between terminal ITA and terminal ITB can be suppressed to a smaller level. Furthermore, as... Figure 1The switch section SW1 is described as follows: when the switch section SW1 is in the open state, the threshold voltages of transistors M1a and M1b drift to the negative side, and the current flowing between terminals ITA and ITB increases. When the switch section SW1 is in the closed state, the threshold voltages of transistors M1a and M1b drift to the positive side, and the current flowing between terminals ITA and ITB decreases.

[0289] In addition, Figure 12A In this configuration, the gates of transistors T1aA and T1bA are connected to wiring GL1, and the gates of transistors T1aB and T1bB are connected to wiring GL1B. Therefore, the back gates of transistors M1a and M1b are supplied with equal fixed potentials at almost the same timing. Thus, as... Figure 12B The switch section SW1N shown is... Figure 12A The switching unit SW1M can combine transistors T1aA and T1bA into one transistor and transistors T1aB and T1bB into one transistor.

[0290] Figure 12B The number of transistors in the switching section SW1N is higher than... Figure 12A The number of SW1M switches is small, thus reducing the area occupied.

[0291] also, Figure 12A The switch section SW1M and Figure 12B The switch section SW1N and Figure 9B , Figure 9C , Figure 10C , Figure 10D , Figure 11C and Figure 11D Similarly, a capacitor CW can be placed between the first terminal of transistor M1a and the first terminal of transistor M1b.

[0292] Specifically, for example, the switch section SW1M can also be changed to Figure 13A The structure of the switch section SW1P is shown. Figure 13A The switch section SW1P shown has the following structure: the first terminal of transistor M1a and the first terminal of transistor M1b are connected to the first terminal of capacitor CW, and the second terminal of capacitor CW is connected to wiring VCN.

[0293] Furthermore, for example, the switch section SW1N can also be changed to... Figure 13B The structure of the switch section SW1Q is shown. Figure 13B The switch section SW1Q shown has the following structure: the first terminal of transistor M1a and the first terminal of transistor M1b are connected to the first terminal of capacitor CW, and the second terminal of capacitor CW is connected to wiring VCN.

[0294] Notice, Figure 13A and Figure 13B The wiring VCN shown can be referenced. Figure 9B Switching section SW1C and Figure 9C Description of the SW1D switch section.

[0295] exist Figure 13A The switch section SW1P and Figure 13B In the switch section SW1Q shown, by connecting the first terminals of transistor M1a and transistor M1b to the first terminal of capacitor CW, and... Figure 9B Switching section SW1C and Figure 9C Similarly, the switching section SW1D can suppress the distribution of charge between the first and second terminals of transistor M1b when the off-state current of transistor M1b is increased, thereby reducing the potential fluctuation of node N1.

[0296] Note that the semiconductor device of one aspect of the present invention is not limited to the pixel circuit structure described above. For example, in the above description, a pixel circuit included in a display device is described as one aspect of the present invention. Figure 3A The switch unit SW1 shown can also be applied to storage circuits such as storage cells included in storage devices.

[0297] For example, in a memory circuit such as DRAM (Dynamic Random Access Memory), one of the source and drain electrodes of the write transistor is connected to one of a pair of electrodes of a capacitor. Figure 3A The switching section SW1 is used for the write transistor. Therefore, as an aspect of the present invention, a memory circuit with a low refresh rate can be constructed. Furthermore, power consumption can be reduced due to the lower refresh rate.

[0298] Furthermore, for example, in a gain-cell type memory circuit, one of the source and drain terminals of the write transistor, one of the pair of electrodes of the capacitor, and the gate of the read transistor are connected to each other. In this memory circuit, the read transistor can... Figure 3A The switching section SW1 is used for the write transistor. Therefore, as an aspect of the present invention, a memory circuit with a low refresh rate can be constructed. Furthermore, power consumption can be reduced due to the lower refresh rate.

[0299] The above description uses DRAM and gain-cell type memory circuits as examples, but write transistors for other memory circuits can also be used. Figure 3A The switch section SW1.

[0300] Furthermore, when the storage circuit includes a switching transistor other than a write transistor, the switching transistor can also be used. Figure 3A The switching section SW1. As a result, the off-state current caused by the switching transistor can be reduced, thus preventing malfunctions in the storage circuit caused by the increase in the off-state current of the switching transistor.

[0301] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in other embodiments.

[0302] (Implementation Method 2) This embodiment describes a pixel circuit of a semiconductor device according to an embodiment of the present invention that differs from the pixel circuits PX1A, PX1B, and PX1C described in Embodiment 1.

[0303] Figure 14 This is an example of a circuit diagram showing a conventional pixel circuit structure that differs from the pixel circuit PX1 in Figure 2. This pixel circuit includes six transistors, two capacitors, and a light-emitting device. Furthermore, in addition to having the functions of writing and maintaining the potential corresponding to the image signal and displaying the image corresponding to the image signal, this pixel circuit also has the function of correcting the threshold voltage of the driving transistors.

[0304] Multiple pixel circuits are arranged in the pixel array of a display device. Therefore, due to manufacturing processes and other factors, the threshold voltages of the driving transistors included in each of the multiple pixel circuits become uneven. When the threshold voltages in each driving transistor are different, the amount of current between the source and drain differs from a predetermined amount, and the brightness of the light emitted by the light-emitting device (ED) also varies. As a result, the display quality of the display device is reduced.

[0305] Figure 14 The pixel circuit PX2 shown has the function of correcting the threshold voltage of the driving transistor to a specified value. Therefore, even if the threshold voltage of each driving transistor is different in the manufacturing process of the display device, this function can make the threshold voltage of each driving transistor the same as the specified value, thus preventing the degradation of the display quality of the display device caused by different threshold voltages.

[0306] Figure 14 The pixel circuit PX2 shown includes transistors DM, M1, M2, M3, M4, and M5, capacitors C1 and C2, and a light-emitting device ED. In particular, transistor DM is used as the driving transistor in the pixel circuit PX2, and transistors M1 to M5 are used as switching transistors.

[0307] Note that transistor DM, transistor M1, transistor M2, capacitor C1, and light-emitting device ED can be included as described in Embodiment 1. Figure 2A Description of transistors DM, M1, M2, capacitor C1, and light-emitting device ED in pixel circuit PX1.

[0308] Furthermore, transistors M3, M4, and M5 can use transistors that can be applied to one of transistors M1, M2, and DM.

[0309] In addition, Figure 14 In the pixel circuit PX2, as an example, the gates and back gates of transistors M1 to M5 are connected to each other. By connecting the gates and back gates to each other, the on-state current of the transistors can be increased when they are turned on.

[0310] The first terminal of transistor M1 is connected to the first terminal of transistor M3, the gate of transistor DM, and the first terminal of capacitor C1. Furthermore, the first terminal of transistor M2 is connected to the second terminal of transistor M3, the first terminal of transistor M5, the first terminal of transistor DM, the second terminal of capacitor C1, and the first terminal of capacitor C2. Additionally, the back gate of transistor DM is connected to the second terminal of capacitor C2 and the first terminal of transistor M4.

[0311] Note that in Figure 14 In the diagram, the region where the first terminal of transistor M1, the first terminal of transistor M3, the gate of transistor DM, and the first terminal of capacitor C1 are connected to each other is illustrated as node N1. Furthermore, the region where the first terminal of transistor M2, the second terminal of transistor M3, the first terminal of transistor M5, the first terminal of transistor DM, the second terminal of capacitor C1, and the first terminal of capacitor C2 are connected to each other is illustrated as node N2. Additionally, the region where the back gate of transistor DM, the second terminal of capacitor C2, and the first terminal of transistor M4 are connected to each other is illustrated as node N3.

[0312] Transistor M1's second terminal is connected to wiring SL, and its gate and back gate are connected to wiring GL1. Similarly, transistor M2's second terminal is connected to wiring V0E, and its gate and back gate are connected to wiring GL1. Transistor M3's gate and back gate are connected to wiring GL2. Transistor DM's second terminal is connected to wiring AN. Furthermore, transistor M5's second terminal is connected to the anode of the light-emitting device ED, and its gate and back gate are connected to wiring GL3. The light-emitting device ED's cathode is connected to wiring CTH. Transistor M4's second terminal is connected to wiring V1E, and its gate and back gate are connected to wiring GL2.

[0313] As an example, wiring GL1, wiring GL2, and wiring GL3 are used as selection signal lines corresponding to pixel circuit PX2. In particular, wiring GL1 is used as the first selection signal line (sometimes referred to as the first gate line) to select the pixel circuit PX2 to be written during image data writing operations.

[0314] Furthermore, wiring GL2 is used as a second selection signal line (sometimes referred to as a second gate wiring) to select the pixel circuit PX2 that includes node N2 when a fixed potential is to be supplied from wiring V0E to node N2. Additionally, wiring GL2 is used as a selection signal line to select the pixel circuit PX2 that includes node N3 when a fixed potential is to be supplied from node N3 to wiring V1E.

[0315] Furthermore, wiring GL3 is used as a third selection signal line (sometimes referred to as the third gate wiring) to select the pixel circuit PX2, which includes the light-emitting device ED to emit light. Specifically, wiring GL3 has the function of supplying selection or non-selection signals to the gate and back gate of transistor M5.

[0316] Note that, as an example, in pixel circuit PX2, the select signal sent to routing GL1 is a high-level potential, and the non-select signal sent to routing GL1 is a low-level potential. Furthermore, as an example, the select signal sent to routing GL2 is a high-level potential, and the non-select signal sent to routing GL2 is a low-level potential. Also, as an example, the select signal sent to routing GL3 is a high-level potential, and the non-select signal sent to routing GL3 is a low-level potential.

[0317] As an example, wiring SL and Figure 2A The pixel circuit PX1 is also used as wiring (sometimes called source line or data line) to send image signals corresponding to the image data written to the pixel circuit PX2.

[0318] As an example, wiring V0E and Figure 2A The pixel circuit PX1 is similarly used as wiring to supply a fixed potential (e.g., an initialization potential) to node N2. Note that, for convenience, this fixed potential is denoted as V0 in this specification.

[0319] As an example, wiring V1E is used to supply a fixed potential (e.g., a potential for initialization) to node N3. Note that in this specification, for convenience, this fixed potential is referred to as V1.

[0320] As an example, wiring AN and Figure 2AThe pixel circuit PX1 is similarly used as wiring to supply a fixed potential to the second terminal of the transistor DM. Note that, for convenience, this fixed potential is denoted as V in this specification. AN Furthermore, wiring AN is also used as wiring to allow current to flow through the anode of the light-emitting device ED. Additionally, as an example, wiring CTH... Figure 2A The pixel circuit PX1 is similarly used for wiring to supply a fixed potential to the cathode of the light-emitting device ED. Note that, for convenience, this fixed potential is denoted as V in this specification. CTH .

[0321] Furthermore, in the operation of the pixel circuit PX2, V0 and Figure 2A Unlike the pixel circuit PX1, it can be used for pixel circuits below V. CTH The potential can also be V. CTH The above potentials.

[0322] Furthermore, in the operation of the pixel circuit PX2, V1 is preferably higher than V0 and lower than V. AN The potential of V1 is particularly preferred to be such that when the back gate-source voltage of transistor DM is V1-V0, the threshold voltage of transistor DM drifts to the negative side, and transistor DM operates normally on.

[0323] Note that in this specification, "normally on" refers to the state where current can flow between the source and drain when the gate-source voltage of the transistor is 0V. Conversely, "normally off" refers to the state where the current flowing between the source and drain is very small when the gate-source voltage of the transistor is 0V. For example, when the semiconductor layer of the transistor contains an oxide (also denoted as IGZO) containing indium (In), gallium (Ga), and zinc (Zn), the current flowing through the source and drain per channel width of 1 μm when the transistor is in the normally off state is 1 × 10⁻⁶ at room temperature. -20 Below A, at 85℃, it is 1×10 -18 A and below or at 125℃ is 1×10 -16 Below A.

[0324] In addition, V AN V is preferred CTH Potentials above V0 and above V1.

[0325] Therefore, a forward bias voltage is applied between the anode and cathode of the light-emitting device ED, so that the light-emitting device ED can emit light according to the brightness of the image data written into the pixel circuit PX.

[0326] Next, an example of how the pixel circuit PX2 works will be explained.

[0327] Figure 15A Show Figure 14 The timing diagram shows an example of the operation of the pixel circuit PX2. Specifically, Figure 15A The timing diagram shows the potential variations of traces SL, GL1, GL2, and GL3 from time T21 to time T28 and in the vicinity. Furthermore, in this example, the high-level potential is denoted as V. H Let the low-level potential be denoted as V. L .

[0328] also, Figure 15B This is a time series diagram showing the potential changes of nodes N1 and N2 from time T21 to time T28 and in the vicinity. Furthermore, Figure 15C This is a time series diagram showing the potential changes of nodes N2 and N3 at and around times T21 to T28.

[0329] Furthermore, wiring V0E is supplied with a fixed potential V0 for initialization of node N2, wiring V1E is supplied with a fixed potential V1 for initialization of node N3, and wiring AN is supplied with a fixed potential V... AN For wiring CTH, a fixed potential is supplied with V. CTH .

[0330] Furthermore, during the timing of the input image signal, the wiring SL is supplied with a potential V corresponding to the image signal. PS Furthermore, in the timing when no image signal is input, wiring SL is used as wiring for the potential supply V0 for the initialization of node N1. Specifically, in Figure 15A In the timing diagram, during the periods from time T21 to time T25 and from time T27 to time T28, routing SL is supplied with V0; during the period from time T26 to time T27, routing SL is supplied with V. PS .

[0331] Before time T21, routing GL1 to GL3 are used as non-selection signal inputs V. L Therefore, the gates of transistors M1 to M5 are supplied with V. L Therefore, transistors M1 through M5 are all in the off state.

[0332] During the period from time T21 to time T22, wiring GL1 and wiring GL2 are supplied as selection signals to V. H Therefore, the gates of transistors M1, M2, M3, and M4 are each supplied with V. H Therefore, transistors M1 through M4 are all in the ON state.

[0333] When transistor M1 is turned on, potential V0 is supplied from wiring SL through transistor M1 to node N1. Similarly, when transistor M2 is turned on, potential V0 is supplied from wiring V0E through transistor M2 to node N2. Furthermore, transistor M3 is turned on; therefore, the potentials of nodes N1 and N2 are the same. This initializes the potentials of nodes N1 and N2.

[0334] Furthermore, when transistor M4 is in the ON state, potential V1 is supplied from wiring V1E through transistor M4 to node N3. Therefore, the voltage between the first and second terminals of capacitor C2 (the back gate-source voltage of transistor DM) is V1-V0. This initializes the potential of node N3. Additionally, since the back gate-source voltage of transistor DM is V1-V0, transistor DM is normally ON.

[0335] During the period from time T22 to time T23, wiring GL1 is used as a non-selection signal input V. L Therefore, the gates of transistors M1 and M2 are each supplied with V. L Therefore, both transistors M1 and M2 are in the off state.

[0336] Transistor M3 is in the ON state, and the connection between nodes N1 and N2 is ON. Therefore, the gate-source voltage of transistor DM is 0V. Note that in transistor DM, the back gate-source voltage is V1-V0, so even though the gate-source voltage is 0V, current flows between the source and drain. Therefore, charge is supplied from wiring AN through transistor DM to node N2. Furthermore, transistors M1, M2, and M5 are in the OFF state, and transistor M3 is in the ON state. Therefore, the charge is supplied to node N1 in addition to node N2. Consequently, the potentials of nodes N1 and N2 rise. Furthermore, as the potentials of nodes N1 and N2 rise, the back gate-source voltage of transistor DM decreases, eventually changing to the voltage at which transistor DM turns OFF. Note that the potentials of nodes N1 and N2 when transistor DM is 0V are V1-V0. B Furthermore, at this time, the back gate-source voltage when transistor DM is in the off state is V1-V. B Furthermore, when the back gate-source voltage of transistor DM reaches V1-V B At that time, the threshold voltage of transistor DM is 0V.

[0337] During the period from time T23 to time T24, wiring GL2 is used as a non-selection signal input V. L Therefore, the gates of transistors M3 and M4 are each supplied with V. LTherefore, transistors M3 and M4 are both in the off state. Furthermore, nodes N1 to N3 are in a floating state, capacitor C1 maintains a voltage of 0V between its first and second terminals, and capacitor C2 maintains a voltage of V1-V between its first and second terminals. B The voltage.

[0338] During the period from time T24 to time T25, wiring GL1 is used as a selection signal input V. H Therefore, the gates of transistors M1 and M2 are each supplied with V. H Therefore, both transistors M1 and M2 are in the ON state.

[0339] Furthermore, at this time, wiring SL and wiring V0E are supplied with V0. Therefore, charge is supplied from wiring SL through transistor M1 to node N1, thereby changing the potential of node N1 from V0. B The voltage changes to V0. Furthermore, charge is supplied from wiring V0E through transistor M2 to node N2, therefore the potential of node N2 changes from V... B It becomes V0.

[0340] Furthermore, during the period from time T24 to time T25, node N3 is in a floating state, therefore when the potential of node N2 changes from V... B When the voltage changes to V0, the potential of node N3 changes from V1 to V1-(V0) through capacitive coupling of capacitor C2. B -V0). Note that at this time, the back gate-source voltage of transistor DM (the voltage between the first and second terminals of capacitor C2) remains at V1-V. B And it does not change.

[0341] During the period from time T25 to time T26, wiring SL is supplied from potential V0 with a potential V corresponding to the image used to display on pixel circuit PX2. PS Therefore, charge is supplied from wiring SL through transistor M1 to node N1, causing the potential of node N1 to change from V0 to V. PS Furthermore, at this time, the gate-source voltage of transistor DM is V. PS -V0.

[0342] During the period from time T26 to time T27, wiring GL1 is used as a non-selection signal input V. L Therefore, the gates of transistors M1 and M2 are each supplied with V. L Therefore, both transistors M1 and M2 are in the off state.

[0343] Furthermore, when transistors M1 and M2 are in the off state, nodes N1 and N2 are both in a floating state, thereby maintaining the potentials of nodes N1 and N2. Additionally, at this time, the gate-source voltage of transistor DM (the voltage between the first and second terminals of capacitor C1) is maintained at V. PS -V0 without change.

[0344] During the period from time T27 to time T28, wiring GL3 is used as the selection signal input V. H Therefore, the gate of transistor M5 is supplied with V. H Therefore, transistor M5 is in the ON state.

[0345] Here, when transistor DM is in the ON state, in other words, when the gate-source voltage V of transistor DM is... PS When V0 exceeds 0V, which is the threshold voltage of transistor DM, node N2 is supplied with charge from wiring AN, and the potential of node N2 rises from V0. Meanwhile, node N1 is in a floating state; therefore, through capacitive coupling with capacitor C1, the potential of node N1 rises as the potential of node N2 rises. Ideally, the potential rise of node N1 should be equal to the potential rise of node N2, and the gate-source voltage of transistor DM (the voltage between the first and second terminals of capacitor C1) should remain at V0. PS -V0 without change.

[0346] Note that in this embodiment, the potential rise of nodes N1 and N2 is set as ΔV. Therefore, the potential of node N1 is V. PS +ΔV, the potential of node N2 is V0+ΔV. Note that ΔV is V CTH The above and V AN The potentials below are determined by the voltage division between the transistor DM and the light-emitting device ED. Specifically, ΔV depends on the resistance values ​​of the transistor DM and the light-emitting device ED.

[0347] Furthermore, node N3 is also in a floating state. Therefore, through the capacitive coupling of capacitor C2, as the potential of node N2 rises, the potential of node N3 also rises by ΔV. Ideally, the potential rise of node N3 should be equal to the potential rise of node N2 by ΔV, and the back gate-source voltage of transistor DM (the voltage between the first and second terminals of capacitor C2) should remain at V1-V. B And it remains unchanged. Note that at this point, the potential of node N3 is V1-V. B +V0+ΔV.

[0348] Furthermore, when transistor DM operates in the saturation region, a voltage V corresponding to the gate-source voltage V flows between the source and drain of transistor DM.PS -V0 is the amount of current. In addition, this current is input to the anode of the light-emitting device (ED), so the ED emits light with a brightness corresponding to this amount of current.

[0349] By correcting the threshold voltage of transistor DM, which acts as the driving transistor, as described above, and by writing image data into pixel circuit PX2 and emitting light corresponding to the brightness of the image data from pixel circuit PX2, image data can be displayed. Furthermore, since the threshold voltage of the driving transistor is also corrected, the display quality of the image displayed by pixel circuit PX2 can be improved.

[0350] <Structure example of pixel circuit PX2A> The transistors M1 to M4 used in the pixel circuit PX2 described above, and which serve as switching transistors, can each be replaced with those described in Embodiment 1. Figure 3A The circuit structure of the switching section SW1.

[0351] Figure 16 An example of the structure of a pixel circuit is shown, in which... Figure 14 The transistors M1 to M4 of the pixel circuit PX2 are replaced with Figure 3A The circuit structure of the switching section SW1. Figure 16 The pixel circuit PX2A shown has the following structure: Figure 14 The transistor M1 in the pixel circuit PX2 is replaced with the switch SW1, and the transistor M1 is replaced with the switch SW1. Figure 14 The transistor M2 in the pixel circuit PX2 is replaced with the switch SW2, and the transistor M2 is replaced with the switch SW2. Figure 14 The transistor M3 in the pixel circuit PX2 is replaced with the switch SW3, and Figure 14 The transistor M4 in the pixel circuit PX2 is replaced with the switch SW4.

[0352] exist Figure 16 In this circuit, switching unit SW1 includes transistor M1, transistor T1A, and transistor T1B. Switching unit SW2 includes transistor M2, transistor T2A, and transistor T2B. Switching unit SW3 includes transistor M3, transistor T3A, and transistor T3B. Switching unit SW4 includes transistor M4, transistor T4A, and transistor T4B.

[0353] Note that transistors T1A, T1B, T2A, T2B, T3A, T3B, T4A, and T4B can, for example, be used as... Figure 14 The pixel circuit PX2A includes transistors M1 to M5 or transistor DM.

[0354] In the switching section SW1, the back gate of transistor M1 is connected to the first terminal of transistor T1A and the first terminal of transistor T1B. Furthermore, the gate of transistor T1A is connected to wiring GL1, and the second terminal of transistor T1A is connected to wiring P1A. Similarly, the gate of transistor T1B is connected to wiring GL1B, and the second terminal of transistor T1B is connected to wiring P1B.

[0355] In the switching section SW2, the back gate of transistor M2 is connected to the first terminal of transistor T2A and the first terminal of transistor T2B. Furthermore, the gate of transistor T2A is connected to wiring GL1, and the second terminal of transistor T2A is connected to wiring P2A. Similarly, the gate of transistor T2B is connected to wiring GL1B, and the second terminal of transistor T2B is connected to wiring P2B.

[0356] In the switching section SW3, the back gate of transistor M3 is connected to the first terminal of transistor T3A and the first terminal of transistor T3B. Furthermore, the gate of transistor T3A is connected to wiring GL2, and the second terminal of transistor T3A is connected to wiring P3A. Additionally, the gate of transistor T3B is connected to wiring GL2B, and the second terminal of transistor T3B is connected to wiring P3B.

[0357] In the switching section SW4, the back gate of transistor M4 is connected to the first terminal of transistor T4A and the first terminal of transistor T4B. Furthermore, the gate of transistor T4A is connected to wiring GL2, and the second terminal of transistor T4A is connected to wiring P4A. Similarly, the gate of transistor T4B is connected to wiring GL2B, and the second terminal of transistor T4B is connected to wiring P4B.

[0358] Figure 16 The wiring P1A, wiring P2A, wiring P3A and wiring P4A shown all have the same characteristics as... Figure 3A The wiring V2A shown is a wiring with the same function as the wiring shown, and as an example, it is used as a wiring to supply a fixed potential. In particular, wiring P1A and wiring P2A are preferably supplied with the same potential as the high-level potential sent to wiring GL1 as the fixed potential. Furthermore, wiring P3A and wiring P4A are preferably supplied with the same potential as the high-level potential sent to wiring GL2 as the fixed potential.

[0359] Figure 16 The wiring P1B, wiring P2B, wiring P3B, and wiring P4B shown all have the same characteristics as... Figure 3A The wiring V3A shown is a wiring with the same function, and as an example, it is used as a wiring to supply a fixed potential. In particular, wiring P1B is preferably used as a negative potential supply -V. th_T1B The wiring. Wiring P2B is preferably used as a negative potential supply -V th_T2BThe wiring. Wiring P3B is preferably used as a negative potential supply -V. th_T3B The wiring. Wiring P4B is preferably used as a negative potential supply -V. th_T4B The wiring. Note that V th_T1B V is the positive threshold voltage of transistor T1B. th_T2B V is the positive threshold voltage of transistor T2B. th_T3B V is the positive threshold voltage of transistor T3B. th_T4B This is the positive threshold voltage of transistor T4B.

[0360] The wiring GL1B is equipped with... Figure 3A The wiring shown, GL1B, serves the same function and, as an example, is used as a select signal line paired with wiring GL1. Therefore, wiring GL1B is input to... Figure 3A The wiring of GL1B is also reversed to the input. Figure 16 The signal logic of the wiring GL1 is shown. Specifically, for example, when pixel circuit PX2A is selected as the object to be written to for image data and the logic of the selection signal input to wiring GL1 is "1", the logic of the selection signal input to wiring GL1B is "0". Furthermore, when pixel circuit PX2A is not selected as the object to be written to for image data, the logic of the non-selection signal input to wiring GL1 is "0" and the logic of the non-selection signal input to wiring GL1B is "1".

[0361] In other words, when pixel circuit PX2A is selected as the target for writing image data, wiring GL1 and wiring GL1B supply a set of selection signals to pixel circuit PX2A. Furthermore, when pixel circuit PX2A is not selected as the target for writing image data, wiring GL1 and wiring GL1B supply a set of non-selection signals to pixel circuit PX2A.

[0362] Note that in pixel circuit PX2A, the logic for "1" is a high level and the logic for "0" is a low level. Therefore, when pixel circuit PX2A is selected as the target for image data writing, wiring GL1 is input with a high level as a selection signal, and wiring GL1B is input with a low level as a selection signal. In other words, when pixel circuit PX1A is selected as the target for image data writing, as the selection signal group, wiring GL1 supplies a high level to pixel circuit PX2A, and wiring GL1B supplies a low level to pixel circuit PX2A.

[0363] Furthermore, when pixel circuit PX2A is not selected as the object to be written to for image data, wiring GL1 is supplied with a low-level potential as a non-selection signal, and wiring GL1B is supplied with a high-level potential as a non-selection signal. In other words, when pixel circuit PX2A is not selected as the object to be written to for image data, wiring GL1 supplies a low-level potential to pixel circuit PX2A, and wiring GL1B supplies a high-level potential to pixel circuit PX2A as a non-selection signal group.

[0364] Furthermore, the GL2B wiring is characterized by... Figure 3A The wiring shown, GL2B, performs the same function as the selected signal line paired with wiring GL2, and is used as an example. Therefore, wiring GL2B is input to... Figure 3A The GL2B wiring is also reversed to the input. Figure 16 The signals of the wiring GL2 shown are logical signals. Specifically, for example, when pixel circuit PX2A is selected to write V0 to node N2 and the logic of the selection signal input to wiring GL2 corresponds to "1", the logic of the selection signal input to wiring GL2B is "0". Furthermore, when pixel circuit PX2A is not selected (V0 is not written to node N2), the logic of the non-selection signal input to wiring GL2 is "0" and the logic of the non-selection signal input to wiring GL2B is "1".

[0365] In other words, when pixel circuit PX2A is selected to write V0 to node N2, routing GL2 and routing GL2B supply a set of selection signals to pixel circuit PX2A. Furthermore, when pixel circuit PX2A is not selected (when V0 is not written to node N2), routing GL2 and routing GL2B supply a set of non-selection signals to pixel circuit PX2A.

[0366] Note that in pixel circuit PX2A, the logic for "1" is a high level and the logic for "0" is a low level. Therefore, when pixel circuit PX2A is selected to write V0 to node N2, wiring GL2 is input as a high-level selection signal, and wiring GL2B is input as a low-level selection signal. In other words, when pixel circuit PX2A is selected to write V0 to node N2, as the selection signal group, wiring GL2 supplies a high-level potential to pixel circuit PX2A, and wiring GL2B supplies a low-level potential to pixel circuit PX2A.

[0367] Furthermore, when pixel circuit PX2A is not selected (V0 is not written to node N2), routing GL2 is input with a low-level potential as a non-selection signal, and routing GL2B is input with a high-level potential as a non-selection signal. In other words, when pixel circuit PX2A is not selected (V0 is not written to node N2), as a group of non-selection signals, routing GL2 supplies a low-level potential to pixel circuit PX2A, and routing GL2B supplies a high-level potential to pixel circuit PX2A.

[0368] Note that the operation of the switching sections SW1 to SW4 of the pixel circuit PX2A can be referred to Figure 3A Explanation of the operation of the switch section SW1.

[0369] As described above, by Figure 14 The transistor M1 of the pixel circuit PX2 is replaced with Figure 3A The circuit structure of the switching section SW1 can improve the signal transmission speed (charge supply speed) from wiring SL to node N1 when the switching section is in the on state. In addition, it can reduce the leakage current between node N1 and wiring SL when the switching section is in the off state.

[0370] In addition, by Figure 14 The pixel circuit PX2's transistor M2 is replaced with Figure 3A The circuit structure of the switching section SW1 can improve the charge supply speed from wiring VOE to node N2 when the switching section is in the on state. Furthermore, it can reduce the leakage current between wiring VOE and node N2 when the switching section is in the off state.

[0371] In addition, by Figure 14 The pixel circuit PX2's transistor M3 is replaced with Figure 3A The circuit structure of the switching section SW1 can increase the charge supply speed from node N2 to node N1 when the switching section is in the on state. Furthermore, it can reduce the leakage current between node N1 and node N2 when the switching section is in the off state.

[0372] In addition, by Figure 14 The pixel circuit PX2's transistor M4 is replaced with Figure 3A The circuit structure of the switching section SW1 can improve the charge supply speed from wiring V1E to node N3 when the switching section is in the on state. Furthermore, it can reduce the leakage current between wiring V1E and node N3 when the switching section is in the off state.

[0373] By multiple Figure 16 The pixel circuit PX2A is configured in the pixel array of the display device, which can display high-quality images.

[0374] The above explains that Figure 14 The transistors M1 to M4 of the pixel circuit PX2 are replaced with Figure 3A In the example of the circuit structure of the switching section SW1, transistor M5 can also be replaced with Figure 3A The circuit structure of the switching section SW1. Specifically, for example, a first transistor and a second transistor are also provided in the pixel circuit PX2A, and the back gate of transistor M5 can be connected to one of the source and drain of the first transistor and one of the source and drain of the second transistor without being connected to wiring GL3 (not shown). Furthermore, the gate of the first transistor can be connected to wiring GL3, the gate of the second transistor can be connected to the wiring that transmits the logic inversion of the signal input to wiring GL3, the other of the source and drain of the first transistor can be connected to the wiring that supplies the same potential as the high-level potential supplied to wiring GL3, and the other of the source and drain of the second transistor can be connected to the wiring that supplies a negative potential. Thus, transistor M5 can be replaced with... Figure 3A The circuit structure of the switching section SW1 is described. By replacing transistor M5 with the circuit structure of the switching section SW1, the off-state current flowing through transistor M5 to the light-emitting device ED can be reduced. This prevents the light-emitting device ED from emitting light due to leakage current from transistor M5. Furthermore, when the light-emitting device ED is a light-emitting device containing organic EL material, the electrical load on the organic EL material is reduced, thereby suppressing its degradation and extending the lifespan of the light-emitting device ED.

[0375] In addition, Figure 14 In the pixel circuit PX2, the gates of transistors M1 and M2 are connected to wiring GL1, and the on and off states of transistors M1 and M2 are synchronized. Figure 16 In this configuration, when the gates of transistors M1, M2, T1A, and T2A are connected to wiring GL1, and the gates of transistors T1B and T2B are connected to wiring GL1B, the on and off states of switching unit SW1 and switch SW2 are synchronized. That is, in... Figure 16 In this circuit, switch SW1 and switch SW2 are in the on or off state at the same time sequence. Therefore, transistors T1A and T2A can be combined into one transistor and transistors T1B and T2B can be combined into one transistor.

[0376] Similarly, in Figure 14 In the pixel circuit PX2, the gates of transistors M3 and M4 are connected to wiring GL2, and the on and off states of transistors M3 and M4 are synchronized. Figure 16In this configuration, when the gates of transistors M3, M4, T3A, and T4A are connected to wiring GL2, and the gates of transistors T3B and T4B are connected to wiring GL2B, the on and off states of switching unit SW3 and switch SW4 are synchronized. That is, in... Figure 16 In the process, switch SW3 and switch SW4 are in the on or off state at the same time sequence. Therefore, transistors T3A and T4A can be combined into one transistor and transistors T3B and T4B can be combined into one transistor.

[0377] Figure 17 The pixel circuit PX2B shown is Figure 16 A modified example of the pixel circuit PX2A, wherein the switching units SW1 and SW2 are combined into a single switching unit SWC1, and the switching units SW3 and SW4 are combined into a single switching unit SWC2.

[0378] The switching unit SWC1 includes transistors M1, M2, T1A, and T1B. Note that transistor M1 corresponds to... Figure 16 In the switching section SW1, transistor M1 and transistor M2 correspond to Figure 16 The transistor M2 in the switching section SW2. Furthermore, in Figure 16 In the switching section SWC1, transistor T1A is a transistor that combines transistor T1A of switching section SW1 and transistor T2A of switching section SW2 into one. Figure 16 In the switching section SWC1, transistor T1B is a transistor that combines transistor T1B of switching section SW1 and transistor T2B of switching section SW2 into one. Furthermore, in... Figure 17 In the middle, Figure 16 The wiring P1A and wiring P2A shown are combined into one wiring P1A, which will Figure 16 The combination of wiring P1B and wiring P2B shown constitutes a single wiring P1B.

[0379] Therefore, in the switching section SWC1, the back gate of transistor M1 is connected to the first terminal of transistor T1A and the first terminal of transistor T1B, and the back gate of transistor M2 is also connected to the first terminal of transistor T1A and the first terminal of transistor T1B. Furthermore, the gates of transistors M1, M2, and T1A are connected to wiring GL1. Additionally, the gate of transistor T1B is connected to wiring GL1B. Furthermore, the second terminal of transistor T1A is connected to wiring P1A, and the second terminal of transistor T1B is connected to wiring P1B.

[0380] Furthermore, the switching unit SWC2 includes transistors M3, M4, T3A, and T3B. Note that transistor M3 corresponds to... Figure 16 Transistor M3 in the switching section SW3, transistor M4 corresponds to Figure 16 The transistor M4 in the switching section SW4. Furthermore, in Figure 16 In the switching section SWC2, transistor T3A is a transistor that combines transistor T3A from switching section SW3 and transistor T4A from switching section SW4 into one. Figure 16 In the switching section SWC2, transistor T3B is a combination of transistor T3B from switching section SW3 and transistor T4B from switching section SW4. Furthermore, in... Figure 17 In the middle, Figure 16 The wiring P3A and wiring P4A shown are combined into one wiring P3A. Figure 16 The combination of wiring P3B and wiring P4B shown constitutes a single wiring P3B.

[0381] Therefore, in the switching section SWC2, the back gate of transistor M3 is connected to the first terminal of transistor T3A and the first terminal of transistor T3B, and the back gate of transistor M4 is also connected to the first terminal of transistor T3A and the first terminal of transistor T3B. Furthermore, the gates of transistors M3, M4, and T3A are connected to wiring GL2. Additionally, the gate of transistor T3B is connected to wiring GL2B. Furthermore, the second terminal of transistor T3A is connected to wiring P3A, and the second terminal of transistor T3B is connected to wiring P3B.

[0382] As described above, by Figure 16 The pixel circuit PX2A was changed to Figure 17 The pixel circuit PX2B reduces the number of transistors in the pixel circuit. Therefore, compared to the pixel circuit PX2A, the pixel circuit PX2B occupies a smaller area. By using the pixel circuit PX2B as a pixel circuit configured in the pixel array, the screen resolution of the pixel array can be improved. Furthermore, the sharpness of the pixel array can be enhanced.

[0383] Furthermore, in Figure 17 In the pixel circuit PX2B, when the fixed potentials supplied to wiring P1A and wiring P3A are equal, wiring P1A and wiring P3A can be combined into one wiring. Similarly, when the fixed potentials supplied to wiring P1B and wiring P3B are equal, wiring P1B and wiring P3B can be combined into one wiring.

[0384] Figure 18A Shown in Figure 17The pixel circuit PX2B combines wirings P1A and P3A into a single wiring PA and further combines them into a single wiring PB. By combining multiple wirings into one, the number of wirings extending across the pixel array is reduced, thus increasing the aperture ratio of the pixel circuit. Furthermore, this improves the screen resolution of the pixel array and enhances its sharpness.

[0385] In addition, Figure 18A In this case, when the fixed potentials supplied to wiring PB and wiring CTH are equal, wiring PB and wiring CTH can also be combined into one wiring. Figure 18B Shown in Figure 18A The wiring PB and wiring CTH are combined into a single wiring PB circuit structure. Therefore, with... Figure 18A Compared to the circuit structure, Figure 18B The circuit structure can reduce the number of wires extending in the pixel array, thereby increasing the aperture ratio of the pixel circuit. Furthermore, it can further improve the screen resolution of the pixel array. Additionally, it can further improve the sharpness of the pixel array.

[0386] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in other embodiments.

[0387] (Implementation Method 3) In this embodiment, an example of the structure of the pixel circuit that can use the switching section described in Embodiment 1 will be described.

[0388] <Example 1 of pixel circuit structure> Figure 19A This is a circuit diagram showing an example of the structure of the pixel circuit in which the switching section described in Embodiment 1 can be used.

[0389] Figure 19A The pixel circuit PX3 shown includes, for example, transistor Tr1, transistor Tr2, capacitor Cs1, capacitor Cs2, and light-emitting device ED.

[0390] Regarding the light-emitting device (ED), please refer to the description of the light-emitting device (ED) described in Embodiment 1.

[0391] The first terminal of transistor Tr1 is connected to wiring SL. The second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1. The gate of transistor Tr1 is connected to wiring GL. Furthermore, the first terminal of transistor Tr2 is connected to wiring IL. The second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs2, and the anode of the light-emitting device ED. Additionally, the second terminal of capacitor Cs2 is connected to wiring VCOM. Finally, the cathode of the light-emitting device ED is connected to wiring VCAT.

[0392] As an example, the wiring SL can be used as the wiring SL described in Embodiments 1 and 2, and has the function of wiring to send image signals to the pixel circuit PX3.

[0393] As an example, the wiring GL can be used as the wiring GL1 and wiring GL2 described in Embodiment 1 and Embodiment 2, and has the function of wiring to send selection signals or non-selection signals to the pixel circuit PX3.

[0394] As an example, wiring IL can be used as wiring AN as described in Embodiments 1 and 2. Therefore, wiring IL also functions as wiring to supply current to the anode of the light-emitting device ED. Therefore, wiring IL is sometimes referred to as a current supply line.

[0395] Wiring VCOM is used to supply a fixed potential to the second terminal of capacitor Cs2. In particular, this fixed potential is sometimes referred to as a common potential. This common potential can be, for example, a low-level potential, a ground potential, or a negative potential. Furthermore, wiring VCOM can also be used to supply a common potential to the second terminal of capacitor Cs2 included in other pixel circuits PX3 within the same pixel array section.

[0396] As an example, wiring VCAT can be used as the wiring CTH described in Embodiments 1 and 2. Wiring VCAT is used as wiring to supply a fixed potential to the cathode of the light-emitting device ED. In particular, this fixed potential is sometimes referred to as the cathode potential. The cathode potential can be, for example, a low-level potential, a ground potential, or a negative potential. In addition, wiring VCAT can also be used to supply a cathode potential to the cathodes of the light-emitting devices ED included in other pixel circuits PX3 in the same pixel array section.

[0397] Note that the common potential supplied by the wiring VCOM and the cathode potential supplied by the wiring VCAT can also be equal. In this case, the wiring VCOM and wiring VCAT can also be the same wiring (not shown).

[0398] Transistor Tr1 is used as the write transistor for image signals in the pixel circuit PX3. Therefore, when it is desirable to increase the frame rate of the display device, a transistor with a high drive frequency is preferably used as transistor Tr1.

[0399] Furthermore, transistor Tr1 is used as a switching transistor. In particular, when it is desired to reduce the frame rate of the display device, it is necessary to maintain the potential corresponding to the image signal for a long time. At this time, by replacing transistor Tr1 with one of the switching units described in Embodiment 1, the writing speed of the image signal in the on state can be increased and the leakage current in the off state can be reduced.

[0400] Furthermore, transistor Tr2 is used as a drive transistor to control the amount of current flowing between the anode and cathode of the light-emitting device ED in the pixel circuit PX3. Therefore, when the potential corresponding to the image signal is high, a transistor with high voltage tolerance is preferably used as transistor Tr2.

[0401] <Example 2 of pixel circuit structure> Figure 19B This illustrates the switch section that can be used in Embodiment 1 and is compatible with... Figure 19A The circuit diagrams show examples of different circuit structures for pixel circuits.

[0402] Figure 19B The pixel circuit PX4 shown includes, for example, transistors Tr1, Tr2, Tr3, and Tr4, capacitors Cs1 and Cs3, and a light-emitting device ED.

[0403] For information on transistors Tr1, Tr2, Cs1, and ED, please refer to the description of transistors Tr1, Tr2, Tr4, Cs1, and ED included in the pixel circuit PX3 described above.

[0404] The pixel circuit PX4 not only emits light according to the intensity of the input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is the driving transistor.

[0405] The first terminal of transistor Tr1 is connected to wiring SL. The second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1. The gate of transistor Tr1 is connected to wiring GL1. Furthermore, the first terminal of transistor Tr2 is connected to the first terminal of transistor Tr3. The second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs3, the first terminal of transistor Tr4, and the anode of the light-emitting device ED. Additionally, the second terminal of transistor Tr3 is connected to wiring VEL, and the gate of transistor Tr3 is connected to wiring GL2. Also, the second terminal of capacitor Cs3 is connected to wiring VEL. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. Finally, the cathode of the light-emitting device ED is connected to wiring VCAT.

[0406] For information on cabling SL and cabling VCAT, please refer to [link / reference]. Figure 19A Description of the wiring SL and wiring VCAT connected to the pixel circuit PX3.

[0407] For information on GL1 wiring, please refer to... Figure 19A Description of the wiring GL1 connected to the pixel circuit PX3.

[0408] As an example, wiring GL2 can be wiring GL3 as described in embodiment 2, and is used as wiring to send a selection signal or a non-selection signal for switching the on and off states of transistor Tr3.

[0409] As an example, wiring GL3 can be wiring GL1, wiring GL2, etc., as described in Embodiment 1 and Embodiment 2, for example, used as wiring to send a selection signal or a non-selection signal for switching the on and off states of transistor Tr4.

[0410] As an example, the wiring VEL can be the wiring AN described in Embodiments 1 and 2. Therefore, the wiring VEL is used as wiring to supply the anode potential of the light-emitting device ED. Furthermore, this potential can be the anode potential of the light-emitting device ED.

[0411] As an example, the wiring INIL can be the wiring VOE described in Embodiments 1 and 2. In particular, this potential can be, for example, an initialization potential used to reset the anode potential of the light-emitting device ED.

[0412] Transistors Tr3 and Tr4 are preferably transistors with high voltage tolerance.

[0413] Furthermore, transistors Tr3 and Tr4 are used as switching transistors. In particular, by replacing transistors Tr3 and Tr4 with one of the switching units described in Embodiment 1, the image signal writing speed in the on state can be improved and the leakage current in the off state can be reduced.

[0414] Additionally, in the pixel circuit PX4, transistors Tr1 and Tr2 can also be transistors that include a back gate. Specifically, as... Figure 20A As shown, the pixel circuit PX4 can also have the following structure, namely, the back gate of transistor Tr1 is connected to the gate of transistor Tr1 and the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2.

[0415] <Example 3 of pixel circuit structure> Figure 19C This illustrates the switch section that can be used in Embodiment 1 and is compatible with... Figure 19A and Figure 19B The circuit diagrams show examples of different circuit structures for pixel circuits.

[0416] Figure 19C The pixel circuit PX5 shown includes, for example, transistors Tr1, Tr2, Tr4, and Tr5, capacitor Cs1, and light-emitting device ED.

[0417] For information on transistors Tr1, Tr2, Tr4, capacitor Cs1, and light-emitting device ED, please refer to the description of transistors Tr1, Tr2, Tr4, capacitor Cs1, and light-emitting device ED included in the pixel circuit PX4 described above.

[0418] Like pixel circuit PX4, pixel circuit PX5 not only emits light according to the intensity of the input image signal, but also has the function of correcting the threshold voltage of transistor Tr2, which is the driving transistor.

[0419] Transistor Tr1's first terminal is connected to wiring SL. Transistor Tr1's second terminal is connected to the gate of transistor Tr2, the first terminal of transistor Tr5, and the first terminal of capacitor Cs1. Transistor Tr1's gate is connected to wiring GL1. Furthermore, transistor Tr2's first terminal is connected to wiring VEL, and its second terminal is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of the light-emitting device ED. Additionally, transistor Tr5's second terminal is connected to wiring VBL, and its gate is connected to wiring GL4. Transistor Tr4's second terminal is connected to wiring INIL, and its gate is connected to wiring GL3. Finally, the light-emitting device ED's cathode is connected to wiring VCAT.

[0420] For information on cabling SL, cabling VCAT, cabling VEL, and cabling INIL, please refer to [link / reference]. Figure 19B Description of wiring SL, wiring VCAT, wiring VEL and wiring INIL connected to the pixel circuit PX4.

[0421] For information on GL1 wiring, please refer to... Figure 19A Description of the wiring GL connected to the pixel circuit PX3.

[0422] For information on GL3 wiring, please refer to... Figure 19B Description of the wiring GL3 connected to the pixel circuit PX4.

[0423] For example, the wiring GL4 has the function of sending control signals to switch the on or off state of transistor Tr5.

[0424] Wiring VBL is used as a wiring to supply a fixed potential to the first terminal of capacitor Cs1. This fixed potential is preferably, for example, the potential input to the gate of transistor Tr2 when correcting the threshold voltage of transistor Tr2, and is almost equal to the potential supplied by wiring VEL.

[0425] Transistor Tr5 is preferably a transistor with high voltage tolerance. For example, transistor Tr5 is preferably a transistor with a thicker gate insulating film.

[0426] Furthermore, transistor Tr5 is used as a switching transistor. In particular, by replacing transistor Tr5 with one of the switching units described in Embodiment 1, the writing speed of the image signal in the on state can be improved and the leakage current in the off state can be reduced.

[0427] <Example 4 of pixel circuit structure> Figure 19D This illustrates the switch section that can be used in Embodiment 1 and is compatible with... Figures 19A to 19C The circuit diagrams show examples of different circuit structures for pixel circuits.

[0428] Figure 19D The pixel circuit PX6 shown includes, for example, transistors Tr1, Tr2, and Tr4, capacitor Cs1, and light-emitting device ED.

[0429] For information on transistors Tr1, Tr2, Tr4, capacitor Cs1, and light-emitting device ED, please refer to the description of transistors Tr1, Tr2, Tr4, capacitor Cs1, and light-emitting device ED included in the pixel circuit PX3 described above.

[0430] Like pixel circuit PX3, pixel circuit PX4 has the function of emitting light with an intensity that varies according to the input image signal.

[0431] The first terminal of transistor Tr1 is connected to wiring SL. The second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1. The gate of transistor Tr1 is connected to wiring GL1. Furthermore, the first terminal of transistor Tr2 is connected to wiring VEL. The second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of the light-emitting device ED. The second terminal of transistor Tr4 is connected to wiring INIL. The gate of transistor Tr4 is connected to wiring GL3. Additionally, the cathode of the light-emitting device ED is connected to wiring VCAT.

[0432] For information on routing SL, routing VCAT, routing INIL, routing GL1, and routing GL3, please refer to [link / reference]. Figure 19C Description of the wiring SL and wiring VCAT connected to the pixel circuit PX3.

[0433] In the pixel circuit PX4, transistor Tr2 can also be a transistor that includes a back gate. Specifically, as... Figure 20B As shown, the pixel circuit PX4 can also have a structure in which the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2.

[0434] Furthermore, similar to pixel circuits PX3 to PX5, transistors Tr1 and Tr4 are used as switching transistors. In particular, by replacing transistors Tr1 and Tr4 with one of the switching sections described in Embodiment 1, the image signal writing speed in the on state can be improved and the leakage current in the off state can be reduced.

[0435] <Example 5 of pixel circuit structure> Figure 21A This illustrates the switch section that can be used in Embodiment 1 and is compatible with... Figures 19A to 19D The circuit diagrams show examples of different circuit structures for pixel circuits.

[0436] Figure 21A The pixel circuit PX7 shown includes, for example, transistors Tr1 to Tr4, transistor Tr6, transistor Tr7, capacitor Cs1, and light-emitting device ED.

[0437] Note that for transistors Tr1 to Tr4, capacitor Cs1, and light-emitting device ED, please refer to the description of transistors Tr1 to Tr4, capacitor Cs1, and light-emitting device ED included in the pixel circuit PX4 above.

[0438] Like pixel circuits PX4 and PX5, pixel circuit PX7 not only emits light according to the intensity of the input image signal, but also has the function of correcting the threshold voltage of transistor Tr2, which is the driving transistor.

[0439] The first terminal of transistor Tr1 is connected to wiring SL. The second terminal of transistor Tr1 is connected to the first terminals of transistors Tr2 and Tr7. The gate of transistor Tr1 is connected to wiring GL1. The second terminal of transistor Tr2 is connected to the first terminals of transistors Tr3 and Tr6. The gate of transistor Tr2 is connected to the second terminal of transistor Tr6 and the first terminal of capacitor Cs1. The second terminal of transistor Tr3 is connected to wiring VEL. The gate of transistor Tr3 is connected to wiring GL2. Additionally, the gate of transistor Tr6 is connected to the gate of transistor Tr4 and wiring GL3. The second terminal of transistor Tr7 is connected to the first terminal of transistor Tr4, the second terminal of capacitor Cs1, and the anode of the light-emitting device ED. Additionally, the second terminal of transistor Tr4 is connected to wiring INIL. Furthermore, the cathode of the light-emitting device ED is connected to wiring VCAT.

[0440] For information on routing SL, routing GL1, routing GL2, routing GL3, routing VCAT, routing VEL, and routing INIL, please refer to the link provided. Figure 19B Description of the wiring SL, wiring GL1, wiring GL2, wiring GL3, wiring VCAT, wiring VEL and wiring INIL of the pixel circuit PX4.

[0441] For example, the GL5 wiring function has the function of sending control signals to switch the on or off state of transistor Tr7.

[0442] Transistors Tr6 and Tr7 are preferably transistors with high voltage tolerance. For example, transistors Tr6 and Tr7 are preferably transistors with thick gate insulating films.

[0443] Furthermore, transistors Tr6 and Tr7 are used as switching transistors. In particular, by replacing transistors Tr6 and Tr7 with one of the switching units described in Embodiment 1, the image signal writing speed in the on state can be improved and the leakage current in the off state can be reduced.

[0444] Note that the pixel circuit of the semiconductor device according to one aspect of the present invention is not limited to... Figure 21A The structure of the pixel circuit PX7 shown can be modified appropriately.

[0445] For example, such as Figure 21BThe pixel circuit shown in the PX7A can also be used in... Figure 21A The pixel circuit PX7 incorporates a capacitor Cs4. The first terminal of capacitor Cs4 is connected to the gate of transistor Tr1 and wiring GL1, while the second terminal of capacitor Cs4 is connected to the first terminal of transistor Tr4, the second terminal of transistor Tr7, the second terminal of capacitor Cs1, and the anode of the light-emitting device ED.

[0446] Additionally, in the pixel circuit PX7A, transistors Tr1, Tr2, and Tr6 can also be transistors that include a back gate. Specifically, as... Figure 22 As shown, the pixel circuit PX7A can also have the following structure: the back gate of transistor Tr1 is connected to the gate of transistor Tr1, the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, and the back gate of transistor Tr6 is connected to the gate of transistor Tr6.

[0447] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in other embodiments.

[0448] (Implementation Method 4) In this embodiment, a display device including a pixel array and a driving circuit having a pixel circuit having a semiconductor device according to one aspect of the present invention will be described.

[0449] <Example of a display device structure> Figure 23 This is a block diagram illustrating a structural example of a display device including a pixel array and a driving circuit of a pixel circuit having a semiconductor device according to one aspect of the present invention. Figure 23 As an example, a display device DSP includes a pixel array PXA, a driving circuit GD, and a driving circuit SD.

[0450] Furthermore, the pixel array PXA, driving circuit GD, and driving circuit SD can also be mounted on the same support. Additionally, some or all of the circuits listed above can be directly formed on the support, or mounted on the support using COG (Chip On Glass) or similar methods. Furthermore, some or all of the circuits listed above can also be mounted on an FPC (Flexible Printed Circuit) connected to the support using COF (Chip On Film) or similar methods.

[0451] A pixel array PXA may include, for example, multiple pixel circuits PX. The multiple pixel circuits PX are arranged in an array within the pixel array PXA. For example, in the pixel array PXA, the multiple pixel circuits PX may be arranged in any of the following configurations: matrix arrangement, stripe arrangement, S-stripe arrangement, Delta arrangement, Bayer arrangement, Pentile arrangement, etc. Furthermore, in... Figure 23 In this diagram, the pixel circuit PX located in the i-th row and j-th column (where i is an integer greater than or equal to 1 and j is an integer greater than or equal to 1) among multiple pixel circuits PX is represented as pixel circuit PX[i, j]. Note that a pixel array PXA may also include one pixel circuit PX without including multiple pixel circuits PX.

[0452] The plurality of pixel circuits PX can, for example, use any one of the pixel circuits PX1A, PX1B, and PX1C described in Embodiment 1. Furthermore, the plurality of pixel circuits PX can, for example, use either pixel circuit PX2A or pixel circuit PX2B described in Embodiment 2. Additionally, the plurality of pixel circuits PX can, for example, use any one of the pixel circuits PX3, PX4, PX5, PX5A, PX6, PX7, and PX7A described in Embodiment 3.

[0453] Multiple pixel circuits PX, for example, have the function of acquiring image signals sent from the driving circuit SD (described later) and emitting light according to the intensity of the image signals. Furthermore, for example, by using one pixel circuit PX as a sub-pixel and setting the colors of the light emitted by the three sub-pixels to red (R), green (G), and blue (B), white light can be emitted.

[0454] Furthermore, the screen resolution of the display device DSP is determined by the number of pixel circuits PX included in the pixel array PXA. For example, when the screen resolution of the display device DSP is 8K4K, the number of pixel circuits PX included in the pixel array PXA is 7680×4320. Moreover, when the pixel circuit PX includes sub-pixel circuits for three colors, such as red (R), green (G), and blue (B), the total number of such sub-pixel circuits included in the pixel array PXA is 7680×4320×3. Note that the screen resolution of the display device DSP can be SD (720×480 pixel circuits PX), HD (1280×720 pixel circuits PX), FHD (1920×1080 pixel circuits PX), or 4K2K (3840×2160 pixel circuits PX). However, the screen resolution of the display device DSP is not limited to the above and can be arbitrarily determined during the design phase of the display device DSP.

[0455] Furthermore, the diagonal size of the display area (e.g., pixel array PXA) of the display device DSP can be determined depending on the electronic device equipped with the display device DSP. For example, in applications such as television devices with large displays, the diagonal size of the display area can sometimes be 20 inches or more, 30 inches or more, 60 inches or more, or 100 inches or more. Additionally, in applications such as tablet information terminals or portable information terminals with small to medium-sized displays, the diagonal size of the display area can sometimes be 3 inches or more and 13 inches or less. Furthermore, in applications such as XR devices and wearable information terminals with small displays, the diagonal size can sometimes be, for example, less than 3 inches, less than 1.5 inches, or less than 1 inch.

[0456] Furthermore, the resolution (sometimes referred to as pixel density) of the display area of ​​the display device DSP is determined based on the aforementioned screen resolution and diagonal size. For example, when the display device DSP is used in a large display, the resolution of the display area of ​​the display device DSP is preferably 50 ppi or more, more preferably 100 ppi or more, and even more preferably 150 ppi or more. Furthermore, when the display device DSP is used in a small to medium-sized display, the resolution of the display area of ​​the display device DSP is preferably 200 ppi or more, more preferably 400 ppi or more, and even more preferably 800 ppi or more. Furthermore, when the display device DSP is used in a small display, the resolution of the display area of ​​the display device DSP is preferably 1000 ppi or more, more preferably 2000 ppi or more, and even more preferably 4000 ppi or more.

[0457] Furthermore, there are no particular restrictions on the screen ratio (aspect ratio) of the display area (e.g., pixel array PXA) of the display device DSP. For example, the display area can correspond to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0458] The driving circuit GD is used, for example, as a gate driver circuit, in which signals of the pixel circuits PX included in the pixel array PXA, which are selected as objects for writing image signals, are sent to the selection signal line.

[0459] In particular, when the pixel circuit PX is the pixel circuit PX1A described in Embodiment 1, the driving circuit GD is connected to the wiring GL1 and wiring GL1B, which serve as selection signal lines. Furthermore, the driving circuit GD functions as follows: when the driving circuit GD selects the pixel circuit PX1, it sends a group of logically inverted selection signals to wiring GL1 and wiring GL1B; when the driving circuit GD does not select the pixel circuit PX1, it sends a group of logically inverted non-selection signals to wiring GL1 and wiring GL1B. Similarly, when the pixel circuit PX is the pixel circuit PX1A described in Embodiment 1, the driving circuit GD is connected to the wiring GL2 and wiring GL2B, which serve as other selection signal lines. Similarly, the driving circuit GD functions as follows: when the driving circuit GD selects the pixel circuit PX1, it sends a group of logically inverted selection signals to wiring GL2 and wiring GL2B; when the driving circuit GD does not select the pixel circuit PX1, it sends a group of logically inverted non-selection signals to wiring GL2 and wiring GL2B.

[0460] In other words, when the pixel circuit PX is the pixel circuit PX1A described in Embodiment 1, the driving circuit GD can also have the function of sending a group of selection signals or a group of non-selection signals that are logically reversed to each other on the two selection signal lines. Note that the same applies when the pixel circuit PX is the pixel circuits PX1B and PX1C described in Embodiment 1, the pixel circuits PX2A and PX2B described in Embodiment 2, and the pixel circuits described in Embodiment 3.

[0461] The driving circuit SD is used, for example, as a source driver circuit to send image signals to the pixel circuits PX included in the pixel array PXA. The driving circuit SD particularly includes shift registers that distribute the image signals to each column, latch circuits that temporarily hold the image signals, and digital-to-analog converter circuits that convert digital image signals into analog signals.

[0462] Pixel circuits PX[i,j] are connected to driving circuits GD, for example, via wiring GLS[i]. Additionally, pixel circuits PX[i,j] are connected to driving circuits SD, for example, via wiring SLS[j].

[0463] The wiring GLS[i] is used, for example, as a selection signal line (sometimes referred to as a gate line, etc.) to send selection signals from the driver circuit GD to the pixel circuit PX[i,j] to drive the pixel circuit PX[i,j]. Note that the wiring GLS[i] can be a single selection signal line or a group of wirings consisting of multiple selection signal lines.

[0464] For example, in the pixel circuit PX1A described in Embodiment 1, the wiring GL1, wiring GL1B, wiring GL2, and wiring GL2B, which serve as selection signal lines, can be Figure 23 The wiring GLS[i] shown is an example. Furthermore, for example, in the pixel circuit PX1B described in Embodiment 1, the wiring GL and wiring GLB, which serve as selection signal lines, can be... Figure 23 The wiring GLS[i] shown is an example. Furthermore, for example, in the pixel circuit PX1C described in Embodiment 1, the wiring GL1 and wiring GL2, which serve as selection signal lines, can be... Figure 23 The wiring GLS[i] shown is shown.

[0465] Furthermore, for example, in the pixel circuits PX2A and PX2B described in Embodiment 2, the wiring GL1, wiring GL1B, wiring GL2, wiring GL2B, and wiring GL3, which serve as selection signal lines, can be... Figure 23 The wiring GLS[i] shown is shown.

[0466] Furthermore, for example, in each pixel circuit described in Embodiment 3, the wiring GL1, wiring GL2, wiring GL3, wiring GL4, and wiring GL4, etc., which serve as selection signal lines, can be... Figure 23 The wiring GLS[i] shown is shown.

[0467] The wiring SLS[j] is used, for example, as wiring to send image signals from the driver circuit SD to the pixel circuit PX[i,j] for displaying an image on the pixel circuit PX[i,j] (sometimes referred to as source line, data line, etc. in this specification). Note that the wiring SLS[j] can be a single wiring or a group of wirings.

[0468] For example, in the pixel circuits PX1A, PX1B, and PX1C described in Embodiment 1, the wiring SL, which serves as the wiring for transmitting image signals, can be... Figure 23 The wiring SLS[j] shown. Furthermore, for example, in the pixel circuits PX2A and PX2 described in Embodiment 2, and each pixel circuit described in Embodiment 3, the wiring SL connected to each circuit can be... Figure 23 The wiring SLS[j] shown is shown.

[0469] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in other embodiments.

[0470] (Implementation Method 5) In this embodiment, an example of the structure of the display device including pixel circuits described in the above embodiments will be explained.

[0471] Figure 24A This is a perspective view of a display device illustrating one aspect of the present invention. The display device DSP1 includes, for example, a display area DIS, a driving circuit area DRV, and a terminal area TMR. Furthermore, the display device DSP1 includes a substrate BS, on which the display area DIS, the driving circuit area DRV, and the terminal area TMR are all located. Note that the display area DIS may, for example, include a pixel array section including pixel circuitry as described in Embodiment 1.

[0472] As a substrate (BS), for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used. In addition to semiconductor substrates, other substrates that can be used as BS include SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, and paper or substrate films containing fibrous materials. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and substrate films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is synthetic resins such as acrylic resins. Yet another example is polypropylene, polyester, ethylene fluoride, or polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited thin film, or paper. Furthermore, when the manufacturing process of the display device DSP1 includes heat treatment, a material with high heat resistance is preferably used as the substrate BS.

[0473] For example, when a semiconductor substrate made of silicon is used as the substrate BS, the transistors used in the display area DIS and the driving circuit area DRV can be Si transistors, which can be formed on the substrate BS.

[0474] Alternatively, for example, when a glass substrate is used as the substrate BS, OS transistors can be used as transistors in the display area DIS and the driving circuit area DRV, and they can be formed on the substrate BS.

[0475] In addition, one or more of the drive circuits GD1, GD2 and SD selected from the drive circuit region DRV can also be mounted as ICs (Integrated Circuits) on the substrate BS using COG technology.

[0476] For example, both drive circuits GD1 and GD2 are used as drive circuits for displaying images on the display area DIS. Specifically, for example, both drive circuits GD1 and GD2 are used as gate drive circuits that send selection signals or non-selection signals to the pixel circuits included in the display area DIS. Furthermore, for example, drive circuit SD is used as a source drive circuit that sends image signals to the pixel circuits included in the display area DIS. Note that for drive circuits GD1 and GD2, refer to the description of drive circuit GD as described in Embodiment 4. Similarly, for drive circuit SD, refer to the description of drive circuit SD as described in Embodiment 4.

[0477] The terminal area TMR includes terminals for supplying image signals and power voltage from outside the display device DSP1 to inside the display device DSP1. Furthermore, the terminal area TMR can also be connected to the FPC. Alternatively, an IC chip can be mounted on the FPC using COF technology. This IC chip may, for example, include driving circuitry for displaying images on the display area DIS.

[0478] The display area DIS may include multiple pixels. Furthermore, the multiple pixels in the display area DIS can also be configured in a matrix.

[0479] Alternatively, as multiple pixels, they may be, for example, one or more pixel circuits selected from liquid crystal display devices, light-emitting devices containing organic EL materials, light-emitting devices containing inorganic EL materials, and light-emitting diodes including micro LEDs.

[0480] Furthermore, each of the multiple pixels can represent one or more colors. In particular, the multiple colors can be, for example, red, green, and blue. Alternatively, the multiple colors can be, for example, two or more selected from red, green, blue, cyan, magenta, yellow, and white. When each pixel representing a different color is referred to as a sub-pixel, and white is represented by these multiple sub-pixels of different colors, these multiple sub-pixels are sometimes collectively referred to as a pixel. In this specification, for convenience, sub-pixels will be referred to as pixels.

[0481] Furthermore, the display device according to one aspect of the present invention is not limited to... Figure 24A The structure of the display device DSP1 shown is illustrated. For example, the display device according to one embodiment of the present invention may also employ... Figure 24BThe structure of the display device DSP2 shown is illustrated.

[0482] Figure 24B The display device DSP2 shown includes, for example, a display area DIS, a circuit area SiC, and a terminal area TMR. Furthermore, like the display device DSP1, the display device DSP2 includes a substrate BS. The difference between the display device DSP2 and the display device DSP1 is that the display device DSP2 has a circuit area SiC and a terminal area TMR disposed on its substrate BS, and the display area DIS is disposed on the circuit area SiC.

[0483] The circuit region SIC includes, for example, the drive circuit region DRV described above. Alternatively, the circuit region SIC may also include various functional circuits other than the drive circuit region DRV. In this embodiment, the functional circuits are included in the functional circuit region MFNC.

[0484] Alternatively, for example, the functional circuit area MFNC may also include a GPU (Graphics Processing Unit). Furthermore, if the display device DSP2 includes a touch panel, the functional circuit area MFNC may also include a sensor controller that controls the touch sensors included in the touch panel.

[0485] Furthermore, when an organic EL (electroluminescent) light-emitting device is used as the display element in the display device DSP2, the functional circuit area MFNC may also include an EL correction circuit. The EL correction circuit, for example, has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. The brightness of the light emitted by the organic EL-containing light-emitting device is proportional to the current; therefore, if the characteristics of the driving transistor connected to the light-emitting device are poor, the brightness of the light emitted by the light-emitting device may sometimes be lower than the desired brightness. The EL correction circuit, for example, can monitor the amount of current flowing through the light-emitting device and increase the amount of current flowing through the light-emitting device when the amount of current is less than the desired amount, thereby increasing the brightness of the light emitted by the light-emitting device. Conversely, when the amount of current is greater than the desired amount of current, the amount of current flowing through the light-emitting device can be adjusted to be less.

[0486] In addition, when a liquid crystal element is used as the display element of the display device DSP2, the functional circuit area MFNC may also include a gamma correction circuit.

[0487] Figure 25 It is shown Figure 24B A block diagram illustrating an example structure of the display device DSP2. Figure 25 The display device DSP2 shown includes, for example, a display area DIS and a circuit area SIC. Additionally, Figure 25The sensor PDA is shown. The sensor PDA can be configured either inside the display device DSP2 or externally.

[0488] in addition, Figure 24A The display device DSP1 can also be connected to the functional circuit area MFNC located outside the display device DSP1 via the terminal area TMR. In this case, the structure of the display device DSP1 can be regarded as being the same as... Figure 25 The display device DSP2 shown has the same structure.

[0489] exist Figure 25 In the diagram, thick solid lines represent multiple wirings or buses.

[0490] In addition, Figure 25 In, for example, multiple pixel circuits PX are configured in a matrix in the display area DIS.

[0491] In addition, as mentioned above, in Figure 25 The SIC (System-in-Chips) circuit area includes the DRV (Driver Circuit Area) and the MFNC (Functional Circuit Area).

[0492] The driving circuit region (DRV) is used, for example, as the peripheral circuitry to drive the display area (DIS). Specifically, the driving circuit region (DRV) includes, for example, the driving circuit SD and the driving circuit GD.

[0493] Additionally, for example, the functional circuit area MFNC may include: a storage device for storing image data to be displayed on the display area DIS; a decoder for decoding the encoded image data; and circuits such as a GPU, power supply circuit, correction circuit, or CPU for processing the image data. Figure 25 In the MFNC functional circuit area, for example, there are storage devices MEM, GPU 22, EL correction circuit ECR, timing controller TMC, CPU (NoffCPU (registered trademark)) 21, sensor controller SCC and power supply circuit EPS.

[0494] Additionally, for example, in Figure 25 In the display device DSP2, the circuits included in the driving circuit area DRV and the circuits included in the functional circuit area MFNC are each connected to the bus BSL.

[0495] The driving circuit SD, for example, has the function of sending image data to the pixel circuit PX included in the display area DIS. Therefore, the driving circuit SD is connected to the pixel circuit PX via wiring SL. Note that the wiring SL described in Embodiments 1 to 3 can be... Figure 25 The wiring SL is shown.

[0496] Alternatively, the driving circuit SD may also include a digital-to-analog conversion circuit. This circuit, for example, has the function of converting image data digitally processed using the GPU or correction circuit described later into analog data. The image data converted to analog data is then sent to the display area DIS via the driving circuit SD. Alternatively, the digital-to-analog conversion circuit may also be configured externally to the driving circuit SD.

[0497] As an example, in the display area DIS, the driving circuit GD has the following functions: sending a selection signal to the pixel circuit PX that is the object of image data transmission; and sending a non-selection signal to the pixel circuit PX that is not the object of image data transmission. Therefore, the driving circuit GD is connected to the pixel circuit PX through wiring GL. Note that the wirings GL1 to GL3, wiring GL1B, wiring GL2B, etc., used as selection signal lines as described in Embodiments 1 to 3 can be... Figure 25 The wiring diagram shown is GL.

[0498] Additionally, the drive circuit SD may also include a level shifter. For example, a level shifter may have the function of converting selection signals input to the pixel circuit of the display area DIS into appropriate levels. Furthermore, a level shifter may also have the function of converting signals input to the drive circuit SD, digital-to-analog converter circuit, drive circuit GD, etc., into appropriate levels.

[0499] The storage device MEM, for example, has the function of storing image data displayed on the display area DIS. Note that the storage device MEM can have a structure that stores image data as digital data or analog data.

[0500] Furthermore, when storing image data in a storage device MEM, a non-volatile memory is preferably used as the storage device MEM. In this case, a NAND flash memory or similar device can be used as the storage device MEM.

[0501] Furthermore, when storing temporary data generated by the GPU22, EL correction circuit ECR, CPU21, etc., in the storage device MEM, volatile memory is preferably used as the storage device MEM. In this case, SRAM, DRAM, etc., can be used as the storage device MEM, for example.

[0502] For example, the GPU 22 has the function of processing image data read from the storage device MEM and depicting it on the display area DIS. In particular, since the GPU 22 has a structure that performs parallel pipelined processing, it can process image data displayed on the display area DIS at high speed. In addition, the GPU 22 may also have the function of a decoder for decoding encoded images.

[0503] Furthermore, the functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display area DIS. For example, a correction circuit (a circuit for color adjustment or dimming) may be provided, which detects color unevenness in the image displayed by the display area DIS and corrects this unevenness to achieve the most suitable image. Additionally, when light-emitting devices containing organic EL materials are used in the pixels of the display area DIS, an EL correction circuit may also be provided in the functional circuit region MFNC. Note that in this embodiment, the case where the pixel circuit PX of the display area DIS uses a light-emitting device containing organic EL materials is described, and the functional circuit region MFNC includes, for example, a correction circuit ECR as an EL correction circuit.

[0504] Furthermore, the image correction described above can also utilize artificial intelligence. For example, the current flowing through the display device including the pixels (or the voltage applied to the display device) can be monitored and acquired, and an image displayed on the display area DIS can be acquired by an image sensor or the like. The current (or voltage) and the image can be used as input data for artificial intelligence calculations (e.g., artificial neural networks), and the image can be determined based on its output results to determine whether the image needs to be corrected.

[0505] Furthermore, artificial intelligence computations can be applied not only to image correction but also to the upconversion processing of image data. Therefore, by upconverting image data with low screen resolution according to the screen resolution of the display area DIS, high-quality images can be displayed on the display area DIS. Additionally, artificial intelligence computations can be applied to the downconversion processing of image data.

[0506] Note that the aforementioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC. In other words, the GPU 22 can be used to perform various correction calculations (correcting color unevenness, upconversion processing, etc.). Additionally, the GPU 22 may also include circuitry 22a for correcting color unevenness and circuitry 22b for upconversion processing.

[0507] Note that in this specification, the GPU performing artificial intelligence calculations is referred to as an AI accelerator. That is, in this specification, the GPU included in the functional circuit area MFNC is sometimes described as an AI accelerator.

[0508] The timing controller (TMC) has, for example, the function of increasing or decreasing the frame rate of the image displayed on the display area (DIS). For instance, when displaying a static image on the DIS, the display device DSP2 can be driven by decreasing the frame rate through the timing controller (TMC); conversely, when displaying a moving image on the DIS, the display device DSP2 can be driven by increasing the frame rate through the timing controller (TMC). In other words, by setting the timing controller (TMC) in the display device DSP2, the frame rate can be changed according to whether the image is static or moving. In particular, when displaying a static image on the DIS, the frame rate can be decreased, thereby reducing the power consumption of the display device DSP2.

[0509] CPU 21, for example, has general processing functions such as executing the operating system, controlling data, performing various calculations, and executing programs. In the display device DSP 2, CPU 21, for example, has the function of executing instructions such as writing or reading image data from the storage device MEM, correcting image data, and operating the sensor (described later). Furthermore, CPU 21 may also have the function of sending control signals to one or more circuits selected from the storage device, GPU, correction circuit, timing controller, and high-frequency circuit, included in the functional circuit area MFNC.

[0510] Alternatively, CPU 21 may include a circuit for temporarily backing up data (hereinafter referred to as a backup circuit). Preferably, the backup circuit can retain the data even if the power supply voltage is stopped. For example, when displaying a static image on the display area DIS, CPU 21 can stop its function until an image different from the current static image is displayed. Thus, by temporarily backing up the data processed in CPU 21 to the backup circuit, and then stopping CPU 21 by stopping the power supply voltage to CPU 21, the dynamic power consumption of CPU 21 can be reduced. In this specification, the CPU including the backup circuit is referred to as the Noff CPU.

[0511] The sensor controller (SCC) has, for example, the function of controlling a sensor PDA. Additionally, in Figure 25 In the diagram, the wiring SNCL is shown as the wiring used to connect the sensor PDA and the sensor controller SCC.

[0512] Additionally, the sensor PDA can be, for example, an illuminance sensor. Specifically, by obtaining the intensity of the external light illuminating the display area DIS using the illuminance sensor, the brightness of the image displayed on the display area DIS can be adjusted according to the external light. For example, when the external light is bright, the brightness of the image displayed on the display area DIS can be increased to improve the image's visibility. Conversely, when the external light is dim, the brightness of the image displayed on the display area DIS can be reduced to decrease power consumption.

[0513] Alternatively, the sensor PDA can be, for example, an image sensor. For instance, by acquiring an image using this image sensor, the image can be displayed on the display area DIS.

[0514] The power supply circuit EPS, for example, has the function of generating voltages to the circuits included in the drive circuit region DRV, the circuits included in the functional circuit region MFNC, and the pixels included in the display region DIS. Note that the power supply circuit EPS may also have the function of selecting which circuits to supply voltage to. For example, during the display of a static image on the display region DIS, the power supply circuit EPS can reduce the overall power consumption of the display device DSP by stopping the supply of voltage to the circuits in the drive circuit region DRV (e.g., drive circuit SD, digital-to-analog conversion circuit, etc.) and the circuits in the functional circuit region MFNC (e.g., CPU21, GPU22, etc.).

[0515] Furthermore, the display device of one embodiment of the present invention can also be modified. Figure 24A The structure of the display device DSP1 is thus made Figure 24C The display device shown is DSP3.

[0516] Display device DSP3 is a modified example of display device DSP1, wherein a sensor area TP is provided in the area overlapping with the display area DIS.

[0517] Furthermore, the display device DSP3 includes a driving circuit TDE and a driving circuit TDR, both of which are disposed on the substrate BS. Additionally, as... Figure 24C As shown, both the drive circuit TDE and the drive circuit TDR are included in the drive circuit region DRV.

[0518] The drive circuit TDR has the function of successively sending pulse signals to the multiple sensors included in the sensor area TP. Additionally, the drive circuit TDE has the function of detecting changes in the amount of current flowing through the multiple sensors included in the sensor area TP.

[0519] As described above, the display device DSP3 has a structure in which a touch panel is provided as a user interface.

[0520] Note that, although not shown, the sensor area TP can also be positioned above the display area DIS of the display device DSP2. In this case, it is preferable to position the drive circuit TDR and drive circuit TDE within the circuit area SIC.

[0521] <Example 1 of the cross-sectional structure of a display device> Next, it will be explained when viewed from the cross-section. Figure 24A The diagram shows an example of the structure of the display device DSP1.

[0522] Figure 26 The display device DSP1A shown is viewed in cross-section. Figure 24A The diagram shows an example of the structure of the display device DSP1A. In the display device DSP1A, pixel circuits, driving circuits, etc., are disposed on the substrate 310. Figure 26 The display device DSP1A also shows Figure 24A The driving circuit area DRV and the display area DIS are shown.

[0523] Figure 26 The substrate 310 in the middle can be Figure 24A The substrate BS is shown. Furthermore, the diagonal size of the display device DSP1A can be determined, for example, based on the type and size of the substrate 310. For example, when manufacturing display devices with diagonal sizes of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for television devices or digital signage electronic devices, a glass substrate can be used as the substrate 310. Alternatively, for example, when manufacturing display devices with diagonal sizes of 1.5 inches or less, 1 inch or less, or 0.5 inches or less for XR devices or wearable information terminals, a semiconductor substrate can be used as the substrate 310.

[0524] Note that in Figure 26 In the description of the display device DSP1A, the substrate 310 is a glass substrate.

[0525] Furthermore, there are no particular restrictions on the screen ratio (aspect ratio) of the display device DSP1A. For example, the display device DSP1A can correspond to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0526] exist Figure 26 In the display device DSP1, transistors MNy and MNx are formed on a substrate. In this specification, transistors MNy and MNx are collectively referred to as transistor MN. Furthermore, a light-emitting device 130 is disposed above transistors MNy and MNx. Figure 26 Among them, light-emitting device 130R, light-emitting device 130G and light-emitting device 130B.

[0527] Transistor MNx is included in the display area DIS and is used, for example, as a transistor included in the pixel circuit PX. Additionally, transistor MNy is used as a transistor included in the drive circuit area DRV. Therefore, transistor MNy can, for example, be a transistor included in the functional circuit area MFNC described in this embodiment. Furthermore, the light-emitting device 130 can also be a light-emitting device ED included in the pixel circuit PX.

[0528] The specific structures of transistors MNy and MNx are described below. Figure 27A A planar schematic diagram of transistor MN is shown. Additionally, Figure 27B It is along Figure 27A The cross-sectional diagram of the section shown by the dotted line A1-A2 is also a cross-sectional diagram of transistor MN. Furthermore, Figure 27C It is along Figure 27A The cross-sectional diagram of the section shown by the dotted line A3-A4 is also a cross-sectional diagram of the transistor MN.

[0529] exist Figures 27A to 27C In this diagram, the direction of the dashed line A1-A2 is considered the X direction, and the direction of the dashed line A3-A4 is considered the Y direction. Furthermore, the direction perpendicular to both the X and Y directions is the Z direction. The X and Y directions can be perpendicular to each other. In subsequent figures, the definitions of the X, Y, and Z directions may sometimes be the same as above and sometimes different. Additionally, in... Figure 27A In the explanation of planar diagrams, the right side is sometimes referred to as the +X direction, the left side as the -X direction, the top side as the +Y direction, and the bottom side as the -Y direction. Additionally, in... Figure 27B In the explanation of cross-sectional diagrams, the right side is sometimes referred to as the +X direction, the left side as the -X direction, the top side as the +Z direction, and the bottom side as the -Z direction. Additionally, in... Figure 27C In the description of the cross-sectional diagram, the right side is sometimes referred to as the +Y direction, the left side as the -Y direction, the top side as the +Z direction, and the bottom side as the -Z direction.

[0530] Figures 27A to 27C The transistor MN includes insulating layers IS1 to IS3, insulating layer GI1, conductive layers ME1 to ME3, and semiconductor layer SC1.

[0531] The insulating layer IS1 is used, for example, as a base film or interlayer film for setting the source, drain and channel formation regions of the transistor MN on it.

[0532] The insulating layer IS1 can be made of, for example, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride. Alternatively, as the insulating layer IS1, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are preferred because they readily form regions containing oxygen released by heating. Alternatively, the insulating layer IS1 can be made of, for example, a resin. Furthermore, the above-mentioned insulating materials can be appropriately combined as materials for the insulating layer IS1.

[0533] In this specification, etc., "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as "silicon oxynitride", it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride", it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0534] Furthermore, an insulating material with a low relative permittivity is preferably used as the insulating layer IS1. By using an insulating material with a low relative permittivity in the interlayer film, parasitic capacitance generated between the wirings can be reduced. Specifically, for example, the relative permittivity of the insulating layer IS1 is preferably less than 4, more preferably less than 3. Examples of insulating materials with a low relative permittivity include silicon oxide, silicon oxynitride, and silicon oxynitride.

[0535] The conductive layer ME1 is a conductor (sometimes also called a terminal, wiring, etc.) used as one of the source and drain electrodes in the transistor MN. Furthermore, the conductive layer ME2 is another conductor (sometimes also called a terminal, wiring, etc.) used as the other of the source and drain electrodes in the transistor MN.

[0536] Note that in Figures 27A to 27C In this configuration, conductive layer ME1 extends in the Y direction, for example, as a wiring. Furthermore, conductive layer ME2 extends in the X direction, for example, as a wiring.

[0537] For conductive layers ME1 and ME2, it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, alloys composed of two or more of the aforementioned metal elements, or combinations of alloys composed of two or more of the aforementioned metal elements. For conductive layer ME1, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements (e.g., phosphorus or arsenic), or silicides (e.g., nickel silicides) can also be used as conductors.

[0538] In addition, insulating layer IS2 is used, for example, as an interlayer film in transistor MN to separate the source and drain.

[0539] As the insulating layer IS2, for example, a material that can be used for the insulating layer IS1 can be used.

[0540] Furthermore, an opening KK1 is formed in the region of the insulating layer IS2 where the transistor MN is disposed, the opening of which has a side surface that is substantially perpendicular to the XY plane (with a cone angle of 70° or more and 110° or less). In particular, the closer the cone angle is to 90°, the smaller the area of ​​the opening KK1 can be, thereby reducing the area used to form the transistor MN. In addition, the semiconductor layer SC1, which includes the channel formation region of the transistor MN, is disposed in such a way that it contacts the conductive layers ME1 and ME2 through the opening KK1.

[0541] Note that in Figure 27A In the top view, the shape of the opening KK1 is, for example, a perfect circle, but one aspect of the invention is not limited to this. The shape of the opening KK1 can be, for example, a figure with a single closed curve as its edge (including an ellipse), or a polygon with rounded corners.

[0542] The semiconductor layer SC1 can be, for example, a metal oxide used as an oxide semiconductor. In this case, the transistor MN is an OS transistor. As an example of this metal oxide, it preferably contains at least indium or zinc. It is particularly preferred to contain indium and zinc. In addition, it is also preferred to contain element M. As element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, element M is preferably selected from one or more selected from aluminum, gallium, yttrium, and tin. Furthermore, element M is more preferably composed of one or both gallium and tin.

[0543] Furthermore, as an example, the semiconductor layer SC1 preferably uses an In-Ga-Zn oxide. In particular, as an In-Ga-Zn oxide, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or similar, a 4:2:3 or similar atomic ratio, or a 3:1:2 or similar atomic ratio is more preferred. Furthermore, as another example, the semiconductor layer SC1 preferably uses an In-Zn oxide. In particular, the In-Zn oxide is more preferably a metal oxide with an In:Zn ratio of 4:1 or similar atomic ratio.

[0544] In addition, in transistor MN, an insulating layer GI1 is disposed on semiconductor layer SC1. Specifically, when viewed from above, insulating layer GI1 overlaps with and is located above the channel forming region in semiconductor layer SC1. Therefore, insulating layer GI1 is used as the gate insulating film of transistor MN.

[0545] As the insulating layer GI1, it is preferable to use an insulator containing so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) as a single layer or in a stack. Alternatively, the insulating layer GI1 may also use an insulator with a relatively high permittivity, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0546] Furthermore, in transistor MN, the conductive layer ME3 is disposed on the insulating layer GI1 in a manner that fills the opening KK1. The conductive layer ME3 serves as a conductor (sometimes referred to as a terminal, wiring, etc.) for the respective gates of transistors MN.

[0547] The conductive layer ME3 can be made of materials that can be used for conductive layer ME1 or conductive layer ME2.

[0548] Note that in Figures 27A to 27C In this case, the conductive layer ME3 extends in the Y direction, for example, as a wiring extension.

[0549] As mentioned above, in Figures 27A to 27C In the transistor MN shown, the conductive layer ME1, which serves as one of the source and drain electrodes, is located below the insulating layer IS2, which forms an interlayer film, while the conductive layer ME2, which serves as the other of the source and drain electrodes, is located above the insulating layer IS2. Therefore, in the transistor MN, the channel formation region is positioned along the opening KK1.

[0550] As mentioned above, in transistor MN, the source and drain electrodes are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction can be said to have a height (vertical) component, so transistor MN can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, etc.

[0551] like Figures 27A to 27CAs shown, by providing the channel formation region of the transistor along the side of the opening of the insulator used as the interlayer film, the transistor formation area can be reduced compared to providing the channel formation region of the transistor along the XY plane. In the transistor MN, the source electrode, semiconductor layer, and drain electrode can be stacked, thus significantly reducing the occupied area compared to a so-called planar transistor where the semiconductor is arranged in a planar shape. Therefore, by using one or both of the transistors MN to form a circuit, the area of ​​the circuit can be reduced. Furthermore, as a result, the miniaturization of the semiconductor device or display device including this circuit can be achieved.

[0552] Transistor MN can be either a p-channel transistor or an n-channel transistor. Alternatively, multiple transistors MN can be configured, using both p-channel and n-channel transistors.

[0553] Alternatively, a VLFET (Vertical Lateral Field Effect Transistor) structure can be used as the transistor MN, instead of using... Figures 27A to 27C The vertical channel transistor shown.

[0554] Figures 28A to 28C The transistor MN shown is a VLFET structure transistor, with current flowing in both the longitudinal and lateral directions. Specifically, the semiconductor layer is in contact with the side surface of an opening in the first insulating layer and the top surface of a second insulating layer corresponding to the bottom of the opening, and the channel formation region of the transistor MN is included in the semiconductor layer. In other words, since the channel length of the transistor MN has components along the side surface of the opening and components along the bottom of the opening, it is easy to increase the channel length compared to the channel length of existing transistor structures. Note that the channel length here can refer to the length between the source and drain of the channel formation region.

[0555] In addition, Figure 28B The transistor MN contains the channel length CHL of the channel formation region in the semiconductor layer SC1.

[0556] By increasing the channel length, the off-state current (leakage current) of the transistor can be reduced. Therefore, for example, by increasing the channel length... Figures 28A to 28C The transistor MN shown is used in transistors M1 to M5 in the pixel circuits described in Embodiments 1 and 2, and transistor Tr1 in the pixel circuit described in Embodiment 3, etc., and can maintain the potential of the first terminal of capacitor C1 for a long time. In other words, it can prevent unintentional potential changes of the first terminal of capacitor C1 caused by leakage current, etc.

[0557] Therefore, for example, in Figures 19A to 19D In each pixel circuit PX, by... Figures 28A to 28C The transistor MN shown serves as transistor Tr1, which can maintain the potential of the first terminal of capacitor Cs1 for a long period of time. In other words, it can prevent unintentional potential fluctuations of the first terminal of capacitor Cs1 caused by leakage current, etc.

[0558] Figure 28A This is a planar schematic diagram of transistor MN. Additionally, Figure 28B It is along Figure 28A The cross-sectional diagram of the section shown by the dotted line A1-A2 is also a cross-sectional diagram of transistor MN. Furthermore, Figure 28C It is along Figure 28A The cross-sectional diagram of the section shown by the dotted line A3-A4 is also a cross-sectional diagram of the transistor MN.

[0559] Figures 28A to 28C The transistor MN includes, for example, insulating layers IS1 to IS3, insulating layer GI1, conductive layer ME2a, conductive layer ME2b, conductive layer ME3, and semiconductor layer SC1.

[0560] Note that regarding Figures 28A to 28C Each of the insulating layers IS1 to IS3, insulating layer GI1, conductive layer ME3, and semiconductor layer SC1 shown can be referred to Figures 27A to 27C Explanation of insulating layers IS1 to IS3, insulating layer GI1, conductive layer ME3, and semiconductor layer SC1. Regarding... Figures 28A to 28C The conductive layers ME2a and ME2b shown can be referenced. Figures 27A to 27C Explanation of the conductive layer ME2 shown.

[0561] The insulating layer IS2, for example, functions as an insulating layer for forming the semiconductor layer SC1. Figures 28A to 28C As shown, the insulating layer IS2 includes an opening KK2, and the transistor MN has a structure in which a portion of the semiconductor layer SC1 is included in the opening KK2. Specifically, the opening KK2 is provided in the insulating layer IS2 such that the semiconductor layer SC1 contacts the sidewall of the insulating layer IS2 corresponding to the side of the opening KK2 and the top surface of the insulating layer IS1 corresponding to the bottom of the opening KK2. Furthermore, the transistor MN has a structure in which the semiconductor layer SC1 disposed inside the opening KK2 includes the channel forming region of the transistor MN.

[0562] Note that in Figure 28A In the top view, the shape of the opening KK2 is, for example, a perfect circle, but one aspect of the invention is not limited to this. The shape of the opening KK2 can be, for example, a shape with a single closed curve as its edge (including an ellipse), or a polygon with rounded corners.

[0563] The conductive layer ME2a functions, for example, as one of the source and drain electrodes of the transistor MN. Similarly, the conductive layer ME2b functions, for example, as the other of the source and drain electrodes of the transistor MN. Note that all or part of the conductive layers ME2a and ME2b are sometimes referred to as electrodes, terminals, wiring, etc.

[0564] Both conductive layers ME2a and ME2b are located above the insulating layer IS2. In particular, in Figure 28A Top view diagram and Figure 28B In the cross-sectional diagram, conductive layers ME2a and ME2b are separated into a pair of conductive layers by opening KK2. Therefore, in Figures 28A to 28C In transistor MN, in Figure 28A In the top view, the widths of conductive layers ME2a and ME2b in the Y direction are preferably shorter than the width of opening KK2 in the Y direction. Note that in Figure 28A In the top view diagram, for example, if the opening KK2 is a perfect circle, the width of the opening KK2 in the Y direction can be the diameter of its perfect circle.

[0565] Note that in Figures 28A to 28C In this circuit, conductor ME2a extends in the -X direction, for example, as a wiring. Furthermore, conductor ME2b extends in the +X direction, for example, as a wiring.

[0566] Furthermore, as described above, the semiconductor layer SC1 has a region that contacts the sidewall of the insulating layer IS2 corresponding to the side of the opening KK2 and the top surface of the insulating layer IS1 corresponding to the bottom of the opening KK2. Also, the semiconductor layer SC1 has a region that contacts the top surfaces of the conductive layers ME2a and ME2b. Furthermore, as described above, the semiconductor layer SC1 includes a channel formation region for the transistor MN. Additionally, the channel length CHL of the channel formation region for the transistor MN is determined based on the area of ​​the bottom of the opening KK2 and the depth of the opening KK2 (the length of the side of the opening KK2 or the thickness of the insulating layer IS2).

[0567] Additionally, the insulating layer GI1 functions, for example, as the gate insulating layer (sometimes called the gate insulating film) of the transistor MN. The insulating layer GI1 has regions that contact the top surface of the semiconductor layer SC1, the top surface of the conductor ME2a, and the top surface of the conductor ME2b.

[0568] In particular, the thickness of the insulating layer GI1 has a significant impact on the electrical characteristics of the transistor MN. For example, a larger thickness of the insulating layer GI1 (resulting in a larger thickness of the gate insulating layer of transistor MN) can smooth the voltage gradient between the gate (conductor ME3) of transistor MN and the channel formation region of the semiconductor layer SC1, thus improving the tolerance to the gate potential (sometimes referred to as the gate-source voltage or gate-drain voltage). On the other hand, a smaller thickness of the gate insulating film of the transistor allows for a faster change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed, thus allowing for a higher driving frequency of the transistor.

[0569] Therefore, for example, in multiple transistors MN, by determining the thickness of the insulating layer GI1, which serves as the gate insulating layer, for each transistor MN, it is easy to form transistors with high gate potential tolerance and transistors with high drive frequency, respectively.

[0570] exist Figure 26 An insulating layer 574 is formed above the transistors MNy and MNx, and an insulating layer 581 is formed on the insulating layer 574. Furthermore, openings are provided in the insulating layers MNy, MNy, MNx, and MNx, into which a conductive layer MPG is embedded. Therefore, the conductive layer ME2 has a region in contact with the conductive layer MPG.

[0571] The insulating layer 574 preferably has the function of inhibiting the diffusion of impurities such as water and hydrogen (e.g., one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film to inhibit the incorporation of such impurities into the transistor MN. Furthermore, the insulating layer 574 preferably has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layers IS3 and 581. In other words, the insulating layer 574 preferably has the function of inhibiting oxygen from detaching from the semiconductor layer SC1 and diffusing above the insulating layer IS3.

[0572] As a hydrogen-barrier membrane, silicon nitride formed by CVD can be used, for example.

[0573] The amount of hydrogen removed can be analyzed, for example, using thermal desorption spectrometry (TDS). For instance, in the TDS analysis, where the membrane surface temperature is in the range of 50°C to 500°C, when converting the amount of hydrogen removed (converted to hydrogen atoms) to the amount per unit area of ​​the insulating layer 324, the preferred amount of hydrogen removed from the insulating layer 324 is 10 × 10⁻⁶. 15 atoms / cm 2 The following is more preferably 5×10 15 atoms / cm2 the following.

[0574] Therefore, the insulating layer 574, as an insulator that suppresses the permeation of impurities such as water and hydrogen, as well as oxygen, can be, for example, a single layer or a stack of insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of metal oxides that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Additionally, examples of oxides containing aluminum and hafnium (hafnium aluminate) can be used as insulators that suppress the permeation of impurities such as water and hydrogen, as well as oxygen. Furthermore, examples of nitrides that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include aluminum nitride, silicon oxynitride, and silicon nitride.

[0575] Particularly preferred is the use of aluminum oxide or silicon nitride as the insulating layer 574. This suppresses the diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MN side. Furthermore, it suppresses the diffusion of oxygen from above the insulating layer 574 to the transistor MN side.

[0576] The dielectric constant of insulating layer 581 is preferably lower than that of insulating layer 574. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Furthermore, the concentration of impurities such as water and hydrogen in insulating layer 581 is preferably reduced.

[0577] Therefore, insulating layer 581 may, for example, use a material that can be used for any one of insulating layers IS1 to insulating layer IS3.

[0578] As materials for the plugs and wiring (e.g., the conductive layer MPG), single layers or stacks of conductive materials selected from one or more of metallic materials, alloy materials, metal nitride materials, and metal oxide materials can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Furthermore, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0579] Insulating layer 592 and insulating layer 594 are sequentially stacked on insulating layer 581 and conductive layer MPG.

[0580] Furthermore, the insulating layer 592 preferably uses a barrier insulating film (also referred to as a barrier insulating film) that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor MN to the region above the insulating layer 592 (e.g., the region where light-emitting devices 130R, 130G, and 130B are disposed). Therefore, the insulating layer 592 can, for example, use any of the materials that can be used in the insulating layers IS1 to IS3.

[0581] Furthermore, the dielectric constant of insulating layer 594 is preferably lower than that of insulating layer 592. Additionally, the concentration of impurities such as water and hydrogen in insulating layer 594 is preferably reduced. Therefore, insulating layer 594 can, for example, use a material that is also suitable for insulating layer 574.

[0582] Furthermore, insulating layers 592 and 594 have embedded conductive layers 596 that connect to light-emitting devices or the like disposed above insulating layer 594. Additionally, conductive layer 596 functions as a plug or wiring. Note that sometimes the same symbol is used to denote multiple conductors used as plugs or wiring. Furthermore, in this specification, wiring and plugs connected to wiring can also be considered as a single component. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0583] The conductive layer 596 can, for example, be made of a material that can be used for the conductive layer MPG.

[0584] Insulating layer 598 and insulating layer 599 are sequentially formed on insulating layer 594 and conductive layer 596.

[0585] For example, similar to insulating layers 581 and 592, insulating layer 598 preferably uses an insulating layer having barrier properties for one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594, insulating layer 599 preferably uses an insulator with a relatively low permittivity to reduce parasitic capacitance generated between wirings. Therefore, insulating layer 598 can use materials that are also suitable for insulating layers 581 or 592.

[0586] Insulating layer 599 functions as an interlayer insulating film and a planarization film.

[0587] Furthermore, the dielectric constant of insulating layer 599 is preferably lower than that of insulating layer 598. In addition, the concentration of impurities such as water and hydrogen in insulating layer 599 is preferably reduced. Therefore, insulating layer 599 can, for example, be made of a material suitable for any one of insulating layers IS1 to IS3.

[0588] A light-emitting device 130 and a connecting portion 140 are formed on the insulating layer 599.

[0589] The connecting portion 140, sometimes referred to as the cathode contact portion, is connected to the respective cathode electrodes of the light-emitting devices 130R, 130G, and 130B. Figure 26 In the connection portion 140, there are: one or more conductive layers selected from conductive layers 112a to 112c described later; at least one conductive layer selected from conductive layers 126a to 126c described later; one or more conductive layers selected from conductive layers 129a to 129c described later; a common layer 114 described later; and a common electrode 115 described later.

[0590] Note that the connecting portion 140 can be arranged either around the four sides of the display unit when viewed from above, or it can be arranged inside the display unit (for example, between adjacent light-emitting devices 130).

[0591] Light-emitting device 130R includes a conductive layer 112a, a conductive layer 126a on the conductive layer 112a, and a conductive layer 129a on the conductive layer 126a. The conductive layers 112a, 126a, and 129a can all be referred to as pixel electrodes, or a portion of the conductive layers 112a, 126a, and 129a can be referred to as pixel electrodes. Similarly, light-emitting device 130G includes a conductive layer 112b, a conductive layer 126b on the conductive layer 112b, and a conductive layer 129b on the conductive layer 126b. Like light-emitting device 130R, the conductive layers 112b, 126b, and 129b can all be referred to as pixel electrodes, or a portion of the conductive layers 112b, 126b, and 129b can be referred to as pixel electrodes. Additionally, the light-emitting device 130B includes a conductive layer 112c, a conductive layer 126c on the conductive layer 112c, and a conductive layer 129c on the conductive layer 126c. Similar to light-emitting devices 130R and 130G, the conductive layers 112c, 126c, and 129c can all be referred to as pixel electrodes, or a portion of the conductive layers 112c, 126c, and 129c can be referred to as a pixel electrode.

[0592] As conductive layers 112a to 112c and 126a to 126c, conductive layers used as reflective electrodes can be used, for example. As conductive layers used as reflective electrodes, conductors with high reflectivity to visible light can be used, such as silver, aluminum, or an alloy film composed of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Alternatively, conductive layers 112a to 112c and 126a to 126c can be, for example, a laminated film of aluminum sandwiched between a pair of titanium atoms (a film sequentially laminated with Ti, Al, and Ti), or a laminated film of silver sandwiched between a pair of indium tin oxide atoms (a film sequentially laminated with ITO, Ag, and ITO).

[0593] Alternatively, conductive layers serving as reflective electrodes can be used as conductive layers 112a to 112c, and highly transparent conductors can be used as conductive layers 126a to 126c. Examples of highly transparent conductors include indium tin oxide (sometimes called ITO). Furthermore, as conductive layers 126a to 126c, any thin film with a thickness sufficient for light transmission can be used, such as an alloy of silver and magnesium.

[0594] As conductive layers 129a to 129c, conductive layers used as transparent electrodes can be used, for example. As conductive layers used as transparent electrodes, the aforementioned conductive material with high light transmittance can be used, for example.

[0595] The conductive layer 112a is connected to the conductive layer 596 embedded in the insulating layer 594 through an opening provided in the insulating layer 599. The end of the conductive layer 112a is located outside the end of the conductive layer 126a. The end of the conductive layer 126a is aligned or substantially aligned with the end of the conductive layer 129a.

[0596] The conductive layers 112b, 126b, and 129b in the light-emitting device 130G, and the conductive layers 112c, 126c, and 129c in the light-emitting device 130B, are the same as the conductive layers 112a, 126a, and 129a in the light-emitting device 130R, so detailed descriptions are omitted.

[0597] Recesses are formed in conductive layers 112a, 112b, and 112c to cover openings in insulating layer 599. Layer 128 is embedded in these recesses.

[0598] Layer 128 has the function of planarizing the recesses of conductive layers 112a to 112c. Conductive layers 126a to 126c, respectively in contact with conductive layers 112a to 112c, are provided on both conductive layers 112a to 112c and layer 128. Therefore, the area overlapping the recesses of conductive layers 112a to 112c can also be used as a light-emitting area, thereby improving the pixel aperture ratio.

[0599] Layer 128 can also be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be appropriately used for layer 128. In particular, layer 128 is preferably formed using an insulating material.

[0600] As layer 128, an insulating layer containing organic materials can be appropriately used. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as layer 128. Alternatively, a photosensitive resin can also be used as layer 128. Examples of photosensitive resins include positive and negative materials.

[0601] By using a photosensitive resin, layer 128 can be manufactured through only exposure and development processes, reducing the impact of dry or wet etching on the surfaces of conductive layers 112a, 112b, and 112c. Furthermore, by using a negative photosensitive resin to form layer 128, it is sometimes possible to use the same photomask forming layer 128 as the photomask (exposure mask) used when forming the opening of insulating layer 599.

[0602] Although Figure 26 An example is shown where the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. For example... Figure 29A As shown, when viewed in cross-section, the top surface of layer 128 can also have a concave curved surface in and around the center. Alternatively, as... Figure 29B As shown, when viewed in cross-section, layer 128 can also have a shape with a convex curved surface in and around its central portion. Additionally, as... Figure 29C As shown, layer 128 can also have a shape with concave and convex surfaces in the central part and its vicinity.

[0603] Light-emitting device 130R includes a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G includes a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B includes a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0604] Furthermore, the first layer 113a is formed to cover the top and side surfaces of the conductive layer 126a and the top and side surfaces of the conductive layer 129a. Similarly, the second layer 113b is formed to cover the top and side surfaces of the conductive layer 126b and the top and side surfaces of the conductive layer 129b. Likewise, the third layer 113c is formed to cover the top and side surfaces of the conductive layer 126c and the top and side surfaces of the conductive layer 129c. Therefore, the entire area where the conductive layers 126a, 126b, and 126c are disposed can be used as the light-emitting area of ​​the light-emitting devices 130R, 130G, and 130B, thereby improving the pixel aperture ratio.

[0605] In light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as the EL layer. Similarly, in light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as the EL layer. Likewise, in light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as the EL layer.

[0606] There are no particular restrictions on the structure of the light-emitting device in this embodiment; a single structure or a series structure can be used.

[0607] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island shapes using photolithography. Therefore, the angle formed between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c is approximately 90°. On the other hand, for example, organic films formed using FMM (Fine Metal Mask) tend to thin closer to the ends; for example, their top surface is formed in a sloping shape in the range of 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0608] The top and side surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are clearly distinguishable. Therefore, in adjacent first layers 113a and second layers 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are opposite each other. The same applies to any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0609] The first layer 113a, the second layer 113b, and the third layer 113c each include at least a light-emitting layer. For example, preferably, the first layer 113a, the second layer 113b, and the third layer 113c each include a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light. In addition, the light-emitting layers may be cyan, magenta, yellow, or white, in addition to the colors mentioned above.

[0610] The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Because the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are sometimes exposed during the manufacturing process of the display device, providing a carrier transport layer on the light-emitting layer can suppress the light-emitting layer from being exposed to the outermost surface, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting device.

[0611] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include either a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. Light-emitting devices 130R, 130G, and 130B collectively include the common layer 114.

[0612] Light-emitting devices 130R, 130G, and 130B collectively include a common electrode 115. Additionally, as... Figure 26 As shown, the common electrode 115, which is shared by multiple light-emitting devices, is in contact with the conductor in the connection portion 140.

[0613] The insulating layer 125 preferably functions as a barrier insulating layer against one or both of water and oxygen. Additionally, the insulating layer 125 preferably functions as a suppressor of the diffusion of one or both of water and oxygen. Furthermore, the insulating layer 125 preferably functions as a trap or fixator (also known as gettering) of one or both of water and oxygen. When the insulating layer 125 functions as a barrier insulating layer or as a gettering layer, the entry of impurities (typically one or both of water and oxygen) that might diffuse from the outside into each light-emitting device can be suppressed. By employing this structure, a highly reliable light-emitting device and a highly reliable display panel can be provided.

[0614] Furthermore, the impurity concentration in the insulating layer 125 is preferably low. This prevents impurities from mixing into the EL layer from the insulating layer 125 and causing EL layer degradation. Additionally, by reducing the impurity concentration in the insulating layer 125, the barrier properties against one or both of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and carbon concentration in the insulating layer 125 is sufficiently low, and preferably both the hydrogen concentration and carbon concentration are sufficiently low.

[0615] As the insulating layer 127, an insulating layer containing organic materials can be suitable. As the organic material, a photosensitive organic resin is preferred; for example, a photosensitive resin composition containing acrylic resin can be used. Furthermore, the viscosity of the material of the insulating layer 127 is preferably 1 cP or more and 1500 cP or less, more preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulating layer 127 within the above range, it is easier to form the insulating layer 127 with the cone shape described later. Note that in this specification, acrylic resin does not refer only to polymethyl methacrylate or methacrylic resin, but sometimes also to acrylic polymers in a broader sense.

[0616] Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface. For example, it is preferable to have a region where the angle (also called the cone angle) formed by the inclined side surface and the substrate surface is less than 90°.

[0617] Note that, as described later, the insulating layer 127 only needs to have a tapered shape on its sides, and the organic materials that can be used for the insulating layer 127 are not limited to the materials mentioned above. For example, sometimes acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as the insulating layer 127. In addition, sometimes polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin and other organic materials can be used as the insulating layer 127. Furthermore, photoresist can sometimes be used as the photosensitive resin as the insulating layer 127. Positive or negative materials can be cited as examples of photosensitive resins.

[0618] The insulating layer 127 can also be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting device through the insulating layer 127, light leakage (stray light) from the light-emitting device to adjacent light-emitting devices can be suppressed. This improves the display quality of the display panel. Furthermore, the display quality can be improved even without using a polarizer in the display panel, thus enabling the display panel to be lightweight and thin.

[0619] Examples of materials that absorb visible light include pigments such as black, dyes, light-absorbing resins (e.g., polyimide), and resins suitable for use in color filters (color filter materials). In particular, resin materials formed by mixing or layering two or more colors of color filter materials are preferred as they improve the effect of blocking visible light. Especially, by mixing three or more colors of color filter materials, a black or near-black resin layer can be achieved.

[0620] The insulating layer 127 can be formed, for example, by wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor blade coating, slot coating, roller coating, curtain coating, and doctor blade coating. In particular, the organic insulating film that will become the insulating layer 127 is preferably formed by spin coating.

[0621] The insulating layer 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature during the formation of the insulating layer 127 is typically below 200°C, preferably below 180°C, more preferably below 160°C, further preferably below 150°C, and even more preferably below 140°C.

[0622] The structure of the insulating layer 127 between light-emitting devices 130R and 130G will be described below as an example. The insulating layer 127 between light-emitting devices 130G and 130B, and between light-emitting devices 130B and 130R, are also the same. Furthermore, the end of the insulating layer 127 on the second layer 113b will sometimes be used as an example in the following description; the ends of the insulating layer 127 on the first layer 113a and the third layer 113c are also the same.

[0623] Preferably, when the display device is viewed in cross-section, the insulating layer 127 has a tapered shape with a cone angle θ1 on its side. The cone angle θ1 is the angle formed between the side surface of the insulating layer 127 and the substrate surface. Note that it is not limited to the substrate surface; the cone angle θ1 can also be the angle formed between the top surface of the flat portion of the insulating layer 125 or the top surface of the flat portion of the second layer 113b and the side surface of the insulating layer 127. In addition, by making the side surface of the insulating layer 127 have a tapered shape, the side surface of the insulating layer 125 and the side surface of the mask layer 118a may also have a tapered shape.

[0624] The cone angle θ1 of the insulating layer 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By giving the side end of the insulating layer 127 this positive cone shape, high coverage deposition can be achieved without breakage or localized thinning in the common layer 114 and common electrode 115 provided on the side end of the insulating layer 127. As a result, the in-plane uniformity of the common layer 114 and common electrode 115 can be improved, thereby improving the display quality of the display device.

[0625] Furthermore, in the cross-sectional view of the display device, the top surface of the insulating layer 127 preferably has a convex curved shape. The convex curved shape of the top surface of the insulating layer 127 is preferably a shape that gently protrudes towards the center. Additionally, it is preferable that the convex curved portion at the center of the top surface of the insulating layer 127 smoothly connects to the tapered portion at the side end. By adopting the above shape as the insulating layer 127, the common layer 114 and the common electrode 115 can be deposited with high coverage over the entire top surface of the insulating layer 127.

[0626] Additionally, an insulating layer 127 is formed in the region between two EL layers (e.g., the region between the first layer 113a and the second layer 113b). In this case, a portion of the insulating layer 127 is sandwiched between the side end of one EL layer (e.g., the first layer 113a) and the side end of the other EL layer (e.g., the second layer 113b).

[0627] Furthermore, preferably, one end of the insulating layer 127 overlaps with the conductive layer 126a used as a pixel electrode, and the other end of the insulating layer 127 overlaps with the conductive layer 126b used as a pixel electrode. By employing the above structure, the end of the insulating layer 127 can be formed on a generally flat area of ​​the first layer 113a (second layer 113b). Therefore, it is relatively easy to process the insulating layer 127 into a tapered shape as described above.

[0628] As described above, by providing the insulating layer 127, it is possible to prevent the formation of disconnections and locally thinned portions in the common layer 114 and common electrode 115 from the generally flat area of ​​the first layer 113a to the generally flat area of ​​the second layer 113b. Therefore, it is possible to suppress poor connections caused by disconnections and resistance increases caused by locally thinner portions in the common layer 114 and common electrode 115 between each light-emitting device.

[0629] In the display device of this embodiment, the distance between light-emitting devices can be reduced. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be reduced to less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is less than 1 μm, preferably a region where the distance is less than 0.5 μm (500 nm), and more preferably a region where the distance is less than 100 nm. By reducing the distance between each light-emitting device as described above, a display device with high definition and high aperture ratio can be provided.

[0630] A protective layer 131 is provided on the light-emitting device 130. The protective layer 131 serves as a passivation film to protect the light-emitting device 130. By providing the protective layer 131 covering the light-emitting device, impurities such as water and oxygen can be prevented from entering the light-emitting device, thereby improving the reliability of the light-emitting device 130. As the protective layer 131, for example, aluminum oxide, silicon nitride, or silicon oxynitride can be used.

[0631] The protective layer 131 and the substrate 110 are bonded together by the adhesive layer 107. The light-emitting device can be sealed using a solid sealing structure or a hollow sealing structure, etc. Figure 26In this configuration, the space between substrate 310 and substrate 110 is filled with adhesive layer 107, thus employing a solid sealing structure. Alternatively, a hollow sealing structure can be used, where the space is filled with an inactive gas (such as nitrogen or argon). In this case, adhesive layer 107 can also be arranged in a manner that does not overlap with the light-emitting device. Furthermore, a resin different from that used for the frame-shaped adhesive layer 107 can be used to fill the space.

[0632] As the adhesive layer 107, various curing adhesives such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, or anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability, such as epoxy resins, are preferred. Furthermore, two-component mixed resins can also be used. Additionally, adhesive sheets can also be used.

[0633] The display device DSP1A has a top-emitting structure. The light-emitting device emits light onto one side of the substrate 110. Therefore, the substrate 110 is preferably made of a material with high transmittance to visible light. For example, as the substrate 110, a substrate with high transmittance to visible light, which can be used in both the substrate 310 and the substrate BS, is preferably selected. Note that the pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that allows visible light to pass through.

[0634] Note that, in one embodiment of the present invention, the display device may also employ a bottom-emitting structure in which the light emitted by the light-emitting device is projected onto one side of the substrate 310, instead of a top-emitting structure. In this case, the substrate 310 is preferably selected as a substrate with high transmittance to visible light.

[0635] Next, an explanation and Figure 26 The display device DSP1A has different cross-sections when viewed. Figure 24A The diagram shows an example of the structure of the display device DSP1.

[0636] Figure 30 The display device DSP1B shown is from Figure 24A The shown diagram is a cross-sectional view of the display device DSP1, which is a structural example of a display device including a transmissive liquid crystal element (sometimes referred to as a liquid crystal display device).

[0637] The display device DSP1B includes substrates 310 and 610, and pixel circuits and driving circuits including liquid crystal elements are sandwiched between substrates 310 and 610.

[0638] The display device DSP1B can display an image, for example, by passing light from a backlight (not shown) that serves as a light source through liquid crystal elements 613a to 613c, which will be described later. Therefore, substrates 310 and 610 are preferably made of materials suitable for use with liquid crystal elements 613a to 613c. Figure 26 The substrate 310 of the described display device DSP1A is a substrate with high visible light transmittance.

[0639] exist Figure 30 In the above, the liquid crystal element 613a, which serves as a display element, includes a conductive layer 112a serving as a first electrode, a conductive layer 631 serving as a second electrode, and a liquid crystal layer 608. Similarly, the liquid crystal element 613b includes a conductive layer 112b serving as a first electrode, a conductive layer 631 serving as a second electrode, and a liquid crystal layer 608, and also includes a conductive layer 112c serving as a first electrode, a conductive layer 631 serving as a second electrode, and a liquid crystal layer 608.

[0640] Note that from now on, liquid crystal elements 613a to 613c will be collectively referred to as liquid crystal element 613.

[0641] Additionally, the display device DSP1B has insulating layers 632 and 633, which serve as alignment films, sandwiching the liquid crystal layer 608. A conductive layer 631 is disposed on one side of the substrate 610, and conductive layers 112a to 112c overlap with the conductive layer 631 across the liquid crystal layer 608. Furthermore, the liquid crystal layer 608 is sealed with a sealant 605 that functions to bond one side of the substrate 310 to the other side of the substrate 610. Transistors MNx disposed in the display area DIS are connected to the liquid crystal element 613.

[0642] Conductive layers 112a to 112c and conductive layer 631 are preferably made of a conductive material that allows visible light to pass through. As such a conductive material, for example, a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn) can be used. Specifically, examples include indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, and zinc oxide containing gallium. Alternatively, conductive layers 112a to 112c and conductive layer 631 can be made of a graphene-containing film. The graphene-containing film can be formed, for example, by reducing a graphene oxide-containing film formed on a film of an insulator or conductor.

[0643] In addition, as Figure 26In the display device DSP1A and the transistor MN of FIG27, each of the insulating layers IS1 to IS3, insulating layer GI1, conductive layers ME1 to ME3, semiconductor layer SC1, insulating layer 574, insulating layer 581, insulating layer 592, insulating layer 594, insulating layer 598, insulating layer 599, conductive layer 596 and conductive layer MPG is preferably made of a material with high light transmittance so that light serving as a backlight (not shown) can pass through.

[0644] As the liquid crystal element 613, for example, a liquid crystal element applying the FFS (Fringe Field Switching) mode can be used. Furthermore, generally speaking, as liquid crystal materials, there are positive liquid crystal materials with a positive dielectric anisotropy (Δε) and negative liquid crystal materials with a negative anisotropy. Both of these materials can be used as the liquid crystal element 613 shown in this embodiment, and the most suitable liquid crystal material can be selected depending on the mode and design used.

[0645] In the display device shown in this embodiment, a negative liquid crystal material is preferably used. In negative liquid crystals, the flexural effect caused by the polarization of liquid crystal molecules can be suppressed, therefore the polarity has almost no impact on transmittance. Thus, flickering as perceived by the user of the display device can be suppressed. The flexural effect refers to the phenomenon of polarization primarily caused by molecular shape and due to orientation distortion. In negative liquid crystal materials, orientation distortions such as stretching and bending deformations are less likely to occur.

[0646] Here, while the liquid crystal element 613 uses the FFS mode, the present invention is not limited to this, and liquid crystal elements of various modes can be used. For example, liquid crystal elements using VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, VA-IPS (Vertical Alignment In-Plane-Switching) mode, guest-host mode, etc., can be used.

[0647] Alternatively, a normally black liquid crystal display device, such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode, can be used for the display device shown in this embodiment. As the vertical alignment mode, MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), ASV (Advanced Super View), and other similar modes can be used.

[0648] Liquid crystal elements (LCDs) are devices that utilize the optical modulation effect of liquid crystals to control the transmission or blocking of light. The optical modulation effect of liquid crystals is controlled by the electric field (horizontal, vertical, or tilted) applied to the liquid crystal. Liquid crystals used in LCD elements can include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, and isotropic phases depending on the conditions.

[0649] Although Figure 30An example of a display device including a liquid crystal element in a vertical electric field manner is shown, but a display device including a liquid crystal element in a horizontal electric field manner can also be used in one aspect of the present invention. In the case of using a horizontal electric field manner, a liquid crystal exhibiting a blue phase without an alignment film can also be used. The blue phase is a type of liquid crystal phase, referring to the phase that appears just before the cholesteric liquid crystal transitions to an isotropic phase when the temperature is raised. Since the blue phase only appears within a narrow temperature range, a liquid crystal composition containing 5 wt% or more of a chiral reagent is used in the liquid crystal layer 608 to improve the temperature range. The liquid crystal composition containing the liquid crystal exhibiting a blue phase and the chiral reagent has a fast response speed and is optically isotropic. Furthermore, the liquid crystal composition containing the liquid crystal exhibiting a blue phase and the chiral reagent does not require alignment processing and has low viewing angle dependence. Additionally, since no alignment film is required and no rubbing process is needed, electrostatic breakdown caused by rubbing processing can be prevented, and defects and damage to the liquid crystal display device during the manufacturing process can be reduced.

[0650] The spacer 635 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the spacing (cell gap) between conductive layers 112a to 112c and conductive layer 631. Note that spherical spacers can also be used.

[0651] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing component, a phase difference component, and an anti-reflection component can be appropriately provided as needed. For example, circular polarization utilizing a polarizing substrate and a phase difference substrate can also be used. Additionally, backlight units or sidelight units (not shown) can be used as light sources. Miniature LEDs can also be used as the aforementioned backlight units and sidelight units. Figure 30 In the display device DSP1B, for example, it may have the following structure (not shown): polarizing substrates are provided on both the surface side of the substrate 610 (the side opposite to the side where the color layer 666R, color layer 666G, color layer 666B and light-shielding layer 642 are provided) and the back side side of the substrate 310 (the side opposite to the side where the transistors MNx and MNy are provided), and a backlight unit is provided on the back side side of the substrate 310 across the polarizing substrates.

[0652] exist Figure 30 In the display device shown, a light-shielding layer 642, a coloring layer 666R, a coloring layer 666G, a coloring layer 666B and an insulating layer 641 are disposed between the substrate 610 and the conductive layer 631.

[0653] Examples of materials that can be used for the light-shielding layer 642 include carbon black, titanium black, metals, metal oxides, or composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film of an inorganic material such as a metal. Furthermore, the light-shielding layer 642 can also be a laminated film containing the material of any one of the coloring layers 666R to 666B. For example, a laminated structure can be used consisting of a film containing the material of coloring layer 666R for transmitting a certain color of light and a film containing the material of coloring layer 666G for transmitting other colors of light. By using the same material for coloring layers 666R to 666B as for the light-shielding layer 642, not only can the same equipment be used, but the process can also be simplified, which is therefore preferable.

[0654] Examples of materials that can be used for coloring layers 666R to 666B include metallic materials, resin materials, and resin materials containing pigments or dyes. The methods for forming the light-shielding layer and the coloring layer can be the same as those for forming the aforementioned layers. For example, inkjet printing can be used.

[0655] The insulating layer 641 is preferably a protective layer with a planarization function. By having a planarization function, a flat insulating film can be formed on the formation surfaces of the coloring layers 666R to 666B and the light-shielding layer 642, which have different thicknesses. By planarizing the insulating layer 641, the conductive layer 631 can be formed flat, thus reducing the unevenness of the thickness of the liquid crystal layer 608. Examples of such an insulating layer 641 include acrylic resin.

[0656] <Example 2 of cross-sectional structure of display device> Next, it will be explained when viewed from the cross-section. Figure 24B The diagram shows an example of the structure of the display device DSP2.

[0657] Figure 31 The display device DSP2A shown is viewed in cross-section. Figure 24B The diagram shows an example of the structure of the display device DSP2A. In the display device DSP2A, pixel circuits, driving circuits, etc., are disposed on the substrate 310. Figure 31 In the display device DSP2A, besides Figure 24B In addition to the circuit area SIC and the display area DIS shown, the wiring area LIN is also shown.

[0658] For example, the circuit region SIC includes a substrate 310 on which a transistor 300d is formed. Furthermore, a wiring region LIN is provided above the transistor 300d, and the wiring region LIN has wiring for connecting the transistor 300d, the transistor 500x (described later), and the light-emitting device 130R, light-emitting device 130G, or light-emitting device 130B. Additionally, a display region DIS is provided above the wiring region LIN, and the display region DIS includes, for example, the transistor 500x and the light-emitting device 130(…). Figure 31 Among them, light-emitting devices 130R, 130G and 130B, etc.

[0659] That is to say, transistor 300d can be a transistor in the circuit region SIC. Furthermore, transistor 500x can be a transistor in the pixel circuit PX. Additionally, the light-emitting device 130 can also be a light-emitting device included in the pixel circuit PX.

[0660] Additionally, regarding the light-emitting device 130 located above transistor 500x ( Figure 31 The light-emitting devices 130R, 130G, and 130B mentioned above can be referred to... Figure 26 Description of the light-emitting device 130.

[0661] As substrate 310, for example, a substrate suitable for substrate BS can be used. In this embodiment, the case where substrate 310 is a semiconductor substrate containing silicon as a material is described. Therefore, the transistor in the circuit region SIC can be a Si transistor. For example, as a Si transistor, a transistor containing monocrystalline silicon in the channel formation region or a transistor containing low-temperature polycrystalline silicon (LTPS) in the channel formation region can be cited.

[0662] Therefore, the structure of the transistor 300d formed on the substrate 310 is similar to... Figure 26 The transistors MNx and MNy shown are different. Note that in... Figure 31 In the display device DSP2A, the transistors included in the circuit region SIC can also be Figure 26 The transistors MNx and MNy are shown. In this case, the substrate 310 is preferably a glass substrate.

[0663] For information regarding the screen ratio (aspect ratio) of the DSP2A display device, please refer to the description of the screen ratio of the DSP1A display device. Additionally, for information regarding the diagonal dimensions of the DSP2A display device, please refer to the description of the diagonal dimensions of the DSP1A display device.

[0664] Transistor 300d includes a device separation layer 312, a conductive layer 316, an insulating layer 315, an insulating layer 317, a semiconductor region 313 formed by a portion of a substrate 310, and low-resistance regions 314a and 314b serving as source or drain regions. Therefore, transistor 300d is a Si transistor. Note that... Figure 31 The diagram illustrates a structure in which one of the source and drain terminals of transistor 300d is connected to conductive layers 330 and 356 (described later) via conductive layer 328. However, the connection structure of a display device according to one embodiment of the present invention is not limited to this. For example, a display device according to one embodiment of the present invention may also employ a structure in which the gate terminal of transistor 300d is connected to conductive layer 328.

[0665] Transistor 300d can be implemented as a fin structure, for example, by employing a structure in which the top surface of semiconductor region 313 and the side surfaces in the channel width direction are covered by a conductive layer 316 with an insulating layer 315 serving as a gate insulator. By forming a fin transistor 300d, the effective channel width can be increased, thus improving the on-state characteristics of transistor 300d. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of transistor 300d can be improved. Alternatively, transistor 300d can also have a planar structure without a fin structure.

[0666] Transistor 300d can be either a p-channel transistor or an n-channel transistor. Alternatively, multiple transistors 300d can be configured, using both p-channel and n-channel transistors.

[0667] The channel formation region of semiconductor region 313, the region theren, and the low-resistance regions 314a and 314b used as source or drain regions preferably comprise silicon-based semiconductors, and more specifically, preferably monocrystalline silicon. Alternatively, the aforementioned regions may also be formed using germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. Silicon with effective quality controlled by applying stress to the crystal lattice to change the interplanar spacing can be used. Alternatively, transistor 300d may also be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0668] As the conductive layer 316 used as the gate electrode, a semiconductor material such as silicon containing elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductive layer 316, conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0669] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, titanium nitride and tantalum nitride, or both, are preferably used as the conductor. In order to achieve both conductivity and embeddability, a stack of metal materials, or both, of tungsten and aluminum, is preferably used as the conductor, especially tungsten, which is preferred in terms of heat resistance.

[0670] To separate the multiple transistors formed on the substrate 310 from each other, a device separation layer 312 is provided. The device separation layer can be formed, for example, using LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation method.

[0671] Fi...

Claims

1. A semiconductor device, comprising: First transistor; Second transistor; as well as The third transistor, The first transistor, the second transistor, and the third transistor all contain oxide semiconductors in the channel formation region. The first transistor includes a back gate. The back gate of the first transistor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. The gate of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the second wiring. The first wiring is input with either a high-level potential or a low-level potential. The second wiring is input to either the high-level potential or the low-level potential. The other of the source and drain terminals of the second transistor is input with the high-level potential. Furthermore, the other of the source and drain terminals of the third transistor is input with a potential less than 0V.

2. The semiconductor device according to claim 1, The oxide semiconductor comprises one or more selected from indium, zinc, and element M. Furthermore, the element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

3. A semiconductor device, comprising: Drive transistors; First transistor; Second transistor; Third transistor; First capacitor; as well as Light-emitting devices The driving transistor, the first transistor, the second transistor, and the third transistor all contain oxide semiconductors in the channel formation region. The first transistor includes a back gate. The back gate of the first transistor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. The gate of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the second wiring. One of the source and drain terminals of the first transistor is electrically connected to the gate of the driving transistor and the first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to the second terminal of the first capacitor and one of the anode and cathode of the light-emitting device.

4. A semiconductor device, comprising: Drive transistors; First transistor; Second transistor; Third transistor; Fourth transistor; First capacitor; as well as Light-emitting devices; The driving transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor all contain oxide semiconductors in the channel formation region. Both the first transistor and the fourth transistor include a back gate. The back gate of the first transistor and the back gate of the fourth transistor are electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. The gate of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the first wiring. The gate of the fourth transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the second wiring. One of the source and drain terminals of the first transistor is electrically connected to the gate of the driving transistor and the first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to the second terminal of the first capacitor, one of the anode and cathode of the light-emitting device, and one of the source and drain of the fourth transistor.

5. The semiconductor device according to claim 3 or 4, The light-emitting device described herein contains organic EL material.

6. The semiconductor device according to claim 5, The oxide semiconductor comprises one or more selected from indium, zinc, and element M. Furthermore, the element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

7. A display device, comprising: The semiconductor device according to claim 6; First driving circuit; as well as Second driving circuit, The first driving circuit has the function of sending the image signal to the other of the source and drain of the first transistor. Furthermore, the second driving circuit has the function of sending a group of selection signals that are logically reversed to each other to the first wiring and the second wiring.

8. An electronic device, comprising: The display device according to claim 7; as well as shell.

9. A semiconductor device, comprising: Drive transistors; First transistor; Second transistor; Third transistor; Fourth transistor; The fifth transistor; The sixth transistor; The seventh transistor; The eighth transistor; The ninth transistor; First capacitor; Second capacitor; as well as Light-emitting devices In this embodiment, the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor all contain oxide semiconductor in the channel formation region. The driving transistor, the first transistor, the fourth transistor, the fifth transistor, and the seventh transistor all include a back gate. The back gate of the first transistor and the back gate of the fourth transistor are electrically connected to one of the source and drain of the second transistor and one of the source and drain of the third transistor. The gate of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the first wiring. The gate of the fourth transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the second wiring. One of the source and drain of the first transistor is electrically connected to the gate of the driving transistor, one of the source and drain of the fifth transistor, and the first terminal of the first capacitor. One of the source and drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the second capacitor, one of the source and drain of the fourth transistor, the other of the source and drain of the fifth transistor, and one of the source and drain of the sixth transistor. The other of the source and drain of the sixth transistor is electrically connected to one of the anode and cathode of the light-emitting device. The back gate of the fifth transistor and the back gate of the seventh transistor are electrically connected to one of the source and drain of the eighth transistor and one of the source and drain of the ninth transistor. The gate of the fifth transistor is electrically connected to the third wiring. The gate of the seventh transistor is electrically connected to the third wiring. The gate of the eighth transistor is electrically connected to the third wiring. The gate of the ninth transistor is electrically connected to the fourth wiring. Furthermore, one of the source and drain of the seventh transistor is electrically connected to the back gate of the driving transistor and the second terminal of the second capacitor.

10. The semiconductor device according to claim 9, The light-emitting device described herein contains organic EL material.

11. The semiconductor device according to claim 10, The oxide semiconductor comprises one or more selected from indium, zinc, and element M. Furthermore, the element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

12. A display device, comprising: The semiconductor device according to any one of claims 9 to 11; First driving circuit; as well as Second driving circuit, The first driving circuit has the function of sending the image signal to the other of the source and drain of the first transistor. Furthermore, the second driving circuit has the function of sending a group of first selection signals that are logically inverted to each other to the first wiring and the second wiring, and the function of sending a group of second selection signals that are logically inverted to each other to the third wiring and the fourth wiring.

13. An electronic device, comprising: The display device according to claim 12; as well as shell.

14. A semiconductor device, comprising: Drive transistors; First transistor; Second transistor; First capacitor; as well as Light-emitting devices The driving transistor, the first transistor, and the second transistor all contain oxide semiconductors in the channel formation region. The gate of the first transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the first wiring. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor. The other of the source and drain of the second transistor is electrically connected to the gate of the driving transistor and the first terminal of the first capacitor. Furthermore, one of the source and drain of the driving transistor is electrically connected to the second terminal of the first capacitor and one of the anode and cathode of the light-emitting device.

15. The semiconductor device of claim 14, further comprising: Third transistor; as well as The fourth transistor, Both the third transistor and the fourth transistor contain oxide semiconductors in the channel formation region. The gate of the third transistor is electrically connected to the second wiring. The gate of the fourth transistor is electrically connected to the second wiring. One of the source and drain terminals of the third transistor is electrically connected to one of the source and drain terminals of the fourth transistor. Furthermore, the other of the source and drain of the fourth transistor is electrically connected to one of the source and drain of the driving transistor, the second terminal of the first capacitor, and one of the anode and cathode of the light-emitting device.

16. The semiconductor device according to claim 15, The light-emitting device described herein contains organic EL material.

17. The semiconductor device according to claim 16, The oxide semiconductor comprises one or more selected from indium, zinc, and element M. Furthermore, the element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

18. A display device, comprising: The semiconductor device according to any one of claims 15 to 17; First driving circuit; as well as Second driving circuit, The first driving circuit has the function of sending the image signal to the other of the source and drain of the first transistor. Furthermore, the second driving circuit has the function of sending a first selection signal to the first wiring and a second selection signal to the second wiring.

19. An electronic device comprising: The display device according to claim 18; as well as shell.

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