A circuit for measuring capacitance based on the charging method

Abstract

This invention proposes a circuit for measuring capacitance based on a charging method. A charging control module precisely controls the charging and discharging timing of an external capacitor under test. A parameter detection unit collects the voltage or current changes during the capacitor's charging process in real time, and the capacitance value is calculated based on the correlation between charging / discharging time and capacitance value. Existing capacitance measurement methods often rely on external instruments for manual operation. This method only enables offline measurement and cannot monitor the capacitor's state during normal chip operation, especially in harsh operating environments where it is difficult to capture dynamic changes in capacitance value in real time. This invention integrates the charging measurement circuit inside the chip, overcoming the limitations of traditional offline measurement and enabling in-service real-time testing of external capacitors under test. It can dynamically track changes in capacitance value; simultaneously, the integrated design architecture effectively enhances the circuit's robustness in complex environments, achieving real-time monitoring of the capacitor's state.

Description

Technical Field

[0001] This invention relates to a circuit for measuring capacitance based on a charging method, belonging to the field of analog integrated circuit technology. Background Technology

[0002] As a fundamental component in electronic circuits, the accurate measurement of capacitor parameters is crucial for ensuring the stable and reliable operation of the circuit. Traditional capacitance measurement methods mostly rely on external instruments for offline testing. While this method can meet the static screening needs during equipment production or R&D, it has a core limitation: it cannot monitor the external capacitor under test in dynamic scenarios where the chip is operating normally. When the chip is in actual operation, especially under harsh environments such as high temperature, high humidity, and strong electromagnetic interference, the capacitance value may dynamically drift. Traditional offline measurement methods cannot capture this capacitance change in real time, nor can they reflect the actual performance of the capacitor under real operating conditions. This poses a potential performance risk and safety hazard for high-precision circuits that rely on stable capacitance parameters.

[0003] The core factor determining the practicality and adaptability of capacitance measurement lies in the choice of measurement method. Currently, mainstream solutions can be divided into two categories: external offline manual measurement and chip-integrated online measurement. External offline manual measurement has the advantage of strong equipment versatility, meeting the needs of static parameter testing in laboratories. However, this method requires operation outside the actual working environment of the chip, which is not only cumbersome but, more importantly, cannot achieve in-service monitoring of the capacitor. On the other hand, the core advantage of chip-integrated online measurement is its deep coupling with the chip's workflow, enabling real-time dynamic detection of capacitance parameters. However, this solution places higher demands on circuit integration design and anti-interference technology. In practical applications of high-precision chips, the capacitance value of the external capacitor under test is easily affected by harsh environments such as high temperature, high humidity, and strong electromagnetic interference, causing dynamic drift, which poses a significant threat to the stable operation of the circuit. Although some simple internal detection circuits have emerged in existing technologies, these circuits generally suffer from insufficient robustness, and related solutions often face technical bottlenecks such as poor measurement stability and susceptibility to external environmental interference. To address this pain point, this invention proposes a capacitance measurement method based on the charging method. By integrating the charging control module and the parameter detection unit inside the chip, the capacitance parameter is detected by utilizing the dynamic change characteristics of the capacitor voltage during the charging process. This not only realizes real-time monitoring and capacitance change tracking of the external capacitor under test, but also effectively improves the stability and reliability of the measurement, and significantly enhances the robustness of the circuit under complex operating conditions.

[0004] To achieve real-time monitoring and dynamic tracking of capacitor parameters during chip operation, a measurement scheme integrating the charging circuit within the chip offers significant technical advantages compared to offline measurement methods relying on external instruments. This scheme controls the start and stop of the charging process through preset precise timing, utilizing the chip's internal signal acquisition and processing unit to capture the dynamic changes in electrical signals during charging in real time, thereby directly calculating the real-time parameters of the external capacitor under test. This design is highly compatible with the chip's in-service operating characteristics, fully leveraging the advantages of internal circuit collaboration and overcoming the technical limitations of traditional offline measurements that cannot synchronize with the chip's operating state. Therefore, based on existing internal detection circuits, this invention focuses on the core requirement of in-service capacitor monitoring, designing a charging-type measurement architecture. Through optimized circuit design, it achieves real-time online measurement of the external capacitor under test, not only dynamically tracking capacitance value drift under harsh environments and complex operating conditions, significantly improving measurement convenience and adaptability, but also effectively reducing overall measurement costs. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a capacitance measurement circuit and method based on a charging method. This invention achieves real-time monitoring of external capacitors by integrating the charging circuit within the chip and utilizing the dynamic voltage changes during charging to detect the parameters of the external capacitor under test. This overcomes the limitations of traditional offline measurement techniques and enables real-time monitoring of external capacitors by the chip during operation. This solution can dynamically track changes in capacitance value within the automated control process of normal chip operation, making it particularly suitable for capacitor status monitoring in harsh environments such as high temperature, high humidity, and strong electromagnetic interference. This invention not only effectively improves the convenience of measurement and reduces the reliance on external instruments and manual operation, but also possesses excellent robustness and can be widely applied in real-time online monitoring scenarios of external capacitors using high-precision integrated chips.

[0006] The technical solution to achieve the objective of this invention is:

[0007] A circuit for measuring capacitance based on a charging method, characterized in that it includes:

[0008] The charging capacitor circuit is the core module used to charge the capacitor under test.

[0009] The charging capacitor circuit includes NMOS transistors mn11 and mn12, PMOS transistors mp11 and mp12, a current source I1, a charging stop switch charge_pd, and the capacitor under test C. The input of current source I1 is connected to the power supply, and its output is connected to the drain and gate of NMOS transistor mn11, the gate of mn12, and one end of the charging stop switch charge_pd. The source of NMOS transistor mn11 is grounded. The drain of NMOS transistor mn12 is connected to the gate and drain of mp11 and the gate of mp12. The drain of NMOS transistor mn12 is grounded. The source of PMOS transistor mp11 is connected to the power supply. The source of PMOS transistor mp12 is connected to the power supply. The drain of PMOS transistor mp12 receives the upper plate of the capacitor under test C. The lower plate of the capacitor under test C is grounded. The control terminal of the charging stop switch charge_pd is connected to the control output of the charging flag generation circuit.

[0010] A charging flag generation circuit is used as a flag to indicate when charging has stopped.

[0011] The charging flag generation circuit includes a comparator comp1, an inverter inv1, and a NAND gate nand1. The positive input of comparator comp1 is connected to cap; the negative input of comparator comp1 is connected to vref; the output of comparator comp1 is connected to the charging flag charge_OK_0; the other end of the charging flag charge_OK_0 is connected to the input of inverter inv1; the output of inverter inv1 is connected to the second input of NAND gate nand1; the first input of NAND gate nand1 is connected to the charging signal charge; the output of NAND gate nand1 is connected to the charging stop switch charge_pd; and the output of NAND gate nand1 is electrically connected to the control terminal of the charging stop switch charge_pd in the charging capacitor circuit of claim 1, outputting a charging stop control signal to the charging capacitor circuit.

[0012] A current mirror is used to provide precise charging current.

[0013] The current mirror includes NMOS transistors mn21, mn22, mn23, mn24, mn25, and mn26; PMOS transistors mp21, mp22, mp23, and mp24; resistor r1; and a reference current source IREF. The input of the reference current source is connected to the power supply, and the output is connected to the drain and gate of NMOS transistor mn21 and the gate of mn22. The source of NMOS transistor mn21 is grounded; the source of NMOS transistor mn22 is grounded; the drain of NMOS transistor mn22 is connected to the gate and drain of PMOS transistor mp21 and the gate of mp22; the source of PMOS transistor mp21 is powered; the source of PMOS transistor mp22 is powered; the drain of PMOS transistor mp22 is connected to one end of resistor r1 and the gates of NMOS transistors mn23 and mn25; the gate of NMOS transistor mn23 is connected to the gate of mn25; the other end of resistor r1 is connected to the NMOS transistor... The drain of transistor MN23 is connected to the gate of NMOS transistors MN24 and MN26. The drain of NMOS transistor MN24 is connected to the source of MN23. The source of NMOS transistor MN24 is grounded. The drain of NMOS transistor MN26 is connected to the source of MN25. The source of NMOS transistor MN26 is grounded. The gate of PMOS transistor MP23 is connected to the drain of MP23 and the gate of MP24. The source of PMOS transistor MP23 is connected to the power supply. The source of PMOS transistor MP24 is connected to the power supply. The drain serves as the current output terminal of the current mirror and is electrically connected to the input terminal of the current source I1 of the charging capacitor circuit in claim 1, thereby outputting a precise charging current I1 to the charging capacitor circuit.

[0014] A comparator is used to compare the charging voltage with a set reference voltage.

[0015] The comparator includes NMOS transistors mn31, mn32, mn33, mn34, mn35, and mn36, PMOS transistors mp31, mp32, mp33, mp34, mp35, and mp36, and a reference current source Iprobe. The input of the reference current source Iprobe is connected to the power supply; the output of the reference current source Iprobe is connected to the gate and drain of NMOS transistor mn31 and the gate of mn32; the source of NMOS transistor mn31 is grounded; the source of NMOS transistor mn32 is grounded; the drain of NMOS transistor mn32 is connected to the gate and drain of PMOS transistor mp31 and the gate of mp32; the source of PMOS transistor mp31 is powered; the source of PMOS transistor mp32 is powered; the drain of PMOS transistor mp32 is connected to the source of PMOS transistor mp33 and the source of mp34; the gate of PMOS transistor mp33 is connected to the negative input of the comparator; the gate of PMOS transistor mp34 is connected to the positive input of the comparator; the drain of PMOS transistor mp33 is connected to the NMOS transistor... The gate and drain of OS transistor MN33 and the gate of MN35 are connected; the drain of PMOS transistor MP34 is connected to the gate and drain of NMOS transistor MN34 and the gate of MN36; the source of NMOS transistor MN35 is powered; the drain of NMOS transistor MN35 is connected to the gate and drain of PMOS transistor MP35 and the gate of MP36; the source of PMOS transistor MP35 is powered; the source of PMOS transistor MP36 is powered; the drain of PMOS transistor MP36 is connected to the drain of NMOS transistor MN36. This connection point serves as the signal output terminal of the comparator and is electrically connected to the positive input terminal of comparator Comp1 of the charging flag generation circuit in claim 1, transmitting the voltage comparison result to the charging flag generation circuit; the source of NMOS transistor MN36 is grounded.

[0016] A circuit for measuring capacitance based on the charging method is described in the following brief description of its operation steps.

[0017] Charging Phase: During charging, the charging stop flag (charge_pd) is turned off, and the current I1 is mirrored through the current mirror to supply power to the capacitor C under test. 待测 Charge.

[0018] Capacitor C under test 待测 The voltage cap on the upper plate increases until the charging voltage cap is greater than the reference voltage vref at the positive terminal of comparator comp1. The charging flag bit charge_ok_0 flips, the charging stop switch charge_pd opens, and the charging process ends. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the charging method circuit for measuring capacitance according to the present invention.

[0020] Figure 2 This is a schematic diagram of the charging flag generation circuit of the present invention.

[0021] Figure 3 This is a schematic diagram of the current mirror structure in the circuit of the present invention.

[0022] Figure 4 This is a schematic diagram of the comparator in the circuit of the present invention.

[0023] Figure 5 This is a schematic diagram of the circuit timing of the present invention. Detailed Implementation

[0024] To make the objectives and technical advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0025] like Figure 1 , Figure 2 , Figure 3 , Figure 4 The diagram shown is a circuit structure diagram of the present invention, a circuit for measuring capacitance using a charging method, including a charging core circuit, a charging flag generation circuit, a current mirror circuit, and a comparator circuit. During the charging phase, as... Figure 3 The diagram shows the structure of the current mirror in the circuit of this invention. The current mirror IREF accurately replicates the current to I1, improving the robustness of the system measurement.

[0026] During the charging phase, such as Figure 2 The diagram shows a schematic of the charging flag generation circuit of the present invention. At this time, the capacitor C to be tested... 待测 The upper plate voltage cap is low, less than the negative input voltage vref of comparator comp1, and the charging flag charge_ok_0 is low. The charging signal charge is high, and a NAND logic is performed with the charging flag charge_ok_0. The charging stop flag charge_pd is low, and the capacitor C under test... 待测 The upper plate voltage cap is used for charging.

[0027] During the charging phase, when the capacitor under test C 待测 When the voltage cap on the upper plate is greater than the voltage vref at the negative input terminal of comparator comp1, the charging flag bit charge_ok_0 toggles high. The charging signal charge is high, and a NAND logic operation is performed with the charging flag bit charge_ok_0. The charging stop flag bit charge_pd is high, and the capacitor C under test... 待测 When the voltage cap on the upper plate stops charging, the measured capacitance value during this process is:

[0028]

[0029] Among them, C 待测 I1 refers to the capacitance value of the capacitor under test, and I1 refers to the magnitude of the mirror current. The reference voltage vref is the pre-charge voltage value. During the charging phase, the charging signal charge jumps from low voltage to high voltage, and the time at this moment is t1. When the capacitance C under test... 待测 When the upper plate voltage cap is greater than the reference voltage vref, charging ends, and the charging flag bit charge_ok_0 jumps from low voltage to high voltage. This time is recorded as t2.

Claims

1. A circuit for measuring capacitance based on the charging method, characterized in that, include: Charging capacitor circuit, charging flag generation circuit, current mirror, comparator; The charging capacitor circuit includes NMOS transistors mn11 and mn12, PMOS transistors mp11 and mp12, a current source I1, a charging stop switch charge_pd, and the capacitor under test C. The input of current source I1 is connected to the power supply, and its output is connected to the drain and gate of NMOS transistor mn11, the gate of mn12, and one end of the charging stop switch charge_pd. The source of NMOS transistor mn11 is grounded. The drain of NMOS transistor mn12 is connected to the gate and drain of mp11 and the gate of mp12. The drain of NMOS transistor mn12 is grounded. The source of PMOS transistor mp11 is connected to the power supply. The source of PMOS transistor mp12 is connected to the power supply. The drain of PMOS transistor mp12 receives the upper plate of the capacitor under test C. The lower plate of the capacitor under test C is grounded. The control terminal of the charging stop switch charge_pd is connected to the control output of the charging flag generation circuit.

2. The circuit according to claim 1, characterized in that, The charging flag generation circuit includes a comparator comp1, an inverter inv1, and a NAND gate nand1. The positive input of comparator comp1 is connected to cap; the negative input of comparator comp1 is connected to vref; the output of comparator comp1 is connected to the charging flag charge_OK_0; the other end of the charging flag charge_OK_0 is connected to the input of inverter inv1; the output of inverter inv1 is connected to the second input of NAND gate nand1; the first input of NAND gate nand1 is connected to the charging signal charge; the output of NAND gate nand1 is connected to the charging stop switch charge_pd; and the output of NAND gate nand1 is electrically connected to the control terminal of the charging stop switch charge_pd of the charging capacitor circuit, outputting a charging stop control signal to the charging capacitor circuit.

3. The circuit according to claim 1, characterized in that, The current mirror circuit includes NMOS transistors mn21, mn22, mn23, mn24, mn25, and mn26; PMOS transistors mp21, mp22, mp23, and mp24; resistor r1; and a reference current source IREF. The input of the reference current source is connected to a power supply, and its output is connected to the drain and gate of NMOS transistor mn21 and the gate of mn22. The source of NMOS transistor mn21 is grounded; the source of NMOS transistor mn22 is grounded; the drain of NMOS transistor mn22 is connected to the gate and drain of PMOS transistor mp21 and the gate of mp22; the source of PMOS transistor mp21 is powered; the source of PMOS transistor mp22 is powered; and the drain of PMOS transistor mp22 is connected to one end of resistor r1. The gates of MN23 and MN25; the gate of NMOS transistor MN23 is connected to the gate of MN25; the other end of resistor R1 is connected to the drain of NMOS transistor MN23, and the gates of NMOS transistors MN24 and MN26; the drain of NMOS transistor MN24 is connected to the source of MN23; the source of NMOS transistor MN24 is grounded; the drain of NMOS transistor MN26 is connected to the source of MN25; the source of NMOS transistor MN26 is grounded; the gate of PMOS transistor MP23 is connected to the drain of MP23 and the gate of MP24; the source of PMOS transistor MP23 is connected to the power supply; the source of PMOS transistor MP24 is connected to the power supply, and the drain is used as the current output terminal of the current mirror, which is electrically connected to the input terminal of the current source I1 of the charging capacitor circuit, outputting the charging current I1 to the charging capacitor circuit.

4. The circuit according to claim 1, characterized in that, The comparator circuit includes, wherein the comparator comprises NMOS transistors mn31, mn32, mn33, mn34, mn35, and mn36, PMOS transistors mp31, mp32, mp33, mp34, mp35, and mp36, and a reference current source Iprobe; the input terminal of the reference current source Iprobe is connected to a power supply; the output terminal of the reference current source Iprobe is connected to the gate and drain of NMOS transistor mn31 and the gate of mn32; the source of NMOS transistor mn31 is grounded; the source of NMOS transistor mn32 is grounded; the drain of NMOS transistor mn32 is connected to the gate and drain of PMOS transistor mp31 and the gate of mp32; the source of PMOS transistor mp31 is powered; the source of PMOS transistor mp32 is powered; the drain of PMOS transistor mp32 is connected to the source of PMOS transistor mp33 and the source of mp34; the PMOS transistor mp... The gate of transistor mp33 is connected to the negative input terminal of the comparator; the gate of PMOS transistor mp34 is connected to the positive input terminal of the comparator; the drain of PMOS transistor mp33 is connected to the gate and drain of NMOS transistor mn33 and the gate of mn35; the drain of PMOS transistor mp34 is connected to the gate and drain of NMOS transistor mn34 and the gate of mn36; the source of NMOS transistor mn35 is powered; the drain of NMOS transistor mn35 is connected to the gate and drain of PMOS transistor mp35 and the gate of mp36; the source of PMOS transistor mp35 is powered; the source of PMOS transistor mp36 is powered; the drain of PMOS transistor mp36 is connected to the drain of NMOS transistor mn36. This connection point serves as the signal output terminal of the comparator and is electrically connected to the positive input terminal of comparator comp1 of the charging flag generation circuit, transmitting the voltage comparison result to the charging flag generation circuit; the source of NMOS transistor mn36 is grounded.

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