An integrated method of optoelectronic thin film and optical chip and optoelectronic chip

Abstract

This invention relates to the field of semiconductor technology, and particularly to a method for integrating a photoelectric thin film and a photoelectric chip, as well as the photoelectric chip itself. The method involves providing a first substrate structure and a second substrate structure. The first substrate structure includes a first substrate and a first dielectric layer stacked together. The second substrate structure includes a second substrate, a modified layer, a second dielectric layer, and a photoelectric thin film arranged sequentially from bottom to top. The first substrate is the photoelectric chip. Using the surfaces of the first dielectric layer and the photoelectric thin film as bonding surfaces, the first substrate structure and the second substrate structure are bonded together to obtain a first bonded structure. The modified layer is then modified to cause the first bonded structure to separate along the modified layer. Finally, the second dielectric layer and any remaining modified layer are removed to obtain the photoelectric chip. This method allows for the rapid and precise transfer of optical functional materials onto a silicon photoelectric substrate, and is simple and low-cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for integrating optoelectronic thin films and optical chips, as well as an optoelectronic chip. Background Technology

[0002] Breakthroughs in deep learning, large-scale model training, and real-time intelligent decision-making have led to an explosive growth in global data traffic, placing extremely high demands on the underlying data transmission architecture. However, traditional electrical signal chip interconnect technologies have revealed physical bottlenecks in terms of bandwidth, latency, and energy consumption, making it difficult to support the future development needs of computing power and communication. Against this backdrop, optical interconnect technology, with its ultra-high bandwidth, extremely low latency, and excellent energy efficiency, is considered a key enabling technology for next-generation high-performance computing and data center interconnects, attracting significant attention from both academia and industry.

[0003] However, the manufacturing path of optical chips is drastically different from that of mature electrical chips. The core of electrical chips, such as silicon-based CMOS technology, has, after decades of development, formed an extremely mature and standardized materials and manufacturing system. In contrast, optical chips lack a single material platform with the same "versatility" and mature technology as silicon is for electronics. Different optoelectronic functions (such as laser generation, high-speed modulation, low-loss waveguides, and high-efficiency detection) often require different materials to achieve optimal performance. Therefore, heterogeneous integration—that is, fusing multiple functional materials (such as III-V compound semiconductors, lithium niobate, lithium tantalate, and silicon) into the same substrate or package using advanced integration technology—has become an inevitable choice for constructing high-performance, multifunctional optoelectronic chips.

[0004] However, a mature, reliable, and low-cost method suitable for large-scale mass production is currently lacking for the precise transfer and bonding of high-quality lithium niobate and lithium tantalate single-crystal thin films onto silicon photonic wafers. Existing methods often suffer from high costs, low yields, or complex processes and incompatibility with existing production lines. Therefore, developing an efficient, low-cost, high-yield heterogeneous optoelectronic thin film transfer technology that is compatible with standard processes has become a core issue that urgently needs to be addressed to promote the research and commercialization of high-performance optical chips. Summary of the Invention

[0005] To address the aforementioned technical problems, this application discloses a method for integrating a photoelectric thin film and an optical chip, the method comprising: A first substrate structure and a second substrate structure are provided; the first substrate structure includes a first substrate and a first dielectric layer stacked together; the second substrate structure includes a second substrate, a modified layer, a second dielectric layer and a photoelectric thin film arranged sequentially from bottom to top; the first substrate is an optical chip; Using the surface of the first dielectric layer and the surface of the optoelectronic thin film as the bonding surfaces, the first substrate structure and the second substrate structure are bonded to obtain a first bonding structure; The modified layer is subjected to a modification treatment to cause the first bonding structure to separate along the modified layer. Then, the second dielectric layer and the residual modified layer are removed to obtain a photoelectric chip.

[0006] In one exemplary embodiment, the modification process includes heat annealing or laser treatment.

[0007] In one exemplary embodiment, when the material of the modified layer is a first type of material, the modification treatment is performed by heating and annealing. When the material of the modified layer is a second type of material, the modification treatment is performed by laser. The first type of material includes silicon, quartz, or low-melting-point alloys; the melting point of the low-melting-point alloys is below 700°C; The second category of materials includes titanium nitride or low-melting-point alloys.

[0008] In one exemplary embodiment, the fabrication process of the second substrate structure includes: A structure comprising a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top, and a third substrate is provided; the material of the third substrate is the same as the material of the photoelectric thin film. Ion implantation is performed on the third substrate with the implantation direction to form a defect layer at a predetermined depth in the third substrate; Using the injection surface and the surface of the second dielectric layer as the bonding surfaces, the third substrate having the defect layer is bonded to the second dielectric layer to obtain a second bonding structure; The second bonding structure is annealed and peeled to separate the second bonding structure along the defect layer, and the residual defect layer on the second substrate is removed to form the photoelectric thin film on the second dielectric layer, thereby obtaining the second substrate structure.

[0009] In one exemplary embodiment, the fabrication process of the structure consisting of a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top includes: Provide a second substrate; A first material layer is deposited on the second substrate; the material of the first material layer includes silicon, quartz, or a low-melting-point alloy; the melting point of the low-melting-point alloy is below 700°C; Ion implantation is performed on the first material layer to form the modified layer; A second medium layer is deposited on the metamorphic layer to form a second medium layer.

[0010] In one exemplary embodiment, the fabrication process of the structure consisting of a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top includes: Provide a second substrate; A second material layer is deposited on the second substrate using a deposition process to form the modified layer; the material of the second material layer includes titanium nitride or a low-melting-point alloy. A second medium layer is deposited on the metamorphic layer to form a second medium layer.

[0011] In one exemplary embodiment, the temperature of the heating annealing is greater than the temperature of the annealing peeling.

[0012] In one exemplary embodiment, the first substrate includes a silicon-based optoelectronic chip or a silicon-based complementary metal-oxide-semiconductor chip.

[0013] In one exemplary embodiment, the photoelectric thin film includes a lithium niobate single crystal thin film, a lithium tantalate single crystal thin film, or a group III-V semiconductor single crystal thin film; The material of the first dielectric layer includes silicon nitride, silicon oxide, or silicon carbon nitride thin film.

[0014] On the other hand, this application also discloses an optoelectronic chip, which is prepared based on the above-described preparation method.

[0015] This application provides a first substrate structure and a second substrate structure. The first substrate structure includes a first substrate and a first dielectric layer stacked together. The second substrate structure includes a second substrate, a modified layer, a second dielectric layer, and a photoelectric thin film arranged sequentially from bottom to top. The first substrate is an optical chip. Using the surface of the first dielectric layer and the surface of the photoelectric thin film as bonding surfaces, the first substrate structure and the second substrate structure are bonded to obtain a first bonded structure. The modified layer is modified to cause the first bonded structure to separate along the modified layer. Then, the second dielectric layer and the remaining modified layer are removed to obtain the photoelectric chip. In this way, optical functional materials can be quickly and accurately transferred onto a silicon photonic substrate, which is simple to operate and low in cost. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure during the fabrication of an optoelectronic chip, provided in an embodiment of this application. Figure 2This is a schematic diagram of a process for preparing a second substrate structure, provided in the application embodiment.

[0018] The following is supplementary explanation of the attached figures: 1-First substrate structure; 101-First substrate; 102-First dielectric layer; 2-Second substrate structure; 201-Second substrate; 202-Modified layer; 203-Second dielectric layer; 204-Photoelectric thin film; 3-Third substrate; 301-Defect layer; 4-First bonding structure; 5-Second bonding structure. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0021] Although the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​listed in the specific examples are reported as precisely as possible. However, any numerical value inherently contains some error that is necessarily caused by the standard deviation found in their respective test measurements.

[0022] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0023] Please see Figure 1 The diagram shown is a structural schematic of a photoelectric chip fabrication process provided in an embodiment of this application. The fabrication method of this heterogeneous substrate may specifically include: S101: Provide a first substrate structure 1 and a second substrate structure 2; the first substrate structure 1 includes a first substrate 101 and a first dielectric layer 102 stacked together; For example, the method for fabricating the first substrate structure 1 includes: providing a first substrate 101; depositing and forming a first dielectric layer 102 on the first substrate 101 to obtain... Figure 1 The first substrate structure 1 is shown in Figure (a).

[0024] For example, the second substrate structure 2 can be as follows: Figure 1 The structure shown in Figure (b) is as follows: the second substrate structure 2 includes a second substrate 201, a modified layer 202, a second dielectric layer 203 and a photoelectric thin film 204 arranged sequentially from bottom to top; the first substrate 101 is an optical chip.

[0025] In one exemplary implementation, please refer to Figure 2 The diagram illustrates a structural schematic of a second substrate structure fabrication process according to an embodiment of the application. The fabrication process of the second substrate structure 2 includes: providing a structure consisting of a second substrate 201, a modified layer 202, and a second dielectric layer 203 arranged sequentially from bottom to top (i.e., as shown in the image). Figure 2 The structure shown in Figure (d) and the third substrate 3 (i.e., as shown in Figure 3) Figure 2 The structure shown in Figure (c)); the material of the third substrate 3 is the same as the material of the photoelectric thin film 204; ion implantation is performed on the third substrate 3 with the implantation surface to form a defect layer 301 at a predetermined depth on the third substrate 3, resulting in the structure shown in Figure (c). Figure 2The structure shown in Figure (e) is as follows: using the injection surface and the surface of the second dielectric layer 203 as the bonding surfaces, the third substrate 3 having the defect layer 301 is bonded to the second dielectric layer 203 to obtain the second bonding structure 5, i.e., as shown in Figure (e). Figure 2 The structure shown in Figure (f) is subjected to annealing and peeling to separate the second bonding structure 5 along the defect layer 301, resulting in the structure shown in Figure (f). Figure 2 The structure shown in Figure (g) is used, and the residual defect layer 301 on the second substrate 201 is removed to form the photoelectric thin film 204 on the second dielectric layer 203, resulting in the second substrate structure 2, i.e., as shown in Figure (g). Figure 2 The structure shown in Figure (h) is as follows.

[0026] In an exemplary embodiment, the fabrication process of the structure consisting of a second substrate 201, a modified layer 202, and a second dielectric layer 203 arranged sequentially from bottom to top includes: providing a second substrate 201 (i.e., as shown in the figure) Figure 2 The structure shown in Figure (a) involves depositing a first material layer on the second substrate 201; the material of the first material layer includes silicon, quartz, or a low-melting-point alloy; the melting point of the low-melting-point alloy is below 700°C; ion implantation is performed on the first material layer to form the modified layer 202, resulting in the structure shown in Figure (a). Figure 2 The structure shown in Figure (b) is obtained by depositing a second dielectric layer 203 on the metamorphic layer 202, resulting in the structure shown in Figure (b). Figure 2 The structure shown in Figure (c)

[0027] In another exemplary embodiment, the fabrication process of the structure consisting of a second substrate 201, a modified layer 202, and a second dielectric layer 203 arranged sequentially from bottom to top includes: providing a second substrate 201; depositing a second material layer on the second substrate 201 using a deposition process to form the modified layer 202; the material of the second material layer includes titanium nitride or a low-melting-point alloy; and depositing a second dielectric layer 203 on the modified layer 202.

[0028] For example, the conditions for forming the second bond structure 5 are: using plasma to activate the bond, and the type of activating gas can be any one of nitrogen, oxygen and argon.

[0029] For example, the annealing and peeling conditions are: a time of 1 to 50 hours; and a temperature of 100 to 300°C. Specifically, the annealing time can be 1 hour, 5 hours, 10 hours, 15 hours, 20 hours, 25 hours, 30 hours, 35 hours, 40 hours, 45 hours, or 50 hours; and the annealing and peeling temperature can be 100°C, 150°C, 200°C, 250°C, or 300°C.

[0030] For example, ion implantation is performed along the implantation surface of the third substrate 3, and the implanted ions can be hydrogen ions, helium ions, or a combination of both. For example, the implanted ions are hydrogen ions, the ion implantation energy is 50 to 250 kiloelectron volts, and the dose is 1 × 10⁻⁶. 16 From 1×10 cm / m² to 1×10 17 per square centimeter.

[0031] In one exemplary embodiment, the first substrate 101 includes a silicon-based optoelectronic chip or a silicon-based complementary metal-oxide-semiconductor chip.

[0032] In one exemplary embodiment, the photoelectric thin film 204 includes a lithium niobate single crystal thin film, a lithium tantalate single crystal thin film, or a III-V group semiconductor single crystal thin film.

[0033] For example, the material of the first dielectric layer 102 includes silicon nitride, silicon oxide, or silicon carbon nitride film.

[0034] For example, the materials of the first substrate 101 and the second substrate 201 can be any one of silicon, silicon oxide, sapphire, diamond, aluminum nitride, quartz, gallium nitride and silicon carbide.

[0035] For example, the material of the second dielectric layer 203 includes silicon oxide or silicon nitride.

[0036] It is understandable that the specific method for removing the residual defect layer 301 on the photoelectric thin film 204 is polishing, such as chemical mechanical polishing; the deposition process can be physical deposition (such as electron beam evaporation), chemical deposition, or a combination of both.

[0037] S103: Using the surface of the first dielectric layer 102 and the surface of the optoelectronic thin film 204 as the bonding surfaces, the first substrate structure 1 and the second substrate structure 2 are bonded to obtain the first bonding structure 4.

[0038] For example, the first bonding structure 4 can be as follows: Figure 1 The structure shown in Figure (c)

[0039] For example, the conditions for forming the first bond structure 4 are: using plasma to activate the bond, and the type of activating gas can be any one of nitrogen, oxygen and argon.

[0040] S105: Modify the altered layer 202 to separate the first bonding structure 4 along the altered layer 202, and then remove the second dielectric layer 203 and the residual altered layer 202 to obtain the optoelectronic chip.

[0041] For example, the separation interface and the optoelectronic chip can be as follows: Figure 1 The structure shown in Figure (d) is as follows.

[0042] In one exemplary embodiment, the modification process includes heat annealing or laser treatment.

[0043] In an exemplary embodiment, when the material of the modified layer 202 is a first type of material, the modification treatment is performed by heating and annealing; when the material of the modified layer 202 is a second type of material, the modification treatment is performed by laser; the first type of material includes silicon, quartz, or a low-melting-point alloy; the melting point of the low-melting-point alloy is below 700°C; the second type of material includes titanium nitride or a low-melting-point alloy.

[0044] For example, the conditions for heat annealing include: a time of 1 to 50 hours; and a temperature of 300 to 700°C. Specifically, the heat annealing time can be 1 hour, 5 hours, 10 hours, 15 hours, 20 hours, 25 hours, 30 hours, 35 hours, 40 hours, 45 hours, or 50 hours; and the heat annealing temperature can be 300°C, 350°C, 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, or 700°C.

[0045] In one exemplary embodiment, the temperature of the heating annealing is higher than the temperature of the annealing peeling to avoid the first dielectric layer 102 and the photoelectric thin film 204 debonding along their bonding interface.

[0046] In one exemplary embodiment, the temperature of the heating annealing is greater than the temperature of the annealing peeling to avoid the cracking of the modified layer 202.

[0047] For example, the laser processing conditions are: the laser beam is any one or a combination of femtosecond lasers, picosecond lasers, and nanosecond lasers; the laser power density is 1×10⁻⁶. 4 ~1×10 8 W / cm 2 Specifically, the laser power density is 1×10⁻⁶. 4 W / cm 2 1×10 5 W / cm 2 1×10 6 W / cm 2 Or 1×10 7 W / cm 2 .

[0048] On the other hand, this application also discloses an optoelectronic chip, which is prepared based on the above-described preparation method.

[0049] Subsequently, the required semiconductor integrated modules can be fabricated on optoelectronic chips using processes such as photolithography, metal growth, etching, and passivation.

[0050] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for integrating a photoelectric thin film and an optical chip, characterized in that, The method includes: A first substrate structure and a second substrate structure are provided; the first substrate structure includes a first substrate and a first dielectric layer stacked together; the second substrate structure includes a second substrate, a modified layer, a second dielectric layer and a photoelectric thin film arranged sequentially from bottom to top; the first substrate is an optical chip; Using the surface of the first dielectric layer and the surface of the optoelectronic thin film as the bonding surfaces, the first substrate structure and the second substrate structure are bonded to obtain a first bonding structure; The modified layer is subjected to a modification treatment to cause the first bonding structure to separate along the modified layer. Then, the second dielectric layer and the residual modified layer are removed to obtain a photoelectric chip.

2. The integration method according to claim 1, characterized in that, The modification process includes heat annealing or laser treatment.

3. The integration method according to claim 2, characterized in that, When the material of the modified layer is a first-class material, the modification treatment is heat annealing; When the material of the modified layer is a second type of material, the modification treatment is performed by laser. The first type of material includes silicon, quartz, or low-melting-point alloys; the melting point of the low-melting-point alloys is below 700°C; The second category of materials includes titanium nitride or low-melting-point alloys.

4. The integration method according to claim 3, characterized in that, The fabrication process of the second substrate structure includes: A structure comprising a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top, and a third substrate is provided; the material of the third substrate is the same as the material of the photoelectric thin film. Ion implantation is performed on the third substrate with the implantation direction to form a defect layer at a predetermined depth in the third substrate; Using the injection surface and the surface of the second dielectric layer as the bonding surfaces, the third substrate having the defect layer is bonded to the second dielectric layer to obtain a second bonding structure; The second bonding structure is annealed and peeled to separate the second bonding structure along the defect layer, and the residual defect layer on the second substrate is removed to form the photoelectric thin film on the second dielectric layer, thereby obtaining the second substrate structure.

5. The integration method according to claim 3, characterized in that, The fabrication process of the structure consisting of a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top includes: Provide a second substrate; A first material layer is deposited on the second substrate; the material of the first material layer includes silicon, quartz, or a low-melting-point alloy; the melting point of the low-melting-point alloy is below 700°C; Ion implantation is performed on the first material layer to form the modified layer; A second medium layer is deposited on the metamorphic layer to form a second medium layer.

6. The integration method according to claim 3, characterized in that, The fabrication process of the structure consisting of a second substrate, a modified layer, and a second dielectric layer arranged sequentially from bottom to top includes: Provide a second substrate; A second material layer is deposited on the second substrate using a deposition process to form the modified layer; the material of the second material layer includes titanium nitride or a low-melting-point alloy. A second medium layer is deposited on the metamorphic layer to form a second medium layer.

7. The integration method according to claim 4, characterized in that, The temperature of the heating annealing is greater than the temperature of the annealing peeling.

8. The integration method according to any one of claims 1-7, characterized in that, The optical chip includes a silicon-based optoelectronic chip or a silicon-based complementary metal-oxide-semiconductor chip.

9. The integration method according to any one of claims 1-7, characterized in that, The optoelectronic thin film includes lithium niobate single crystal thin film, lithium tantalate single crystal thin film, or group III-V semiconductor single crystal thin film. The material of the first dielectric layer includes silicon nitride, silicon oxide, or silicon carbon nitride thin film.

10. A photoelectric chip, characterized in that, It is prepared based on the integration method described in any one of claims 1-9.

Images