A shipboard electronic equipment integration outfield comprehensive test system and method

Abstract

This invention discloses an integrated field comprehensive testing system and method for shipborne electronic equipment, belonging to the field of microwave testing technology. The system employs a physically isolated intelligent control domain and RF front-end domain. Within the RF front-end domain, the main control module analyzes the logic testing requirements based on a weighted directed graph optimization algorithm, coordinates the online loading of the algorithm kernel by the reconfigurable signal processing module, controls the shared broadband frequency synthesis module to allocate the local oscillator signal in a time-division manner, and directly drives the programmable RF switching matrix to perform non-blocking switching, rapidly instantiating the end-to-end physical test link. This invention, through the coordination of reconfigurable signal processing, shared frequency synthesis, and the programmable RF switching matrix by the main control module, achieves single-connection and millisecond-level fully automatic reconfiguration of test tasks. Combined with a three-level progressive clock synchronization architecture, it significantly reduces equipment size and power consumption while meeting the stringent requirements of multi-channel coherent testing and tactical collaborative verification in complex electromagnetic environments.

Description

Technical Field

[0001] This invention belongs to the field of military electronic testing and integrated support technology, specifically relating to an integrated field testing system and method for shipborne electronic equipment. Background Technology

[0002] With the increasing complexity of modern naval combat systems, the operational readiness of key electronic equipment such as radar, electronic countermeasures, communications, and data links directly impacts combat effectiveness. Currently, existing technologies for the field testing and support of such equipment (dockside, deck) face the following prominent challenges:

[0003] Firstly, in terms of system architecture and operating mode, existing technologies mostly adopt a "discrete instrument combination mode" or a "fixed function integration mode" based on PXI / VXI. The former relies on manual identification and plugging / unplugging of RF cables, resulting in poor system consistency and extremely low efficiency. The test mode switching is time-consuming and easily leads to connector wear and poor contact. The latter's functions are implemented by a fixed combination of hardware modules, which is essentially a static "module stacking". The underlying RF physical connection relationship is fixed and it is difficult to dynamically reconfigure according to the changing test tasks.

[0004] Secondly, regarding resource utilization and equipment form factor (SWaP-C), existing systems mostly adopt a resource-dedicated design approach of "one function, one link" or "one frequency band, one hardware". To cover different frequency bands, multiple independent dedicated local oscillators, frequency conversion channels, and processing boards are usually required. This design results in severe hardware resource redundancy, with equipment that is bulky, heavy, and consumes a lot of power, making it difficult to pass through the narrow hatches inside ships and to operate for extended periods at forward sites with limited power supply capabilities.

[0005] Secondly, regarding spatiotemporal synchronization performance, common distributed testing systems often rely on operating system software clocks or common network synchronization protocols (such as NTP) for time alignment. The synchronization accuracy is mostly in the range of hundreds of milliseconds to milliseconds, with fixed delays and random jitter at the microsecond level. The lack of an end-to-end high-precision time unification design scheme from physical layer clock circuits to higher-level control protocols makes it extremely easy for phase mismatch to occur when performing multi-channel strictly phase-coherent testing tasks (such as complex electromagnetic environment simulation).

[0006] Finally, regarding operational safety and control system safety, existing technologies require operators to have close contact with high-power radio frequency front-ends, exposing them to potential electromagnetic radiation risks. If conventional unencrypted wired / wireless networks are used for remote control, in complex, combat-ready electromagnetic environments, they are highly susceptible to communication eavesdropping, data tampering, or malicious command injection. Summary of the Invention

[0007] Purpose of the invention: The purpose of this invention is to address the shortcomings of existing technologies by providing an integrated field testing system and method for shipborne electronic equipment. It aims to achieve millisecond-level automatic reconstruction of the test link, high-precision spatiotemporal synchronization, and high-safety operation through the ultimate reuse of underlying hardware resources and software-defined intelligent routing.

[0008] Technical solution: The present invention includes a physically isolated intelligent control domain and a radio frequency front-end domain, as well as a secure communication link connecting the intelligent control domain and the radio frequency front-end domain;

[0009] The intelligent control domain includes a control terminal for planning test tasks, setting parameters, monitoring status, and generating logical test requirements.

[0010] The radio frequency front-end domain is integrated within a ruggedized chassis and includes a main control module, a reconfigurable signal processing module, a shared broadband frequency synthesis module, a frequency converter and power amplifier module, and a programmable radio frequency switching matrix, all interconnected via a high-speed dedicated backplane; wherein:

[0011] The main control module is used to receive the logic test requirements issued by the control terminal via the secure communication link, parse the logic test requirements to generate the underlying hardware control instruction set, and perform unified scheduling of global hardware resources.

[0012] The reconfigurable signal processing module is used to dynamically load a specified signal processing algorithm kernel according to the underlying hardware control instruction set, so as to generate the digital baseband or intermediate frequency signal required for test stimulus, or to process the received digital response signal.

[0013] The shared broadband frequency synthesis module, as the global RF reference of the RF front-end domain, is used to generate a local oscillator signal of the target frequency according to the underlying hardware control instruction set, and dynamically allocate it to the designated frequency conversion channel of the frequency conversion and power amplifier module through the internal switching network to complete the frequency conversion processing of the signal.

[0014] The programmable RF switching matrix, directly driven by the main control module, is used to establish a physical signal path that can be dynamically configured by software between the frequency converter and power amplifier module, the system's built-in measurement unit, and the external physical port.

[0015] The main control module is configured to, upon receiving a test task, synchronously schedule the reconfigurable signal processing module to load the algorithm kernel, the shared broadband frequency synthesis module to allocate the local oscillator signal, and drive the programmable RF switching matrix to switch on and off, thereby instantiating an end-to-end physical test link that matches the logical test requirements within the RF front-end domain.

[0016] This invention provides a microwave synthesis test method based on software-defined topology and dynamic reconfiguration, applied to the aforementioned system, comprising the following steps:

[0017] Step 1, Parse the resource occupancy set: Receive the logic test requirements issued by the intelligent control domain, and parse the logic test requirement script into the resource occupancy set of the underlying hardware through the resource management engine. The resource occupancy set includes at least the virtual radio frequency port, the signal processing algorithm kernel, the local oscillator center frequency, and the logical connection topology.

[0018] Step 2, Dynamically reconfigure the signal processing module: Based on the resource occupancy set, call the hardware bitstream of the corresponding signal processing algorithm kernel from the repository and dynamically load it into the specified reconfigurable partition of the field-programmable gate array in the reconfigurable signal processing module;

[0019] Step 3, Configure and allocate global local oscillator: Send instructions to the shared broadband frequency integration module to control its internal phase-locked loop to generate a local oscillator signal corresponding to the center frequency of the local oscillator, and control its internal multi-output microwave switch matrix to dynamically route the local oscillator signal to the designated frequency conversion module;

[0020] Step 4, drive the RF matrix to close and reconstruct the topology: Based on the connection diagram of all available switching nodes in the system, use the path optimization algorithm to calculate the physical routing path that satisfies the logical connection topology and has the best signal insertion loss, and compile the physical routing path into the underlying driver code to directly drive the microwave switching unit in the programmable RF switching matrix to close, and automatically complete the construction of the end-to-end physical test link.

[0021] Step 5, Hardware-Software Cooperative Closed-Loop Time Synchronization: After the physical test link is constructed and during test execution, the synchronization message of the precision time protocol is captured by the hardware timestamp unit. The absolute time offset of the local clock of each functional module relative to the primary reference clock is calculated. The absolute time offset is directly converted into a hardware control word and written into the feedback frequency divider register or digital delay line of the secondary phase-locked loop in the functional module. The oscillation phase of the local physical clock is hard corrected to compensate for the clock jitter error caused by temperature drift and transmission path, ensuring nanosecond-level alignment of the entire system link timing.

[0022] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows:

[0023] This invention achieves software-defined physical link configuration through deep collaboration between the main control module's resource management engine and the underlying programmable RF switching matrix. The resource management engine automatically calculates switch states based on the shortest path algorithm and performs microsecond-level direct drive via FPGA, completely replacing the manual identification and plugging / unplugging of high-frequency coaxial cables in traditional field testing. This mechanism not only reduces link switching time between multiple test items from tens of minutes to milliseconds, but also eliminates wear, poor contact, and wiring errors caused by repeated plugging and unplugging of physical connectors, truly achieving extremely high agility and reliability of "one-time connection, fully automated testing."

[0024] This invention significantly optimizes the SWaP-C (size, weight, power consumption, cost) performance of the system under harsh environments. It abandons the "one function, one hardware" stacked architecture, introducing a shared broadband frequency synthesis module as a global RF reference. This allows for time-division multiplexing of a single high-purity local oscillator signal to the required channels, eliminating redundant local oscillator sources. Combined with the FPGA dynamic partial reconfiguration technology of the reconfigurable signal processing module, online reuse of processing power is achieved. This deeply integrated solution reduces the overall size and weight by more than 50% compared to traditional discrete instruments, and lowers power consumption by more than 35%, meeting the requirements for high-density deployment in the confined spaces of ships.

[0025] This invention pioneers a software-hardware collaborative closed-loop control architecture combining a three-stage progressive hardware synchronization circuit with an enhanced PTP protocol. Unlike traditional software time alignment that relies on operating system scheduling, this invention directly converts time offsets into low-level hardware control parameters, which are applied to a secondary phase-locked loop with an active proportional-integral filter to perform "hard correction" on the oscillation phase of the local physical clock. This effectively compensates for system temperature drift and jitter caused by transmission paths, providing absolute time uniformity accuracy at the nanosecond to picosecond level, and laying a rigorous time base for multi-channel coherent radar target simulation, coherent interference, and distributed collaborative performance testing.

[0026] This invention establishes an inherently safe operating mode in terms of architecture and communication mechanisms. Through the physical separation of the "intelligent control domain and radio frequency front-end domain," operators can remotely control the system from a remote compartment, completely avoiding the risks of high-power microwave radiation. Simultaneously, national cryptographic security chips are embedded at both ends of the link, enabling real-time hardware-level end-to-end data encryption through two-way authentication and SM block cipher algorithm-based encryption. This ensures that wireless control commands and test data are protected from eavesdropping and tampering in strong electromagnetic countermeasures environments, meeting the extremely high security and compliance requirements of military systems. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall architecture of the integrated field comprehensive testing system provided by the present invention.

[0028] Figure 2 is a logical framework diagram of the security isolation and system integration protection technical solution based on physical isolation and encrypted communication mechanism in an embodiment of the present invention;

[0029] Figure 3 is a diagram of the core architecture innovation design of the embodiment of the present invention based on the shared broadband frequency integration module and high-density modular integration to achieve the goal of low SWaP-C;

[0030] Figure 4 The figure shows the simulation results of the wide temperature variation adaptability and compensation efficiency of the global spatiotemporal unified architecture using a three-level progressive hardware synchronization circuit in the embodiment of the present invention.

[0031] Figure 5 This is a flowchart of the automated test process reconstruction method based on a programmable radio frequency switching matrix according to the present invention;

[0032] Figure 6 This is a flowchart illustrating the hardware and software collaboration process of the resource management engine inside the main control module in this embodiment of the invention, which performs dynamic reconstruction of the digital processing layer and flexible configuration of the radio frequency link layer.

[0033] Figure 7 This is a flowchart illustrating the verification of multi-parameter equipment collaborative response testing and timing scheduling capabilities based on high-precision absolute time scales in an embodiment of the present invention. Detailed Implementation

[0034] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the embodiments described.

[0035] Example 1: Reference Figure 1 This invention proposes a test system based on physical separation and high-density integration. The system is physically divided into an "intelligent control domain" and an "RF front-end domain," which are interconnected through a secure communication link based on a hardware root of trust.

[0036] I. Composition and Functions of Intelligent Control Domain

[0037] The intelligent control domain serves as the system's human-computer interaction and task command center. It primarily comprises a display and control terminal, an external control computer, or an external networked node, providing a graphical interface for task planning, parameter setting, status monitoring, and data display. The system also offers a standard encrypted network interface, allowing users to connect using their own computers or dedicated test nodes for remote control or data interaction, enhancing the system's flexibility in integrating into existing security systems.

[0038] II. Composition and Functions of the Encrypted Communication Module

[0039] The encrypted communication module constructs a trusted communication bridge, performing mandatory two-way authentication of access devices based on digital certificates and hardware fingerprints, strictly enforcing the "no authentication, no connection" security policy. Simultaneously, it employs a security chip compliant with national cryptographic standards to perform real-time link-layer encryption (using the SM block cipher algorithm) on all wireless communication data, ensuring the confidentiality and integrity of control commands and test data transmissions. This security mechanism allows operators to fully control the system from a safe distance using portable terminals, effectively mitigating the risks of high-power radio frequency radiation and meeting the security compliance requirements of military information systems.

[0040] III. Composition, Connections, and Coordination of the RF Front-End Domain

[0041] The radio frequency front-end domain is the core physical execution platform of this invention. All hardware modules in this domain are housed in a high-density ruggedized chassis and interconnected via a built-in high-speed PXIe dedicated backplane. The system features an innovative SWaP-C core architecture within the chassis. Its built-in high-speed backplane carries the PCI Express data stream and PXI timing bus, ensuring the real-time performance and integrity of large-capacity data transmission. Simultaneously, a star-shaped clock network distributes the system master clock directly to each module via a dedicated clock line with equal-length paths, achieving extremely low phase deviation and jitter. This provides a high-precision reference for core timing synchronization. Combined with direct-connection control I / O and trigger buses, it ensures efficient and stable control signal transmission and deterministic, low-latency coordination of multi-module operations. Ultimately, this makes the system a highly reliable, high-performance, high-synchronization-accuracy, and easily expandable and maintainable mobile signal generation and processing platform. The specific design of its internal modules is as follows:

[0042] The main control module, serving as the system's control and data processing hub, operates throughout the entire testing process. It receives operation commands from authorized display and control terminals / external control computers / external networked nodes via a wireless encrypted link or a wired transmission link. After parsing, it sends control parameters to the multi-functional complex scene signal generation module via a high-speed dedicated backplane and automatically loads them according to the test items. The multi-functional complex scene signal generation module generates the required intermediate frequency signal based on the control parameters and directly controls various frequency conversion modules, shared broadband frequency integration modules, power amplifier modules, and programmable RF switching matrices via the high-speed customized dedicated backplane to generate the required output signal and output it through a designated path. Simultaneously, it aggregates measurement data and communication data uploaded by the spectrum analyzer, the multi-functional complex scene signal generation module, and the serial communication module, along with status information reported by each module, for fusion processing and storage. During task execution, this module continuously monitors the system's health. Upon detecting power anomalies, module failures, or communication interruptions, it immediately triggers preset emergency procedures, such as sending protective commands to the matrix switch and power module, ensuring the safety of the system and field equipment.

[0043] The reconfigurable signal processing module is the core of the system's software-defined waveform capability. It adopts a dual-threshold detection mechanism and consists of two large-scale programmable logic devices (FPGA1 and FPGA2) and a multi-channel high-speed AD / DA converter. FPGA1 / FPGA2 acts as a reconfigurable signal processing engine. According to the task code issued by the computer, it dynamically loads the corresponding algorithm kernel and directly generates baseband or intermediate frequency digital signal streams at the hardware level, including complex radar signal generation, data link signals (Link16, Link4A, PL16, etc.), radar target signal simulation, SAR echo signal simulation, navigation signal simulation, guidance signal simulation, etc. These digital streams are converted into intermediate frequency analog signals (IF) by four high-speed DAs (DA1-DA4) and sent to the subsequent frequency conversion modules 1, 2, and 3, respectively. At the same time, the high-speed AD channel receives the intermediate frequency signal after down-conversion from frequency conversion module 3 and sends it to FPGA1 for closed-loop analysis.

[0044] The shared broadband frequency synthesis module serves as the frequency reference for the entire RF link. It receives the 100MHz clock synchronization signal from the main control module and, through internal multi-loop phase-locked loop (PLL) technology, generates low-phase-noise local oscillator signals (LO1, LO2, LO3, LO4) covering the entire frequency band required by the system. These signals are then precisely distributed to frequency conversion modules 1, 2, and 3 via an equal-length RF blind-plug backplane. Furthermore, it generates a clean synchronization clock signal, which is output to the programmable logic device in the reconfigurable signal processing module. This ensures that the timing of the digital signal generation is strictly aligned with the local oscillator phase of the RF frequency conversion, enabling high-fidelity simulation of complex electromagnetic scenarios.

[0045] The frequency converter module and power amplifier module (RF link layer) consist of frequency converter module 1, frequency converter module 2, frequency converter module 3 and power amplifier module.

[0046] The frequency converter module 1 is internally composed of frequency converter module 1-1 (7GHz~13GHz transmitter module) and frequency converter module 1-2 (2GHz~18GHz transmitter module). The main function of frequency converter module 1-1 (7GHz~13GHz transmitter module) is to filter, amplify, attenuate, and mix the 0.1GHz~1.1GHz baseband signal multiple times to a 7GHz~13GHz radio frequency signal; the main function of frequency converter module 1-2 (2GHz~18GHz transmitter module) is to filter, amplify, attenuate, and mix the 0.1GHz~1.1GHz baseband signal multiple times to a 2GHz~18GHz radio frequency signal. By adopting a segmented coupling or segmented power divider output followed by final RF signal synthesis via microwave switching, the frequency conversion module achieves a dynamic attenuation range of up to 110dB with an attenuation step accuracy of 0.5dB. This effectively solves the engineering challenges of insertion loss deterioration and nonlinearity in single broadband devices, ensuring high fidelity and flatness of the field test excitation signal over a very wide power range (-110dBm to 0dBm).

[0047] Frequency converter module 1 receives the intermediate frequency (IF) signals (0.1GHz~1.1GHz) output from DA1 and DA2, and performs independent two-way frequency conversion operations in conjunction with the LO signal allocated by the frequency synthesizer. The up-converted RF signals are then sent to power amplifier module 1 (covering 7-13GHz) and power amplifier module 2 (covering 2-18GHz) respectively through power divider 1 and power divider 2. Frequency converter module 2 receives the IF signal (0.1GHz~1.1GHz) from DA4, up-converts it, and sends it to power amplifier module 4 (covering 2-18GHz) for linear amplification. Frequency converter modules 1 and 2 mainly complete the frequency shifting and preliminary conditioning of the signals, providing RF signals that meet the input requirements for the power amplifier links.

[0048] Frequency conversion module 3 (bidirectional): In the transmitting direction, it receives the DA3 signal, up-converts it, and sends it to the power amplifier module 3 (covering 0.1-18GHz); in the receiving direction, it receives externally input high-frequency signals such as "radar excitation signals", down-converts them into intermediate frequency signals, and sends them back to the AD channel of the reconfigurable signal processing module.

[0049] The power amplifier modules are responsible for linearly amplifying the frequency-converted signal to achieve the radiated power level required for field testing. Each power amplifier module is optimized for its specific operating frequency band (Power Amplifier Module 1: 7-13GHz; Power Amplifier Module 2: 2-18GHz; Power Amplifier Module 3: 2-18GHz; Power Amplifier Module 4: 0.1-18GHz) to ensure sufficient output power, good linearity, and gain flatness across a wide frequency range. The modules integrate comprehensive power monitoring, temperature compensation, and protection circuits, enabling stable operation under the harsh environmental temperature changes of the ship's deck. They also automatically implement protective measures in case of overload or deterioration of the standing wave ratio (VSWR) to ensure equipment safety.

[0050] The programmable RF switching matrix module, serving as the intelligent routing hub of this system, employs a broadband solid-state MEMS microwave switch array (isolation >70dB, response <5ms). Its core function is to replace manual cable plugging and unplugging, enabling software-defined test topology. The matrix's inputs aggregate various high-power output signals from power amplifier modules 1 to 4, external radar excitation inputs, and signals under test. Based on the direct drive commands from the main control module, the matrix routes these signals millisecond-level to the physical output ports on the front panel (such as the 7-13G output of scenario 1, the 2-18G output of scenario 2, etc.) or back to the internal spectrum analyzer module via the closing of internal cross-point switches.

[0051] As a built-in measurement unit of the system, the spectrum analyzer module provides standard frequency domain signal analysis capabilities. It receives the signal under test routed by the matrix switch and can measure multiple indicators such as spectrum, power, phase noise, and spurious signals in real time. The results are then uploaded to the main control module through a dedicated backplane. This allows operators to perform self-testing of the generated signal quality or preliminary evaluation of the response of the device under test within the system without connecting an external oscilloscope or spectrum analyzer, thus achieving integrated "test-analysis".

[0052] The IFF (Identification Friend or Foe) module is a dedicated signal processing unit that fully implements the simulation and calculation functions of the IFF interrogation and response protocol. It can generate standard-compliant interrogation signal waveforms according to instructions, amplify them, and transmit them. Simultaneously, its receiving channel can process and decode signals from the transponder in real time, completing identification and information extraction, and reporting the results to the main control system. The integration of this module enables the platform to have independent IFF equipment testing and verification capabilities.

[0053] The power conversion module is compatible with both AC mains and DC power inputs, adapting to diverse power supply environments on the ship's deck, and performs preliminary rectification, filtering, and voltage regulation. The high-reliability power module performs secondary DC-DC conversion, providing multi-channel isolated, low-noise, and precise voltages to different units such as computers, radio frequency, and digital circuits. It also features complete voltage and current monitoring and overload protection functions. The entire unit undergoes meticulous thermal design and enhanced heat dissipation measures, and is fully protected against three-dimensional weathering processes, ensuring stable and reliable operation in extreme temperatures ranging from -40°C to +70°C, as well as in harsh ship deck environments such as strong vibration and shock, salt spray, and humid heat.

[0054] Example 2: Addressing the unique characteristics of high-power radio frequency (RF) operations in the field, the system is designed around the principles of "safety isolation + system integration." Through the aforementioned systematic optimization, a field protection technology solution integrating "physical separation, mandatory authentication, and controlled interconnection" is proposed, based on the operational mode and system architecture levels. Figure 2 As shown.

[0055] 1) Physical Separation: The system is physically divided into a physically isolated intelligent control domain and an RF front-end domain. By separating the control terminal from the RF front-end host, a distributed operating environment is constructed, keeping operators away from radiation sources and ultimately achieving the comprehensive effect of "eliminating personnel radiation risks".

[0056] 2) Confidentiality and Trustworthiness: Establishing a hardware-level secure communication mechanism. For secure wireless communication links, the system embeds hardware security chips conforming to national cryptographic standards in both the intelligent control domain and the radio frequency front-end domain. When the secure communication link is wireless, during the connection establishment phase, two-way authentication is performed based on the digital certificate pre-installed in the hardware security chip, and a session key is negotiated. During communication, both commands issued by the control terminal and data transmitted back are encrypted and protected for integrity end-to-end in real time using block cipher algorithms by the security chip, thereby achieving the effect of "ensuring the security and trustworthiness of the control link".

[0057] 3) Controlled Interconnection: Define standardized intelligent nodes to access the ship's internal support network, thereby achieving the comprehensive benefits of "supporting remote collaboration, task scheduling and data fusion analysis".

[0058] Example 3: To resolve the conflict between portability and full functionality, the system features a deep sharing and redesign of core hardware resources (shared broadband frequency integration module and high-density PXIe modular integration), such as... Figure 3 As shown, a "shared broadband frequency synthesis module" replaces multiple independent local oscillators, combined with "high-density PXIe modular integration" technology. The shared broadband frequency synthesis module employs a hybrid architecture of phase-locked loop (PLL) and direct digital frequency synthesis (DDS), internally integrating a multi-output microwave switch matrix and a filter network. The main control module can generate a low-phase-noise local oscillator signal at the target frequency based on the currently received underlying hardware control command set, time-division multiplex it, and dynamically route it through the internal switch network to designated channels of the frequency converter and power amplifier modules.

[0059] Based on this, the system adopts a high-standard military-grade ruggedized modular design, integrating all functional units in a high-density manner and interconnecting them through a unified high-speed backplane, which greatly reduces internal cables and structural components, achieving an extremely compact physical form.

[0060] Example 4: To ensure that multiple pieces of equipment under test are strictly aligned in tactical simulation, the system adopts a global spatiotemporal unified architecture and implements a three-level progressive hardware synchronization.

[0061] The first-level reference source uses a satellite-disciplined high-stability oven-controlled crystal oscillator (OCXO) as the primary reference, ensuring its long-term stability is synchronized with UTC. It is also compatible with external high-stability clock inputs (such as the main clock of shipborne radar), so that the system and the main combat equipment have the same clock source.

[0062] The second-level distribution and regeneration network is responsible for the purification and distribution of clock signals. As a high-performance phase-locked loop configured as a second-level distribution with low-bandwidth filtering mode, it generates multiple low-jitter (<50fs RMS) clock replicas and ensures that the transmission delay deviation of each path is less than 25ps through strict equal-length wiring design on a dedicated backplane.

[0063] The third-level terminal is synchronously deployed in each functional module. It generates a local clock through a secondary phase-locked loop and an FPGA-embedded phase-locked loop, and introduces fixed delay measurement and dynamic phase calibration algorithms to compensate for phase errors caused by production tolerances and temperature drift in real time.

[0064] In the hardware-software collaborative closed-loop control logic, the master control module uses a hardware timestamp unit to capture IEEE 1588 (PTP) synchronization messages. Its core innovation lies in using the master-slave clock offset calculated by PTP not only for software timestamp correction, but also directly converting the absolute time offset into hardware control parameters and writing them into the feedback frequency divider register or digitally controlled oscillator of the secondary phase-locked loop to dynamically compensate and hard correct the oscillation phase of the local physical clock.

[0065] To achieve optimal synchronization performance, the secondary phase-locked loop is configured with a multi-source proportional-integral (PI) filter, whose closed-loop phase transfer function strictly follows:

[0066]

[0067] in, For phase detector gain, For voltage-controlled oscillator gain, This is the filter transfer function.

[0068] To achieve zero steady-state error phase tracking and excellent dynamic adjustment performance, F(s) is designed as an active proportional-integral (PI) filter with the following transfer function: By rationally selecting the loop bandwidth and damping coefficient, an optimal balance is achieved between fast phase tracking capability and strong in-band phase noise suppression, thus meeting the stringent requirements of synchronization systems for dynamic response and static purity under complex external environments.

[0069] To quantitatively evaluate and control the final accuracy of the system, the main error sources were modeled and targeted for suppression. The system's global synchronization accuracy ΔT is mainly constrained by the following three errors: measurement calibration error ΔTmeasurement, transmission path jitter ΔTjitter, and temperature drift error ΔTtemperature. By employing high-precision calibration methods, optimizing power supply and wiring design, and implementing a dynamic temperature compensation algorithm, the theoretical design goal of the system is:

[0070]

[0071] By specifically suppressing each source of error, theoretically it is possible to ensure For stable operation at less than 100 picoseconds, in terms of engineering implementation and on-site support requirements, as long as it reaches the microsecond level, it can meet the requirements of various support conditions.

[0072] like Figure 4 As shown in the system simulation results, even within a wide temperature range where the ambient temperature cyclically changes, after dynamic compensation, the system's clock phase offset (green curve) is strictly limited. Within the range, the timing disorder caused by temperature drift was completely eliminated.

[0073] Example 5: To overcome the problem of poor adaptability of traditional test systems when facing multiple heterogeneous equipment support tasks in limited frontier deployment scenarios, this example provides an automated test process reconstruction scheme based on a programmable radio frequency switching matrix.

[0074] like Figure 5 As shown, in the test process, after parsing the configuration file, the main control module drives the programmable RF switching matrix (directly driven by the main control module). On one hand, by utilizing multiple sets of broadband solid-state microwave switching units covering different frequency bands within the matrix, and the field-programmable gate array hardware direct-drive control circuit, a physical connection path is established instantaneously within milliseconds. On the other hand, in the digital domain, the internal logic resources of the field-programmable gate array (FPGA) within the reconfigurable signal processing module are divided into a static functional area and multiple reconfigurable partitions, configured to load the hardware bitstream of radar and other signal processing algorithm kernels online into the designated reconfigurable partitions through dynamic partial reconfiguration technology.

[0075] Furthermore, the reconfigurable signal processing module internally deploys digital automatic gain control logic. This logic employs a dual-threshold detection mechanism, utilizing the field-programmable gate array (FPGA) to obtain the maximum value of the data acquired by the analog-to-digital converter within the gate and comparing it with preset upper and lower thresholds to output the control code for the digitally controlled attenuator. The core design lies in the fact that the range difference between the upper and lower thresholds is set to be strictly greater than the single attenuation step of the digitally controlled attenuator (e.g., an attenuation step of 0.5 dB, preferably 3 dB). This special design effectively prevents high-frequency flipping oscillations of the gain control code caused when a large input signal happens to be at the judgment boundary.

[0076] Example 6: To overcome the poor adaptability of traditional testing systems due to their fixed functions, this system implements dynamic reconfiguration through software and hardware collaboration. For example... Figure 6 As shown, its core lies in the "resource management engine" running inside the main control module. At the software level, the resource management engine abstracts the entire programmable RF switching matrix and its surrounding modules into a weighted directed graph. Among them, vertex set Represents all physical nodes in the system, including RF signal source ports, receiver ports, and all internal input / output crossover points of the microwave switch matrix; edge set This represents all possible physical connection paths between the aforementioned nodes via internal coaxial cables or closed microwave switches. In this weighted directed graph, each edge is assigned a weight, which specifically represents the high-frequency signal insertion loss (insertion loss) value and / or isolation penalty value of that physical path or microwave switch in the current test frequency band. The insertion loss value is pre-stored in the system database based on the factory calibration data.

[0077] Upon receiving a logic test request (i.e., specifying the source vertex and the destination vertex), the resource management engine transforms the problem into a graph test. The system solves the shortest path problem with constraints. It runs Dijkstra's algorithm or a variant, using the objective function of minimizing the sum of the weights of all traversed edges (i.e., the total insertion loss of the RF link). The resulting optimal subgraph is the physical routing path that satisfies the logical requirements. Subsequently, the system sets the edges that constitute this subgraph. Mapped to a The configuration of the cross-point switch state table is compiled into driver code and sent to the underlying hardware for execution.

[0078] Example 7: Based on the above architecture, this invention provides a microwave integrated testing method based on software-defined topology and dynamic reconfiguration, covering the test cycle of test link reconfiguration and timing synchronization, including the following steps:

[0079] Step 1: Analyze the resource usage set:

[0080] When conducting in-flight testing of a certain type of shipborne radar, the main control module receives a logical test requirement script in XML or JSON format from the control terminal. This script only describes the business requirements (e.g., "Generate a 7-13GHz linear frequency modulated radar target echo with a pulse width of 10µs and connect it to the radar receiving antenna port"). The resource management engine within the main control module translates this business requirement into a "resource occupancy set" for the underlying hardware. Specifically, the resource occupancy set includes: the external physical test port to be called (e.g., port A), the specific radar target generation algorithm IP core, the required local oscillator center frequency (e.g., 10GHz), and the logical connection topology (i.e., the abstract connection relationship of baseband → upconverter → power amplifier → port A).

[0081] Step 2, Dynamic Reconstruction Signal Processing Module:

[0082] Based on the parsed resource usage set, the main control module extracts the pre-compiled hardware bitstream file (.bit or .bin file) of the radar target generation algorithm from the local solid-state repository via a high-speed dedicated backplane (such as a PXIe bus). Utilizing the FPGA's dynamic partial reconfiguration technology, without interrupting the FPGA's global clock and other resident control logic, the bitstream is loaded into the designated reconfigurable partition within milliseconds via a dedicated ICAP or PCAP configuration port. At this moment, the FPGA partition is instantly "shaped" into a dedicated radar signal generator.

[0083] Step 3: Configure and allocate the global local oscillator:

[0084] The main control module sends SPI / I2C control commands to the only shared broadband frequency synthesis module in the system. It controls the internal broadband phase-locked loop (PLL) to lock and generate the required high-purity 10GHz local oscillator signal. Subsequently, it controls the microwave multiplexer matrix inside the frequency synthesis module to precisely route the 10GHz local oscillator signal through an internal coaxial RF cable of equal length to the local oscillator input port of "Conversion Module 1," which is assigned to perform the upconversion task. This completely eliminates the need for independent local oscillator sources required by traditional frequency conversion channels.

[0085] Step 4: Drive the RF matrix to close and reconstruct the topology:

[0086] Based on a weighted directed graph composed of all available switching nodes within the system, and using the insertion loss and channel isolation of each microwave switching unit in the current test frequency band as weight constraints, the optimal subgraph with the minimum sum of edge weights is calculated as the physical routing path. This subgraph is then compiled into low-level driver code to directly drive the closing action of the microwave switching units within the programmable RF switching matrix. The end-to-end test link from the FPGA to the inverter and then to physical output port A is instantly constructed, achieving "single physical connection, fully automatic internal routing".

[0087] Step 5: Software and hardware collaborative closed-loop time synchronization (timing alignment):

[0088] To ensure that the generated high-frequency radar signal and the equipment under test have strict phase coherence characteristics, the system initiates a hard correction synchronization mechanism after the physical link is established.

[0089] Specifically, the hardware timestamp units distributed on each functional board capture the synchronization messages of the IEEE 1588 Precision Time Protocol (PTP) by listening to the dedicated time trigger network, and calculate the absolute time offset of the current local clock of the board relative to the primary reference clock (such as a GPS-tamed temperature-controlled crystal oscillator) (e.g., a deviation of +45 picoseconds).

[0090] This invention overcomes the limitations of traditional software synchronization. The main control logic completely bypasses the operating system's software interrupt scheduling, directly converting the absolute time offset into a low-level hardware control word. This word is then written directly to the feedback divider register of the local secondary phase-locked loop (PLL) chip via the low-level bus, or to the programmable digital delay line. This direct "hard correction" of the physical clock oscillation phase completely eliminates random jitter caused by temperature drift and software system load, ensuring nanosecond-level or even picosecond-level alignment of the entire system's data acquisition and signal transmission timing.

[0091] Step Six: Cooperative Actions Triggered by Absolute Time Scale

[0092] The main control module further analyzes the event timing in the logic test requirements, converts it into event instructions with absolute timestamps, and distributes them to each module through the time synchronization network. Each module triggers the generation of multi-channel coherent signals and cross-system collaborative actions at precise absolute times according to the received absolute timestamps.

[0093] To illustrate the software-defined and dynamic configuration capabilities of the reconfigurable signal processing module of this invention, the following are examples of resource configuration in various typical test scenarios. The system dynamically loads different algorithm kernels onto the FPGA through software instructions and configures the corresponding RF and digital signal links, thereby enabling rapid switching between multiple test functions on a single hardware platform. The core logic of each scenario configuration is as follows:

[0094] Scenario 1 (Radar Target Generation - Dual Channel): The system function is to generate dual-channel radar target simulation signals in the 7-13GHz frequency band. FPGA1 is loaded with a radar target generation algorithm, and FPGA2 is loaded with a radar signal generation algorithm to provide background or reference signals. The AD module and frequency conversion modules 1-2 are in operation for possible signal acquisition or feedback; DA1 and DA2 ports are configured to output "Radar Target 1" and "Radar Target 2" signals, respectively, and are up-converted to radio frequency by their associated frequency conversion modules 1-1 and 2. Other unused frequency conversion modules and DA ports are in sleep mode to save power.

[0095] Scenario 2 (Radar Signal Generation - Single-Channel Wideband Coverage): The system needs to generate single-channel radar signals in the 0.1-18GHz and 18-40GHz frequency bands. In this scenario, both FPGA1 and FPGA2 are loaded with radar signal generation algorithms to handle wideband or complex waveforms. The main signal generation links are implemented through ports DA3 and DA4, which are connected to frequency converter modules 3-1 and 3-2 respectively, thus covering the two sub-bands. Other acquisition and generation channels related to the preceding scenario are in sleep mode.

[0096] Scenario 3 (High Pulse Density Radar Signal Generation - 4 Channels): This scenario requires the simultaneous generation of 4 channels of radar test signals, including two channels from 7-13GHz, one channel from 0.1-18GHz, and one channel from 18-40GHz, to simulate a high-density target environment. Both FPGAs are used for radar signal processing. All four output ports (DA1, DA2, DA3, and DA4) and their corresponding frequency conversion modules are activated, forming four parallel signal generation links.

[0097] Scenario 4 (Communication Signal Generation): The system function switches to communication signal generation. FPGA2 loads the communication signal generation algorithm, while FPGA1, although loaded with the radar target generation algorithm, may be in standby or auxiliary mode. Only the DA3 port and its associated frequency converter module 3-1 are activated to output communication signals, while the other channels are in sleep mode, reflecting the on-demand allocation of resources.

[0098] Scenario 5 (Hybrid Generation of Communication and Radar Signals): The system needs to generate both communication and radar signals (2-18GHz) simultaneously. FPGA1 processes the radar signal, and FPGA2 processes the communication signal. Accordingly, the DA2 port (associated with frequency converter module 2) is activated to output the radar signal, and the DA3 port (associated with frequency converter module 3-1) is activated to output the communication signal, forming two independent concurrent excitation links.

[0099] Scenario 6 (Hybrid Generation of Radar Targets and Communication Signals): This scenario combines radar target simulation with communication signal generation. FPGA1 is responsible for radar target generation, and FPGA2 is responsible for communication signal generation. The AD module and frequency conversion modules 1-2 operate, possibly for monitoring or closed-loop testing; DA1 and DA2 output radar targets, and DA3 outputs communication signals, achieving synchronous simulation capability of multiple signal types.

[0100] Scenario 7 (Synthetic Aperture Radar - SAR Signal Processing): Dedicated to SAR testing. FPGA1 is loaded with a SAR-specific processing algorithm, while FPGA2 is loaded with a general radar signal algorithm as support. The main signals are output through the DA1 port and the frequency converter module 1-1, while other links are in sleep mode, demonstrating customized configuration capabilities for specific high-end testing.

[0101] Scenario 8 (Special Radar Mode SA2 / SA3 Mixed with Radar Signal): The system needs to generate a mixed scenario of special radar mode (SA2 / SA3) signals and regular radar signals. FPGA2 loads a composite algorithm that integrates SA2 / SA3 and radar signals. The output is handled by both the DA3 port (outputting SA2 / SA3 signals) and the DA4 port (outputting radar signals).

[0102] Scenario 9 (Backward Interference Simulation and Waveform Comparison): This scenario is used for electronic countermeasures testing, including interference signal generation and original waveform comparison and analysis. FPGA1 integrates signal generation and waveform comparison algorithms. The AD module and frequency converter modules 1-2 operate to acquire the response of the device under test; the DA1 port outputs a radar signal as interference or a comparison benchmark, realizing a closed-loop test of "generation-acquisition-analysis".

[0103] Scenario 10 (Multi-channel Radar Target and Signal Wideband Coverage): This scenario simultaneously generates radar targets and signals within a 0.1-18GHz wideband. FPGA1 handles target generation, and FPGA2 handles signal generation. AD and frequency conversion modules 1-2 operate, with all four ports (DA1, DA2, DA3, and DA4) activated to output two radar target signals and two radar signal signals, respectively. This demonstrates the system's powerful parallel processing capabilities under high complexity and wideband multi-tasking conditions.

[0104] Scenario 11 (Data Link Communication Parsing): The system function switches to parsing data link signals such as 12 / 16A / 16B. FPGA1 loads the data link communication parsing algorithm. The AD module, frequency converter modules 1-2, DA1, DA2, and associated frequency converter modules are all in working state, forming a complete data link signal reception, down-conversion, digital acquisition, and real-time interpretation link.

[0105] Scenario 12 (Ultra-wideband agile signal generation): To achieve the generation of agile frequency-agile signals with an instantaneous bandwidth of 6GHz, the system employs a special configuration. FPGA2 is loaded with a broadband radar signal generation algorithm, possibly combined with agile frequency-agile control logic. The signal is output through the DA3 port and frequency converter module 3-1, utilizing the broadband processing capability of this channel to achieve high-performance signal simulation.

[0106] Table 1 shows the configuration of the reconfigurable signal processing module under different operating scenarios and modes.

[0107]

[0108] Example 8: Figure 7 illustrates the verification process for multi-equipment coordinated response testing based on the high-precision timing environment of this invention. This example further illustrates the specific application of "triggering multi-channel coherent signal generation and cross-system coordinated action at precise absolute moments" as described in claim 10.

[0109] Test scenario: Simulate enemy fire control radar illumination, triggering a coordinated anti-detection response from the ship's radar and electronic warfare equipment.

[0110] Test objective: To quantitatively verify the time consistency of multiple real avionics devices on the ship executing predetermined coordinated defense actions under the triggering of external threat signals, and to test the timing scheduling capability of this support system as the coordinated control center.

[0111] Test parameter settings: Trigger signal: The system generates a simulated enemy fire control radar illumination pulse train, which is transmitted through a radiating antenna; Participating equipment: The ship's actual radar and electronic warfare systems. The radar and electronic warfare onboard data control and monitoring interfaces are connected to this system via a test cable; Desired synchronization point: The leading edge of the trigger signal (time scale) Within Δt=100ms after the occurrence, all devices complete the response action; test rounds: N=10 times, taking into account both statistical validity and test efficiency.

[0112] Test Initialization: Connect this support system to the test ports or signal injection ports of the radar, electronic warfare, and communication equipment under test; configure coordinated response rules in the support system's main control software: when a simulated threat signal of a specific pattern is detected, simultaneously issue a preset "anti-detection mode" switching command to the three devices. The command includes the expected action start time window based on the global clock; activate the support system's precision timing module, and distribute the time base to the data acquisition units of each participating device via hardware signals or network protocols (such as PTP) to ensure that the time synchronization error of each node is less than 1 millisecond.

[0113] Multi-round test execution: In the first round of testing, the signal generation unit of the support system transmits a pre-generated simulated enemy fire control radar signal through an RF switch matrix and a radiating antenna. The system accurately records the absolute time stamp T0 of the signal transmission; after receiving the threat signal, the three actual devices execute preset actions (such as radar frequency hopping, electronic warfare suppression pulse, and communication silence) according to their own processing logic or the received instructions from the support system; when each device completes the final node of its own physical or logical layer action, it sends a hardwired acknowledgment pulse with a local timestamp Tᵢ to the support system through digital I / O or a dedicated data channel.

[0114] Data Acquisition and Single-Pass Error Calculation: Ensure the system's data acquisition unit synchronously captures three confirmation pulses and reads their timestamps T1, T2, and T3; calculate the synchronization error of coordinated actions in a single round of testing. In other words, the dispersion (sample standard deviation) of the completion timestamps of the three actions relative to their mean:

[0115]

[0116] Store the current round And each original timestamp.

[0117] Overall Statistics and Evaluation: After completing 10 rounds of testing, calculate the overall average synchronization error. and maximum single-wheel error Generate a test report, analyze the distribution of synchronization errors (whether it is stable, whether a certain device is consistently delayed), and compare it with the system design requirements (requirements). Compare these to determine whether the collaborative performance meets the standards.

[0118] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An integrated field testing system for shipborne electronic equipment, characterized in that, It includes a physically isolated intelligent control domain and a radio frequency front-end domain, as well as a secure communication link connecting the intelligent control domain and the radio frequency front-end domain; The intelligent control domain includes a control terminal for planning test tasks, setting parameters, monitoring status, and generating logical test requirements. The radio frequency front-end domain is integrated within a ruggedized chassis and includes a main control module, a reconfigurable signal processing module, a shared broadband frequency synthesis module, a frequency converter and power amplifier module, and a programmable radio frequency switching matrix, all interconnected via a high-speed dedicated backplane; wherein: The main control module is used to receive the logic test requirements issued by the control terminal via the secure communication link, parse the logic test requirements to generate the underlying hardware control instruction set, and perform unified scheduling of global hardware resources. The reconfigurable signal processing module is used to dynamically load a specified signal processing algorithm kernel according to the underlying hardware control instruction set, so as to generate the digital baseband or intermediate frequency signal required for test stimulus, or to process the received digital response signal. The shared broadband frequency synthesis module, as the global RF reference of the RF front-end domain, is used to generate a local oscillator signal of the target frequency according to the underlying hardware control instruction set, and dynamically allocate it to the designated frequency conversion channel of the frequency conversion and power amplifier module through the internal switching network to complete the frequency conversion processing of the signal. The programmable RF switching matrix, directly driven by the main control module, is used to establish a physical signal path that can be dynamically configured by software between the frequency converter and power amplifier module, the system's built-in measurement unit, and the external physical port. The main control module is configured to, upon receiving a test task, synchronously schedule the reconfigurable signal processing module to load the algorithm kernel, the shared broadband frequency synthesis module to allocate the local oscillator signal, and drive the programmable RF switching matrix to switch on and off, thereby instantiating an end-to-end physical test link that matches the logical test requirements within the RF front-end domain.

2. The integrated field testing system for shipborne electronic equipment according to claim 1, characterized in that, The main control module internally runs a resource management engine, which is configured as follows: Establish a logical model that abstracts physical RF ports, instrument modules, and switch nodes into a unified virtual resource; Based on the aforementioned logical testing requirements, a weighted directed graph is constructed. The vertex set of the weighted directed graph represents the signal source port, receiver port, and input / output intersection of each microwave switch within the system, while the edge set represents the physical connection paths that can be established between nodes. Using the insertion loss and channel isolation of the microwave switch in the current test frequency band as weight constraints, the physical routing path that meets the logic test requirements and has the optimal signal insertion loss is calculated based on the shortest path algorithm; the physical routing path is then compiled into a driving code frame containing the specific matrix channel switch states.

3. The integrated field testing system for shipborne electronic equipment according to claim 2, characterized in that, The programmable RF switching matrix includes multiple sets of broadband solid-state microwave switching units covering different frequency bands, as well as a field-programmable gate array hardware direct-drive control circuit that communicates with the main control module. The field-programmable gate array hardware direct drive control circuit is used to parse the drive code group frame, generate low-voltage differential drive signals or transistor-to-transistor logic signals, and control the closing and opening of the broadband solid-state microwave switch unit within the delay to achieve non-blocking routing of radio frequency signals.

4. The integrated field testing system for shipborne electronic equipment according to claim 1, characterized in that, The reconfigurable signal processing module includes a field-programmable gate array, multiple high-speed digital-to-analog converter channels connected to the field-programmable gate array, and multiple high-performance analog-to-digital converter channels. The internal logic resources of the field-programmable gate array are divided into a static functional area and multiple reconfigurable partitions, and are configured to load the hardware bitstream of the signal processing algorithm kernel into the specified reconfigurable partitions online through dynamic partial reconfiguration technology. The reconfigurable signal processing module is internally equipped with digital automatic gain control logic. The digital automatic gain control logic adopts a dual-threshold detection mechanism, which uses the field-programmable gate array to obtain the maximum value of the data collected by the analog-to-digital converter in the gate and compares it with the preset upper and lower thresholds to output the control code of the digitally controlled attenuator. The range difference between the upper and lower thresholds is set to be strictly greater than the single attenuation step of the digitally controlled attenuator.

5. The integrated field testing system for shipborne electronic equipment according to claim 1, characterized in that, The shared broadband frequency synthesis module adopts a hybrid architecture of phase-locked loop and direct digital frequency synthesis, and integrates a multi-output microwave switch matrix and filter network. The shared broadband frequency synthesis module is configured to generate a low phase noise local oscillator signal based on the underlying hardware control instruction set, and then time-division multiplex and route it to the frequency converter and power amplifier module. The shared broadband frequency synthesis module is also configured to generate a synchronous clock signal and output it to the reconfigurable signal processing module to ensure strict alignment between the digital signal generation timing and the local oscillator phase of the RF frequency converter link.

6. The integrated field testing system for shipborne electronic equipment according to claim 1, characterized in that, The radio frequency front-end domain adopts a global spatiotemporal unified architecture, which includes: The three-stage progressive hardware synchronization circuit includes a satellite disciplined high-stability isothermal crystal oscillator as the primary reference, a central phase-locked loop and equal-length wiring network configured as the secondary distribution in low-bandwidth filtering mode, and secondary phase-locked loops and digitally controlled oscillators deployed in each functional module as the third-stage end synchronization. The hardware-software co-operated closed-loop control logic is used to run a precision time protocol, capture synchronization messages and calculate the absolute time offset, convert the absolute time offset into hardware control parameters and write them into the feedback frequency divider register of the secondary phase-locked loop or the digitally controlled oscillator, and perform dynamic compensation and hard correction of the oscillation phase of the local physical clock.

7. The integrated field testing system for shipborne electronic equipment according to claim 1, characterized in that, The secure communication link is a differentiated encryption control link based on a hardware root of trust, including hardware security chips compliant with national cryptographic standards deployed in the intelligent control domain and the radio frequency front-end domain respectively. When the secure communication link is a wireless link, the intelligent control domain and the radio frequency front-end domain perform two-way authentication based on the digital certificate pre-installed in the hardware security chip and negotiate a session key. During the communication process, the control commands issued by the control terminal and the test data returned by the radio frequency front-end domain are both encrypted and protected for integrity by the hardware security chip using a block cipher algorithm in real time.

8. A microwave synthesis test method based on software-defined topology and dynamic reconfiguration, characterized in that, Applied to the integrated field test system for shipborne electronic equipment as described in any one of claims 1 to 7, the method covers the test cycle of test link reconstruction and timing synchronization, and includes the following steps: Step 1, Parse the resource occupancy set: Receive the logic test requirements issued by the intelligent control domain, and parse the logic test requirement script into the resource occupancy set of the underlying hardware through the resource management engine. The resource occupancy set includes at least the virtual radio frequency port, the signal processing algorithm kernel, the local oscillator center frequency, and the logical connection topology. Step 2, Dynamically reconfigure the signal processing module: Based on the resource occupancy set, call the hardware bitstream of the corresponding signal processing algorithm kernel from the repository and dynamically load it into the specified reconfigurable partition of the field-programmable gate array in the reconfigurable signal processing module; Step 3, Configure and allocate global local oscillator: Send instructions to the shared broadband frequency integration module to control its internal phase-locked loop to generate a local oscillator signal corresponding to the center frequency of the local oscillator, and control its internal multi-output microwave switch matrix to dynamically route the local oscillator signal to the designated frequency conversion module; Step 4, drive the RF matrix to close and reconstruct the topology: Based on the connection diagram of all available switch nodes in the system, use the path optimization algorithm to calculate the physical routing path that satisfies the logical connection topology and has the best signal insertion loss, and compile the physical routing path into the underlying driver code to directly drive the microwave switch unit in the programmable RF switching matrix to close, and automatically complete the construction of the end-to-end physical test link. Step 5, Hardware-Software Cooperative Closed-Loop Time Synchronization: After the physical test link is constructed and during test execution, the synchronization message of the precision time protocol is captured by the hardware timestamp unit. The absolute time offset of the local clock of each functional module relative to the primary reference clock is calculated. The absolute time offset is directly converted into a hardware control word and written into the feedback frequency divider register or digital delay line of the secondary phase-locked loop in the functional module. The oscillation phase of the local physical clock is hard corrected to compensate for the clock jitter error caused by temperature drift and transmission path, ensuring nanosecond-level alignment of the entire system link timing.

9. The method according to claim 8, characterized in that, In step four, the connection graph is a weighted directed graph, whose vertex set represents all signal source ports, receiver ports, and internal input and output intersections of the microwave switch matrix within the system; the edge set represents all possible physical connection paths between nodes established through internal coaxial cables or closed microwave switches. The path optimization algorithm uses the insertion loss and channel isolation of each microwave switching unit in the current test frequency band as weight constraints to solve for the optimal subgraph with the minimum sum of weights of the traversed edges as the physical routing path.

10. The method according to claim 8, characterized in that, The logic test requirement script is an extensible markup language script containing tactical scenarios. The main control module further parses the event timing in the script, converts it into event instructions with absolute timestamps, and distributes them to each module through a time synchronization network. Each module triggers multi-channel coherent signal generation and cross-system collaborative actions at precise absolute times according to the received absolute timestamps.

Images